JP2014038937A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device that can sufficiently relax electric field concentration around an end of a depletion layer extending from a pn junction to the inside of a breakdown voltage holding structure and has a sufficiently high breakdown voltage.
A transition region and a RESURF region are formed in a p-type termination region that surrounds a semiconductor element formed on an n-type semiconductor substrate. The p-type per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 decreases in the transition region 71 as the p-type impurity concentration increases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. The amount of change in the impurity concentration is formed so as to decrease from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. The RESURF region 72 is formed so that the p-type impurity concentration is equal to or lower than the minimum value of the p-type impurity concentration of the transition region 31.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor device including a semiconductor element having a vertical structure, for example, a diode, a field effect transistor (abbreviation: MOSFET), or an insulated gate bipolar transistor (abbreviation: IGBT). .

  2. Description of the Related Art A semiconductor device including a semiconductor element having a relatively high breakdown voltage (hereinafter sometimes referred to as a “high breakdown voltage semiconductor element”) as a vertical structure semiconductor element is connected to an outer peripheral portion of the high breakdown voltage semiconductor element in order to ensure a breakdown voltage. And a termination region having a breakdown voltage holding structure. For example, in the case of a semiconductor device in which a high breakdown voltage semiconductor element is provided in an active region of an n type drift layer, a termination region having a p type breakdown voltage holding structure is formed so as to surround the active region. In such a semiconductor device, when a high voltage is applied, the depletion layer extending from the pn junction between the n-type drift layer and the p-type breakdown voltage holding structure alleviates electric field concentration at the end of the active region. Holds pressure resistance.

  There are various types of pressure-resistant holding structures, and a guard ring structure, a reduced surface field (abbreviation: RESURF) structure, and the like are well known.

  In the guard ring structure, a p-type semiconductor layer containing a p-type impurity at a relatively high concentration surrounds the periphery of the semiconductor element so that the depletion layer does not spread so much from the pn junction to the inside of the breakdown voltage holding structure. It is formed by dividing into rings. The plurality of rings are arranged side by side from the inner side toward the outer side in order from the smallest diameter, and the potential is shared by each ring during reverse bias. However, as the withstand voltage class increases and the required withstand voltage increases, the number of rings tends to increase, so it is difficult to optimize the width of each ring and the spacing between rings, and the desired withstand voltage may not be obtained. There is a problem.

  In the RESURF structure, the p-type semiconductor layer containing the p-type impurity at a relatively low concentration is uniformly formed without being divided, so that the depletion layer extends from the pn junction to the inside of the breakdown voltage holding structure. The withstand voltage can be maintained in a terminal area having a small area. However, there is a problem that electric field concentration is likely to occur at one location in the termination region, and there is a limit to increasing the breakdown voltage by relaxing the electric field concentration.

  As a withstand voltage holding structure capable of solving the above problems, a withstand voltage holding structure having a plurality of density gradations in a direction parallel to the surface of the substrate is disclosed (for example, see Patent Documents 1 and 2). For example, in the technique disclosed in Patent Document 2, the above-described withstand voltage holding structure is realized by a VLD (Variation of Lateral Doping) structure in which the impurity concentration in the direction parallel to the surface of the substrate is controlled by the opening pattern of the implantation mask. Yes.

JP-A-8-316480 JP-A-3-0949469

  In the semiconductor device having a withstand voltage holding structure disclosed in Patent Documents 1 and 2, compared to a semiconductor device having a withstand voltage holding structure such as a guard ring structure or a RESURF structure, the electric field concentration is reduced, and a high withstand voltage can be achieved. Is possible. However, in the semiconductor device having a withstand voltage holding structure disclosed in Patent Documents 1 and 2, the electric field around the end of the depletion layer extending from the pn junction to the inside of the withstand voltage holding structure is not sufficient. In order to further increase the breakdown voltage, further ingenuity is necessary.

  An object of the present invention is to provide a semiconductor device having a sufficiently high breakdown voltage that can sufficiently alleviate electric field concentration around an end of a depletion layer extending from a pn junction to the inside of a breakdown voltage holding structure.

  The semiconductor device of the present invention includes a semiconductor element formed on a first conductivity type semiconductor substrate, and a second conductivity type termination region surrounding the semiconductor element and formed on the semiconductor substrate. The region is formed in a portion on the outer peripheral portion side of the semiconductor element in a direction perpendicular to the thickness direction of the semiconductor substrate, and the second conductivity type impurity concentration, which is the concentration of the second conductivity type impurity, is A transition region that decreases from the outer peripheral portion side toward the outer peripheral portion side of the semiconductor substrate, and a transition region that is formed in a portion closer to the outer peripheral portion side of the semiconductor substrate than the transition region in the direction perpendicular to the thickness direction. The second conductivity type impurity concentration is equal to or lower than the minimum value of the second conductivity type impurity concentration of the transition region and includes a uniform RESURF region, and the transition region is perpendicular to the thickness direction. direction Variation of the second conductivity type impurity concentration per definitive unit length, characterized by comprising smaller toward the outer peripheral side of the semiconductor element on the outer peripheral side of the semiconductor substrate.

  According to the semiconductor device of the present invention, a semiconductor element and a second conductivity type termination region surrounding the semiconductor element are formed on the first conductivity type semiconductor substrate. In the termination region, a transition region is formed in a portion on the outer peripheral portion side of the semiconductor element in a direction perpendicular to the thickness direction of the semiconductor substrate, and a portion on the outer peripheral portion side of the semiconductor substrate from the transition region is connected to the transition region. A RESURF region is formed. In the transition region, the second conductivity type impurity concentration decreases as it goes from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate, and the second conductivity per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate. The amount of change in the type impurity concentration decreases from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate. In the RESURF region, the second conductivity type impurity concentration is equal to or less than the minimum value of the second conductivity type impurity concentration in the transition region, and is uniform.

  With this configuration, since the electric field concentration region can be dispersed over a wide area inside the termination region, a depletion layer that extends from the junction between the first conductivity type semiconductor substrate and the second conductivity type termination region to the inside of the termination region. The electric field concentration around the edge of the substrate can be sufficiently relaxed. As a result, local electric field concentration in the termination region can be suppressed, so that the maximum electric field strength in the termination region can be reduced. Therefore, since the avalanche breakdown voltage can be increased, a semiconductor device having a sufficiently high breakdown voltage can be realized.

1 is a cross-sectional view showing a configuration of a semiconductor device 100 as a basis of a first embodiment of the present invention. It is sectional drawing which shows typically the state of the part of the pressure | voltage resistant holding structure 6 when a voltage is applied to the semiconductor device 100 used as the foundation of the 1st Embodiment of this invention. 4 is a plan view showing a configuration of an implantation mask 40 used for forming the breakdown voltage holding structure 6. FIG. It is sectional drawing which shows the structure of the semiconductor device 110 of the 1st Embodiment of this invention. It is a graph which shows typically the amount of doses to termination field 2 in a 1st embodiment of the present invention. It is sectional drawing which shows typically the state of the part of the pressure | voltage resistant holding structure 6A when a voltage is applied to the semiconductor device 110 of the 1st Embodiment of this invention. Electric field strength in the direction perpendicular to the thickness direction of the semiconductor substrate 11 of the semiconductor device 20 of the second prerequisite technology, the semiconductor device 100 as the basis of the first embodiment, and the semiconductor device 110 of the first embodiment. It is a graph which shows distribution. It is sectional drawing which shows the structure of 100 A of semiconductor devices used as the foundation of the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of 110 A of semiconductor devices of the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 100B of the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 110B of the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 120 of the 4th Embodiment of this invention. It is sectional drawing which shows a mode that the pressure | voltage resistant holding structure 7 in the 4th Embodiment of this invention is formed. It is a graph which shows an example of the dose amount of the transition area | region 91 in the 4th Embodiment of this invention. It is a graph which shows the other example of the dosage of the transition area | region 91 in the 4th Embodiment of this invention. It is sectional drawing which shows the structure of 120 A of semiconductor devices of the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 120B of the 6th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 10 of the 1st premise technique of this invention. It is sectional drawing which shows the structure of the semiconductor device 20 of the 2nd premise technique of this invention. It is sectional drawing which shows typically the state of the part of the resurf structure 5 when a voltage is applied to the semiconductor device 20 of the 2nd premise technique of this invention.

<Prerequisite technology>
FIG. 18 is a cross-sectional view showing the configuration of the semiconductor device 10 according to the first prerequisite technology of the present invention. The semiconductor device 10 includes a semiconductor element 3 formed on the semiconductor substrate 11 and a termination region 2 formed on the semiconductor substrate 11 so as to surround the semiconductor element 3.

  The semiconductor substrate 11 includes a base substrate (not shown) and a drift layer 12 provided on one surface in the thickness direction of the base substrate (hereinafter sometimes referred to as “one surface”). In the first prerequisite technology, the semiconductor substrate 11 is an n-type semiconductor substrate having n-type conductivity. Therefore, the base substrate and the drift layer 12 have n-type conductivity and are made of an n-type semiconductor material. In the following description, the drift layer 12 may be referred to as “n-type drift layer 12”.

  The semiconductor element 3 is formed in the active region 1 of the semiconductor substrate 11. The semiconductor element 3 includes a p-type base region 13 formed in the active region 1 of the semiconductor substrate 11 and an element electrode 14 provided on one surface of the active region 1 in the thickness direction of the semiconductor substrate 11. The p-type base region 13 constitutes a part of the n-type drift layer 12.

  The p-type base region 13 has a relatively high concentration of p-type impurities. The n-type drift layer 12 has a relatively low concentration of n-type impurities. In each figure, a region or layer having a relatively high impurity concentration is indicated by “+”, for example, “p +”. A region or layer having a relatively low impurity concentration is indicated by “-”, for example, “n−”.

  Termination region 2 has p-type guard ring structure 4 as a breakdown voltage holding structure. The guard ring structure 4 is formed by dividing a p-type semiconductor layer containing a p-type impurity at a relatively high concentration into a plurality of band-shaped rings 15, 16, and 17 surrounding the periphery of the semiconductor element 3. The plurality of rings 15, 16, and 17 are arranged side by side from the inner side to the outer side in the direction perpendicular to the thickness direction of the semiconductor substrate 11 in order from the smallest diameter. For example, when the semiconductor element 13 is formed in a circular shape when viewed from one side in the thickness direction of the semiconductor substrate 11, the plurality of rings 15, 16, and 17 are concentric when viewed from one side in the thickness direction of the semiconductor substrate 11. They are formed and are arranged in order from the inside toward the outside in the direction perpendicular to the thickness direction of the semiconductor substrate 11 in order from the smallest.

  In the guard ring structure 4, the number of rings 15, 16, and 17 tends to increase as the breakdown voltage class increases and the required breakdown voltage increases. Therefore, it is difficult to optimize the width of each ring 15, 16, 17 and the interval between rings 15, 16, 17, and there is a problem that a desired breakdown voltage may not be obtained.

  FIG. 19 is a cross-sectional view showing the configuration of the semiconductor device 20 according to the second prerequisite technology of the present invention. Since the semiconductor device 20 of the second base technology is similar in configuration to the semiconductor device 10 of the first base technology described above, the corresponding configurations are denoted by the same reference numerals and description thereof is omitted. The semiconductor device 20 has a RESURF structure 5 as a breakdown voltage holding structure in the termination region 2. The RESURF structure 5 is constituted by a p-type semiconductor layer 21 containing a p-type impurity at a relatively low concentration. The p-type semiconductor layer 21 is uniformly formed without being divided, and the concentration of the p-type impurity is uniform.

  FIG. 20 is a cross-sectional view schematically showing a state of a portion of the RESURF structure 5 when a voltage is applied to the semiconductor device 20 according to the second prerequisite technology of the present invention. When a voltage is applied to the semiconductor device 20, the depletion layer 22 extends from the pn junction between the n-type drift layer 12 and the p-type semiconductor layer 21 to the inside of the p-type semiconductor layer 21. At this time, in the RESURF structure 5, an electric field concentration region 23 having a higher electric field than the peripheral portion is likely to be generated in the portion closer to the n-type drift layer 12 than the end portion 22 a of the depletion layer 22. Depending on the depth of the pn junction, the electric field concentration region 23 may extend to the outside of the pn junction, that is, the n-type drift layer 12.

  Therefore, the RESURF structure 5 shown in FIG. 19 and FIG. 20 has a problem that electric field concentration is likely to occur in one place in the termination region 2, and there is a limit to increasing the breakdown voltage by relaxing the electric field concentration.

When the RESURF structure 5 is applied as a breakdown voltage holding structure to the high breakdown voltage semiconductor device 20 using a Si substrate made of silicon (Si) as the semiconductor substrate 11, even if electric field concentration occurs in the RESURF structure 5, a certain breakdown voltage is achieved. Is expected to be obtained when the dose amount is about 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ⁻² without significantly changing depending on the impurity concentration of the n-type drift layer 12. However, in order to further increase the breakdown voltage, it is necessary to suppress the unipolar concentration of the electric field in the electric field concentration region 23.

  As a breakdown voltage holding structure capable of solving the problems in the guard ring structure 4 shown in FIG. 18 and the RESURF structure 5 shown in FIGS. 19 and 20, a plurality of density gradations are provided in a direction parallel to the surface of the semiconductor substrate 11. A pressure holding structure has been proposed. However, the relaxation of the electric field in the vicinity of the end of the depletion layer extending from the pn junction to the inside of the breakdown voltage holding structures 4 and 5 is not sufficient. In order to further increase the breakdown voltage, further ingenuity is necessary. Therefore, in the present invention, the configurations of the following embodiments are employed.

<First Embodiment>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 which is the basis of the first embodiment of the present invention. Since the configuration of the semiconductor device 100 is similar to that of the semiconductor devices 10 and 20 of the first and second prerequisite technologies described above, the corresponding configurations are denoted by the same reference numerals and description thereof is omitted. The semiconductor device 100 includes a semiconductor element 3 formed on the semiconductor substrate 11 and a termination region 2 formed on the semiconductor substrate 11 so as to surround the semiconductor element 3. The semiconductor substrate 11 is, for example, a small semiconductor chip.

  The semiconductor element 3 is a high breakdown voltage semiconductor element having a relatively high breakdown voltage. The semiconductor device 100 of the present embodiment is configured with such a high breakdown voltage semiconductor element. Therefore, the semiconductor device 100 of the present embodiment is a high breakdown voltage semiconductor device having a relatively high breakdown voltage, and is used as a power device. In the present embodiment, the semiconductor element 3 is a vertical structure semiconductor element 3, for example, a vertical structure diode, MOSFET, or IGBT. The semiconductor element 3 is formed in the active region 1 of the semiconductor substrate 11.

  The semiconductor device 100 has a breakdown voltage holding structure 6 in a termination region 2 surrounding the active region 1 of the semiconductor substrate 11. The breakdown voltage holding structure 6 is formed continuously with the p-type base region 13 constituting the outer peripheral portion of the semiconductor element 3 and is physically and electrically connected to the p-type base region 13. Termination region 2 has the second conductivity type, in this embodiment, p-type conductivity.

  Termination region 2 includes a p-type connection region 30 that is a region connected to semiconductor element 3, a p-type transition region 31, and a p-type RESURF region 32. The connection region 30, the transition region 31, and the RESURF region 32 are formed side by side in this order from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11 in the direction perpendicular to the thickness direction of the semiconductor substrate 11. .

  Here, the direction perpendicular to the thickness direction of the semiconductor substrate 11 means that when one surface that is one surface in the thickness direction of the semiconductor substrate 11 is parallel to the other surface that is the other surface, In the case where one surface in the thickness direction of the semiconductor substrate 11 is not parallel to the other surface, the direction parallel to one surface in the thickness direction of the semiconductor substrate 11 is referred to.

  The connection region 30 is formed continuously to the outer peripheral portion of the semiconductor element 3, specifically, the p-type base region 13 that constitutes the outer peripheral portion of the semiconductor element 3. As a result, the connection region 30 is physically and electrically connected to the outer peripheral portion of the semiconductor element 3.

  The transition region 31 is formed in a portion on the outer peripheral portion side of the semiconductor element 3 in a direction perpendicular to the thickness direction of the semiconductor substrate 11. The transition region 31 is formed continuously with the connection region 30. As a result, the transition region 31 is physically and electrically connected to the connection region 30.

  In the transition region 31, the p-type impurity concentration, which is the p-type impurity concentration, gradually decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. More specifically, in the transition region 31, the p-type impurity concentration continuously decreases from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11.

  In the transition region 31, the amount of change in the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 is constant from the outer peripheral side of the semiconductor element 3 to the outer peripheral side of the semiconductor substrate 11. It has become. Here, the “impurity concentration” is an impurity concentration per unit area, that is, a dose amount, and corresponds to a value obtained by integrating the impurity concentration per unit volume in the depth direction, that is, the thickness direction of the semiconductor substrate 11. To do.

  The RESURF region 32 is formed in a portion closer to the outer peripheral portion of the semiconductor substrate 11 than the transition region 31 in a direction perpendicular to the thickness direction of the semiconductor substrate 11. The resurf region 32 is formed continuously with the transition region 31. As a result, the RESURF region 32 is physically and electrically connected to the transition region 31. The RESURF region 32 has a p-type impurity concentration that is equal to or less than the minimum value of the p-type impurity concentration of the transition region 31 and is uniform. That is, in the RESURF region 32, the p-type impurity concentration is constant to some extent.

  The connection region 30, the transition region 31, and the RESURF region 32 are configured by a p-type semiconductor layer 33 formed by injecting a p-type impurity into the n-type drift layer 12. The p-type semiconductor layer 33 contains a p-type impurity. That is, the connection region 30, the transition region 31, and the RESURF region 32 contain p-type impurities. The p-type semiconductor layer 33 is formed continuously with the p-type base region 13 constituting the outer peripheral portion of the semiconductor element 3.

  The p-type semiconductor layer 33 is formed from a portion in contact with the outer peripheral portion of the semiconductor element 3 to a portion excluding the end portion of the outer peripheral portion of the semiconductor substrate 11. The p-type semiconductor layer 33 in the connection region 30, the p-type semiconductor layer 33 in the transition region 31, and the p-type semiconductor layer 33 in the RESURF region 32 are formed continuously. The p-type semiconductor layer 33 in the connection region 30, the transition region 31, and the resurf region 32, in other words, the connection region 30, the transition region 31, and the resurf region 32 constitute the breakdown voltage holding structure 6.

  The semiconductor substrate 11 is realized by, for example, a Si substrate made of silicon (Si). In this case, examples of the n-type impurity forming the n-type region include phosphorus and arsenic. Examples of the p-type impurity forming the p-type region include boron and aluminum.

  In the breakdown voltage holding structure 6, in order to obtain a high avalanche breakdown voltage sufficient to achieve a desired breakdown voltage, the impurity concentration distribution in the transition region 31 and the resurf region 32 is important. In the present embodiment, a relatively gentle concentration distribution is formed in the transition region 31 in order to disperse the electric field concentration regions inside and around the breakdown voltage holding structure 6.

For example, when the high breakdown voltage semiconductor device 100 is configured using a Si substrate as the semiconductor substrate 11, when the breakdown voltage holding structure 6 is formed, the depletion layer sufficiently extends to the inside of the transition region 31 when the avalanche breakdown occurs. The transition region 31 includes a region where the effective dose amount is about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² .

  Further, in order to prevent electric field concentration in the connection region 30 which is a connection portion between the p-type base region 13 and the breakdown voltage holding structure 6, the dose amount in the connection region 30 needs to be increased to some extent. However, even when the dose in the connection region 30 is low, electric field concentration in the connection region 30 can be prevented by diffusing the impurity deeply, for example, by extending the time of heat treatment performed when diffusing the impurity. .

In order to satisfy the above conditions, for example, it is gradually effective from about 1 × 10 ¹³ cm ⁻² to 2 × 10 ¹³ cm ^{−2 to} about 1 × 10 ¹² cm ⁻² to 2 × 10 ¹² cm ^−2. The connection region 30 and the transition region 31 are formed by reducing the dose. At this time, the amount of change in the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 is constant from the outer peripheral side of the semiconductor element 3 to the outer peripheral side of the semiconductor substrate 11 as described above. Thus, the dose amount of the transition region 31 is decreased.

  FIG. 2 is a cross-sectional view schematically showing a state of a portion of the breakdown voltage holding structure 6 when a voltage is applied to the semiconductor device 100 which is the basis of the first embodiment of the present invention. When a voltage is applied to the semiconductor device 100, the depletion layer 34 extends from the pn junction between the n-type drift layer 12 and the p-type semiconductor layer 33 to the inside of the p-type semiconductor layer 33. At this time, also in the semiconductor device 100 that is the basis of the present embodiment, the electric field concentration region 35 that has a higher electric field than the peripheral portion is formed in the portion closer to the n-type drift layer 12 than the end 34a of the depletion layer 34. Prone to occur.

  However, the breakdown voltage holding structure 6 of the semiconductor device 100 which is the basis of the present embodiment is configured by the p-type semiconductor layer 21 having no change in the p-type impurity concentration shown in FIG. 20 as shown in FIG. Compared with the case where the RESURF structure 5 is provided as the withstand voltage holding structure, the electric field concentration region 35 is distributed over a wide range inside the withstand voltage holding structure 6. Therefore, in the semiconductor device 100 which is the basis of the present embodiment, the electric field concentration is reduced as compared with the semiconductor device 20 of the second prerequisite technology shown in FIG.

  In the breakdown voltage holding structure 6 of the semiconductor device 100 which is the basis of the present embodiment, the area projected on one surface of the semiconductor substrate 11 of the electric field concentration region 35 (hereinafter sometimes referred to as “projected area”) is shown in FIG. This is wider than the projected area of the electric field concentration region 23 in the RESURF structure 5. However, since the maximum electric field strength decreases in the breakdown voltage holding structure 6 of the semiconductor device 100 which is the basis of the present embodiment, the avalanche breakdown voltage of the breakdown voltage holding structure 6 can be increased.

  As described above, according to the semiconductor device 100 as the basis of the present embodiment, the n-type semiconductor substrate 11 is formed with the semiconductor element 3 and the p-type termination region 2 surrounding the semiconductor element 3. . In the termination region 2, a transition region 31 is formed in a portion on the outer peripheral side of the semiconductor element 3 in a direction perpendicular to the thickness direction of the semiconductor substrate 11, and the transition region 31 is connected to the semiconductor substrate more than the transition region 31. A RESURF region 32 is formed in a portion on the outer peripheral portion side of 11. In the transition region 31, the p-type impurity concentration decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. The RESURF region 31 has a p-type impurity concentration that is equal to or lower than the minimum value of the p-type impurity concentration of the transition region 31 and is uniform.

  With this configuration, since the electric field concentration region can be dispersed over a wide area inside the termination region 31, the depletion extending from the pn junction between the n-type semiconductor substrate 11 and the p-type termination region 2 to the inside of the termination region 2. Electric field concentration around the end 34a of the layer 34 can be sufficiently relaxed. As a result, local electric field concentration in the termination region 2 can be suppressed, so that the maximum electric field strength in the termination region 2 can be reduced. Therefore, since the avalanche breakdown voltage can be increased, the semiconductor device 100 having a sufficiently high breakdown voltage can be realized.

  In the semiconductor device 100 that is the basis of the present embodiment, the transition region 31 has a p-type impurity concentration that continuously decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. . As a result, the following effects can be obtained.

  Consider the case where the p-type impurity concentration decreases stepwise unlike the semiconductor device 100 which is the basis of the present embodiment. For example, as shown in FIG. 12 to be described later, the transition region 91 is composed of a plurality of impurity regions 93, 94, 95, and the plurality of impurity regions 93, 94, 95 are reduced in a stepwise manner. Consider the case where In this case, if the dose amount is the same as that of the semiconductor device 100 that is the basis of the present embodiment, the entire size of the electric field concentration region is the same as that of the semiconductor device 100 that is the basis of the present embodiment. become. However, an electric field peak further occurs in the portion of the transition region 91 where the concentration changes, that is, in each of the impurity regions 93, 94, and 95 constituting the transition region 91, and electric field concentration occurs.

  In the semiconductor device 100 which is the basis of the present embodiment, the p-type impurity concentration in the transition region 31 is continuously changed as described above. Therefore, when the p-type impurity concentration is decreased stepwise as described above, the concentration is increased. It is possible to suppress electric field concentration that further occurs in a portion where there is a change. Therefore, the semiconductor device 100 having a higher breakdown voltage can be realized.

  FIG. 3 is a plan view showing the configuration of the implantation mask 40 used for forming the breakdown voltage holding structure 6. The breakdown voltage holding structure 6 can be formed, for example, by performing thermal diffusion after ion implantation using the implantation mask 40 having the pattern shown in FIG. The implantation mask 40 is formed by a silicon oxide film 41, for example.

  The implantation mask 40 has opening patterns 42 to 46 and 51 to 67 such as lines or dots in which the silicon oxide film 41 is not formed. The implantation mask 40 has an opening ratio of the opening patterns 42 to 46 and 51 to 67 (hereinafter may be referred to as “pattern opening ratio”). In the connection region 30 and the transition region 31, the semiconductor substrate 3 is exposed from the outer peripheral side. 11 gradually decreases toward the outer peripheral portion side, and the RESURF region 32 is manufactured to be constant to some extent. Here, the aperture ratio refers to the ratio of the area of the opening pattern to the total area of the region of interest of the implantation mask 40.

When an implantation mask 40 as shown in FIG. 3 is used, for example, when ion implantation is performed in a region having an aperture ratio of 10% with a dose amount of 1 × 10 ¹³ cm ⁻² , the average dose amount in that region is 1 It becomes 10% of 1 × 10 ¹² cm ^{−2 of} × 10 ¹³ cm ⁻² . Further, by performing thermal diffusion after ion implantation, the impurity regions implanted into the respective opening patterns 41 to 46 and 51 to 67 are connected as shown in FIG. 1, and the dose amount is substantially 1 × 10 ¹² cm ^−. The concentration distribution equivalent to the case where ion implantation is performed in ² can be obtained. In FIG. 1, regions into which impurities are implanted from the respective opening patterns 41 to 46 and 51 to 56 are indicated by broken lines. Also in the drawings after FIG. 2, the region into which the impurity is implanted may be indicated by a broken line as in FIG.

  Thus, by controlling the aperture ratio of the implantation mask, the effective dose can be changed in the direction perpendicular to the thickness direction of the semiconductor substrate 11. As a result, the connection region 30, the transition region 31, and the RESURF region 32 that constitute the breakdown voltage holding structure 6 having a concentration distribution in a direction perpendicular to the thickness direction of the semiconductor substrate 11 can be formed in a lump.

  Alternatively, ion implantation is performed through a mask using a mask made of an oxide film or a resist that gradually increases in thickness from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. It is possible to obtain a breakdown voltage holding structure 6 similar to that in the case of controlling the aperture ratio of the mask.

  In addition, in the connection region 30 where the p-type base region 13 and the breakdown voltage holding structure 6 overlap, the p-type impurity concentration of the breakdown voltage holding structure 6 is the highest. %, And may be decreased from the connection region 30 toward the outer peripheral side of the semiconductor substrate 1. Therefore, with the same mask as the p-type base region 13, the breakdown voltage holding structure 6 may be formed by lowering the aperture ratio of the implantation mask in the termination region 2 where the breakdown voltage holding structure 6 is formed.

  In the semiconductor device 100 that is the basis of the present embodiment described above, the transition region 31 has a change amount of the p-type impurity concentration per unit length in a direction perpendicular to the thickness direction of the semiconductor substrate 11. From the outer peripheral side to the outer peripheral side of the semiconductor substrate 11. The transition region 31 is not limited to this, and the amount of change in the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 varies from the outer peripheral portion side of the semiconductor element 3 to the outer peripheral portion of the semiconductor substrate 11. You may gradually become large toward the side. Even in this case, the same effect as that of the semiconductor device 100 which is the basis of the present embodiment can be obtained.

  In the transition region 31, the amount of change in the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 gradually increases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. It is preferable that it is small. This configuration corresponds to the semiconductor device 110 according to the first embodiment shown in FIG. 4 described later. With this configuration, the following effects can be obtained.

  FIG. 4 is a sectional view showing the configuration of the semiconductor device 110 according to the first embodiment of the present invention. The semiconductor device 110 of the present embodiment is similar in configuration to the semiconductor device 100 that is the basis of the first embodiment described above, and therefore, the corresponding components are denoted by the same reference numerals and description thereof is omitted. To do. FIG. 5 is a graph schematically showing a dose amount to the termination region 2 in the first embodiment of the present invention. In FIG. 5, the horizontal axis represents the distance L from the active region 1, and the vertical axis represents the dose amount D.

  In the semiconductor device 110 of the present embodiment, the breakdown voltage holding structure 6A includes the connection region 70, the transition region 71, and the RESURF region 72 that are formed with the dose shown in FIG. The connection region 70, the transition region 71, and the RESURF region 72 are configured by the p-type semiconductor layer 73. The p-type semiconductor layer 73 in the present embodiment is different from the p-type impurity in the transition region 71 in the dose amount and implantation depth, except for the p-type in the semiconductor device 100 that is the basis of the first embodiment. The structure is the same as that of the semiconductor layer 33.

  More specifically, in the present embodiment, as shown in FIG. 5, the dose of the transition region 71 is set to a change amount of the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11. However, it changes so that it may become small as it goes to the outer peripheral part side of the semiconductor substrate 11 from the outer peripheral part side of the semiconductor element 3. FIG.

  That is, in the semiconductor device 110 according to the present embodiment, the transition region 71 has a change amount of the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 from the outer peripheral side of the semiconductor element 3. It becomes smaller as it goes to the outer peripheral side of the semiconductor substrate 11.

  FIG. 6 is a cross-sectional view schematically showing the state of the voltage holding structure 6A when a voltage is applied to the semiconductor device 110 according to the first embodiment of the present invention. When a voltage is applied to the semiconductor device 110, the depletion layer 74 extends from the pn junction between the n-type drift layer 12 and the p-type semiconductor layer 73 to the inside of the p-type semiconductor layer 73. Also in the present embodiment, the electric field concentration region 75 is likely to occur in the portion closer to the n-type drift layer 12 than the end 74a of the depletion layer 74. In the breakdown voltage holding structure 6A of the present embodiment, as shown in FIG. 6, the depletion layer 74 is located on the inner side of the semiconductor substrate 11 as compared with the semiconductor device 100 that is the basis of the first embodiment shown in FIG. The electric field concentration region 75 is spread over a wide range of the withstand voltage holding structure 6A, and the electric field concentration is further relaxed.

  FIG. 7 shows the semiconductor device 20 of the second prerequisite technology, the semiconductor device 100 as the basis of the first embodiment, and the semiconductor device 110 of the first embodiment, perpendicular to the thickness direction of the semiconductor substrate 11. It is a graph which shows electric field strength distribution in a direction. In FIG. 7, the horizontal axis represents the distance L from the active region 1, and the vertical axis represents the electric field strength E. In FIG. 7, the electric field strength distribution of the semiconductor device 20 of the second prerequisite technology is represented by a broken line indicated by reference numeral “24”, and the electric field strength distribution of the semiconductor device 100 that is the basis of the first embodiment is indicated by the reference numeral. The electric field intensity distribution of the semiconductor device 110 of the first embodiment is indicated by a solid line indicated by reference numeral “76”. In FIG. 7, a portion corresponding to the electric field concentration region 35 formed in the semiconductor device 100 which is the basis of the first embodiment shown in FIG.

  As is clear from FIG. 7, the dose amount of the transition region 71 is set to the p-type per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11 as in the present embodiment indicated by reference numeral “76”. When the amount of change in the impurity concentration is changed so as to decrease from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11, the semiconductor device 20 of the second prerequisite technology and the first implementation Compared with the semiconductor device 100 which is the basis of the form, the electric field concentration region can be dispersed and the maximum electric field strength can be reduced.

  As described above, according to the present embodiment, the electric field concentration region can be further dispersed as compared with the semiconductor device 100 that is the basis of the first embodiment shown in FIGS. 1 and 2 described above. The maximum electric field strength can be further reduced. Thereby, the avalanche breakdown voltage of the breakdown voltage holding structure 6A can be increased.

As described above, when the dose of the transition region 71 is changed so that the change amount per unit length of the impurity concentration decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11, 71 is depleted to the surface in a region where the effective dose amount is about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² or less at the time of avalanche breakdown. Therefore, if the transition region 71 includes a dose region of about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² or more, the curvature of the end portion 74 a of the depletion layer 74 is relaxed. , Can effectively disperse the electric field concentration.

  In order to form the concentration profile of the transition region 71 as described above, for example, the implantation mask 40 shown in FIG. It is only necessary to make it so as to decrease in accordance with the downward convex function as it goes to. Examples of downward convex functions include exponential functions and quadratic functions.

When the aperture ratio of the silicon oxide film 41 is decreased in accordance with an exponential function from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11, the outer periphery of the semiconductor substrate 11 is changed from the inner peripheral portion of the transition region 71. The silicon oxide film 41 is formed so that the position in the direction toward the portion is x and the aperture ratio at the position x is 100 × exp (−ax)%. As a result, the effective dose at x = 2.3 / a is reduced to about 1/10 of the case where the aperture ratio is 100%. At this time, by appropriately selecting the dose amount, the size of the transition region 71 and the value of a, the effective dose amount is about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ^{12 with} a width of about 0.41 / a. A region of about cm ⁻² is obtained. Thereby, the effect of dispersing the electric field concentration can be obtained.

  As described above, in this embodiment, an example is shown in which an exponential function is used as a downward convex function. However, when the dose is reduced in accordance with another downward convex function or the like, However, the same effect can be obtained.

<Second Embodiment>
FIG. 8 is a cross-sectional view showing the configuration of a semiconductor device 100A that is the basis of the second embodiment of the present invention. The semiconductor device 100A of the present embodiment is similar in configuration to the semiconductor device 100 that is the basis of the first embodiment described above, and therefore, the corresponding components are denoted by the same reference numerals and description thereof is omitted. To do.

  FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device 110A according to the second embodiment of the present invention. Since the semiconductor device 110A of the present embodiment is similar in configuration to the semiconductor device 110 of the first embodiment described above, the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor device 110A according to the present embodiment and the semiconductor device 100A serving as the basis thereof include an insulating film 81 on one surface of the semiconductor element 3A and the termination region 2 in the thickness direction of the semiconductor substrate 11. The semiconductor element 3 </ b> A includes an element electrode 14 </ b> A that extends over the insulating film 81. The semiconductor element 3A has the same configuration as that of the semiconductor element 3 in the first embodiment and the semiconductor devices 110 and 100 serving as the basis thereof, except that the configuration of the element electrode 14A is different.

  Thus, by providing the element electrode 14A so as to protrude above the insulating film 81, the element electrode 14A can serve as a field plate. Thereby, the electric field concentration in the breakdown voltage holding structure 6 can be further dispersed.

  The insulating film 81 is realized by a field oxide film, for example. The field oxide film is formed by oxidizing the n-type drift layer 12 constituting the semiconductor substrate 11. In the present embodiment, the element electrode 14 </ b> A extends over the transition region 31, but may extend over the resurf region 32.

  As the element electrode 14A, an anode electrode can be used when the semiconductor element 3A is a vertical diode, and when the semiconductor element 3A is a MOSFET or IGBT, a source electrode, an emitter electrode, a gate electrode, or the like. Can be used.

<Third Embodiment>
FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 100B that is the basis of the third embodiment of the present invention. Since the semiconductor device 100B of the present embodiment is similar in configuration to the semiconductor device 100 that is the basis of the first embodiment described above, the corresponding components are denoted by the same reference numerals and description thereof is omitted. To do.

  FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device 110B according to the third embodiment of the present invention. Since the semiconductor device 110B of the present embodiment is similar in configuration to the semiconductor device 110 of the first embodiment described above, the corresponding configuration is denoted by the same reference numeral and description thereof is omitted.

  The semiconductor device 110B of this embodiment and the semiconductor device 100B serving as the basis thereof further include a semiconductor element 3B, an insulating film 82, a floating field plate 83, a channel stopper region 84, and a channel stopper field plate 85. The semiconductor element 3B has the same configuration as that of the semiconductor element 3 in the first embodiment and the semiconductor devices 110 and 100 serving as the basis thereof, except that the configuration of the element electrode 14B is different.

  The insulating film 82 is provided on one surface in the thickness direction of the semiconductor substrate 11 in the termination region 2. The semiconductor element 3 </ b> B includes an element electrode 14 </ b> B that extends over the insulating film 82. As the device electrode 14B, an anode electrode can be used when the semiconductor device 3B is a vertical diode, and when the semiconductor device 3B is a MOSFET or IGBT, a source electrode, an emitter electrode, a gate electrode, or the like. Can be used.

  The channel stopper region 84 is formed at the end of the outer peripheral portion of the semiconductor substrate 11 so as to surround the termination region 2. In this embodiment, channel stopper region 84 has p-type conductivity. The channel stopper region 84 may have n-type conductivity. The channel stopper field plate 85 is provided on one surface of the channel stopper region 84 in the thickness direction of the semiconductor substrate 11.

  The floating field plate 83 is provided on the semiconductor substrate 11 between the element electrode 14B and the channel stopper field plate 85 and spaced from the element electrode 14B and the channel stopper field plate 85. In the present embodiment, the semiconductor device 100B includes a plurality of, specifically five, floating field plates 83. The number of the floating field plates 83 is not limited to this, and the semiconductor device 100B may include one or more floating field plates.

  According to the present embodiment, the floating field plate 83, the channel stopper region 84, and the channel stopper field plate 85 can increase the ratio of potential sharing to the RESURF region 32. Thereby, the electric field concentration in the breakdown voltage holding structure 6 can be further dispersed.

  The floating field plate 83, the channel stopper region 84, and the channel stopper field plate 85 can be formed as follows, for example. For example, when the channel stopper 13 is p-type, it can be formed simultaneously with the step of forming another p-type region such as the breakdown voltage holding structure 6. When the channel stopper 13 is n-type, it can be formed simultaneously with the step of forming another n-type region such as a MOSFET or IGBT cell region.

<Fourth embodiment>
FIG. 12 is a cross-sectional view showing a configuration of a semiconductor device 120 according to the fourth embodiment of the present invention. Since the semiconductor device 120 of the present embodiment is similar in configuration to the semiconductor device 110 of the first embodiment described above, the corresponding components are denoted by the same reference numerals and description thereof is omitted.

  Similar to the semiconductor device 100 of the first embodiment, the semiconductor device 120 of the present embodiment includes the breakdown voltage holding structure 7. In the present embodiment, the breakdown voltage holding structure 7 includes a p-type transition region 91 and a RESURF region 92 connected to the transition region 91. The transition region 91 is continuous with the p-type base region 13 constituting the semiconductor element 3. As a result, the transition region 91 is physically and electrically connected to the p-type base region 13. The semiconductor element 3 is realized by a vertical structure diode, MOSFET, or IGBT, for example.

  In the transition region 91 of the present embodiment, the p-type impurity concentration gradually decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. Transition region 91 includes a plurality of impurity regions 93 to 95 containing p-type impurities, and three impurity regions 93 to 95 in the present embodiment. Each of the impurity regions 93 to 95 has a uniform p-type impurity concentration. That is, each of the impurity regions 93 to 95 has a uniform impurity concentration.

  The plurality of impurity regions 93 to 95 have different p-type impurity concentrations and implantation depths. The plurality of impurity regions 93 to 95 are perpendicular to the thickness direction of the semiconductor substrate 11 so that the p-type impurity concentration gradually decreases from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11. It is formed side by side in various directions.

  The RESURF region 92 is configured in the same manner as the RESURF region 72 in the first embodiment, and has a uniform p-type impurity concentration. The RESURF region 92 is constituted by one impurity region 96 containing a p-type impurity. The impurity region 96 constituting the RESURF region 92 has a lower p-type impurity concentration than the impurity regions 93 to 95 constituting the transition region 91. In FIG. 12, the low p-type impurity concentration is expressed as “p−”. Hereinafter, the impurity regions 93 to 96 constituting the transition region 91 and the RESURF region 92 may be referred to as “p-type regions”.

  Also in the present embodiment, in order to obtain a high avalanche breakdown voltage in the breakdown voltage holding structure 7, the impurity concentration distribution in the transition region 91 and the resurf region 92 is important.

In the breakdown voltage holding structure 7 of the present embodiment, a relatively gentle concentration distribution is formed in the transition region 91 in order to disperse the electric field concentration inside the breakdown voltage holding structure 7. For example, when the breakdown voltage holding structure 7 of the present embodiment is formed in the high breakdown voltage semiconductor device 120 made of a Si substrate, the transition region 91 is effective so that the depletion layer sufficiently extends to the inside of the transition region 91 at the time of avalanche breakdown. A region where the typical dose amount is about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² is included.

  Further, in order to prevent electric field concentration at the connection portion between the p-type base region 13 and the breakdown voltage holding structure 7, it is necessary to increase the dose of the transition region 91 at the connection portion between the p-type base region 13 and the breakdown voltage holding structure 7 to some extent. There is. However, even when the dose of the transition region 91 at the connection portion between the p-type base region 13 and the breakdown voltage holding structure 7 is low, the impurity is diffused deeply, for example, by extending the time of heat treatment performed when the impurity is diffused. Thus, electric field concentration at the connection portion between the p-type base region 13 and the breakdown voltage holding structure 7 can be prevented.

In order to satisfy the above conditions, for example, it is effective stepwise from about 1 × 10 ¹³ cm ⁻² to 2 × 10 ¹³ cm ^{−2 to} about 1 × 10 ¹² cm ⁻² to about 2 × 10 ¹² cm ^−2. A transition region 91 in which the dose amount decreases is formed.

  By forming in this way, the same effect as the first embodiment can be obtained. Specifically, since the electric field concentration region can be dispersed over a wide area inside the transition region 91, it spreads from the pn junction between the n-type semiconductor substrate 11 and the p-type termination region 2 to the inside of the termination region 2. Electric field concentration around the edge of the depletion layer can be sufficiently relaxed. As a result, local electric field concentration in the termination region 2 can be suppressed, so that the maximum electric field strength in the termination region 2 can be reduced. Therefore, since the avalanche breakdown voltage can be increased, the semiconductor device 120 having a sufficiently high breakdown voltage can be realized.

  In the present embodiment, transition region 91 includes a plurality of impurity regions 93 to 95 having a uniform p-type impurity concentration. The plurality of impurity regions 93 to 95 are formed side by side so that the p-type impurity concentration gradually decreases from the outer peripheral side of the semiconductor element 3 toward the outer peripheral side of the semiconductor substrate 11. Thereby, the transition region 91 in which the p-type impurity concentration decreases from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11 can be easily realized. Therefore, the high breakdown voltage semiconductor device 120 as described above can be easily realized.

  The breakdown voltage holding structure 7 of the present embodiment can be formed by performing thermal diffusion after ion implantation using, for example, a silicon oxide film or a resist as an implantation mask. Specifically, a plurality of p-type regions having different impurity concentrations are formed by performing ion implantation multiple times with different doses using a plurality of implantation masks, and a transition region 91 and a RESURF region 92 are formed. be able to.

  Further, the breakdown voltage holding structure 7 of the present embodiment uses a plurality of p-type regions having different impurity concentrations in each region using, for example, the implantation mask 40 as shown in FIG. 3 having different aperture ratios in each region. It is also possible to form by forming all together.

  In addition, a plurality of p-type regions having different impurity concentrations for each region can be collectively formed by ion implantation through a mask using an oxide film or resist mask having a different thickness for each region. It is also possible to form a pressure-resistant holding structure 7 having a form.

  FIG. 13 is a cross-sectional view showing a manner in which the breakdown voltage holding structure 7 according to the fourth embodiment of the present invention is formed. The breakdown voltage holding structure 7 of the present embodiment can also be formed using a plurality of mask patterns 111 to 113 as shown in FIG. 13, for example. In this case, a breakdown voltage holding structure 7 is formed by forming a plurality of p-type regions having different impurity concentrations for each region by providing a region where multiple implantations are performed at the same or different doses. FIG. 13 shows a case where the transition region 91 is composed of six p-type regions 101 to 106 so that the effect of the overlap implantation becomes clear.

  FIG. 14 is a graph showing an example of the dose amount of the transition region 91 in the fourth embodiment of the present invention. In FIG. 14, the horizontal axis represents the distance L from the active region 1, and the vertical axis represents the dose amount D. In the present embodiment, as shown in FIG. 14, a plurality of impurity regions constituting transition region 91, for example, dose variations D1 to Dn between p-type regions 101 to 106 in FIG. In addition, the dose D of the p-type impurity in the transition region 91 is set so that all the widths W1 to Wn-1 in the direction perpendicular to the thickness direction of the semiconductor substrate 11 (hereinafter sometimes simply referred to as “width”) are the same. Is decreasing.

  As a result, the electric field concentration region can be dispersed as compared with the breakdown voltage holding structure 5 having no concentration change in the semiconductor device 20 of the second premise technique shown in FIG. 19 and FIG. The avalanche breakdown voltage can be improved.

  As for the dose amount D of the p-type impurity in the transition region 91, the dose change amounts D1 to Dn gradually increase from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11, or the impurity region 101. The widths W1 to Wn-1 of .about.106 may be gradually reduced or reduced so as to change both. Even in this case, as in the case described above, the electric field concentration region can be dispersed as compared with the breakdown voltage holding structure 5 in the semiconductor device 20 of the second premise technique shown in FIGS. Therefore, the avalanche breakdown voltage of the breakdown voltage holding structure 7 can be improved.

  FIG. 15 is a graph showing another example of the dose amount of the transition region 91 in the fourth embodiment of the present invention. In FIG. 15, the horizontal axis represents the distance L from the active region 1, and the vertical axis represents the dose amount D. As shown in FIG. 15, the dose amount of the transition region 91 is such that the change amounts D1 to Dn of the dose amount gradually decrease from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11 or impurities. It is preferable that the widths W1 to Wn-1 of the regions 101 to 106 are gradually increased or decreased so as to change both.

  Thereby, as shown in FIG. 14, the amount of change D1 to Dn of the dose amount and the widths W1 to Wn−1 of the impurity regions 101 to 106 are all the same, or the outer peripheral portion of the semiconductor substrate 11 from the outer peripheral portion side of the semiconductor element 3. The transition region 91 is changed so that the change amounts D1 to Dn of the dose amount gradually increase or the widths W1 to Wn-1 of the impurity regions gradually decrease or both of them change. The electric field concentration region can be further dispersed as compared with the case where the dose amount is reduced. Therefore, the avalanche breakdown voltage of the breakdown voltage holding structure 7 can be further increased.

  In particular, when the dose amount of the transition region 91 is decreased so that the change amounts D1 to Dn of the dose amount gradually decrease from the outer peripheral portion side of the semiconductor element 3 toward the outer peripheral portion side of the semiconductor substrate 11, the transition region 91 A plurality of impurity regions constituting 91 can be formed side by side so as to reduce the amount of change in the p-type impurity concentration per unit length in the direction perpendicular to the thickness direction of the semiconductor substrate 11. As a result, as in the first embodiment described above, the electric field concentration region can be more dispersed, and the maximum electric field strength can be further reduced. Therefore, the avalanche breakdown voltage of the breakdown voltage holding structure 7 can be further increased.

When the dose amount of the transition region 91 changes as shown in FIG. 15, the transition region 91 reaches the surface in a region where the dose amount is about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² or less at the time of avalanche breakdown. Depleted. Therefore, in a region where the dose amount of the transition region 91 changes as shown in FIG. 15, if a region having a dose amount of about 2 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ⁻² or more is included, depletion occurs. The curvature of the edge of the layer is relaxed and the electric field concentration can be effectively dispersed.

<Fifth embodiment>
FIG. 16 is a cross-sectional view showing a configuration of a semiconductor device 120A according to the fifth embodiment of the present invention. Since the semiconductor device 120A of the present embodiment is similar in configuration to the semiconductor devices 110A and 120 of the second and fourth embodiments described above, the corresponding components are described with the same reference numerals. Is omitted. The semiconductor device 120A according to the present embodiment includes an insulating film 81 on one surface in the thickness direction of the semiconductor element 3A and the semiconductor substrate 11 in the termination region 2. The semiconductor element 3 </ b> A includes an element electrode 14 </ b> A that extends over the insulating film 81.

  Thus, by providing the element electrode 14A so as to protrude above the insulating film 81, the element electrode 14A can serve as a field plate. Thereby, the electric field concentration in the breakdown voltage holding structure 6 can be further dispersed.

  The insulating film 81 is realized by a field oxide film, for example. The field oxide film is formed by oxidizing the n-type drift layer 12 constituting the semiconductor substrate 11. In the present embodiment, the element electrode 14 </ b> A extends over the transition region 31, but may extend over the resurf region 32.

  Also in the present embodiment, as the element electrode 14A, an anode electrode can be used when the semiconductor element 3A is a vertical diode, and a source electrode when the semiconductor element 3A is a MOSFET or an IGBT. An emitter electrode or a gate electrode can be used.

<Sixth Embodiment>
FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device 120B according to the sixth embodiment of the present invention. Since the semiconductor device 120B of the present embodiment is similar in configuration to the semiconductor devices 110B and 120 of the third and fourth embodiments described above, the corresponding components are described with the same reference numerals. Is omitted.

  Similar to the semiconductor device 110B of the third embodiment, the semiconductor device 120B of the present embodiment further includes a semiconductor element 3B, an insulating film 82, a floating field plate 83, a channel stopper region 84, and a channel stopper field plate 85. . The insulating film 82 is provided on one surface in the thickness direction of the semiconductor substrate 11 in the termination region 2. The semiconductor element 3 </ b> B includes an element electrode 14 </ b> B that extends over the insulating film 82. As the device electrode 14B, an anode electrode can be used when the semiconductor device 3B is a vertical diode, and when the semiconductor device 3B is a MOSFET or IGBT, a source electrode, an emitter electrode, a gate electrode, or the like. Can be used.

  According to the present embodiment, the floating field plate 83, the channel stopper region 84, and the channel stopper field plate 85 can increase the ratio of potential sharing in the resurf region 32. Thereby, the electric field concentration in the breakdown voltage holding structure 6 can be further dispersed.

  The floating field plate 83, the channel stopper region 84, and the channel stopper field plate 85 can be formed in the same manner as in the third embodiment.

  As described in the above embodiments, the dimensions of the transition areas 31, 71, 91 and the RESURF areas 32, 72, 92 can be designed independently. As each dimension increases, a higher withstand voltage holding structure 6, 6A, 6B, 7 tends to be obtained. However, it is possible to obtain a sufficiently high breakdown voltage even in the case of the termination region 2 having a small area compared to a conventional guard ring structure or the like.

  In each of the above embodiments, the Si substrate is taken as an example of the semiconductor substrate 11, but a semiconductor substrate made of a semiconductor material having another band gap such as silicon carbide (SiC) may be used. In this case, although the optimum values such as the dose amount are different, the effect of relaxing the electric field concentration can be obtained as in the case of using the Si substrate. Therefore, the semiconductor device of the present invention can be applied not only to the Si power device but also to the SiC power device.

  In each of the above embodiments, the semiconductor device in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the n-type and p-type conductivity types may be reversed.

  Each of the drawings shown in the above embodiments shows the structure and the like in a simple and easy-to-understand manner, and the scale and aspect ratio may be different from the actual ones.

  The present invention can be freely combined with the above-described embodiments within the scope of the invention, and arbitrary constituent elements of the embodiments can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Active area | region, 2 termination | terminus area | region, 3, 3A semiconductor element, 6, 6A, 6B, 7 pressure | voltage resistant holding structure, 11 semiconductor substrate, 12 n-type drift layer, 13 p-type base area | region, 14, 14A element electrode, 22, 34 , 74 Depletion layer, 100, 100A, 100B, 110, 110A, 110B, 120, 120A, 120B Semiconductor device, 30, 70 Connection region, 31, 71, 91 Transition region, 32, 72, 92 RESURF region, 81, 82 Insulating film, 83 floating field plate, 84 channel stopper region, 85 channel stopper field plate.

Claims (6)

A semiconductor element formed on a first conductivity type semiconductor substrate;
A second conductivity type termination region formed on the semiconductor substrate surrounding the semiconductor element;
The termination region is
In a direction perpendicular to the thickness direction of the semiconductor substrate, a second conductivity type impurity concentration, which is a concentration of a second conductivity type impurity formed in a portion on the outer periphery side of the semiconductor element, is on the outer periphery side of the semiconductor element. A transition region that decreases from the outer periphery of the semiconductor substrate toward the outer peripheral side,
In a direction perpendicular to the thickness direction, the transition region is formed at a portion closer to the outer peripheral portion of the semiconductor substrate, is connected to the transition region, and the second conductivity type impurity concentration is the second conductivity type of the transition region. Including a uniform resurf region that is less than or equal to the minimum impurity concentration,
In the transition region, the amount of change in the second conductivity type impurity concentration per unit length in a direction perpendicular to the thickness direction becomes smaller from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate. A semiconductor device.   2. The semiconductor device according to claim 1, wherein in the transition region, the second conductivity type impurity concentration continuously decreases from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate. . The transition region includes a plurality of impurity regions having a uniform second conductivity type impurity concentration,
The plurality of impurity regions are formed side by side such that the second conductivity type impurity concentration decreases stepwise from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate. The semiconductor device according to claim 1.   In the transition region, the concentration of the second conductivity type impurity gradually decreases from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate, and in a direction perpendicular to the thickness direction of the semiconductor substrate. 4. The semiconductor device according to claim 3, wherein a width of the impurity region includes a region that increases from the outer peripheral side of the semiconductor element toward the outer peripheral side of the semiconductor substrate. An insulating film is provided on one surface of the termination region in the thickness direction of the semiconductor substrate,
The semiconductor element comprises an element electrode provided on one surface in the thickness direction of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the element electrode is provided so as to protrude from an upper portion of the insulating film. A channel stopper region of a first conductivity type or a second conductivity type formed at an end of the outer periphery of the semiconductor substrate surrounding the termination region;
A channel stopper field plate provided on one surface of the channel stopper region in the thickness direction of the semiconductor substrate;
One or more floating field plates provided on the semiconductor substrate between the device electrode and the channel stopper field plate and spaced from the device electrode and the channel stopper field plate. Item 6. The semiconductor device according to Item 5.

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