JP2014038922A - Semiconductor device - Google Patents

Abstract

In a snapback EDS protection element, a hold voltage is made higher than that in the prior art.
In a semiconductor device, a first diffusion layer 11A to which a collector terminal 19A is connected and a second and third diffusion layers 6 and 11B to which a base and an emitter terminal 19B are connected are internally provided. A trench 7 filled with a conductive substance 9 is formed through an insulating film 8. The bottom surface of the trench 7 reaches a position close to the buried diffusion layer 2 or reaches a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried diffusion layer 2.
[Selection] Figure 9

Description

  The present invention relates to a semiconductor device, and is suitably used for, for example, a semiconductor device provided with an electrostatic protection circuit.

  In order to prevent the semiconductor device from being damaged or malfunctioning due to ESD (Electro-Static Discharge), an ESD protection circuit is provided in the semiconductor device. As an ESD protection circuit, a clamp method and a snapback method are known.

  The clamp type ESD protection circuit includes a voltage detection unit configured using a Zener diode or the like, and a MOS (Metal Oxide Semiconductor) transistor. When detecting that a predetermined clamp voltage is applied to the input node, the voltage detector turns on the MOS transistor connected to the input node so that the voltage at the input node does not exceed the clamp voltage.

  The snap-back type ESD protection circuit uses the snap-back characteristic of a MOS transistor in which a gate and a source are connected. When a high voltage is applied between the drain and the source, an avalanche breakdown occurs in the drain-base depletion layer, and a parasitic bipolar transistor formed between the drain and the source is turned on (snapback). As a result, current flows through the ESD protection circuit, so that overvoltage is prevented from being applied to the semiconductor device.

  A trench will be described as another technique related to the present invention. A trench refers to a trench dug on a semiconductor substrate to obtain desired characteristics.

  For example, Japanese Unexamined Patent Application Publication No. 2009-88188 (Patent Document 1) discloses a MOS transistor having a trench gate structure. Specifically, a gate insulating film is formed in a trench formed in the semiconductor layer, and a gate electrode is formed to cover the gate insulating film in the trench.

  Japanese Patent Laying-Open No. 2005-217202 (Patent Document 2) discloses an IGBT (Insulated Gate Bipolar Transistor) in which a lateral MOS transistor and a bipolar transistor are fused. Specifically, an emitter region and a gate electrode having a trench gate structure (first trench) are provided on the surface side of the semiconductor device. A collector region is provided at the bottom of a deep trench comprising the second and third trenches. A plug is drawn from the collector region through the second and third trenches to the surface of the semiconductor device to form a collector electrode.

JP 2009-88188 A JP-A-2005-217202

  The MOS transistor used as the snapback type ESD protection element can reduce the element size as compared with the clamp type. However, the hold voltage, which is the minimum value of the drain voltage after snapback, becomes a relatively low value. For this reason, when a surge voltage is received while the semiconductor device is operating with an external power supply voltage higher than the hold voltage, the ESD protection element is brought into a latch-up state.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

In the semiconductor device according to the embodiment, an insulating film is interposed between the first diffusion layer to which the collector terminal is connected and the second and third diffusion layers to which the base and emitter terminals are connected. A trench filled with a conductive material is formed. The bottom surface of the trench reaches a position close to the buried diffusion layer or reaches a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried diffusion layer.

  According to the above-described embodiment, the hold voltage can be made higher than the conventional one.

It is a circuit diagram which shows the structural example of the ESD protection circuit by a clamp system. It is a circuit diagram which shows the structural example of the ESD protection circuit by a snapback system. FIG. 3 is a plan view showing an example of the configuration of the NMOS transistor of FIG. 2. It is a figure which shows an example of the current voltage characteristic of an NMOS transistor. It is a figure which shows the simulation result of the drain current which flows after snapback in the element structure of FIG. It is sectional drawing which shows the structure of the NPN type bipolar transistor which performed the simulation. FIG. 7 is a diagram showing an impurity concentration profile along the Y direction in the bipolar transistor of FIG. 6. It is a figure which shows the simulation result of a current-voltage characteristic. 3 is a cross-sectional view showing a structure of an ESD protection element provided in the semiconductor device according to the first embodiment. FIG. It is the top view which looked at the ESD protection element shown in FIG. 9 from the direction perpendicular | vertical to a board | substrate. It is a figure which shows the circuit diagram of the ESD protection element of a structure of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is sectional drawing for demonstrating the manufacturing process of the ESD protection element of FIG. It is a figure which shows the simulation result of the drain current which flows after snapback (when the depth of a trench is 6 micrometers). It is a figure which shows the simulation result of a current-voltage characteristic (when the depth of a trench is 6 micrometers). It is a figure which shows the profile of impurity concentration (when the depth of a trench is 6 micrometers). It is sectional drawing which shows the case where the structure of the ESD protection element of FIG. 9 is changed. It is a figure which shows the simulation result of the drain current which flows after snapback (when the depth of a trench is 8.5 micrometers). It is a figure which shows the simulation result of a current-voltage characteristic (when the depth of a trench is 8.5 micrometers). It is a figure which shows the profile of impurity concentration (when the depth of a trench is 8.5 micrometers). It is a figure which shows the profile of impurity concentration (when the depth of a trench is 8 micrometers). It is a figure which shows the relationship between the depth of a trench, and hold voltage. It is a figure which shows the relationship between the distance between the bottom face of a trench, and the high concentration layer of 10 < ¹⁷ > / cm < ³ > or more, and a hold voltage. It is a figure which shows an example of the floor plan of a semiconductor integrated circuit in case the ESD protection element by the clamp system demonstrated in FIG. 1 is provided. FIG. 26 is a diagram illustrating an example of a floor plan of a semiconductor integrated circuit when the ESD protection element of FIG. 9 or FIG. 25 is provided. 5 is a cross-sectional view showing a structure of an ESD protection element provided in a semiconductor device according to a second embodiment. FIG. It is the top view which looked at the ESD protection element shown in FIG. 34 from the direction perpendicular | vertical to a board | substrate. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34. FIG. 35 is a cross-sectional view for explaining a manufacturing step for the ESD protection element of FIG. 34.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
First, problems of the prior art will be described, and then means for solving the problems will be described.

[Problems of conventional technology]
(ESD protection circuit by clamp method)
FIG. 1 is a circuit diagram showing a configuration example of an ESD protection circuit using a clamp method. FIG. 1 shows an example of an ESD protection circuit 910 provided for suppressing a surge voltage flowing into the power supply line 921 of the semiconductor device 900. In addition to the EDS protection circuit 910 shown in FIG. 1, a similar ESD protection circuit is provided for each signal line.

  Referring to FIG. 1, ESD protection circuit 910 is provided between a power supply line 921 that receives power supply voltage VCC from the outside and a ground line 922 that receives ground voltage GND. The ESD protection circuit 910 includes an NMOS (Negative-channel MOS) transistor 914, a plurality of Zener diodes 912A, 912B, 912C, and a resistance element 913. In FIG. 1, one NMOS transistor 914 is typically provided, but in an actual circuit, a plurality of NMOS transistors are provided in parallel.

  Zener diodes 912A, 912B, and 912C are connected in series between the power supply line 921 and the ground line 922 so that the cathode is on the power supply side. NMOS transistor 914 has a drain connected to power supply line 921, a source connected to ground line 922, and a gate connected to a connection node of Zener diodes 912B and 912C. The resistance element 913 is connected between the gate and source of the NMOS transistor 914.

  When a surge voltage exceeding the total of the Zener voltages of the plurality of Zener diodes 912A, 912B, and 912C (hereinafter referred to as “clamp voltage”) is input, the NMOS transistor 914 is turned on. As a result, the input voltage is limited to the clamp voltage or less, so that the internal circuit 920 can be prevented from being damaged or malfunctioning.

  In the ESD protection circuit 910 having the configuration shown in FIG. 1, since a relatively large current flows through the NMOS transistor when the NMOS transistor is turned on, the size of the NMOS transistor has to be increased, which increases the circuit area. There is.

(ESD protection circuit by snap-back method)
FIG. 2 is a circuit diagram illustrating a configuration example of an ESD protection circuit using a snapback method. Referring to FIG. 2, ESD protection circuit 911 includes an NMOS transistor 914 provided between power supply line 921 and ground line 922. The gate and source of the NMOS transistor 914 are connected to each other. In FIG. 2, one NMOS transistor 914 is typically provided, but in an actual circuit, a plurality of NMOS transistors are provided in parallel.

  FIG. 3 is a plan view showing an example of the configuration of the NMOS transistor of FIG. Referring to FIG. 3, a high breakdown voltage lateral NMOS transistor is formed as an ESD protection element on a low-concentration P-type (P−) substrate 1.

  Specifically, a high concentration N type (N +) buried diffusion layer 2 is formed from a low concentration P type (P−) substrate 1 to a low concentration N type (N−) epitaxial layer 3. On the surface side of the N− epitaxial layer 3, an intermediate concentration N-type (N) diffusion layer 4 and an intermediate concentration P-type (P) diffusion layer 6 are formed. A metal wiring layer 19A is connected to the N + diffusion layer 11A formed on the surface side of the N diffusion layer 4 through a contact (tungsten plug 18) penetrating the oxide films 12 and 16. A metal wiring layer 19B is connected to the N + diffusion layer 11B formed on the surface side of the P diffusion layer 6 through a contact. A gate layer 20 is formed on the surface of the P diffusion layer 6 via a gate oxide film. Further, a LOCOS (Lo-Cal Oxidation of Silicon) oxide film 5 is formed for isolation of the diffusion layer, and a trench 13 filled with an insulating material 15 is formed for element isolation.

  In the above configuration, the N− epitaxial layer 3, the N diffusion layer 4, and the N + diffusion layer 11 </ b> A constitute the drain of the NMOS transistor 914. The P diffusion layer 6 constitutes a back gate, and the N + diffusion layer 11B constitutes a source.

  FIG. 4 is a diagram illustrating an example of current-voltage characteristics of the NMOS transistor. A current-voltage characteristic measured by a TLP (Transmission Line Pulsing) method is indicated by a solid line, and a measurement result of a leakage current is indicated by a broken line. The leakage current is displayed as a power of 10. For example, 1 × 10 −9 is displayed as “1E-09”.

  When a snapback voltage Vsb (about 55 V in the case of FIG. 4) is applied as a drain voltage, an avalanche breakdown occurs in a drain-base depletion layer, and as a result, a drain-source parasitic bipolar transistor Turns on. As a result, the drain voltage decreases as the drain current increases (snapback operation).

  In the case of the snapback method, since the parasitic bipolar transistor is turned on, there is a merit that a considerable current can flow even if the area of the element is small. However, the hold voltage VH, which is the minimum value of the drain voltage after snapback, is as low as about 3V. For this reason, when a surge voltage is received while the semiconductor device is operating with an external power supply voltage higher than the hold voltage, the ESD protection element is brought into a latch-up state.

[Method to improve hold voltage]
FIG. 5 is a diagram showing a simulation result of drain current flowing after snapback in the element structure of FIG. In FIG. 5, a P + diffusion layer 10 is provided on the surface of a P diffusion layer 6 used as a back gate. The metal wiring layer 19B is connected to both the N + diffusion layer 11B and the P + diffusion layer 10.

  Referring to FIG. 5, the drain current flow line 30 is concentrated in a relatively shallow region of the N− epitaxial layer 3, and almost no drain current is generated via the buried N + diffusion layer 2. The reason is considered that conductivity modulation occurs because electrons and holes increase rapidly in the N-epitaxial layer 3 after snapback, and as a result, the resistance value of the N-epitaxial layer 3 becomes considerably small.

One method for increasing the hold voltage after snapback is to suppress conductivity modulation. Specifically, it is utilized that conductivity modulation does not occur in a high concentration diffusion layer of 10 ¹⁷ / cm ³ or more. Hereinafter, description will be given with reference to simulation results for the bipolar transistor.

  FIG. 6 is a cross-sectional view showing the structure of a simulated NPN bipolar transistor. The bipolar transistor of FIG. 6 includes an N + diffusion layer 40 used as an emitter, a P diffusion layer 42 used as a base, an N− epitaxial layer 43 and a buried N + diffusion layer 44 used as a collector. The bipolar transistor is further provided with a P + diffusion layer 41 for ohmic connection with the base terminal. N + diffusion layer 40 and P + diffusion layer 41 are connected to emitter terminal 47. The buried N + diffusion layer 44 is connected to the collector terminal 48.

FIG. 7 is a diagram showing an impurity concentration profile along the Y direction in the bipolar transistor of FIG. It is assumed that the impurity concentration in the X direction is uniform. Referring to FIG. 7, solid line impurity concentration profile 31 shows a case where the impurity concentration changes relatively steeply between buried N + diffusion layer 44 and N− epitaxial layer 43 in FIG. 6. Specifically, the impurity concentration of the N + diffusion layer 40 and the P + diffusion layer 41 of FIG. 6 is 10 ¹⁹ / cm ³ , the impurity concentration of the P diffusion layer 42 is 10 ¹⁷ / cm ^3, and the impurity concentration of the N− epitaxial layer 43 is Is 10 ¹⁵ / cm ^3, and the impurity concentration of the buried N + diffusion layer 44 is 10 ¹⁹ / cm ³ .

A broken-line impurity concentration profile 32 shows a case where the impurity concentration changes relatively slowly between the buried N + diffusion layer 44 and the N− epitaxial layer 43 in FIG. 6. Therefore, a relatively high concentration N diffusion layer 45 of 10 ¹⁷ / cm ³ or more is formed in the vicinity of the buried N + diffusion layer 44.

  FIG. 8 is a diagram illustrating a simulation result of current-voltage characteristics. The solid line graph corresponds to the impurity concentration profile 31 of FIG. 7, and the broken line graph corresponds to the impurity concentration profile 32 of FIG.

  Referring to FIG. 8, in the current-voltage characteristics corresponding to the impurity concentration profile 31 in FIG. 7, the hold voltage VH1 after snapback is about 9 V, whereas in the current-voltage characteristics corresponding to the impurity concentration profile 32, The hold voltage VH2 after snapback rises to about 19V. Since the resistance value of the relatively high concentration N diffusion layer 45 in the vicinity of the buried diffusion layer 44 is added to the resistance value between the collector and the emitter, it is considered that the hold voltage becomes high.

[Configuration of ESD protection element]
Based on the simulation results, in the lateral bipolar transistor for an ESD protection element provided in the semiconductor device of the first embodiment, between the N + diffusion layer connected to the collector terminal and the P diffusion layer used as the base. A trench is formed. With such a structure, the current flowing through the buried N + diffusion layer increases, so the hold voltage increases. Hereinafter, a specific element structure will be described.

  FIG. 9 is a cross-sectional view showing the structure of the ESD protection element provided in the semiconductor device according to the first embodiment. Referring to FIG. 9, the ESD protection element is formed on the surface side of N− epitaxial layer 3 formed on P− substrate 1, buried N + diffusion layer 2, and N− epitaxial layer 3 at intervals. N + diffusion layer 11A and P + diffusion layer 6 formed, trench 7 formed between diffusion layers 11A and 6 and P + diffusion layer 10 and N + diffusion layer 11B formed on the surface side of P + diffusion layer 6 Including.

The N− epitaxial layer 3 and the buried N + diffusion layer 2 are used as a collector region of an NPN bipolar transistor. Inside the buried N + diffusion layer 2 is a high concentration layer having an impurity density of 10 ¹⁷ / cm ³ or more. In the high concentration layer, conductivity modulation does not occur even after snapback.

  The N + diffusion layer 11A is formed by implanting, for example, arsenic using the resist pattern formed by the photolithography process as a mask. The N + diffusion layer 11A is provided to improve the ohmic contact in the collector region.

  The P diffusion layer 6 is formed by implanting, for example, boron (boron) using the resist pattern as a mask. The P diffusion layer 6 becomes the base region of the NPN bipolar transistor. The P + diffusion layer 10 is formed by, for example, boron implantation in order to improve the ohmic contact of the base region.

  N + diffusion layer 11B is formed by implanting, for example, arsenic using a resist pattern as a mask. The N + diffusion layer 11B becomes an emitter region of an NPN type bipolar transistor.

The trench 7 is formed from the surface of the N− epitaxial layer 3 toward the buried N + diffusion layer 11 </ b> B (particularly, an internal high concentration layer having an impurity density of 10 ¹⁷ / cm ³ or more). In order to increase the breakdown voltage, the inside of the trench 7 is filled with a conductive substance 9 (for example, polysilicon) through a thin oxide film 8. P + diffusion layer 10 is formed adjacent to trench 7, while N + diffusion layer 11 </ b> B is formed away from trench 7. This is because the trench 7 does not function as a gate.

  The ESD protection element further includes oxide films 5, 12, and 16 stacked on the N-epitaxial layer 3, a LOCOS oxide film 5 for isolating the diffusion layer, an element isolation trench 13, and a metal wiring. Layers 19A and 19B.

  The trench 13 is formed by etching the oxide film 12 using the resist pattern formed by the photolithography process as a mask and etching each semiconductor layer using the etched oxide film 12 as a mask. The trench 13 penetrates the oxide film 12, the LOCOS oxide film 5, the N− epitaxial layer 3, and the buried N + diffusion layer 2 and reaches the inside of the P− substrate 1. Inside the P− substrate 1, a P + diffusion layer 14 is formed by impurity implantation through the trench 13 after the trench 13 is formed. Thereafter, the inside of the trench 13 is filled with an insulating material 15 such as an oxide film.

  The metal wiring layer 19A used as the collector terminal is connected to the N + diffusion layer 11A through the tungsten plug 18. The tungsten plug 18 is formed by forming a contact hole 17 penetrating the oxide films 12 and 16 and then depositing tungsten by a sputtering method. Similarly, the metal wiring layer 19B corresponding to the emitter terminal and the base terminal is connected to the P + diffusion layer 10 and the N + diffusion layer 11B through the tungsten plug 18. In order to increase the breakdown voltage, it is desirable that the polysilicon 9 filled in the trench 7 is also connected to the metal wiring layer 19B via the tungsten plug 18.

  FIG. 10 is a plan view of the ESD protection element shown in FIG. 9 viewed from a direction perpendicular to the substrate. However, FIG. 10 shows only one side across the symmetry line 39. The oxide films 12 and 16, the tungsten plug 18, and the metal wiring layers 19A and 19B in FIG. 9 are not shown.

  Referring to FIGS. 9 and 10, LOCOS oxide film 5 is formed so as to surround N + diffusion layer 11 </ b> A in a plan view from a direction perpendicular to the semiconductor substrate, and trench 7 (oxide) is formed so as to surround LOCOS oxide film 5. A film 8, polysilicon 9) is formed. Further, a P + diffusion layer 10 is formed so as to be in contact with and surround the trench 7, and an N + diffusion layer 11B is formed around the P + diffusion layer 10 with the LOCOS oxide film 5 interposed therebetween. Further, a trench 13 (insulating film 15) is formed so as to surround the N + diffusion layer 11B.

  With the above arrangement, the breakdown voltage of the ESD protection element can be increased. From the viewpoint of breakdown voltage, it is desirable that the corners of the trenches 7 (oxide film 8 and polysilicon 9) be chamfered at an angle of 45 degrees (in the actually manufactured device, the corners are rounded). become).

  FIG. 11 is a diagram showing a circuit diagram of the ESD protection element having the configuration of FIG. Referring to FIG. 11, ESD protection element 110 is formed of an NPN-type bipolar transistor 111 having a gate and an emitter connected to each other. Bipolar transistor 111 has a collector connected to power supply line 121 receiving power supply voltage VCC, and an emitter connected to ground line 122 receiving ground voltage GND. FIG. 11 representatively shows one NPN-type bipolar transistor 111, but in an actual circuit, a plurality of bipolar transistors are provided in parallel. In addition to the EDS protection element 110 illustrated in FIG. 11, a similar ESD protection element is provided for each signal line supplied to the internal circuit 120 of the semiconductor device 100.

  Instead of the NPN bipolar transistor described with reference to FIGS. 9 to 11, a PNP bipolar transistor in which the P type and the N type are interchanged may be used. In this case, the emitter and base are connected to the power supply line 121, and the collector is connected to the ground line 122.

[Method for Manufacturing ESD Protection Element]
Next, a manufacturing method of the ESD protection element (bipolar transistor) having the above configuration will be described. 12 to 21 are cross-sectional views for explaining a manufacturing process of the ESD protection element of FIG.

Referring to FIG. 12, first, the outermost surface of the P-substrate is oxidized by 500 nm to 1000 nm to form a silicon oxide film. The silicon oxide film is etched using the resist pattern formed by the photolithography process as a mask. After removing the resist, 10 ¹⁵ / cm ² or more of antimony or arsenic is implanted using the silicon oxide film as a mask, and then heat treatment at 1100 ° C. or more is performed for 3 hours or more. Thereby, the buried N + diffusion layer 2 is formed.

  Referring to FIGS. 12 and 13, next, after removing the silicon oxide film, N-epitaxial layer 3 is deposited on the outermost surface by 5 μm or more (about 10 μm in the first embodiment). Since the N-type impurity implanted into the P-substrate 1 in the process of forming the N-epitaxial layer 3 is diffused into the N-epitaxial layer 3, the buried N + diffusion layer 2 extends to the N-epitaxial layer 3.

  Referring to FIGS. 13 and 14, next, the outermost surface of N-epitaxial layer 3 is oxidized by 30 nm, and a nitride film is deposited thereon. The nitride film is etched using the resist pattern formed by the photolithography process as a mask. After removing the resist, LOCOS oxide film 5 is formed by performing thermal oxidation at 850 ° C. or higher.

Referring to FIGS. 14 and 15, next, boron is implanted by 7.5 × 10 ¹² / cm ² or more using the resist pattern formed by the photolithography process as a mask. After removing the resist, a P diffusion layer 6 is formed by performing a heat treatment at 1100 ° C. or more for 3 hours or more. Alternatively, the P diffusion layer 6 may be formed by performing multi-stage implantation with ion energy of MeV order.

  Referring to FIGS. 15 and 16, next, trench 7 is formed by etching oxide film 5 and N-epitaxial layer 3 using the resist pattern formed by the photolithography process as a mask. Next, an oxide film 8 is formed on the inner surface of the trench 7 by performing oxidation at 700 ° C. to 900 ° C. Next, after depositing polysilicon, the buried polysilicon layer 9 is formed inside the trench 7 by etching back.

Referring to FIGS. 16 and 17, next, boron or BF ₂ (boron fluoride) is implanted at 1.0 × 10 ¹⁵ / cm ² or more using the resist pattern formed by the photolithography process as a mask. To form the P + diffusion layer 10.

Referring to FIGS. 17 and 18, arsenic is implanted at 1.0 × 10 ¹⁵ / cm ² or more using the resist pattern formed by the photolithography process as a mask. N + diffusion layers 11A and 11B are formed by performing heat treatment after removing the resist.

18 and 19, next, an oxide film 12 is deposited on the outermost surface of the wafer. Subsequently, using the resist pattern formed by the photolithography process as a mask, the oxide films 12 and 5, the epitaxial layer 3, the buried N + diffusion layer 2, and a part of the P− substrate 1 are etched to form the trench 13. . Next, boron is implanted at 1.0 × 10 ¹³ / cm ² or more to form the P + diffusion layer 14. After removing the resist pattern, an oxide film is deposited until the trench 13 is filled and etched back to form an oxide film 15 inside the trench 13.

  Referring to FIGS. 19 and 20, next, an oxide film 16 is deposited on the outermost surface of the wafer. Using the resist pattern formed by the photolithography process as a mask, the deposited oxide film 16 is etched to form a contact hole 17. Thereafter, the resist pattern is removed.

  Referring to FIGS. 20 and 21, next, tungsten 18 is deposited on the outermost surface of the wafer and etched back to fill the inside of the contact hole 17 with tungsten 18.

  Referring to FIGS. 21 and 9, next, a metal (AlSiCu (aluminum / silicon / copper), AuCu, Cu, etc.) is deposited on the outermost surface. Next, metal wiring layers 19A and 19B are formed by etching the deposited metal using the resist pattern formed by the photolithography process as a mask. Thereafter, the ESD protection element shown in FIG. 9 is obtained by removing the resist pattern.

[Operation and Effect of ESD Protection Element According to Embodiment 1]
Referring to FIG. 9 again, a high voltage is applied with the collector terminal (metal wiring layer 19A) as the positive potential and the base and emitter terminals (metal wiring layer 19B) as the ground potential (that is, P diffusion layer 6 and N− A high voltage is applied so that the epitaxial layer 3 is reverse-biased). As a result, a depletion layer spreads in the N− epitaxial layer 3, and a strong electric field is formed near the edge of the bottom of the trench 7. As a result, snapback occurs due to holes generated by impact ionization.

  After snapback, conductivity modulation occurs in the N-epitaxial layer 3 due to holes generated by impact ionization and electrons supplied from the emitter when the NPN bipolar transistor is turned on. The resistance value becomes considerably small (smaller than the resistance value of the buried N + diffusion layer 2). By providing the trench 7 as shown in FIG. 9, a certain proportion of the current flowing between the collector and the emitter after snapback flows through the buried N + diffusion layer 2, so that the hold voltage VH can be made higher than in the prior art. Hereinafter, further detailed description will be given with reference to simulation results.

[Simulation result I: When the trench depth is 6 μm]
FIG. 22 is a diagram showing a simulation result of the drain current flowing after snapback (when the trench depth is 6 μm). FIG. 23 is a diagram showing simulation results of current-voltage characteristics (when the trench depth is 6 μm).

  Referring to FIG. 22, when N− epitaxial layer 3 has a thickness of 9.3 μm, and trench 7 has a depth of 6 μm, a part of collector current is applied to buried N + diffusion layer 2 after snapback. Most of the collector current flows through the N-epitaxial layer 3. For this reason, as shown in FIG. 23, the hold voltage after snapback is about 7.5 V, which is not so increased as compared with the hold voltage (5 V) when the trench 7 is not provided.

FIG. 24 is a diagram showing a profile of impurity concentration (when the trench depth is 6 μm). Referring to FIG. 24, the position in the thickness direction = 0 μm represents the surface of P-substrate 1. The lower end 51 of the trench is at a position of −3.5 μm, and the upper end of the buried N + diffusion layer 2 is at a position of −1.6 μm. The buried N + diffusion layer 2 extends from the N− epitaxial layer 3 to the P− substrate 1. It is considered that conductivity modulation does not occur in a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried N + diffusion layer, but in the case shown in FIG. 24, the distance from the bottom surface of the trench 7 to this high concentration layer is 2 .3 μm wide. For this reason, most of the collector current flows through the N-epitaxial layer 3, and it is considered that the increase of the hold voltage is not sufficient.

[Simulation result II: When the trench depth is 8.5 μm]
If the bottom of the trench 7 reaches a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried N + diffusion layer, all the drain currents pass through this high concentration layer, so that the hold voltage is considered to increase considerably. It is done. Hereinafter, the simulation result in this case will be described.

25 is a cross-sectional view showing a case where the structure of the ESD protection element of FIG. 9 is changed. The ESD protection element of FIG. 25 differs from the structure of FIG. 9 in that the bottom surface of the trench 7 reaches a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried N + diffusion layer 2. Other configurations in FIG. 25 are the same as those in FIG. 9, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

  FIG. 26 is a diagram showing a simulation result of the drain current flowing after snapback (when the trench depth is 8.5 μm). FIG. 27 is a diagram showing simulation results of current-voltage characteristics (when the trench depth is 8.5 μm).

  Referring to FIG. 26, when N− epitaxial layer 3 has a thickness of 9.3 μm, but trench 7 has a depth of 8.5 μm, the bottom surface of trench 7 is located inside buried N + diffusion layer 2. Reach. Therefore, all the collector current flows through the buried N + diffusion layer 2 after snapback. As a result, as shown in FIG. 27, the hold voltage after snapback is about 18.5V, which is sufficiently higher than the hold voltage (5V) when the trench 7 is not provided.

FIG. 28 is a diagram showing a profile of impurity concentration (when the trench depth is 8.5 μm). Referring to FIG. 28, the position in the thickness direction = 0 μm represents the surface of P-substrate 1. The lower end 51 of the trench is at a position of −0.8 μm, and reaches the buried N + diffusion layer 2 (particularly, a high concentration layer of 10 ¹⁷ / cm ³ or more which is considered not to cause conductivity modulation).

[Summary of simulation results]
When the trench depth is between 8.5 μm and 6.0 μm, the hold voltage is 18.5 V corresponding to the depth of 8.5 μm and 7.5 V corresponding to the depth of 6.0 μm. It is thought that it becomes the value between. Therefore, a simulation was also performed when the trench depth was 8.0 μm.

FIG. 29 is a diagram showing a profile of impurity concentration (when the trench depth is 8 μm). Referring to FIG. 29, the position in the thickness direction = 0 μm represents the surface of P-substrate 1. The lower end 51 of the trench is at a position of −1.7 μm, and the upper end of the buried N + diffusion layer 2 is at a position of −1.5 μm. It is considered that conductivity modulation does not occur in a high concentration layer of 10 ¹⁷ / cm ³ or more inside the buried N + diffusion layer, but in the case shown in FIG. 29, the distance from the bottom surface of the trench 7 to this high concentration layer is 0. 0.7 μm, which is relatively short. For this reason, it is considered that the hold voltage becomes relatively high because the collector current flowing through the buried N + diffusion layer 2 increases. As a result of simulation, 9.5 V was obtained as the hold voltage.

  FIG. 30 is a diagram illustrating the relationship between the trench depth and the hold voltage. As shown in FIG. 30, the hold voltage VH increases as the depth of the trench 7 increases.

FIG. 31 is a diagram showing the relationship between the hold voltage and the distance between the bottom of the trench and the high concentration layer of 10 ¹⁷ / cm ³ or more. As shown in FIG. 31, as the distance between the bottom surface of the trench 7 and the high concentration layer of 10 ¹⁷ / cm ³ or more is shortened, the collector current passing through the high concentration layer increases, so the hold voltage VH increases. . In order to prevent latch-up from occurring after snapback, the trench depth (that is, 10 ¹⁷ / cm ³ from the bottom surface of the trench) is set so that the hold voltage VH is higher than the power supply voltage supplied to the semiconductor device. The distance to the above high concentration layer) is adjusted.

  As described above, in the ESD protection element provided in the semiconductor layer according to the first embodiment, by providing the collector layer with the trench 7 that restricts the flow of the collector current, the hold voltage after snapback can be increased more than before. . Furthermore, since the ESD protection is performed by utilizing the snapback characteristic of the bipolar transistor, the area occupied by the ESD protection element can be reduced as compared with the conventional case.

  FIG. 32 is a diagram showing an example of a floor plan of a semiconductor integrated circuit in the case where the clamp type ESD protection element described in FIG. 1 is provided. Referring to FIG. 32, an analog circuit 61, a logic circuit 62, output buffers (output transistors (Tr)) 63A to 63D, and an ESD protection element 910 are formed on a semiconductor chip 60. The ESD protection element 910 is provided corresponding to the output buffers 63A to 63D.

  FIG. 33 is a diagram showing an example of a floor plan of a semiconductor integrated circuit when the ESD protection element of FIG. 9 or FIG. 25 is provided. The exclusive area of the ESD protection element 110 is about 5% in the case of FIG.

<Embodiment 2>
In the second embodiment, an example is shown in which the structure of the ESD protection element described with reference to FIGS. 9 and 25 is changed in order to reduce the number of manufacturing steps.

[Configuration of ESD protection element]
FIG. 34 is a cross-sectional view showing the structure of the ESD protection element provided in the semiconductor device according to the second embodiment. FIG. 35 is a plan view of the ESD protection element shown in FIG. 34 viewed from a direction perpendicular to the substrate.

  The ESD protection elements shown in FIGS. 34 and 35 differ from the ESD protection elements shown in FIGS. 9, 10 and 25 in that trenches 171A and 171B are provided in place of the trenches 7 and 13, respectively.

  The trench 171A is formed in a process immediately before the process of forming the contact hole 17 by depositing the oxide film 12. An oxide film 161 is formed on the inner surface of the trench 171A, and tungsten 181 is buried therein. The tungsten 181 inside the trench 171A is connected to the metal wiring layer 19B.

  The bottom surface of the trench 171B reaches the inside of the P + diffusion layer 24 formed from the P− substrate 1 to the N− epitaxial layer 3. An oxide film 161 is formed on the inner surface of the trench 171B, and tungsten 181 is buried therein. Tungsten 181 inside trench 171B is connected to metal wiring layer 19C.

  The other configurations in FIGS. 34 and 35 are the same as those in FIGS. 9, 10, and 25, and therefore the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

[Method for Manufacturing ESD Protection Element]
Next, a manufacturing method of the ESD protection element (bipolar transistor) configured as shown in FIG. 34 will be described. 36 to 45 are cross-sectional views for explaining a manufacturing process of the ESD protection element of FIG.

Referring to FIG. 36, first, the outermost surface of the P-substrate is oxidized by 500 nm to 1000 nm to form a silicon oxide film. The silicon oxide film is etched using the resist pattern formed by the photolithography process as a mask. After removing the resist, 10 ¹⁵ / cm ² or more of antimony or arsenic is implanted using the silicon oxide film as a mask, and then heat treatment at 1100 ° C. or more is performed for 3 hours or more. Thereby, the buried N + diffusion layer 2 is formed.

Referring to FIGS. 36 and 37, next, the outermost surface of the wafer is oxidized to form a silicon oxide film. The silicon oxide film is etched using the resist pattern formed by the photolithography process as a mask. After removing the resist, boron is implanted at 10 ¹⁴ / cm ² or more using the silicon oxide film as a mask, and then heat treatment at 1100 ° C. or more is performed for 3 hours or more. Thereby, the P + diffusion layer 24 is formed.

  Referring to FIGS. 37 and 38, after removing the silicon oxide film, N-epitaxial layer 3 is deposited on the outermost surface by 5 μm or more. Since the N-type impurity and the P-type impurity implanted into the P-substrate in the formation process of the N-epitaxial layer 3 are diffused into the N-epitaxial layer 3, the buried N + diffusion layer 2 and the P + diffusion layer 24 are N-epitaxial layers. It spreads to three.

  Referring to FIGS. 38 and 39, next, the outermost surface of N-epitaxial layer 3 is oxidized by 30 nm, and a nitride film is deposited thereon. The nitride film is etched using the resist pattern formed by the photolithography process as a mask. After removing the resist, LOCOS oxide film 5 is formed by performing thermal oxidation at 850 ° C. or higher.

Referring to FIGS. 39 and 40, boron is implanted by 7.5 × 10 ¹² / cm ² or more using the resist pattern formed by the photolithography process as a mask. After removing the resist, a P diffusion layer 6 is formed by performing heat treatment at 1100 ° C. or more for 3 hours or more. Alternatively, the P diffusion layer 6 may be formed by performing multi-stage implantation with ion energy of MeV order.

Referring to FIGS. 40 and 41, next, boron or BF ₂ (boron fluoride) is implanted at 1.0 × 10 ¹⁵ / cm ² or more using the resist pattern formed by the photolithography process as a mask. To form the P + diffusion layer 10.

Referring to FIGS. 41 and 42, arsenic is implanted at 1.0 × 10 ¹⁵ / cm ² or more using the resist pattern formed by the photolithography process as a mask. N + diffusion layers 11A and 11B are formed by performing heat treatment after removing the resist.

  Referring to FIGS. 42 and 43, next, oxide film 12 is deposited on the outermost surface of the wafer. Subsequently, using the resist pattern formed by the photoengraving process as a mask, the oxide films 12 and 5, the epitaxial layer 3, a part of the buried N + diffusion layer 2, and a part of the P diffusion layer 24 are etched to etch the trench 171A. , 171B. The bottom surface of the trench 171A reaches the inside of the buried diffusion layer 2, and the bottom surface of the trench 171B reaches the inside of the P diffusion layer 24. After removing the resist, an oxide film 161 is deposited so as to fill the trenches 171A and 171B, and etched back. As a result, the oxide film 161 is formed inside the trenches 171A and 171B. However, since the trenches 171A and 171B are deep, a cavity is formed in the trench.

  Referring to FIGS. 43 and 44, next, oxide film 16 is deposited on the outermost surface of the wafer. Using the resist pattern formed by the photolithography process as a mask, the deposited oxide film 16 is etched to form a contact hole 17. The contact hole 17 formed in the upper part of the trenches 171A and 171B is connected to a cavity inside the trenches 171A and 171B. Thereafter, the resist pattern is removed.

  44 and 45, tungsten 18 is deposited on the outermost surface of the wafer and etched back to fill the contact holes 17 and the trenches 171A and 171B with the tungsten 18.

  45 and 34, a metal (AlSiCu (aluminum / silicon / copper), AuCu, Cu, etc.) is deposited on the outermost surface. Next, the metal wiring layers 19A, 19B, and 19C are formed by etching the deposited metal using the resist pattern formed by the photolithography process as a mask. Thereafter, the ESD protection element shown in FIG. 34 is obtained by removing the resist pattern.

  As described above, according to the ESD protection element provided in the semiconductor device according to the second embodiment, in addition to the effects of the first embodiment, the number of manufacturing steps can be reduced as compared with the case of the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1 P-substrate, 2 buried N + diffusion layer, 3 N-epitaxial layer, 5 LOCOS oxide film, 6 P diffusion layer, 7, 13, 171A, 171B trench, 8, 12, 15, 16, 161 oxide film, 9 poly Silicon layer, 10P + diffusion layer, 11A, 11B N + diffusion layer, 14P + diffusion layer, 17 contact hole, 18,181 tungsten plug, 19A, 19B, 19C metal wiring layer.

Claims (8)

A second conductivity type epitaxial layer formed on the first conductivity type semiconductor substrate;
A first buried diffusion layer of a second conductivity type formed from the semiconductor substrate to the epitaxial layer and having a high concentration layer of 10 ¹⁷ / cm ³ or more inside;
A first conductivity type first diffusion layer and a first conductivity type second diffusion layer formed on the surface side of the epitaxial layer apart from each other;
A first trench formed between the first and second diffusion layers so as to reach the surface or the inside of the high-concentration layer from the surface of the epitaxial layer and filled with a conductive substance through an insulating film. When,
A third diffusion layer of the first conductivity type formed away from the first trench on the surface side of the second diffusion layer;
A first metal wiring layer connected to the first diffusion layer;
A semiconductor device comprising: a second metal wiring layer connected to the second and third diffusion layers. A second conductivity type epitaxial layer formed on the first conductivity type semiconductor substrate;
A first buried diffusion layer of a second conductivity type formed from the semiconductor substrate to the epitaxial layer and having a high concentration layer of 10 ¹⁷ / cm ³ or more inside;
A first conductivity type first diffusion layer and a first conductivity type second diffusion layer formed on the surface side of the epitaxial layer apart from each other;
A first trench formed between the first and second diffusion layers from the surface of the epitaxial layer toward the high-concentration layer and filled with a conductive substance through an insulating film;
A third diffusion layer of the first conductivity type formed away from the first trench on the surface side of the second diffusion layer;
A first metal wiring layer connected to the first diffusion layer;
A second metal wiring layer connected to the second and third diffusion layers,
The semiconductor device, wherein a bottom surface of the first trench and the high concentration layer are formed close to each other. When a voltage that reverse biases the epitaxial layer and the second diffusion layer is applied between the first and second metal wiring layers, the voltage between the first and second metal wiring layers after snapback is reduced. The hold voltage, which is a minimum value, increases as the bottom surface of the first trench approaches the high concentration layer,
The semiconductor device according to claim 2, wherein an interval between a bottom surface of the first trench and the high concentration layer is formed such that the hold voltage is larger than a power supply voltage.   4. The semiconductor device according to claim 1, wherein the conductive material filled in the first trench is connected to the second metal wiring layer. 5. In plan view of the semiconductor substrate, the first trench is formed so as to surround the periphery of the first diffusion layer,
In plan view of the semiconductor substrate, the second diffusion layer is formed to contact and surround the first trench,
4. The semiconductor device according to claim 1, wherein the third diffusion layer is formed so as to surround and surround the first trench when viewed from above the semiconductor substrate. . The semiconductor substrate further includes a second trench that is formed so as to surround the periphery of the semiconductor substrate apart from the third diffusion layer in plan view, and is filled with an insulating material.
The semiconductor device according to claim 5, wherein a bottom surface of the second trench reaches into the semiconductor substrate. A first conductivity type second buried diffusion layer formed from the semiconductor substrate to the epitaxial layer and disposed so as to surround the semiconductor substrate apart from the first buried diffusion layer in plan view; ,
A second trench formed to surround the periphery of the semiconductor substrate apart from the third diffusion layer in plan view, and filled with a conductive material through an insulating film;
A third metal wiring layer connected to the conductive material filled in the two trenches;
The semiconductor device according to claim 5, wherein a bottom surface of the second trench reaches the second buried diffusion layer. The first diffusion layer, the epitaxial layer, and the first buried diffusion layer function as a collector of a bipolar transistor used as an electrostatic protection element,
The second diffusion layer functions as a base of the bipolar transistor;
The semiconductor device according to claim 1, wherein the third diffusion layer functions as an emitter of the bipolar transistor.