JP2014033079A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The reliability of a semiconductor device is improved.
A gate trench TR1 and a gate lead trench TR2 connected to each other are formed on a substrate SUB, and an insulating film GI for a gate insulating film is formed on the inner surface of the trenches TR1 and TR2, and then a trench TR1 is formed. , TR2 are embedded with a laminated film LM having a conductive film CD1, a material film MT thereon, and a conductive film CD2 thereon. A gate electrode GE is formed by the stacked film LM embedded in the trench TR1. Then, after forming an insulating film IL2 over the substrate SUB, contact holes CT1 and CT2 are formed. At this time, on the trench TR2, the insulating film IL2, the conductive film CD2 in the trench TR2, and the material film MT are etched to form the contact hole CT2 exposing the conductive film CD1, but the conductive film CD2 is etched. The material film MT functions as an etching stopper film.
[Selection] Figure 44

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device including a trench gate type MISFET and the semiconductor device.

  A trench gate type MISFET has a structure in which a gate electrode is embedded in a groove dug in a main surface of a semiconductor substrate via a gate insulating film.

  In Japanese Patent Laid-Open No. 2008-085278 (Patent Document 1), a gate electrode polysilicon 11 is formed in a trench 7, and a gate contact recess 19 having a width larger than that of the trench 7 is continuous with the trench 7. A technique is described in which a contact polysilicon 21 is formed and a gate connection hole 25 g is formed on the gate contact polysilicon 21.

  In JP 2007-073757 A (Patent Document 2), after forming the trench 13 in the substrate 1, the oxide film 31, the polysilicon film 32, the insulating film 33, and the polysilicon film 34 are sequentially formed. A technique for filling the trench 13 is described.

  In Japanese Patent Laid-Open No. 2000-299460 (Patent Document 3), a trench 31 is formed, a silicon oxide film 32 to be a gate insulating film is formed, a polysilicon film 33 to be a gate electrode is formed, and CVD oxidation is performed. A technique is described in which the film 35 is formed, the polysilicon film 36 is formed, and the trench 31 is embedded.

  In Japanese Patent Laid-Open No. 2002-37388 (Patent Document 4), a gate pad portion 5a is formed continuously with a gate electrode 5 in a concave groove 12 provided simultaneously with the concave groove 11 for embedding the gate electrode 5, and metal A technique for connecting to a gate wiring 9 made of a film is described.

  Japanese Laid-Open Patent Publication No. 2006-135038 (Patent Document 5) describes a technique in which a gate electrode 107 is embedded in a trench 105 and a contact hole 109g is formed on the gate electrode 107.

JP 2008-085278 A JP 2007-073757 A JP 2000-299460 A Japanese Patent Laid-Open No. 2002-37388 JP 2006-135038 A

  Although there is a semiconductor device provided with a trench gate type MISFET, it is desired to improve the reliability of such a semiconductor device as much as possible.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, when forming a semiconductor device having a trench gate type field effect transistor, a gate groove and a gate extraction groove connected to each other are formed in a semiconductor substrate, and After forming an insulating film for the gate insulating film on the inner surface, the trenches are filled with a laminated film having a first conductive film, a first material film thereon, and a second conductive film thereon. Then, after forming an interlayer insulating film on the semiconductor substrate, a contact hole is formed. At this time, a first contact hole for exposing the first conductive film is formed on the gate lead trench by etching the interlayer insulating film and the second conductive film and the first material film in the gate lead trench. However, the first material film functions as an etching stopper film when the second conductive film is etched.

  According to one embodiment, a gate groove and a gate lead-out groove connected to each other are formed in the semiconductor substrate, and the gate insulating film is interposed in the gate groove. A gate electrode is embedded, and a first conductive film is formed on the inner surface of the gate lead-out groove via a first insulating film. An interlayer insulating film is formed on the semiconductor substrate so as to cover the gate electrode. The first insulating film penetrates the interlayer insulating film on the gate lead-out groove and exposes the first conductive film in the gate lead-out groove. Contact holes are formed. In the first contact hole, a first connecting conductor is buried and electrically connected to the first conductive film. The gate electrode includes a first conductive film formed on the inner surface of the gate groove so as to be in contact with the first insulating film, a first material film on the first conductive film, and a second conductive film on the first material film. The first conductive film and the second conductive film are formed of the same material, and the first material film is formed of a material different from that of the first conductive film and the second conductive film. The first conductive film in the gate groove and the first conductive film in the gate lead-out groove are integrally formed.

  According to one embodiment, the reliability of a semiconductor device can be improved.

1 is an overall plan view of a semiconductor device according to an embodiment; 1 is a partially enlarged plan view of a semiconductor device according to an embodiment; 1 is a partially enlarged plan view of a semiconductor device according to an embodiment; 1 is a partially enlarged plan view of a semiconductor device according to an embodiment; It is principal part sectional drawing of the semiconductor device of one embodiment. It is a partial expanded sectional view of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a process flow figure showing a manufacturing process of a semiconductor device of one embodiment. It is a process flow figure showing a manufacturing process of a semiconductor device of one embodiment. FIG. 9 is a process flow diagram showing a detailed manufacturing process in step S4 in FIG. 8. It is a process flowchart which shows the detailed manufacturing process of step S5 in FIG. FIG. 9 is a process flow diagram showing a detailed manufacturing process in step S9 in FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one Embodiment. FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part plan view of the same semiconductor device as in FIG. 16 in manufacturing process; FIG. 17 is an essential part plan view of the same semiconductor device as in FIG. 16 in manufacturing process; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; It is a partial expanded sectional view of FIG. FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; It is the elements on larger scale of FIG. FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 21 and FIG. 25; FIG. 27 is an essential part cross sectional view of the same semiconductor device as in FIG. 26 during a manufacturing step; It is a partial expanded sectional view of FIG. FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 21 and FIG. 25; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIGS. 26 and 32; FIG. 34 is an essential part plan view of the same semiconductor device as in FIG. 33 in manufacturing process; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 36 is an essential part plan view of the same semiconductor device as in FIG. 35 in manufacturing process; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part plan view of the same semiconductor device as in FIG. 38 in manufacturing process; FIG. 39 is a plan view of relevant parts of another embodiment in the same manufacturing process of the semiconductor device as FIG. 38; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 42 is an essential part cross sectional view of the same semiconductor device as in FIG. 41 during a manufacturing step; It is a partial expanded sectional view of FIG. FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; FIG. 45 is an essential part cross sectional view of the same semiconductor device as in FIG. 44 during a manufacturing step; It is a partial expanded sectional view of FIG. FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 48 is an essential part cross sectional view of the same semiconductor device as in FIG. 47 during a manufacturing step; It is a partial expanded sectional view of FIG. FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 47; FIG. 51 is an essential part cross sectional view of the same semiconductor device as in FIG. 50 during a manufacturing step; It is a partial expanded sectional view of FIG. FIG. 51 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38 and FIG. 50; FIG. 54 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 53; FIG. 55 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 54; FIG. 56 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 55; FIG. 57 is an essential part cross sectional view of the same semiconductor device as in FIG. 56 during a manufacturing step; FIG. 51 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38 and FIG. 50; FIG. 59 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 58; FIG. 57 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 56; FIG. 61 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 60; It is sectional drawing for demonstrating the method of pulling out the gate electrode embedded in the groove | channel on a board | substrate, and connecting to wiring. It is principal part sectional drawing in the manufacturing process of the semiconductor device of an examination example. FIG. 64 is a main-portion cross-sectional view of the semiconductor device of the study example following FIG. 63 during the manufacturing process; FIG. 65 is a main-portion cross-sectional view of the semiconductor device of the study example following FIG. 64 during the manufacturing process; FIG. 66 is a main-portion cross-sectional view of the semiconductor device of the study example following FIG. FIG. 67 is a main-portion cross-sectional view of the semiconductor device of the study example following FIG. 66 during the manufacturing process; FIG. 67 is a partially enlarged cross-sectional view of FIG. 66. FIG. 70 is a main-portion cross-sectional view of the semiconductor device of the study example following FIG. 68 during the manufacturing process;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the mentioned number, and may be more or less than the mentioned number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
<Structure of semiconductor device>
FIG. 1 is an overall plan view of a semiconductor device (semiconductor chip) CP of the present embodiment, FIGS. 2 to 4 are partially enlarged plan views of the semiconductor device CP of FIG. 1, and FIG. It is principal part sectional drawing of this semiconductor device CP. 6 is a partially enlarged cross-sectional view of FIG. FIG. 7 is a cross-sectional view of another main part of the semiconductor device CP of FIG.

  2 to 4 are enlarged views of a region RG1 surrounded by a two-dot chain line in FIG. FIG. 5 corresponds to a cross-sectional view taken along line AA in FIG. FIG. 7 corresponds to a cross-sectional view taken along line BB in FIG.

  2 to 4 show the same planar region (plan view of the region RG1), but FIG. 2 is a plan view showing a planar layout of the trenches TR (TR1, TR2) in the region RG1. 3 is a plan view in which contact holes CT1 and CT2 are added to FIG. 2, and FIG. 4 is a plan view in which wiring M1 (source wiring M1S and gate wiring M1G) is added to FIG. 2 to 4 are plan views, but for the sake of easy understanding, in FIG. 2, the region where the trench TR is formed is hatched, and in FIG. 3, the contact holes CT1 and CT2 are formed. The formed region is hatched. In FIG. 4, the region where the source wiring M1S and the gate wiring M1G are formed is hatched. In FIG. 4, the trench TR is indicated by a solid line, and the ends of the source wiring M1S and the gate wiring M1G are indicated by two-dot chain lines.

  6 shows an enlarged view of the regions RG2 and RG3 surrounded by the alternate long and short dash line in FIG. 5. The right side of FIG. 6 corresponds to the enlarged view of the region RG2 of FIG. Corresponds to an enlarged view of the region RG3 in FIG. However, in FIG. 6, in order to make the drawing easy to see, the barrier conductor film BR and the main conductor film MC <b> 1 constituting the plug PG are simply illustrated as the plug PG without being separated.

  Further, FIG. 1 is a plan view, but the formation region of the source wiring M1S and the gate wiring M1G is hatched, and the source wiring M1S and the gate wiring M1G are exposed. An opening OP3 that forms a bonding pad is indicated by a dotted line. In FIG. 1, a trench TR1 is formed in a mesh shape below the entire source wiring M1S (see FIGS. 2 and 4), and a trench TR2 is formed below the gate wiring M1G along the gate wiring M1G. (See FIGS. 2 and 4), however, the illustration of the trenches TR (TR1, TR2) is omitted in FIG.

  The semiconductor device of the present embodiment is a semiconductor device provided with a trench gate type field effect transistor, for example, a trench gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the semiconductor device of the present embodiment is a semiconductor device including a vertical field effect transistor.

  Hereinafter, the structure of the semiconductor device of this embodiment will be specifically described with reference to FIGS.

As shown in FIGS. 1 to 7, a trench gate type MISFET is formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) SUB. As shown in FIGS. 5 and 7, the substrate SUB includes a substrate body (semiconductor substrate, semiconductor wafer) SB made of n ⁺ type single crystal silicon into which an n type impurity such as arsenic (As) is introduced, for example. And an epitaxial layer (semiconductor layer) EP made of, for example, n ⁻ type single crystal silicon, formed on the main surface of the substrate body SB. Therefore, the substrate SUB is a so-called epitaxial wafer. The substrate body SB and the epitaxial layer EP have the same conductivity type (here, n-type), but the impurity concentration (n-type impurity concentration) of the substrate body SB is greater than the impurity concentration (n-type impurity concentration) of the epitaxial layer EP. The resistivity (specific resistance) of the substrate body SB is lower than the resistivity (specific resistance) of the epitaxial layer EP.

  A trench gate type MISFET is formed in the epitaxial layer EP. The trench gate type MISFET is a MISFET having a trench type gate structure (a gate electrode structure embedded in a groove provided in a substrate).

  The substrate SUB is formed with a trench TR extending from the main surface thereof in the thickness direction of the substrate SUB. The trench TR includes a trench TR1 for forming a trench gate (gate electrode GE) and a trench TR2 for leading out the gate, and the trench TR2 is connected to the trench TR1. The bottom surface of the trench TR does not reach the substrate body SB and is located in the middle of the epitaxial layer EP (in the middle of the depth direction).

The trench TR1 is formed so as to divide the surface layer portion of the epitaxial layer EP into an island shape in a staggered arrangement. In other words, the trench TR1 is formed in a mesh shape on the surface of the epitaxial layer EP. In FIG. 2, the island-shaped epitaxial layer EP (including the p-type semiconductor region PR and the n ⁺ -type semiconductor region NR) surrounded by the trench TR1 is denoted by reference numeral EP1. This is called an island-shaped part EP1. A vertical transistor cell is formed by the island-shaped portion EP1 and the gate electrode GE embedded in the trench TR1 surrounding the island-shaped portion EP1. This vertical transistor cell is formed of a trench gate type MISFET, and this vertical transistor cell is regularly (here, staggered) arranged in the transistor cell region CE in the center of the semiconductor device CP. Yes. The transistor cell region CE is indicated by a two-dot chain line in FIG. 2, but in FIG. 1, almost the entire region where the source wiring M1S is formed is the transistor cell region CE. The vertical transistor cells regularly arranged in the transistor cell region CE are connected in parallel to form an entire transistor (vertical power transistor).

  2 to 4 show a case where the trench TR1 is formed in a mesh shape on the surface of the epitaxial layer EP, and the island portions EP1 surrounded by the trench TR1 are arranged in a staggered arrangement. As a form, the trench TR1 can be formed in a lattice shape on the surface of the epitaxial layer EP, and the island-shaped portions EP1 surrounded by the trench TR1 can be linearly arranged in an array. As another form, the trench TR1 can be formed in a stripe shape on the surface of the epitaxial layer EP.

  In the semiconductor device CP, a source wiring M1S is formed above the entire transistor cell region CE, a gate wiring M1G is formed so as to surround the outer periphery of the transistor cell region CE, and a gate is formed below the gate wiring M1G. A trench TR2 is formed along the wiring M1G. That is, the trench TR2 extends below the gate wiring M1G so as to surround the outer periphery of the transistor cell region CE, but the trench TR2 is connected to the trench TR1. That is, the trench TR1 is formed in a mesh shape in the transistor cell region CE, but extends from the transistor cell region CE to the outside of the transistor cell region CE and is connected to the trench TR2. In other words, the end of the trench TR1 is connected to the trench TR2 outside the transistor cell region CE.

Adjacent to the trench TR1, a p-type semiconductor region (p-type base region) PR is formed as a base region in the epitaxial layer EP. In the epitaxial layer EP, an n ⁺ type semiconductor region (n ⁺ type source region) NR is formed as a source region adjacent to the trench TR1 and above the p type semiconductor region PR. Under the p-type semiconductor region PR is an n ⁻ -type epitaxial layer EP. If the grooves TR1 is formed in a mesh shape, the surface layer to the n ⁺ -type semiconductor region NR of the epitaxial layer EP surrounded by plane by a groove TR1 (i.e. islands EP1) is formed, the n ⁺ -type semiconductor A p-type semiconductor region PR is formed under the region NR, and an n ⁻ type epitaxial layer EP is formed under the p-type semiconductor region PR. The p-type semiconductor region PR is a p-type semiconductor region for a channel region (channel formation region), and the n ⁺ -type semiconductor region NR is an n-type semiconductor region for a source region. The bottom surface of the trench TR is deeper than the bottom surface (bottom surface) of the p-type semiconductor region PR, but does not reach the substrate body SB and is positioned in the middle of the epitaxial layer EP (in the depth direction).

The conductor (here, the conductive film CD1) formed in the trench TR2 is formed integrally with the gate electrode GE embedded in the trench TR1, but does not function as the gate electrode of the MISFET. In EP, a source n-type semiconductor region (here, n ⁺ -type semiconductor region NR) is not formed in a region adjacent to the trench TR2. However, in the epitaxial layer EP, the p-type semiconductor region PR can be formed in a region adjacent to the trench TR2.

  An insulating film GI such as a silicon oxide film is formed on the inner surface (side surface and bottom surface) of the trench TR (TR1, TR2). The insulating film GI is an insulating film for a gate insulating film. The insulating film GI on the inner surface (side surface and bottom surface) of the trench TR1 can function as a gate insulating film of the trench gate type MISFET. The insulating film GI on the inner surface (side surface and bottom surface) of the trench TR2 does not function as the gate insulating film of the MISFET, but the conductor (here, the conductive film CD1) formed in the trench TR2 and the epitaxial layer EP It functions to insulate the gap. A gate electrode GE is buried in the trench TR1 through an insulating film GI (gate insulating film).

  The gate electrode GE is formed by a stacked film LM embedded in the trench TR1. The laminated film LM is a laminated film of a conductive film (conductor film) CD1, a material film MT on the conductive film CD1, and a conductive film (conductor film) CD2 on the material film MT. The conductive film CD1 and the conductive film CD2 are preferably formed of the same material, and particularly preferably a polysilicon film. In the case where the conductive film CD1 and the conductive film CD2 are polysilicon films, a doped polysilicon film into which impurities are introduced is preferable in order to reduce resistance, for example, phosphorus or the like is introduced. The material film MT is preferably a silicon oxide film or a silicon nitride film, and particularly preferably a silicon oxide film.

  The gate electrode GE is formed of a stacked film LM of the conductive film CD1, the material film MT, and the conductive film CD2 embedded in the trench TR1. That is, the gate electrode GE includes the conductive film CD1 formed with a substantially uniform thickness so as to be in contact with the insulating film GI along the inner surface (side surface and bottom surface) of the trench TR1, and the surface (insulating film) of the conductive film CD1. And a conductive film CD2 formed so as to contact the material film MT and fill the trench TR1. In the gate electrode GE, the material film MT is in a state of being interposed between the conductive film CD1 and the conductive film CD2.

  A conductive film CD1 is formed (covered) on the inner surface (side surface and bottom surface) of the trench TR2 via the insulating film GI. For this reason, the inner surface (side surface and bottom surface) of the trench TR2 is covered with the conductive film CD1 having a substantially uniform (uniform) film thickness via the insulating film GI.

  The film thickness of the conductive film CD1 inside the gate lead trench TR2 is substantially uniform (uniform). That is, the thickness T1a of the conductive film CD1 that covers the bottom surface of the trench TR2 via the insulating film GI, and the thickness T1b of the conductive film CD1 that covers the opposite side surfaces of the trench TR2 via the insulating film GI; T1c is substantially the same (that is, T1a≈T1b≈T1c, see FIG. 6). This is because a conductive film CD1 having a substantially uniform film thickness (T1) is formed conformally to the trench TR2 in step S4a described later, and the material film MT functions as an etching stopper film in step S9 described later. This is because the etching of the conductive film CD1 in the trench TR2 is suppressed or prevented, and thereby the uniform thickness of the conductive film CD1 in the trench TR2 is maintained. For this reason, the thicknesses T1a, T1b, and T1c are substantially the same as the formation thickness (T1) of the conductive film CD1 in step S4a described later.

  The upper surface of the gate electrode GE embedded in the trench TR1 and the upper surface of the conductive film CD1 formed in the trench TR2 are more than the upper surface of the epitaxial layer EP outside the trenches TR1 and TR2 (that is, the upper surface of the substrate SUB). It is in a low position. That is, with reference to the upper surface of the substrate SUB, the gate electrode GE in the trench TR1 and the conductive film CD1 in the trench TR2 exist only at a position lower than that. On the upper surface of the epitaxial layer EP (substrate SUB) outside the trenches TR1 and TR2, a film in the same layer as the gate electrode GE (that is, a film integrally connected to the gate electrode GE) does not extend, The conductive film CD1 does not extend. That is, the gate electrode GE and the film formed integrally and continuously with the gate electrode GE are completely embedded in the trench TR, and are formed on the upper surface of the substrate SUB (epitaxial layer EP) outside the trench TR. Is not formed.

  In order to improve the filling property of the trench TR (TR1, TR2), it is preferable that the side surface of the trench TR is tapered (inclined). That is, it is preferable that the trench TR has a taper such that the opening of the trench TR becomes smaller as the depth becomes deeper. The taper angle (corresponding to α in FIG. 16 described later) is preferably 83 to 87 °, and can be, for example, about 85 °.

  On the main surface of the substrate SUB (that is, the main surface of the epitaxial layer EP), an insulating film IL2 is formed so as to cover the gate electrode GE. The insulating film IL2 is an interlayer insulating film, and is made of, for example, a silicon oxide film.

  Contact holes CT1 and CT2 (openings, holes, through holes, connection holes) are formed in the insulating film IL2. The contact hole CT1 is a source contact hole, and the contact hole CT2 is a gate lead-out contact hole.

  In the contact holes CT1, CT2, a conductive plug PG is embedded as a conductor portion (connection conductor portion). Here, the plug PG embedded in the contact hole CT1 is referred to as a plug PG1, and the plug PG embedded in the contact hole CT2 is referred to as a plug PG2. The plug PG includes a barrier conductor film BR made of a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated film thereof on the side surface and the bottom surface, and the inner side of the barrier conductor film BR is made of tungsten. It is composed of body membrane MC1.

  A wiring M1 made of a conductive film is formed on the insulating film IL2 in which the plug PG is embedded. The wiring M1 includes a gate wiring M1G and a source wiring M1S. The gate wiring M1G is formed so as to include the plug PG2 in a plan view, and is in contact with and electrically connected to the plug PG2. The source wiring M1S is in contact with and electrically connected to the plurality of plugs PG1 in the entire transistor cell region CE.

In the transistor cell region CE, the contact hole CT1 is formed above the epitaxial layer EP between the trenches TR1 in plan view, and penetrates through the insulating films IL2 and GI and the n ⁺ type semiconductor region NR to contact hole CT1. Is located in the middle of the thickness direction of the p-type semiconductor region PR. For this reason, the plug PG1 formed in the contact hole CT1 also penetrates the insulating films IL2 and GI and the n ⁺ type semiconductor region NR, and the bottom of the plug PG1 is located in the middle of the thickness direction of the p type semiconductor region PR. ing. Therefore, the plug PG1 is in contact with and electrically connected to both the n ⁺ type semiconductor region NR and the p type semiconductor region PR.

When the trench TR1 is formed in a mesh shape, a contact hole CT1 is formed in each of the epitaxial layers EP (island portions EP1) planarly surrounded by the trench TR1, and the contact hole CT1 is an n ⁺ type semiconductor region. It penetrates NR and reaches the middle in the thickness direction of the p-type semiconductor region PR. In the transistor cell region CE, a plurality of island portions EP1 surrounded by the trench TR1 are arranged, and a contact hole CT1 is provided for each of the island portions EP1, so that the contact hole CT1 is formed in the transistor cell region CE. Is formed. The plug PG1 embedded in the plurality of contact holes CT1 formed in the transistor cell region CE is electrically connected to the common source wiring M1S.

The source wiring M1S is electrically connected to the n ⁺ type semiconductor region NR and the p ⁺ type semiconductor region PR of the transistor cell region CE through the plug PG1. That is, the source n ⁺ type semiconductor region NR and the p ⁺ type semiconductor region PR therebelow are electrically connected to the source wiring M1S through the plug PG1.

  The contact hole CT2 is formed on the trench TR2, and is formed in a strip shape along the extending direction of the trench TR2. The contact hole CT2 and the plug PG2 embedded therein are formed at a position included in the trench TR2 in plan view, but the plug PG2 is in contact with the conductive film CD1 in the trench TR2 and is electrically connected thereto. Yes. The plug PG2 electrically connects the conductive film CD1 in the trench TR2 and the gate wiring M1G located immediately above the trench TR2.

  A part of the plug PG2 is located inside the groove TR2. That is, the plug PG2 is formed at a position included in the trench TR2 in plan view, and the bottom of the plug PG2 is located at a position lower than the upper surface of the substrate SUB (epitaxial layer EP) outside the trench TR2. The inner surface (side surface and bottom surface) of the trench TR2 is covered with the conductive film CD1 having a substantially uniform (uniform) film thickness via the insulating film GI as described above. A plug PG2 is in contact with CD1 and is electrically connected. That is, the inner surface (side surface and bottom surface) of the trench TR2 is covered with the conductive film CD1 having a substantially uniform film thickness via the insulating film GI, and the inside (the groove whose inner surface is covered with the insulating film GI and the conductive film CD1). The interior of TR2 is filled with plug PG2. Since the conductive film CD1 is interposed between the insulating film GI formed on the inner surface (side surface and bottom surface) of the trench TR2 and the plug PG2, the plug PG2 is not in contact with the insulating film GI.

  Further, as can be seen from FIG. 7, the conductive film CD2 and the conductive film CD1 are electrically connected through the plug PG2. This is a contact hole when viewed in a cross section (corresponding to a cross section taken along line BB in FIG. 2, ie, a cross section in FIG. 7) passing through the connecting portion between the trench TR2 and the trench TR1 and extending in the extending direction of the trench TR1. This is because a part of the conductive film CD2 is exposed on the side surface of the CT2, and the exposed conductive film CD2 is in contact with the plug PG2. That is, the conductive film CD2 and the conductive film CD1 are not in direct contact with each other because the material film MT is interposed therebetween, but the plug PG2 is in contact with both the conductive film CD2 and the conductive film CD1. Therefore, the conductive film CD2 and the conductive film CD1 are electrically connected via the plug PG2. For this reason, the conductive film CD1 and the conductive film CD2 constituting the gate electrode GE are also electrically connected to each other. For this reason, even if the material film MT is interposed between the conductive film CD1 and the conductive film CD2 constituting the gate electrode GE, it is possible to suppress or prevent the gate resistance from increasing.

  Gate wiring M1G is electrically connected to conductive film CD1 covering the inner surface (side surface and bottom surface) of trench TR2 through plug PG2. The conductive film CD1 constituting the gate electrode GE embedded in the trench TR1 is formed integrally with the conductive film CD1 covering the inner surface (side surface and bottom surface) of the trench TR2. Further, as described above, the plug PG2 is also in contact with and electrically connected to the conductive film CD2. For this reason, the gate wiring M1G is electrically connected to the gate electrode GE embedded in the trench TR1 through the conductive film CD1 covering the plug PG2 and the inner surface (side surface and bottom surface) of the trench TR2.

  As shown in FIGS. 5 and 7, the wiring M1 (the gate wiring M1G and the source wiring M1S) is covered with an insulating film IL3 for surface protection. That is, the insulating film IL3 is formed on the insulating film IL2 so as to cover the wiring M1 (the gate wiring M1G and the source wiring M1S). This insulating film IL3 is the uppermost film (insulating film) of the semiconductor device.

  As shown in FIGS. 1, 5, and 7, a plurality of openings OP3 are formed in the insulating film IL3, and a part of the wiring M1 is exposed from each opening OP3. The wiring M1 exposed from the opening OP3 serves as a bonding pad (pad electrode). That is, the source bonding pad is formed by the source wiring M1S exposed from the opening OP3 (opening OP3 for forming the source bonding pad in the opening OP3) formed in the insulating film IL3. The A gate bonding pad is formed by the gate wiring M1G exposed from the opening OP3 (opening OP3 for forming the gate bonding pad of the opening OP3) formed in the insulating film IL3. The

  A drain electrode back surface electrode (back surface drain electrode) BE is formed on the entire back surface of the substrate SUB (that is, the back surface of the substrate body SB). The back electrode BE can be formed by, for example, a laminated film of a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer in order from the back surface of the substrate SUB.

  In the substrate SUB, the main surface opposite to the side on which the epitaxial layer EP is formed is referred to as the back surface of the substrate SUB. In the substrate body SB, the main surface opposite to the side on which the epitaxial layer EP is formed is referred to as the back surface of the substrate body SB. For this reason, the back surface of the substrate SUB and the back surface of the substrate body SB are the same.

In the semiconductor device having such a configuration, the operating current of the trench gate type MISFET formed in the transistor cell region CE is generated between the drain epitaxial layer EP and the source n ⁺ type semiconductor region NR through the gate electrode GE. It flows in the thickness direction of the substrate SUB along the side surface (that is, the side surface of the trench TR1). That is, the channel is formed along the thickness direction of the substrate SUB. Of the p-type semiconductor region PR, the region adjacent to the gate electrode GE via the insulating film GI (gate insulating film), that is, the trench TR1 between the n ⁺ -type semiconductor region NR and the n ⁻ -type epitaxial layer EP. The region along the line becomes a channel formation region (channel layer).

  For this reason, the trench gate type MISFET formed in the transistor cell region CE is also a vertical MISFET (vertical field effect transistor). Here, the vertical MISFET corresponds to a MISFET in which a current between the source and the drain flows in the thickness direction of the semiconductor substrate (here, the substrate SUB) (a direction substantially perpendicular to the main surface of the semiconductor substrate).

In order to pass a current through the trench gate type MISFET, a voltage higher than V _th (channel inversion voltage, threshold voltage) is applied from the gate bonding pad to the gate electrode GE via the gate wiring M1G and the like. . Thus, the source wiring M1S, the source region (n-type semiconductor region NR), the channel layer, the epitaxial layer EP (drain region), and the substrate body SB are interposed between the source bonding pad and the back electrode BE. , Current can flow. That is, by applying a predetermined voltage between the gate electrode GE and the source wiring M1S so that the gate electrode GE has a high potential, the p-type semiconductor region PR facing the gate electrode GE via the insulating film GI is applied. A channel is formed, and a current flows between the drain region (epitaxial layer EP and substrate body SB) and the source region (n ⁺ type semiconductor region NR) through the channel.

<About semiconductor device manufacturing process>
Next, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. 8 and 9 are process flow diagrams showing the manufacturing process of the semiconductor device of the present embodiment. FIG. 10 is a process flow diagram showing the detailed manufacturing process of step S4 in FIG. FIG. 11 is a process flow diagram showing the detailed manufacturing process of step S5 in FIG. FIG. 12 is a process flow diagram showing the detailed manufacturing process of step S9 in FIG. 13 to 61 are principal part cross-sectional views or principal part plan views during the manufacturing process of the semiconductor device. 13, FIG. 18, FIG. 34, FIG. 36, FIG. 39 and FIG. 40 are plan views, and a plan view of a region corresponding to FIG. 2 is shown. 13 to 61, FIGS. 19 to 33, 35, 37, 38, and 41 to 61 are cross-sectional views. 13 to 16, 19, 21, 23 to 26, 29 to 33, 35, 37, 38, 41, 44, 47, 50, 53 to 56 and 58 to 61 show a cross section (cross section taken along line AA) corresponding to FIG. 5 described above. 27, FIG. 42, FIG. 45, FIG. 48, FIG. 51, and FIG. 57 show cross sections (cross sections taken along line BB) corresponding to FIG. FIGS. 20, 22, 28, 43, 46, 49, and 52 are partially enlarged sectional views corresponding to FIG.

  To manufacture the semiconductor device of the present embodiment, first, as shown in FIG. 13, a semiconductor substrate (hereinafter simply referred to as a substrate) SUB is prepared (step S1 in FIG. 8).

The substrate (semiconductor substrate, semiconductor wafer) SUB is on the main surface of the substrate body SB, which is a semiconductor substrate (semiconductor wafer) made of n ⁺ type single crystal silicon into which an n type impurity such as arsenic (As) is introduced. Further, for example, an epitaxial layer EP made of n ⁻ type single crystal silicon into which an n type impurity such as phosphorus (P) is introduced can be epitaxially grown. The substrate SUB is a so-called epitaxial wafer. The impurity concentration (n-type impurity concentration) of the substrate body SB is higher than the impurity concentration (n-type impurity concentration) of the epitaxial layer EP, and the resistivity (specific resistance) of the substrate body SB is the resistance of the epitaxial layer EP. Lower than the rate (specific resistance).

  Next, a trench (trench) TR is formed in the main surface of the substrate SUB (step S2 in FIG. 8). The trench TR includes a trench (trench, gate trench, gate trench, gate electrode trench) TR1 for forming a trench gate (gate electrode GE) and a gate lead-out trench (trench, contact trench) TR2. Contains. That is, the trench TR1 is a trench for embedding the gate electrode, and the trench TR2 is a trench for pulling out the gate directly above (directly above the trench TR2) and connecting it to the wiring. The groove TR2 is connected to the groove TR1.

  Specifically, the trench TR (TR1, TR2) can be formed as follows, for example.

  First, as shown in FIG. 14, the insulating film IL1 is formed over the substrate SUB (on the entire main surface of the substrate SUB). The insulating film IL1 is made of, for example, a stacked film of a silicon nitride film SN1 and a silicon oxide film SO1 over the silicon nitride film SN1. Each of the silicon nitride film SN1 and the silicon oxide film SO1 can be formed by, for example, a CVD (Chemical Vapor Deposition) method. Then, a photoresist pattern (resist pattern, mask layer) RP1 is formed on the insulating film IL1 using a photolithography technique. The photoresist pattern RP1 has an opening in the region where the trench TR is to be formed. Then, the silicon oxide film SO1 is etched (for example, dry etching) using the photoresist pattern RP1 as an etching mask, thereby selectively removing the silicon oxide film SO1 in the region where the trench TR is to be formed. Then, the photoresist pattern RP1 is removed. Since the silicon oxide film SO1 has an opening in the region where the trench TR is to be formed, the silicon nitride film SN1 and the epitaxial layer EP are etched using the silicon oxide film SO1 as an etching mask (hard mask). By performing (for example, dry etching), as shown in FIG. 15, trenches TR (TR1, TR2) are formed in the epitaxial layer EP. Thereafter, as shown in FIG. 16, the insulating film IL1 (silicon oxide film SO1 and silicon nitride film SN1) is removed by etching (for example, wet etching) or the like. In this way, the trench TR (TR1, TR2) can be formed.

  As another form, the epitaxial layer EP is etched (for example, dry etching) using a photoresist pattern (a photoresist pattern similar to the photoresist pattern RP1) formed on the substrate SUB by using a photolithography technique as an etching mask. ), The trench TR (TR1, TR2) can also be formed.

  17 and 18 are main part plan views of the semiconductor device in the same process stage as FIG. 16, and the same plane area as that of FIG. 2 is shown. FIGS. 17 and 18 are plan views of the same region. In order to facilitate understanding of the trench TR formation region, FIG. 17 shows a region where the trench TR (that is, the trench TR1 and the trench TR2) is formed. In FIG. 18, the hatched area of the trench TR2 is hatched. 18, the layout of the trench TR2 can be easily understood, and the layout of the trench TR1 can be easily understood by comparing FIG. 17 with FIG. FIG. 16 corresponds to a cross-sectional view taken along line AA in FIG.

  The trench TR1 is formed so as to divide the surface layer portion of the epitaxial layer EP into an island shape in a staggered arrangement. In other words, the trench TR1 is formed in a mesh shape on the surface of the epitaxial layer EP (each mesh portion has a staggered arrangement). As another form, the trench TR1 can be formed in a lattice shape, or the trench TR1 can be formed in a stripe shape.

  As can be seen from FIG. 2, FIG. 17, and FIG. 18, the trench TR1 is formed in a mesh shape (or lattice shape or stripe shape) in the entire transistor cell region CE, and the trench TR2 is formed in the transistor cell region CE. It extends so as to surround the outer periphery, and the trench TR2 is connected to the trench TR1. That is, the trench TR1 extends from the transistor cell region CE to the outside of the transistor cell region CE and is connected to the trench TR2, that is, the end of the trench TR1 is connected to the trench TR2 outside the transistor cell region CE. ing.

  The trench gate trench TR1 and the gate lead trench TR2 are formed by the same process (the same etching process). For this reason, the depth of the trench gate trench TR1 and the depth of the gate lead trench TR2 are substantially the same. The depth of the trench TR (TR1, TR2) can be, for example, about 0.6 μm to 6 μm, and can be exemplified by about 1.0 μm.

  The depth of trench TR1 for trench gate is deeper than the bottom (junction surface) of p-type semiconductor region PR to be formed later, and from the bottom of epitaxial layer EP (that is, the interface between epitaxial layer EP and substrate body SB). Is a shallower dimension. That is, the trench TR does not penetrate the epitaxial layer EP, and the epitaxial layer EP remains under the trench TR.

  The width W2 of the gate lead trench TR2 is equal to or greater than the width W1 of the trench gate trench TR1 (that is, W2 ≧ W1). Here, the width W2 of the trench TR2 corresponds to a width (dimension) in a direction parallel to the main surface of the substrate SUB (and hence the main surface of the epitaxial layer EP) and perpendicular to the extending direction of the trench TR2. Further, the width W1 of the trench TR1 corresponds to the width (dimension) in the direction parallel to the main surface of the substrate SUB (and hence the main surface of the epitaxial layer EP) and perpendicular to the extending direction of the trench TR1.

  The width W2 of the gate lead trench TR2 is equal to or greater than the width W1 of the trench gate trench TR1 (that is, W2 ≧ W1), but the width W2 of the gate lead trench TR2 is equal to the width of the trench gate trench TR1. If it is about 1 to 2 times W1 (that is, W1 ≦ W2 ≦ W1 × 2), the ratio of the width W2 to the width W1 is suitable. For example, the width W1 of the trench gate trench TR1 can be about 0.5 μm, and the width W2 of the gate lead trench TR2 can be about 1.0 μm.

  Further, if the width W1 of the trench TR1 is excessively increased, it is disadvantageous for downsizing (reducing the area) of the semiconductor device. If the width W2 of the trench TR2 is excessively decreased, the contact hole CT2 is formed on the trench TR2. It becomes difficult. Therefore, the width W2 of the trench TR2 is larger than the width W1 of the trench TR1 (that is, W2) from the viewpoint of securing the width W2 of the trench TR2 that can form the contact hole CT while suppressing the width W1 of the trench TR1 to some extent. > W1) is more preferable. For this reason, it is more preferable that the width W2 of the trench TR2 is greater than 1 time and less than or equal to 2 times the width W1 of the trench TR1 (that is, W1 <W2 ≦ W1 × 2).

  Further, in the case of the examination examples described later (FIGS. 63 to 69), the smaller the width of the trench TR202 described later, the more the insulating film GI201 on the inner surface of the trench TR202 is exposed and etching damage may occur when the contact hole CT202 is formed. Increases nature. However, in the present embodiment, as will be described in detail later, the material film MT functions as an etching stopper when forming the contact hole CT2, so that the contact hole CT2 is formed on the inner surface of the trench TR2 in the etching process for forming the contact hole CT2. The insulating film GI can be prevented from being exposed. Therefore, in the present embodiment, the width W2 of the trench TR2 can be reduced while preventing the insulating film GI on the inner surface of the trench TR2 from being exposed from the contact hole CT2, and the width W2 of the trench TR2 is reduced to the trench TR2. It is also possible to make it less than twice the width W1 of TR1 (that is, W2 ≦ W1 × 2).

  Further, in order to improve the embedding property of the trench TR (the embedding property of the trench TR by the laminated film LM to be formed later), the trench TR is formed so that the side surface (side wall) of the trench TR has a taper (inclination). It is preferable. That is, the side surface (side wall) of the trench TR is inclined so that the opening of the trench TR becomes smaller as the depth becomes deeper (in other words, the opening of the trench TR becomes larger as the depth becomes shallower). It is preferable. Therefore, the angle (taper angle) α formed between the main surface of the substrate SUB (that is, the main surface of the epitaxial layer EP) and the side surface of the trench TR is smaller than 90 ° (that is, α <90 °, that is, α is An acute angle). The angle α is preferably less than 90 °, but is particularly preferably 83 to 87 °, and can be about 85 °, for example. Further, since the trench TR1 and the trench TR2 are formed in the same process, the taper (inclination) angle α of the side surface (side wall) is substantially the same in the trench TR1 and the trench TR2.

  By providing a taper on the side surface of the trench TR (TR1, TR2), the embedding property of the laminated film LM in the trench TR (TR1, TR2) can be improved when the laminated film LM is formed later. Furthermore, since the side surface of the trench TR2 has a taper, and the contact hole CT2 is formed in the groove TR2 having this taper, the contact hole CT2 in the portion in the trench TR2 is also tapered. The embedding property of the conductive film (main conductor film MC1) for the plug PG2 can also be improved.

As a method for providing a taper on the side surface (side wall) of the trench TR, for example, a method of etching using a reactive gas containing carbon (for example, CBrF ₃ ) can be used (the epitaxial layer EP is etched by this etching method). Groove TR is formed). In this method, carbon synthesizes organic matter (organic matter deposit) in plasma and deposits on the side surface of the trench (TR) to act as an etching mask. As the etching progresses, the side surface of the trench (TR) is obtained. A taper (inclination) is formed. When there is much carbon, taper (inclination) will become large. The method of providing a taper (inclination) on the side surface (side wall) of the trench TR is not particularly limited to this, and various methods can be selected. For example, after the trench TR is opened in the epitaxial layer EP using the etching mask, isotropic etching is performed so as to recede the vicinity of the peripheral edge of the opening of the trench TR in the etching mask, and then the etching mask is used. A taper (inclination) may be formed on the side surface (side wall) of the trench TR by a method of etching the epitaxial layer EP by CDE (Chemical Dry Etching).

  Further, after the formation of the trench TR and before the removal of the insulating film IL1, a sacrificial oxide film (not shown) is formed on the inner surface (side surface and bottom surface) of the trench TR by heat treatment in an oxygen atmosphere (for example, heat treatment at about 1100 ° C.). It is more preferable to perform a step of removing the sacrificial oxide film after the growth (for example, removal by wet etching). Thereby, etching damage at the time of forming the trench TR can be removed, and the corner of the opening of the trench TR and the corner of the bottom of the trench TR can be rounded.

  Next (that is, after the formation of the trench TR and after the removal of the insulating film IL1), as shown in FIGS. 19 and 20, the inner surface (side surface) of the trench TR (TR1, TR2), for example, using a thermal oxidation method or the like. An insulating film GI made of a relatively thin silicon oxide film or the like is formed on the upper surface and the bottom (step S3 in FIG. 8). This insulating film GI is an insulating film for a gate insulating film. The insulating film GI formed on the inner surface (side surface and bottom surface) of the trench TR1 will later become the gate insulating film of the trench gate type MISFET.

  In step S3, the insulating film GI is formed on the inner surface (side surface and bottom surface) of the trench TR (TR1, TR2) and the upper surface where the epitaxial layer EP is exposed. For this reason, when the insulating film GI is formed in step S3, the inner surfaces (side surfaces and bottom surface) of the trench TR (TR1, TR2) are covered with the insulating film GI. The thickness of the insulating film GI can be about 30 nm, for example.

  Next, as shown in FIGS. 21 and 22, a laminated film LM is formed on the main surface (entire main surface) of the substrate SUB so as to fill the trench TR (TR1, TR2) (FIG. 8). Step S4).

  The laminated film LM is a laminated film of a conductive film (conductor film) CD1, a material film MT, and a conductive film (conductor film) CD2. In the laminated film LM, the lowermost layer is the conductive film CD1, the uppermost layer is the conductive film CD2, and the material film MT is interposed between the conductive film CD1 and the conductive film CD2. That is, the stacked film LM includes the conductive film CD1, the material film MT on the conductive film CD1, and the conductive film CD2 on the material film MT.

  The step S4 of forming the laminated film LM includes sub-steps S4a, S4b, and S4c shown in FIG. That is, after performing the process up to step S3 to obtain the structure of FIG. 19, first, as shown in FIG. 23, the conductive film (conductor film) CD1 is formed on the main surface (main surface) of the substrate SUB. (Step S4a in FIG. 10). Then, as shown in FIG. 24, a material film MT is formed on the main surface (entire main surface) of the substrate SUB, that is, on the conductive film CD1 (step S4b in FIG. 10). Then, as shown in FIG. 25, a conductive film (conductor film) CD2 is formed on the main surface (entire main surface) of the substrate SUB, that is, on the material film MT (step S4c in FIG. 10). By these steps S4a, S4b, and S4c, a laminated film LM composed of the conductive film CD1, the material film MT, and the conductive film CD2 is formed. The stage of FIG. 25 in which the conductive film CD2 forming step of step S4c is performed corresponds to the stage of FIG. That is, the structure of FIG. 25 is the same as the structure of FIG.

  The conductive film CD1 and the conductive film CD2 are preferably formed of the same material. More preferably, each of the conductive film CD1 and the conductive film CD2 is a silicon film such as a polysilicon film (polycrystalline silicon film), and an impurity (for example, an n-type impurity) is introduced to have a low resistivity. Yes. Therefore, it is particularly preferable that both the conductive film CD1 and the conductive film CD2 are doped polysilicon films. The introduction of impurities (for example, phosphorus) into the conductive films CD1 and CD2 is preferably performed by adding a doping gas to the deposition gas when forming the conductive films CD1 and CD2.

  The material film MT is a film made of a material different from those of the conductive films CD1 and CD2. That is, the material film MT is made of a material different from that of the conductive film CD1, and the material film MT is made of a material different from that of the conductive film CD2. The material film MT is preferably formed of a material that can ensure an etching selectivity with respect to the conductive films CD1 and CD2. When the conductive film CD1 and the conductive film CD2 are both silicon films (polysilicon films), the material film MT is preferably a silicon oxide film or a silicon nitride film, and particularly preferably a silicon oxide film.

  In step S4a, the conductive film CD1 is formed (see FIG. 23). In this step S4a, the conductive film CD1 is formed on the main surface of the substrate SUB in which the trench TR is formed, and therefore only on the upper surface of the epitaxial layer EP. In addition, the conductive film CD1 is also formed on the sidewall and the bottom of the trench TR. However, since the insulating film GI is formed in step S3 before step S4a, the insulating film GI is interposed between the conductive film CD1 and the epitaxial layer EP. That is, in step S4a, the conductive film CD1 is formed on the upper surface of the epitaxial layer EP and the inner surface (side surface and bottom surface) of the trench TR via the insulating film GI.

  In step S4a, the conductive film CD1 is formed, but the gate lead trench TR2 is not completely filled with the conductive film CD1. That is, in step S4a, the thickness (deposited film thickness) T1 of the conductive film CD1 and the width W2 of the trench TR2 are set so that the trench TR2 for extracting the gate is not completely filled with the conductive film CD1. Here, the thickness of the gate insulating film GI on the side surface of the trench TR2 after the gate insulating film GI is formed in the trench TR2 is Tg, and the opening of the trench TR2 after the gate insulating film GI is formed in the trench TR2. The width (opening width) is W2g. At this time, W2g = W2-Tg × 2. Using this definition, the thickness (deposited film thickness) T1 of the conductive film CD1 is made smaller than half of the width W2g of the trench TR2 (that is, T1 <W2g × 1/2).

  In step S4a, by making the thickness T1 of the conductive film CD1 smaller than half of the width W2g of the trench TR2, the conductive film CD1 conforms to the shape of the trench TR2 (with respect to the trench TR2). The conductive film CD1 is formed on the inner surface (side surface and bottom surface) of the trench TR2 via the insulating film GI, but the trench TR2 is not completely filled with the conductive film CD1.

  That is, as shown in FIG. 23, the conductive film CD1 having a thickness of T1 is formed on the bottom surface and the side surfaces SW1 and SW2 of the trench TR2. However, by setting T1 <W2g × 1/2, the trench TR2 is formed. In the width direction, the surface of the conductive film CD1 formed on one side surface SW1 of the trench TR2 and the surface of the conductive film CD1 formed on the other side surface SW2 of the trench TR2 do not stick (no contact). ). As a result, the trench TR2 is not completely filled with the conductive film CD1. Here, the side surface SW1 and the side surface SW2 of the trench TR2 are side surfaces facing each other. The width direction of the trench TR2 is a measurement direction of the width W2, and corresponds to a direction parallel to the main surface of the substrate SUB (and hence the main surface of the epitaxial layer EP) and perpendicular to the extending direction of the trench TR2. doing.

  Further, since the conductive film CD1 is formed conformally with respect to the trench TR2, it is deposited on the inner surface (side surface and bottom surface) of the trench TR2 with a substantially uniform (uniform) thickness. Since the conductive film CD1 is formed with a substantially uniform thickness on the inner surface (side surface and bottom surface) of the trench TR2, when the conductive film CD1 is formed in step S4a, the portion of the conductive film CD1 formed on the side surface of the trench TR2 is formed. Is substantially parallel to the side surface of the trench TR2. Therefore, when the side surface of the trench TR2 has a taper and the taper angle is α, the surface of the conductive film CD1 formed on the side surface of the trench TR2 is also the main surface of the substrate SUB (that is, the epitaxial surface). It is inclined with respect to the main surface of the layer EP, and the inclination angle is substantially the same as α (the taper angle of the side surface of the trench TR2).

  When the conductive film CD1 is formed in step S4a, a recess (recess, groove) RS1 that is a portion where the conductive film CD1 is not formed is formed in the trench TR2 (that is, between the side surface SW1 and the side surface SW2 of the trench TR2). Will exist. That is, the conductive film CD1 (the conductive film CD1 having a thickness of T1) is formed in the region adjacent to the side surface SW1 of the trench TR2, the region adjacent to the side surface SW2 of the trench TR2, and the region adjacent to the bottom surface of the trench TR2. The conductive film CD1 is not formed in the central portion between the side surface SW1 and the side surface SW2 of the trench TR2.

  As described above, since the thickness T1 of the conductive film CD1 is insufficient to fill the trench TR2, the trench TR2 is not completely buried at the stage where step S4a is performed.

  Since the trench TR2 is not completely filled with the conductive film CD1 in step S4a, when the material film MT is formed in step S4b, the material film MT is not only the upper portion of the conductive film CD1 on the upper surface of the epitaxial layer EP but also the trench. It is also formed on the conductive film CD1 on the inner surface (side surface and bottom surface) of TR.

  In step S4b, the material film MT is formed, but the trench TR2 for extracting the gate is not completely filled with the conductive film CD1 and the material film MT. That is, in steps S4a and S4b, the total thickness (deposited film thickness) T2 of the conductive film CD1 and the material film MT so that the gate lead trench TR2 is not completely filled with the conductive film CD1 and the material film MT. And the width W2 of the trench TR2.

  Specifically, the total thickness T2 of the conductive film CD1 and the material film MT is made smaller than half of the width W2g of the trench TR2 (W2g = W2-Tg × 2 here) (that is, T2 <W2g × 1). / 2). In this way, the conductive film CD1 and the material film MT are formed conformally (conformally with respect to the trench TR2) reflecting the shape of the trench TR2, and conductive on the inner surface (side surface and bottom surface) of the trench TR2. Although the stacked film of the film CD1 and the material film MT is formed through the insulating film GI, the trench TR2 is not completely filled with the stacked film LM1 of the conductive film CD1 and the material film MT. Here, the laminated film of the conductive film CD1 and the material film MT is referred to as a laminated film LM1. The total thickness T2 of the conductive film CD1 and the material film MT is obtained by adding the thickness (deposition thickness) of the material film MT to the thickness T1 of the conductive film CD1.

  That is, as shown in FIG. 24, the laminated film LM1 having a thickness of approximately T2 is formed on the bottom surface of the trench TR2 and on the side surfaces SW1 and SW2, but by setting T2 <W2g × 1/2, In the width direction of the trench TR2, the surface of the laminated film LM1 formed on one side surface SW1 of the trench TR2 and the surface of the laminated film LM1 formed on the other side surface SW2 of the trench TR2 do not stick (contact). No longer). For this reason, the trench TR2 is not completely filled with the laminated film LM1.

  When the conductive film CD1 and the material film MT are formed in Steps S4a and S4b, the conductive film CD1 and the material film MT are not formed in the trench TR2 (that is, between the side surface SW1 and the side surface SW2 of the trench TR2). A certain depression (recess, groove) RS2 exists. That is, the laminated film LM1 (a laminated film LM1 having a thickness of approximately T2) is formed in a region adjacent to the side surface SW1 of the trench TR2, a region adjacent to the side surface SW2 of the trench TR2, and a region adjacent to the bottom surface of the trench TR2. However, the conductive film CD1 and the material film MT are not formed in the central portion between the side surface SW1 and the side surface SW2 of the trench TR2.

  Thus, since the thickness T2 of the laminated film LM1 is insufficient to fill the trench TR2, the trench TR2 is not completely buried at the stage where Steps S4a and S4b are performed.

  In steps S4a and S4b, the trench TR2 is not completely filled with the conductive film CD1 and the material film MT, but in step S4c, the conductive film CD2 is formed so as to be completely filled in the trench TR2. That is, at the stage where the conductive film CD1 and the material film MT are formed in steps S4a and S4b, the trench TR (TR1, TR2) is not completely filled. When the conductive film CD2 is formed in step S4c, the trench TR (TR1, TR1) is formed. TR2) is completely filled.

  Therefore, in steps S4a, S4b, and S4c, the conductive film CD1 and the material film MT are formed so that the gate lead trench TR2 is completely filled with the laminated film LM of the conductive film CD1, the material film MT, and the conductive film CD2. A total thickness (deposited film thickness) T3 with the conductive film CD2 and a width W2 of the trench TR2 are set.

  Specifically, the total thickness T2 of the conductive film CD1 and the material film MT is made smaller than half the width W2g of the trench TR2 (W2g = W2−Tg × 2), and the conductive film CD1 and the material film The total thickness T3 of the MT and the conductive film CD2 is set to be more than half of the width W2g of the trench TR2 (that is, T2 <W2g × 1/2 ≦ T3). Thus, the conductive film CD1 and the material film MT are formed conformally to the trench TR2, and the trench TR1 is not completely filled at the stage where the conductive film CD1 and the material film MT are formed. When CD2 is formed, the trench TR2 is completely filled with the laminated film LM of the conductive film CD1, the material film MT, and the conductive film CD2. Here, the total thickness T3 of the conductive film CD1, the material film MT, and the conductive film CD2 is obtained by adding the thickness (deposition thickness) of the conductive film CD2 to the total thickness T2 of the conductive film CD1 and the material film MT. .

  That is, as shown in FIG. 25, by setting T2 <W2g × 1/2 ≦ T3, in the width direction of the trench TR2, the surface of the conductive film CD2 deposited on one side surface SW1 of the trench TR2 and the trench The surface of the conductive film CD2 deposited on the other side surface SW2 of TR2 is attached (contacted) and integrated, so that the trench TR2 is a laminated film LM of the conductive film CD1, the material film MT, and the conductive film CD2. Will be completely buried.

  When the conductive film CD1 and the material film MT are formed in steps S4a and S4b, the depression RS2 is present in the trench TR2 (that is, between the side surface SW1 and the side surface SW2 of the trench TR2), but in step S4c When the conductive film CD2 is formed, the recess RS2 is filled with the conductive film CD2. That is, the laminated film LM is embedded between the side surface SW1 and the side surface SW2 of the trench TR2, and the conductive film CD2 exists in the center portion between the side surface SW1 and the side surface SW2 of the trench TR2.

  Thus, since the thickness T3 of the laminated film LM is sufficient to fill the trench TR2, the conductive film CD1, the material film MT, and the conductive film CD2 are contained in the trench TR2 when the steps S4a, S4b, and S4c are performed. Embedded in the laminated film LM.

  As a preferred example of step S4, the case where steps S4a, S4b, and S4c are performed in one continuous LPCVD (Low Pressure Chemical Vapor Deposition) process including condition change will be specifically described below.

First, as shown in FIG. 23, as shown in FIG. 23, as the conductive film CD1, the conductive film CD1 has a predetermined phosphorus content by LPCVD using a mixed gas of monosilane (SiH ₄ ) and phosphine (PH ₃ ) as a source gas. For example, a doped polysilicon film having a thickness of about 150 nm is formed. Thereby, the inner surface (side surface and bottom surface) of the trench TR (TR1, TR2) is covered with the doped polysilicon film (conductive film CD1) having a uniform film thickness.

  Subsequently, by supplying oxygen gas of a predetermined concentration (to the chamber of the film forming apparatus) during the LPCVD process, the material is formed on the doped polysilicon film as the conductive film CD1 as shown in FIG. As the film MT, for example, a thin silicon oxide film (mask oxide film) of about 50 mm (50 angstroms) is formed. The film thickness of the silicon oxide film as the material film MT is set to an appropriate film thickness to serve as an etching stopper later. The film thickness of the silicon oxide film as the material film MT can be controlled by the oxygen gas supply time.

  In this way, a silicon oxide film (material film MT) that later functions as an etching stopper film (etching mask) can be formed in self-alignment with the trench TR (TR1, TR2), and the trench TR (TR1, TR2). There is no need to allow for a margin of misalignment with respect to.

  In addition, in order to form a silicon oxide film as the material film MT on the doped polysilicon film as the conductive film CD1, it is only necessary to supply / stop oxygen gas during the LPCVD process. There is no need to provide a process for forming (etching mask).

  When a thin silicon oxide film (mask oxide film) as the material film MT can be formed, the oxygen supply (to the chamber of the film forming apparatus) is stopped, and subsequently, as shown in FIG. A doped polysilicon film as the conductive film CD2 is formed on the silicon oxide film as the film MT. The doped polysilicon film as the conductive film CD2 has the same phosphorus concentration as the doped polysilicon film as the conductive film CD1, completely fills the inside of the trench TR (TR1, TR2), and then further has a substrate. A certain thickness is deposited on the surface.

  Thus, the lower doped polysilicon film (conductive film CD1) and silicon oxide film (material film MT), and the upper doped polysilicon film (conductive film CD2) are embedded in the trench TR (TR1, TR2). ) Is formed (laminated film LM). In this way, steps S4a, S4b, and S4c can be continuously performed in the same manufacturing apparatus (film forming apparatus) by changing the film forming conditions (changing the gas introduced into the film forming apparatus).

  That is, by providing a period in which oxygen gas is mixed with the film forming gas in the middle of the film forming process of the doped polysilicon film by the CVD method (here LPCVD method), the oxygen gas is mixed with the film forming gas. When not, doped polysilicon films (conductive films CD1, CD2) are formed, and when an oxygen gas is mixed with the film forming gas, a silicon oxide film (material film MT) is formed. Thereby, a laminated film (LM) having a configuration in which the silicon oxide film (material film MT) is sandwiched between the doped polysilicon films (conductive films CD1, CD2) can be formed.

  As described above, in the state where the substrate SUB is disposed in the same film forming apparatus, the step of forming the conductive film CD1 (step S4a), and oxygen gas is supplied (added) during the film formation to form the conductive film CD1. A step of forming an oxide film (material film MT) on the surface (step S4b) and a step of forming the conductive film CD2 of the same material as the conductive film CD1 by stopping the supply of oxygen and continuing the film formation (step S4c) ) Can be performed continuously. Thus, the trench TR (TR1, TR2) is filled with the gate electrode film (here, the laminated film LM) without increasing the number of manufacturing steps and the manufacturing time, and the gate electrode film is contacted later. A film (here, the material film MT) that can function as an etching stopper when forming the hole CT2 can be included.

  Further, if the doped polysilicon film as the conductive film CD1 and the doped polysilicon film as the conductive film CD2 are made to have the same type and concentration of impurities, the conductive film CD1 and the conductive film CD1 will be described in step S5c described later. It becomes easy to make the etching rate of the conductive film CD2 the same. Further, if the doped polysilicon film as the conductive film CD1 and the doped polysilicon film as the conductive film CD2 have the same kind and concentration of the doped impurities, switching between steps S4a, S4b, and S4c is performed. Can be easily performed by switching the oxygen gas, and the laminated film LM having the structure in which the material film MT is sandwiched between the conductive films CD1 and CD2 can be formed easily and accurately.

  Next (that is, after forming the laminated film LM), the laminated film LM is etched (etched back) to remove the laminated film LM outside the trench TR as shown in FIGS. The laminated film LM is left inside (step S5 in FIG. 8).

  In step S5, the laminated film LM is etched back using anisotropic etching, so that the conductive film CD2, the material film MT, and the conductive film CD1 on the substrate SUB are sequentially etched and removed, and the trench TR The external laminated film LM is removed, and the laminated film LM remains in the trench TR.

  Step S5 has substeps of steps S5a, S5b, and S5c shown in FIG.

  By performing the etching process of step S5 by the sub-steps of steps S5a, S5b, and S5c, the progress of the etching in step S5 proceeds more evenly over the entire main surface of the substrate SUB. The etching in step S5a, the etching in step S5b, and the etching in step S5c can be switched by changing the etching gas. Therefore, the etching in step S5a, the etching in step S5b, and the etching in step S5c can be performed continuously while changing the etching gas.

  In the etching in step S5a, the etching in step S5b, and the etching in step S5c, the etching gas is changed in consideration of the etching selectivity between the conductive films CD1 and CD2 and the material film MT.

  Hereinafter, steps S5a, S5b, and S5c will be described in detail.

  That is, after performing step S4 to obtain the structure of FIG. 21 (that is, the structure of FIG. 25), first, as shown in FIG. 29, the conductive film CD2 is etched (step S5a of FIG. 11).

  In this step S5a, etching is performed under conditions (etching conditions) such that the etching rate of the conductive film CD2 is higher (faster) than the etching rate of the material film MT. Since the material film MT is formed of a material different from that of the conductive film CD2, the etching selectivity of the conductive film CD2 with respect to the material film MT can be ensured.

  In step S5a, the etching of step S5a is terminated when the conductive film CD2 is etched and the material film MT is exposed. As a result, the conductive film CD2 remains in the trench TR. That is, in step S5a, the conductive film CD2 outside the trench TR is removed, and the conductive film CD2 in the trench TR remains. In step S5a, dry etching is preferably used as etching, and anisotropic dry etching is more preferable.

  The height position of the upper surface of the conductive film CD2 remaining after step S5a is preferably higher than the upper surface of the epitaxial layer EP (the upper surface of the region where the trench TR is not formed), and the trench TR is formed. It is preferable that the upper surface of the conductive film CD1 on the epitaxial layer EP in the non-existing region is substantially at the same height position. Note that the height or height position refers to a height or height position in a direction perpendicular to the main surface of the substrate SUB.

  Subsequently, the material film MT exposed by etching the conductive film CD2 in step S5a is etched as shown in FIG. 30 (step S5b in FIG. 11).

  It is preferable that the value obtained by dividing the etching rate of the conductive films CD1 and CD2 by the etching rate of the material film MT is smaller in step S5b than in steps S5a and S5c. That is, in steps S5a and S5c, the etching selectivity of the conductive films CD1 and CD2 with respect to the material film MT is high. In contrast, in step S5b, the etching selectivity of the conductive films CD1 and CD2 with respect to the material film MT is low. It is preferable to adjust the etching conditions. Since the material film MT is formed of a material different from that of the conductive films CD1 and CD2, the etching selectivity of the conductive films CD1 and CD2 with respect to the material film MT can be adjusted as described above. In step S5b, dry etching is preferably used as etching, and anisotropic dry etching is more preferable.

  In step S5b, the etching of step S5b is terminated when the material film MT is etched and the conductive film CD1 is exposed. As a result, the conductive films CD1 and CD2 and the material film MT remain in the trench TR. That is, the etching of step S5b removes the material film MT outside the trench TR to expose the conductive film CD1 outside the trench TR, and the conductive films CD1 and CD2 and the material film MT remain in the trench TR.

  In step S5b, not only the material film MT but also the conductive film CD1 can be removed. However, as described above, in step S5b compared to steps S5a and S5c, the material film MT is etched in step S5b by lowering the etching selectivity of the conductive films CD1 and CD2 with respect to the material film MT. It is possible to suppress or prevent the conductive film CD2 from being excessively etched. As a result, the upper surface of the conductive film CD2 remaining after step S5b can be approximately at the same height as the upper surface of the conductive film CD1.

  Subsequently, the conductive film CD1 exposed by etching the material film MT in step S5b and the remaining conductive film CD2 are etched as shown in FIG. 31 (step S5c in FIG. 11).

  In step S5c, etching is preferably performed so that the etching rates of the conductive film CD1 and the conductive film CD2 are substantially the same. This can be easily realized by forming the conductive film CD1 and the conductive film CD2 from the same material. For example, by forming both the conductive film CD1 and the conductive film CD2 from a polysilicon film (doped polysilicon film), the etching rates of the conductive film CD1 and the conductive film CD2 can be made substantially the same. . In step S5c, dry etching is preferably used as etching, and anisotropic dry etching is more preferable.

  In step S5c, the conductive film CD1 outside the trench TR is removed, and the conductive films CD1 and CD2 and the material film MT between the conductive films CD1 and CD2 are left in the trench TR. It is preferable that the height positions of the upper surfaces of the conductive films CD1 and CD2 remaining in the trench TR after step S5c are substantially the same. This can be realized by making the etching rates of the conductive film CD1 and the conductive film CD2 substantially the same in step S5c. In addition, the height position of the upper surfaces of the conductive films CD1 and CD2 remaining in the trench TR after step S5c is preferably lower than the upper surface of the epitaxial layer EP.

  As described above, for the stacked film LM (conductive film CD1, material film MT, and conductive film CD2) in a region that does not overlap the trench TR in plan view, the conductive film CD2 is removed in step S5a, and the material film MT is changed in step S5b. The conductive film CD1 is removed in step S5c. On the other hand, for the laminated film LM (conductive film CD1, material film MT and conductive film CD2) in the region overlapping with the trench TR in plan view, a part of the conductive film CD2 is removed in step S5a, and in step S5b, the material film MT and Part of the conductive film CD2 is removed, and part of the conductive films CD1 and CD2 is removed in step S5c.

  Although the case where the etching conditions are changed in steps S5a, S5b, and S5c has been described here, as another embodiment, steps S5a, S5b, and S5c are continuously performed without changing the etching conditions, and the layer outside the trench TR is stacked. It is also possible to remove the film LM and leave the laminated film LM in the trench TR. In this case, since the material film MT is thinner than the conductive films CD1 and CD2, it is preferable to employ conditions (etching conditions) such that the etching rate of the conductive films CD1 and CD2 is higher than the etching rate of the material film MT.

Further, when a polysilicon film is used for the conductive films CD1 and CD2 and a silicon oxide film is used for the material film MT, each etching in steps S5a, S5b, and S5c is performed using Cl ₂ gas, HBr gas, and O ₂ gas. Dry etching using a mixed gas can be used. The etching selection ratio of the doped polysilicon film (conductive films CD1, CD2) to the silicon oxide film (material film MT) can be adjusted by the mixing ratio of Cl ₂ gas in this mixed gas. Specifically, a doped polysilicon film (conductive film CD1) with respect to a silicon oxide film (material film MT) is increased by increasing the mixing ratio of Cl ₂ gas in a mixed gas of Cl ₂ gas, HBr gas, and O ₂ gas. , CD2) can be increased in etching selectivity. For this reason, steps S5a, S5b, and S5c can be performed continuously by switching the mixing ratio of the Cl ₂ gas. Note that when the etching selectivity of the doped polysilicon film (conductive films CD1, CD2) to the silicon oxide film (material film MT) is lowered, a mixed gas of Cl ₂ gas, HBr gas, and O ₂ gas is used. In dry etching, the mixing ratio of Cl ₂ gas can be made zero.

  In step S3, not only the inner surface (side surface and bottom surface) of the trench TR (TR1, TR2) but also the upper surface of the epitaxial layer EP (upper surface of the epitaxial layer EP where the trench TR is not formed) are insulated. A film GI is formed. Therefore, when the conductive film CD1 outside the trench TR (TR1, TR2) is removed by etching in step S5c, the insulating film GI on the upper surface of the epitaxial layer EP outside the trench TR (TR1, TR2) is exposed. . At this time, it is preferable that the insulating film GI is left in layers on the epitaxial layer EP so that the upper surface (Si surface) of the epitaxial layer EP outside the trench TR (TR1, TR2) is not exposed. Thereby, it is possible to prevent the upper surface (Si surface) of the epitaxial layer EP from being exposed and being damaged by etching in step S5c. From this viewpoint, it is preferable to perform the etching in step S5c under conditions (etching conditions) such that the etching rate of the insulating film GI is smaller (slower) than the etching rates of the conductive films CD1 and CD2. As a result, in step S5c, the insulating film GI formed on the surface of the epitaxial layer EP can function as an etching stopper film outside the trench TR (TR1, TR2), and the epitaxial layer EP is exposed in step S5c. Thus, etching can be prevented.

  In addition, after step S5c, as shown in FIG. 31, a part of the material film MT may protrude upward from the upper surfaces (surfaces) of the conductive films CD1 and CD2 remaining in the trench TR. This may occur when the etching in step S5c is performed under the condition that the etching rate of the conductive films CD1 and CD2 is higher than the etching rate of the material film MT, and the etching is anisotropic. In this case, after step S5c (and before step S6 described later), as shown in FIG. 32, the material film of the portion (protruding portion) protruding from the upper surface of the conductive films CD1 and CD2 remaining in the trench TR. It is more preferable if MT is removed by wet etching or the like. Thereby, the flatness of the insulating film IL2 to be formed later can be improved. The process step in FIG. 32 corresponds to the process step in FIG. That is, the structure of FIG. 32 is the same as the structure of FIG. As another form, when the flatness of the insulating film IL2 is not emphasized, the material film MT of the portion (protruding portion) protruding from the upper surface of the conductive films CD1 and CD2 remaining in the trench TR is removed as shown in FIG. It is also possible to leave it after that.

  Thus, by performing step S5 (S5a, S5b, S5c), the laminated film LM outside the trench TR is removed, and the laminated film LM is left in the trench TR. That is, when step S5 is performed, as shown in FIGS. 26 to 28, the laminated film LM is embedded in the trench TR (TR1, TR2) via the insulating film GI. The insulating film GI remaining in the trench TR1 becomes a gate insulating film, and the stacked film LM remaining in the trench TR1 becomes a gate electrode GE. That is, the laminated film LM embedded in the trench TR1 via the insulating film GI serves as the gate electrode GE, and the insulating film GI interposed between the inner surface (side surface and bottom surface) of the trench TR1 and the gate electrode GE It becomes a gate insulating film. Therefore, the gate electrode GE is in a state of being buried in the trench TR1 via the gate insulating film (insulating film GI). Further, the insulating film GI and the laminated film LM remain in the trench TR2. That is, the laminated film LM is embedded in the trench TR2 via the insulating film GI. The laminated film LM remaining in the trench TR2 after step S5 (that is, the laminated film LM embedded in the trench TR2 via the insulating film GI) is hereinafter referred to as a laminated film LM2 with reference numeral LM2. .

  Since the gate electrode GE embedded in the trench TR1 and the stacked film LM2 embedded in the trench TR2 are formed in the same process, as shown in FIG. The upper surface UPS1 of the embedded gate electrode GE and the upper surface UPS2 of the stacked film LM2 embedded in the trench TR2 have substantially the same height.

As shown in FIG. 28, the upper surface UPS1 of the gate electrode GE embedded in the trench TR1 and the upper surface UPS2 of the stacked film LM2 embedded in the trench TR2 recede from the upper surface UPS3 of the epitaxial layer EP (high). Is preferable). That is, in step S5, the upper surface (UPS1, UPS2) of the laminated film LM (that is, the gate electrode GE and the laminated film LM2) remaining in the trench TR (TR1, TR2) is slightly lower than the upper surface UPS3 of the epitaxial layer EP. It is preferable to etch back the laminated film LM. In Figure 28, when the upper surface UPS2 laminated films LM2 embedded in the upper surface UPS1 and grooves TR2 gate electrode GE embedded in the groove TR1 is lower by a distance _{L 1} from the upper surface UPS3 of the epitaxial layer EP is It is shown. Here, it is assumed that the side closer to the back surface of the substrate SUB is low and the side far from the back surface of the substrate SUB is high. The reason for this is to prevent etching residues of the conductive films CD1 and CD2 constituting the stacked film LM from remaining on the epitaxial layer EP outside the trench TR when step S5 is completed.

  If an unnecessary etching residue of the conductive film exists on the epitaxial layer EP outside the trench TR, there is a possibility that a defect due to this conductive etching residue occurs. For this reason, it is desirable to prevent an unnecessary etching residue of the conductive films CD1 and CD2 constituting the stacked film LM from remaining on the epitaxial layer EP outside the trench TR when Step S5 is completed. Therefore, in step S5c, the conductive films CD1 and CD2 are slightly over-etched, so that unnecessary etching residues of the conductive films CD1 and CD2 constituting the stacked film LM are formed on the epitaxial layer EP outside the trench TR. It is preferable to prevent it from remaining. In such a case, the height of the upper surface UPS1 of the gate electrode GE embedded in the trench TR1 and the height of the upper surface UPS2 of the stacked film LM2 embedded in the trench TR2 are inevitably lower than the upper surface UPS3 of the epitaxial layer EP.

  Therefore, after step S5, the upper surface UPS1 of the gate electrode GE embedded in the trench TR1 is at a position lower than the upper surface UPS3 of the epitaxial layer EP in the region outside the trench TR1 and adjacent to the trench TR1, and The upper surface UPS2 of the laminated film LM2 embedded in the trench TR2 is at a position lower than the upper surface UPS3 of the epitaxial layer EP in the region adjacent to the trench TR2 outside the trench TR2. After step S5, the laminated film LM does not extend on the upper surface UPS3 of the epitaxial layer EP outside the trenches TR1 and TR2. That is, after step S5, the film integrally connected to the gate electrode GE (here, the laminated film LM) exists inside the trench TR (TR1, TR2), but outside the trench TR1, TR2. The epitaxial layer EP is not formed on the upper surface. Therefore, after step S5, the gate electrode GE and the film formed integrally and continuously with the gate electrode GE are completely embedded in the trench TR, and the substrate SUB (epitaxial) outside the trench TR. It is not formed on the upper surface of the layer EP). Note that the upper surface of the epitaxial layer EP can also be regarded as the upper surface of the substrate SUB.

However, even when the upper surface UPS2 laminated films LM2 embedded in the upper surface UPS1 and grooves TR2 gate electrode GE embedded in the groove TR1 is lower by a distance _{L 1} from the upper surface UPS3 of the epitaxial layer E, the the distance L ₁ is less than n ⁺ -type semiconductor region depth NR (thickness) to be formed later. That is, the upper surface UPS1 of the gate electrode GE is positioned higher than the bottom surface (lower surface) of the n ⁺ type semiconductor region NR that will be formed later. Accordingly, when a predetermined voltage is applied to the gate electrode GE to invert the channel, the side surface (that is, the groove) of the gate electrode GE is interposed between the source n ⁺ type semiconductor region NR and the drain epitaxial layer EP. A current can be accurately passed along the side surface of TR1.

  In addition, since the trench TR2 is connected to the trench TR1, the laminated film LM embedded in the trench TR2 (that is, the laminated film LM2) and the laminated film LM embedded in the trench TR1 (that is, the gate electrode GE) are integrally formed. Formed and connected. That is, the conductive film CD1 constituting the gate electrode GE embedded in the trench TR1 is integrally formed with and connected to the conductive film CD1 constituting the stacked film LM2 embedded in the trench TR2. The conductive film CD2 constituting the buried gate electrode GE is formed integrally with the conductive film CD2 constituting the laminated film LM2 buried in the trench TR2. Further, the material film MT in the gate electrode GE embedded in the trench TR1 is integrally formed and connected to the material film MT in the stacked film LM2 embedded in the trench TR2.

  Next, as shown in FIGS. 33 and 34, a p-type semiconductor region (p-type base region) is formed by ion-implanting a p-type impurity (for example, boron (B)) into the main surface of the substrate SUB. ) PR is formed (step S6 in FIG. 8). The p-type semiconductor region PR is a p-type semiconductor region for a channel region, and is formed in the epitaxial layer EP. The depth (depth position of the bottom portion) of the p-type semiconductor region PR is shallower than the depth (depth position of the bottom portion) of the trench TR1.

  FIG. 34 is a plan view of the principal part of the semiconductor device in the same process stage as FIG. 33, and shows the same plane area as FIG. 34 is a plan view, but in order to facilitate understanding of the p-type semiconductor region PR formation region, in FIG. 34, the region where the p-type semiconductor region PR is formed is hatched.

  In step S6, a region of the epitaxial layer EP where the p-type impurity is not desired to be implanted is previously covered with an ion implantation blocking mask (not shown) such as a photoresist pattern, and the ion implantation blocking mask is used as a mask. A p-type impurity may be ion-implanted into the epitaxial layer EP. This ion implantation blocking mask is removed after the ion implantation in step S6.

Next, as shown in FIGS. 35 and 36, an n ⁺ type semiconductor region (n ⁺ type) is formed by ion-implanting an n type impurity (for example, arsenic (As)) into the main surface of the substrate SUB. Source region) NR is formed (step S7 in FIG. 8). The n ⁺ type semiconductor region NR is an n type semiconductor region for the source region, and is formed in the epitaxial layer EP. The depth (bottom depth position) of the n ⁺ -type semiconductor region NR is shallower than the depth (bottom depth position) of the p-type semiconductor region PR. The impurity concentration (n-type impurity concentration) of the n ⁺ -type semiconductor region NR is higher than the impurity concentration (n-type impurity concentration) of the n ⁻ -type epitaxial layer EP.

FIG. 36 is a plan view of the principal part of the semiconductor device in the same process stage as FIG. 35, and shows the same plane area as FIG. FIG. 36 is a plan view, but in order to facilitate understanding of the n ⁺ type semiconductor region NR formation region, in FIG. 36, the region where the p type semiconductor region PR is formed and the n ⁺ type semiconductor region NR are formed. Each region is hatched in a different direction. In FIG. 36, a p-type semiconductor region PR exists under the n ⁺ -type semiconductor region NR formation region.

  In step S7, a region in the epitaxial layer EP where the n-type impurity is not desired to be implanted is previously covered with an ion implantation blocking mask (not shown) such as a photoresist pattern, and the ion implantation blocking mask is used as a mask. An n-type impurity may be ion-implanted into the epitaxial layer EP. This ion implantation blocking mask is removed after the ion implantation in step S7.

After performing ion implantation for forming the p-type semiconductor region PR and ion implantation for forming the n ⁺ -type semiconductor region NR in steps S6 and S7, heat treatment (activation annealing) can also be performed. Thereby, diffusion and activation of impurities introduced by ion implantation can be performed.

In this way, in the region adjacent to the trench TR1 in the substrate SUB (epitaxial layer EP), the n ⁺ type semiconductor region NR for source and the p type semiconductor region PR located under the n ⁺ type semiconductor region NR are formed. It is formed.

When the p-type semiconductor region PR and the n ⁺ -type semiconductor region NR are formed in the epitaxial layer EP in steps S6 and S7, as shown in FIG. 35, the p-type semiconductor region PR is brought into contact with the p-type semiconductor region PR. n ⁺ -type state semiconductor region NR is formed, in other words, the a state of the p-type semiconductor region PR is formed in contact with the n ⁺ -type semiconductor region NR under the n ⁺ -type semiconductor region NR. Therefore, when viewed in the thickness direction of the substrate SUB, the p-type semiconductor region PR is formed on the n ⁻ -type epitaxial layer EP, and the n ⁺ -type semiconductor region NR is formed on the p-type semiconductor region PR. . That is, on the n ⁻ type epitaxial layer EP, a stacked structure of the p type semiconductor region PR and the n ⁺ type semiconductor region NR (a stack of the p type semiconductor region PR and the n ⁺ type semiconductor region NR on the p type semiconductor region PR). (Structure) is formed.

The n ⁺ type semiconductor region NR has a function as a source region of the trench gate type MISFET and can be regarded as a semiconductor region for the source, while the p type semiconductor region PR is a channel of the trench gate type MISFET. It functions as a formation region. Since the stacked structure of the p-type semiconductor region PR and the n ⁺ -type semiconductor region NR is formed shallower than the trench TR1, the trench TR1 penetrates the stacked structure of the p-type semiconductor region PR and the n ⁺ -type semiconductor region NR. In this state, it is terminated in the lower epitaxial layer EP (n ⁻ type epitaxial layer EP).

In addition, since the stacked structure of the p-type semiconductor region PR and the n ⁺ -type semiconductor region NR is formed at a position adjacent to the trench TR1 in plan view, the gate electrode GE embedded in the trench TR1 has the insulating film GI ( Adjacent to the n ⁺ type semiconductor region NR and the p type semiconductor region PR through the gate insulating film). Further, since the stacked film LM (that is, the gate electrode GE) embedded in the trench TR1 functions as a gate electrode of the MISFET, it is necessary to provide an n ⁺ type semiconductor region NR at a position adjacent to the trench TR1. On the other hand, since the laminated film LM2 embedded in the trench TR2 does not function as a gate electrode of the MISFET, the n ⁺ type semiconductor region NR is not provided at a position adjacent to the trench TR2. Therefore, the grooves TR1 is adjacent to the ^{n +} -type semiconductor region NR in plan view, the groove TR2 is not adjacent to the ^{n +} -type semiconductor region NR in plan view. The p-type semiconductor region PR can be provided not only in the region adjacent to the trench TR1 but also in the region adjacent to the trench TR2 in the epitaxial layer EP.

Here, the case where the n ⁺ type semiconductor region NR is formed after the p type semiconductor region PR is formed has been described, but as another form, the n ⁺ type semiconductor region NR is formed first. Thus, the p-type semiconductor region PR can be formed (that is, the ion implantation for forming the n ⁺ -type semiconductor region NR is performed first and then the ion implantation for forming the p-type semiconductor region PR is performed).

  Next, as shown in FIG. 37, an insulating film IL2 as an interlayer insulating film is formed on the main surface of the substrate SUB so as to cover the laminated film LM (GE, LM2) embedded in the trench TR (TR1, TR2). Is formed (step S8 in FIG. 8). The insulating film IL2 is made of, for example, a silicon oxide film. For example, the insulating film IL2 can be formed by NSG (None-doped Silicate Glass) or BPSG (Boron Phosphorus Silicate Glass).

  Next, by performing etching (anisotropic etching) using the photoresist pattern (RP2) as an etching mask, as shown in FIGS. 38 and 39, contact holes (openings, holes, through holes, connections) Holes CT1 and CT2 are formed (step S9 in FIG. 8).

  39 is a plan view of the principal part of the semiconductor device in the same process step as FIG. 38, and shows the same plane area as that of FIG. FIG. 39 is a plan view, but in order to facilitate understanding of the contact hole CT1, CT2 formation region, in FIG. 39, the region where the contact holes CT1, CT2 are formed is hatched.

  The contact hole CT1 is a source contact hole, and the contact hole CT2 is a gate lead-out contact hole. That is, the contact hole CT1 is a contact hole for embedding the source plug (PG) PG1, and the contact hole CT2 is a contact hole for embedding the gate lead plug PG2.

  Contact hole CT1 and contact hole CT2 are formed in the same process. That is, in step S9, the source contact hole CT1 and the gate lead-out contact hole CT2 are formed simultaneously (in the same process) by anisotropic etching.

Contact hole CT1 is formed in a region adjacent to trench TR1 in substrate SUB (epitaxial layer EP) and spaced from trench TR1. More specifically, the contact hole CT1 is formed at a position included in the n ⁺ -type semiconductor region NR adjacent to the trench TR1 (that is, between the adjacent trenches TR1) in plan view. Contact hole CT1 does not overlap groove TR in plan view. This can be realized by providing an opening OP1 of a photoresist pattern RP2 to be described later so as to be included in the n ⁺ type semiconductor region NR in a plan view. Note that the contact hole CT1 is formed at a position included in the n ⁺ type semiconductor region NR in plan view, but penetrates the n ⁺ type semiconductor region NR and the bottom of the contact hole CT1 is the p type semiconductor region PR. It is formed so as to be located in the middle of the thickness direction. That is, in step S9, the contact hole CT1 is formed so as to penetrate the insulating films IL2, GI and the n ⁺ type semiconductor region NR and reach the p type semiconductor region PR.

  The contact hole CT2 is formed at a position enclosed in the trench TR2 in plan view. This can be realized by providing an opening OP2 of a photoresist pattern RP2 described later so as to be included in the trench TR2 in a plan view.

  In the substrate SUB, the trench TR2 extends so as to surround the outer periphery of the transistor cell region CE (see FIG. 2 above), but the contact hole CT2 is formed so as to extend along the trench TR2. Is done. For this reason, the dimension of the contact hole CT2 is larger in the dimension along the extending direction of the trench TR2 than in the dimension along the width direction of the trench TR2.

  Further, one contact hole CT2 can be provided in the trench TR2 as shown in FIG. 39, but a plurality of contact holes CT2 can be provided in the trench TR2 as shown in FIG. In the case where a plurality of contact holes CT2 are provided for the trench TR2, as shown in FIG. 40, the plurality of contact holes CT2 are arranged in a line along the extending direction of the trench TR2, and the contact holes CT2 are extended from the trench TR2. They are separated by a predetermined distance in the current direction. As the number of contact holes CT2 provided for the trench TR2 is increased, the size of the contact hole CT2 along the extending direction of the trench TR2 is reduced. Here, FIG. 40 is a plan view of a principal part of a semiconductor device of a modified example in the same process stage as FIGS. FIG. 40 is a plan view, but in order to facilitate understanding of the contact hole CT1, CT2 formation region, in FIG. 40, the region where the contact holes CT1, CT2 are formed is hatched.

  Step S9 has substeps of steps S9a, S9b, and S9c shown in FIG. Details of step S9 (S9a, S9b, S9c) will be described below.

In step S9, prior to the etching in step S9a described later, first, as shown in FIGS. 41 to 43, a photoresist pattern (resist pattern, mask layer) RP2 is formed on the insulating film IL2 using a photolithography technique. Form. The photoresist pattern RP2 has openings OP1 and OP2 in regions where the contact holes CT1 and CT2 are to be formed. The opening OP1 in the photoresist pattern RP2 is formed in the region where the contact hole CT1 is to be formed, and the opening OP2 in the photoresist pattern RP2 is formed in the region where the contact hole CT2 is to be formed. That is, the opening OP1 is an opening for forming the contact hole CT1, and the opening OP2 is an opening for forming the contact hole CT2. The opening OP1 is formed at a position included in the n ⁺ -type semiconductor region NR adjacent to the trench TR1 (that is, between the adjacent trenches TR1) in plan view. Further, the opening OP2 is formed at a position enclosed in the groove TR2 in plan view.

After forming the photoresist pattern RP2, as shown in FIGS. 44 to 46, the insulating film IL2 is etched using the photoresist pattern RP2 as an etching mask (step S9a in FIG. 12). In this step S9a, the insulating film IL2 is etched to form contact holes CT1 and CT2 in the insulating film IL2, and the epitaxial layer EP (a portion of the epitaxial layer EP that becomes the n ⁺ type semiconductor region NR is formed at the bottom of the contact hole CT1). And the conductive film CD2 of the laminated film LM2 embedded in the trench TR2 is exposed at the bottom of the contact hole CT2. In step S9a, dry etching is preferably used as etching, and anisotropic dry etching is more preferable.

In step S9a, the etching rates of the insulating films IL2 and GI are higher than the etching rates of the conductive film CD2 and the n ⁺ type semiconductor region NR (the epitaxial layer EP in the portion that is the n ⁺ type semiconductor region NR) ( Etching is performed under conditions (etching conditions) that are faster.

  In this step S9a, the insulating film IL2 exposed from the opening OP1 of the photoresist pattern RP2 and the insulating film GI therebelow are removed by etching, and the insulating film IL2 exposed from the opening OP2 of the photoresist pattern RP2 is etched. Remove with. As a result, the contact hole CT1 is formed in the insulating films IL2 and GI so as to be aligned with the opening OP1 of the photoresist pattern RP2, and the contact hole CT2 is formed in the insulating film IL2 so as to be aligned with the opening OP2 of the photoresist pattern RP2. It is formed.

In step S8, the insulating film GI is formed in a state where the insulating film GI remains on the n ⁺ type semiconductor region NR, whereby the insulating film IL2 is formed on the insulating film GI on the n ⁺ type semiconductor region NR. Is formed. The opening OP1 of the photoresist pattern RP2 is provided at a position included in the n ⁺ type semiconductor region NR in plan view. For this reason, in step S9a, the insulating film IL2 exposed from the opening OP1 of the photoresist pattern RP2 and the insulating film GI therebelow are removed, and the contact hole CT1 penetrates the insulating film IL2 and the insulating film GI to form a contact hole. The n ⁺ type semiconductor region NR is exposed at the bottom of CT1.

  In step S8, the insulating film IL2 is formed over the stacked film LM2 embedded in the trench TR2. The opening OP2 of the photoresist pattern RP2 is provided at a position included in the trench TR2 in plan view. Therefore, in step S9a, the insulating film IL2 exposed from the opening OP2 of the photoresist pattern RP2 is removed, and the contact hole CT2 penetrates the insulating film IL2 and is buried in the trench TR2 at the bottom of the contact hole CT2. The laminated film LM2 is exposed. However, in step S9a, the conductive film CD2 of the stacked film LM2 embedded in the trench TR2 is exposed from the bottom of the contact hole CT2, but the conductive film CD1 of the stacked film LM2 embedded in the trench TR2 is exposed. Avoid exposure. That is, the conductive film CD2 of the stacked film LM2 embedded in the trench TR2 is exposed from the bottom of the contact hole CT2, but the conductive film CD1 of the stacked film LM2 embedded in the trench TR2 is not exposed. Then, the position and shape of the contact hole CT2 are set (thus setting the position and shape of the opening OP2 in the photoresist pattern RP2). This is because the opening OP2 of the photoresist pattern RP2 is positioned so as to be included in the portion of the conductive film CD2 exposed on the upper surface (UPS2) of the multilayer film LM2 embedded in the trench TR2 in plan view. This can be realized by forming the pattern RP2. Thereby, in step S9a, the insulating film IL2 exposed from the opening OP2 of the photoresist pattern RP2 is removed, and the conductive film CD2 of the stacked film LM2 embedded in the trench TR2 is exposed at the bottom of the contact hole CT2. (The conductive film CD1 is not exposed).

Therefore, the etching step S9a, the bottom of the contact hole CT1 is exposed ^{n +} -type semiconductor region NR ^{(n +} -type semiconductor region epitaxial layer of which parts become NR EP), in the bottom of the contact hole CT2, grooves TR2 The conductive film CD2 in the laminated film LM2 embedded in is exposed. In step S9a, by using etching conditions such that the etching rate of the conductive film CD2 and the n ⁺ type semiconductor region NR is smaller (slower) than the etching rate of the insulating films IL2 and GI, n ^{+ at} the bottom of the contact hole CT1 is used. Excessive etching of the type semiconductor region NR and the conductive film CD2 at the bottom of the contact hole CT2 can be suppressed or prevented.

If the insulating film IL2 is formed with the insulating film GI remaining on the n ⁺ type semiconductor region NR in step S8, only the insulating film IL2 is used to form the contact hole CT1. However, the insulating film GI is also etched. On the other hand, in order to form the contact hole CT2, the insulating film IL2 is etched, but it is not necessary to etch the insulating film GI.

Next, as shown in FIGS. 47 to 49, the epitaxial layer EP (the epitaxial layer EP that is the n ⁺ type semiconductor region NR or the p type semiconductor region PR) exposed at the bottom of the contact holes CT1 and CT2 in step S9a. ) And the conductive film CD2 are etched (step S9b in FIG. 12). In this step S9b, the epitaxial layer EP exposed from the contact hole CT1 (epitaxial layer EP serving as the n ⁺ -type semiconductor region NR and the p-type semiconductor region PR) is etched, and the laminated film LM2 exposed from the contact hole CT2 The conductive film CD2 is etched to expose the material film MT from the contact hole CT2. In step S9b, dry etching is preferably used as etching, and anisotropic dry etching is more preferable.

In step S9b, the etching rate of the epitaxial layer EP (epitaxial layer EP that is the n ⁺ type semiconductor region NR or p type semiconductor region PR) and the conductive film CD2 is larger (faster) than the etching rate of the material film MT. Etching is performed under such conditions (etching conditions). In other words, in step S9b, the etching rate of the material film MT is higher than the etching rates of the epitaxial layer EP (epitaxial layer EP that is the n ⁺ -type semiconductor region NR or the p-type semiconductor region PR) and the conductive film CD2. Etching is performed under conditions (etching conditions) that reduce (slow) the film thickness. In other words, in step S9b, the material film MT is less likely to be etched (etching) than the epitaxial layer EP (epitaxial layer EP that is the n ⁺ -type semiconductor region NR or the p-type semiconductor region PR) and the conductive film CD2. Etching is performed under (Condition).

For example, when the epitaxial layer EP (including the n ⁺ -type semiconductor region NR and the p-type semiconductor region PR) is made of single crystal silicon, the conductive film CD2 is made of polysilicon, and the material film MT is made of silicon oxide, the single crystal Etching in step S9b is performed under conditions (etching conditions) such that the etching rate of silicon and polysilicon is greater (faster) than the etching rate of silicon oxide. That is, in this case, it is preferable to perform the etching in step S9b under conditions (etching conditions) that increase the etching selection ratio between silicon (single crystal silicon and polysilicon) and silicon oxide. As a result, the effect of the silicon oxide film (material film MT) serving as an etching stopper (etching mask) can be increased when the contact hole CT2 for extracting the gate is formed. Note that the etching conditions may include selection of the type and flow rate of the etching gas to be used.

In this step S9b, the epitaxial layer EP exposed at the bottom of the contact hole CT1 (epitaxial layer EP that is an n ⁺ -type semiconductor region NR or a p-type semiconductor region PR) is etched, so that the contact hole CT1 becomes n The bottom of the contact hole CT1 is positioned in the middle of the thickness direction of the p-type semiconductor region PR through the ⁺ -type semiconductor region NR. That is, in step S9b, until the contact hole CT1 penetrates the n ⁺ type semiconductor region NR and the bottom of the contact hole CT1 is located in the middle of the thickness direction (depth direction) of the p type semiconductor region PR, Continue etching.

  In step S9b, the conductive film CD2 exposed at the bottom of the contact hole CT2 is also etched, so that the material film MT is exposed at the bottom of the contact hole CT2. This material film MT functions as an etching stopper. To do. That is, in step S9b, the material film MT can function as an etching stopper film because etching is performed under conditions (etching conditions) in which the material film MT is less likely to be etched than the conductive film CD2. When the etching in step S9b is performed, the material film MT is exposed from the contact hole CT2, but the conductive film CD1 is not exposed because the material film MT functions as an etching stopper film.

  When Steps S9a and S9b are performed, the contact hole CT2 is more likely to be etched earlier than the contact hole CT1. That is, unlike the present embodiment, if there is no material film MT in the laminated film LM2, the bottom of the contact hole CT2 becomes deeper than the bottom of the contact hole CT1 when step S9b is completed. . This is due to the following reason.

First, the insulating film GI is etched when the contact hole CT1 is formed, whereas the insulating film GI is not etched when the contact hole CT2 is formed. Therefore, in step S9a, the contact hole CT1 is determined depending on whether or not the insulating film GI is etched. Compared with the n ⁺ type semiconductor region NR at the bottom of the contact hole CT2, the conductive film CD2 at the bottom of the contact hole CT2 tends to have a larger amount of overetching. Further, as described above, the height position of the upper surface of the laminated film LM2 embedded in the trench TR2 before the step S9 is the upper surface of the portion of the epitaxial layer EP that is the n ⁺ type semiconductor region NR. It is in a position lower than the height position. Further, since the polysilicon film (conductive film CD2) is likely to have a higher (faster) etching rate than the single crystal silicon layer (n ⁺ type semiconductor region NR and p type semiconductor region PR), When the polysilicon film is etched for the same etching time, the polysilicon film is etched to a deeper position than the single crystal silicon layer. For this reason, when steps S9a and S9b are performed, the contact hole CT2 is more likely to be etched earlier than the contact hole CT1.

  However, in this embodiment, when the conductive film CD2 exposed from the contact hole CT2 is etched and the material film MT is exposed from the contact hole CT2 in step S9b, the material film MT may function as an etching stopper. Therefore, it is possible to prevent the conductive film CD1 from being exposed from the contact hole CT2 in step S9b. In step S9b, the material film MT is etched subsequent to the conductive film CD2, so that even if the conductive film CD1 is exposed from the contact hole CT2, the time required for etching the material film MT is reduced. It is possible to prevent the film CD1 from being excessively etched.

  Next, as shown in FIGS. 50 to 52, the material film MT exposed from the contact hole CT2 in step S9b is removed by etching (step S9c in FIG. 12). In this step S9c, the material film MT exposed from the contact hole CT2 is etched to expose the conductive film CD1 from the contact hole CT2.

In the etching of step S9c, the etching rate of the material film MT is higher than the etching rates of the epitaxial layer EP (epitaxial layer EP that is the n ⁺ type semiconductor region NR or the p type semiconductor region PR) and the conductive film CD1. Etching is performed under conditions (etching conditions) such that (fast). In other words, the etching in step S9c is performed with respect to each of the epitaxial layer EP (epitaxial layer EP that is the n ⁺ -type semiconductor region NR or the p-type semiconductor region PR) and the conductive film CD1 rather than the etching rate of the material film MT. Etching is performed under conditions (etching conditions) that reduce (slow) the etching rate. That is, in step S9c, the epitaxial layer EP (epitaxial layer EP that is the n ⁺ -type semiconductor region NR or the p-type semiconductor region PR) and the conductive film CD1 are less likely to be etched than the material film MT (etching). Etching is performed under (Condition).

For example, when the epitaxial layer EP (including the n ⁺ -type semiconductor region NR and the p-type semiconductor region PR) is made of single crystal silicon, the conductive film CD1 is made of polysilicon, and the material film MT is made of silicon oxide, the single crystal is formed. Etching in step S9c is performed under conditions (etching conditions) such that the etching rate of silicon oxide is higher (faster) than the etching rate of silicon and polysilicon. That is, in this case, it is preferable to perform the etching in step S9c under conditions (etching conditions) that increase the etching selectivity between silicon oxide and silicon (single crystal silicon and polysilicon). Thus, the material film MT exposed from the contact hole CT2 can be removed in step S9c, and the conductive film CD1 exposed from the contact hole CT2 and the n ⁺ type exposed from the contact hole CT1 by removing the material film MT. It is possible to suppress or prevent the semiconductor region NR and the p-type semiconductor region PR from being etched.

The etching in step S9c is preferably wet etching. When the epitaxial layer EP (including the n ⁺ -type semiconductor region NR and the p-type semiconductor region PR) is made of single crystal silicon, the conductive film CD1 is made of polysilicon, and the material film MT is made of silicon oxide, etching in step S9c is performed. As such, wet etching using an aqueous solution of hydrofluoric acid can be suitably used.

  Note that as the material film MT, a material that can ensure an etching selectivity with respect to the conductive films CD1 and CD2 is preferably used, and a silicon oxide film or a silicon nitride film is preferable, and a silicon oxide film is particularly preferable.

The etching in step S9c can also be performed as wet etching (wet cleaning) for pre-processing in the film forming process of the barrier conductor film BR in step S10 described later. In this case, if a natural oxide film is formed in the silicon regions (n ⁺ type semiconductor region NR, p type semiconductor region PR, conductive film CD2) exposed from the contact holes CT1 and CT2, the natural oxide film is also stepped. In S9c, the material film MT can be removed at the same time, and the barrier conductor film BR can be formed on the clean silicon surface from which the natural oxide film has been removed. In this case, the number of manufacturing steps can be suppressed. Step S9c may be performed after performing steps S9a and 9b and before performing later-described step S10 (particularly, the barrier conductor film BR film forming step).

  By removing the material film MT exposed from the contact hole CT2 in step S9c, the conductive film CD1 is exposed from the contact hole CT2. In this step S9c, etching is performed under etching conditions that make the conductive film CD1 difficult to be etched compared to the material film MT (wet etching using a hydrofluoric acid aqueous solution when the material film MT is a silicon oxide film and the conductive film CD1 is a polysilicon film). Therefore, even if the conductive film CD1 is exposed from the contact hole CT2, it is possible to suppress or prevent the conductive film CD1 from being etched. For this reason, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is kept covered with the conductive film CD1, and the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not exposed from the contact hole CT2. Since the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not exposed from the contact hole CT2, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is damaged by the etching for forming the contact hole CT2. There is no.

  In step S9c, the etching is performed under the etching conditions in which the conductive film CD1 is less likely to be etched than in the material film MT. More preferably, the etching is performed in the etching conditions in which the conductive films CD1 and CD2 are less likely to be etched than in the material film MT. I do. Thereby, in addition to suppressing or preventing the conductive film CD1 from being etched in step S9c, etching of the conductive film CD2 can also be suppressed or prevented.

  The photoresist pattern RP2 is removed after the etching process in step S9c and before step S10 described later (that is, before the film forming process of the barrier conductor film BR), or after the etching process in step S9b. And it removes before the etching process of step S9c. When step S9c is performed by wet etching, it is preferable to remove the photoresist pattern RP2 after step S9b and before step S9c.

  Further, when the etching in step S9c is performed as wet etching (wet cleaning) for pretreatment in the film forming process of the barrier conductor film BR, the photoresist pattern RP2 is removed after step S9b, and then the barrier conductor film It is preferable to perform the barrier conductor film BR film formation step after performing step S9c which also serves as pre-treatment wet etching for the BR film formation step.

  In this way, contact holes CT1 and CT2 are formed.

  In the present embodiment, in step S9b, before the conductive film CD1 is exposed from the contact hole CT2 by causing the material film MT to function as an etching stopper film (that is, the conductive film CD1 is exposed from the contact hole CT2). The case has been described where the etching in step S9b is terminated (when not exposed). The film thickness of the material film MT (the film thickness of the material film MT formed in step S4b) is set to a film thickness suitable for serving as an etching stopper film (etching mask). When the material film MT is left in the contact hole CT2 in step S9b (the conductive film CD1 is not exposed), the film thickness of the material film MT when the stacked film LM is formed in step S4 is set in the contact hole CT2 in step S9b. It is sufficient to make it thicker than the etching amount (etching thickness) of the material film MT. When the film thickness of the material film MT (the film thickness of the material film MT formed in step S4b) is set to be thick so that the material film MT remains in the contact hole CT2 in step S9b (that is, the conductive film CD1 is not exposed) The material film MT exposed from the contact hole CT2 in step S9b needs to be removed by etching in step S9c. The removal process of the material film MT in step S9c is the same as the wet etching as a pre-process of the barrier conductor film BR formation process (specifically, the film formation process of the barrier conductor film BR by sputtering) in the subsequent step S10. It is more preferable to perform the process and remove the material film MT simultaneously with the removal of the natural oxide film by this wet etching because the number of manufacturing processes can be suppressed.

  As another form, the conductive film CD1 can be exposed from the contact hole CT2 by etching (dry etching) the material film MT after the conductive film CD2 in the contact hole CT2 by the etching in step S9b. In this case, the film thickness of the material film MT when the stacked film LM is formed in step S4 is set to be equal to or less than the etching amount (etching thickness) of the material film MT in the contact hole CT2 in step S9b. In this case, in step S9b, not only the conductive film CD2 exposed from the contact hole CT2 is removed by etching, but also the material film MT exposed by removing the conductive film CD2 is removed by etching, so that the contact hole CT2 is removed. At the stage (state) where the conductive film CD1 is exposed, the etching in step S9b is completed. That is, the thickness of the material film MT (the thickness of the material film MT formed in step S4b) is thinned in advance so that the material film MT is slightly over-etched in the contact hole CT2 in step S9b to expose the conductive film CD1. The material film MT exposed from the contact hole CT2 is completely removed (that is, the conductive film CD1 is exposed) by the etching (etchback) in step S9b. Also in this case, the etching in step S9b is performed under etching conditions in which the material film MT is less likely to be etched than the conductive films CD1 and CD2. Therefore, even when the conductive film CD1 is exposed from the contact hole CT2 in step S9b, the material film MT is not provided because the etching of the material film MT takes time (that is, the stacked film LM does not form the material film MT). The etching amount (etching thickness) of the conductive film CD1 exposed from the contact hole CT2 can be suppressed as compared with the case of not having it. Therefore, even when the conductive film CD1 is exposed from the contact hole CT2 in step S9b, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is kept covered with the conductive film CD1, and the contact hole CT2 Thus, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 can be prevented from being exposed. Since the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not exposed from the contact hole CT2, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not damaged by the etching for forming the contact hole CT2. Can be.

  When the conductive film CD1 is exposed from the contact hole CT2 in step S9b, the material film MT removal process in step S9c does not have to be performed, which is advantageous in reducing the number of manufacturing processes. That is, in step S9b, when the material film MT is removed in the contact hole CT2 to expose the conductive film CD1, the subsequent process (step S9b is performed without performing the material film MT removal process in step S9c). The process can proceed to a barrier conductor film BR forming step in step S10 described later.

  Note that, when the conductive film CD1 is exposed by etching the conductive film CD2 after the conductive film CD2 in the contact hole CT2 by the etching in step S9b, which is described as another embodiment, the steps S9b and S9c are continuously performed. It corresponds to the case where it is performed as a (consistent) dry etching process.

  On the other hand, when the material film MT is exposed from the contact hole CT2 in step S9b but the conductive film CD1 is not exposed, it is necessary to remove the material film MT exposed from the contact hole CT2 in step S9c. Etching conditions in which the conductive film CD1 is less likely to be etched than the film MT can be employed. For this reason, when step S9 is completed, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is more reliably covered with the conductive film CD1, and the inner surface (bottom surface and side surface) of the trench TR2 from the contact hole CT2. ) Can be more reliably prevented from being exposed. Therefore, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 can be more reliably prevented from being damaged by the etching for forming the contact hole CT2.

  Further, after the etching process of step S9c and before step S10 described later, or after the etching process of step S9b and before step S10 described later, the p-type semiconductor region PR at the bottom of the contact hole CT1 is formed. A p-type impurity can also be ion-implanted. Thereby, the contact resistance between the plug PG1 to be formed later and the p-type semiconductor region PR can be reduced.

  After forming the contact holes CT1 and CT2 in step S9, conductive plugs PG are formed in the contact holes CT1 and CT2 as conductor portions (connecting conductor portions) (step S10 in FIG. 8). In step S10, the plug PG can be formed as follows.

  That is, first, as shown in FIG. 53, a barrier conductor film (barrier metal film) BR is formed (deposited) on the insulating film IL2 including the inner surfaces (bottom surface and side surfaces) of the contact holes CT1 and CT2. The barrier conductor film BR can be formed by sputtering or the like, and is made of, for example, a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated film thereof. Then, the main conductor film MC1 is formed on the barrier conductor film BR so as to fill the contact holes CT1 and CT2. The main conductor film MC1 is made of a tungsten film or the like and can be formed using a CVD method or the like. By forming the barrier conductor film BR and the main conductor film MC1, the contact holes CT1 and CT2 are filled with the barrier conductor film BR and the main conductor film MC1. After the formation of the barrier conductor film BR and the main conductor film MC1, as shown in FIG. 54, the unnecessary main conductor film MC1 on the insulating film IL2 is subjected to a CMP (Chemical Mechanical Polishing) method or etch back. By removing by a method or the like, the plug PG can be formed. The plug PG is composed of a barrier conductor film BR and a main conductor film MC1 remaining (embedded) in the contact holes CT1 and CT2.

  FIG. 54 illustrates the case where the barrier conductor film BR is left on the upper surface of the insulating film IL2 when the main conductor film MC1 is subjected to the CMP process or the etch back process. In this case, when the main conductor film MC1 outside the contact holes CT1 and CT2 is subjected to the CMP process or the etch back process, the barrier conductor film BR on the upper surface of the insulating film IL2 functions as a stopper film for the CMP process or the etch back process. Can be made. As another form, when the main conductor film MC1 outside the contact holes CT1 and CT2 is subjected to the CMP process or the etch back process, the barrier conductor film BR outside the contact holes CT1 and CT2 is also removed, and the upper surface of the insulating film IL2 is formed. It is also possible to expose.

Of the plugs PG, the plug PG embedded in the contact hole CT1 is referred to as a plug PG1 with a reference numeral PG1, and the plug PG embedded in the contact hole CT2 is referred to as a plug PG2 with a reference numeral PG2. To do. The plug PG1 embedded in the contact hole CT1 is a source plug (source plug) PG1, and the plug PG2 embedded in the contact hole CT2 is a gate lead plug (gate plug, gate plug) PG2. . The plug PG1 embedded in the contact hole CT1 is in contact with and electrically connected to the n ⁺ type semiconductor region NR and the p type semiconductor region PR. The plug PG2 embedded in the contact hole CT2 is in contact with and electrically connected to the conductive film CD1 in the trench TR2. For this reason, the plug PG2 is electrically connected to the gate electrode GE via the conductive film CD1.

  Further, as described above, when the side surface (side wall) of the trench TR2 has a taper (inclination), the contact hole CT2 in the portion in the trench TR2 can also be provided with a taper (inclination). The embedding property of the main conductor film MC1 in the contact hole CT2 can be improved.

  Next, the wiring M1 is formed (step S11 in FIG. 9). In step S11, the wiring M1 can be formed as follows.

  That is, as shown in FIG. 55, first, on the main surface of the substrate SUB, that is, on the insulating film IL2 in which the plug PG is embedded (if the barrier conductor film BR is left on the insulating film IL2, the barrier conductor A conductor film MC2 for wiring is formed on the film BR). The conductor film MC2 is a metal film mainly composed of, for example, an aluminum film or an aluminum alloy film, and can be formed by a sputtering method or the like. Then, as shown in FIGS. 56 and 57, the conductor film MC2 is patterned by using the photolithography technique and the etching technique, thereby forming the wiring M1. The wiring M1 is made of a patterned main conductor film MC1. In the case where the conductor film MC2 is formed with the barrier conductor film BR remaining on the insulating film IL2, the laminated film of the conductor film MC2 and the barrier conductor film BR therebelow is patterned. M1 is formed of a laminated film of a patterned main conductor film MC1 and a barrier conductor film BR below it.

The source wiring M1S of the wiring M1 is electrically connected to the n ⁺ type semiconductor region NR and the p ⁺ type semiconductor region PR via the plug PG1. In addition, the gate wiring M1G of the wiring M1 is electrically connected to the conductive film CD1 in the trench TR2 through the plug PG2.

  Since the trench TR1 and the trench TR2 are connected, the conductive film CD1 in the trench TR1 and the conductive film CD1 in the trench TR2 are integrally formed and connected. That is, the conductive film CD1 continuously extends from the trench TR1 to the trench TR2. Therefore, the plug PG2 is in contact with and connected to the conductive film CD1 in the trench TR2, so that the conductive film CD1 constituting the gate electrode GE embedded in the trench TR1 (that is, the conductive film CD1 in the trench TR1) It is electrically connected to the plug PG2 through the conductive film CD1 extending from TR1 to the trench TR2. Thereby, the gate electrode GE can be drawn out to the gate wiring M1G through the plug PG2.

  Further, as can be seen from FIG. 57, the conductive film CD2 and the conductive film CD1 are electrically connected via the plug PG2. This is because a part of the conductive film CD2 is seen on the side surface of the contact hole CT2 when viewed in a cross section (corresponding to the cross section of FIG. 57) passing through the connecting portion between the trench TR2 and the trench TR1 and extending in the extending direction of the trench TR1. This is because it is exposed and contacts the plug PG2. That is, the conductive film CD2 and the conductive film CD1 are not in direct contact with each other because the material film MT is interposed therebetween, but the plug PG2 is in contact with both the conductive film CD2 and the conductive film CD1. Therefore, the conductive film CD2 and the conductive film CD1 are electrically connected via the plug PG2. For this reason, the conductive film CD1 and the conductive film CD2 constituting the gate electrode GE are also electrically connected to each other.

  For this reason, the conductive film CD1 constituting the gate electrode GE continuously extends from the trench TR1 to the trench TR2 and is electrically connected to the plug PG2 through the trench TR2, and the conductive film CD2 constituting the gate electrode GE is also electrically connected. The groove TR1 continuously extends from the groove TR1 and is electrically connected to the plug PG2 through the groove TR2. Therefore, the gate electrode GE (conducting conductive films CD1, CD2) can be pulled out above the trench TR2 by the plug PG2 and connected to the gate wiring M1G.

  Even when the conductive film CD2 is not electrically connected to the conductive film CD1, the conductive film CD1 constituting the gate electrode GE can function as the gate electrode of the trench gate type MISFET, but the conductive film CD2 is the conductive film CD1. Is electrically connected to the conductive film CD1 and the conductive film CD2 constituting the gate electrode GE, and the resistance of the gate electrode GE can be reduced, which is more preferable.

  Here, the case where the plug PG and the wiring M1 are formed separately has been described. As another form, the plug PG and the wiring M1 can be integrally formed. In this case, as shown in FIG. 58, after the formation of the barrier conductor film BR, a conductor film (on the main surface of the substrate SUB (that is, on the barrier conductor film BR) is embedded so as to fill the contact holes CT1 and CT2. For example, a metal film MC3 mainly composed of an aluminum film or an aluminum alloy film is formed. Then, as shown in FIG. 59, the conductor film MC3 and the underlying barrier conductor film BR are patterned using a photolithography technique and an etching technique, thereby forming a wiring M1 integrated with the plug PG. To do. In this case, the plug PG is formed as a part of the wiring M1 (that is, the plug PG is formed integrally with the wiring M1). That is, the source plug PG1 is formed integrally with the source wiring M1S, and the gate lead-out plug PG2 is formed integrally with the gate wiring M1G. When the plug PG and the wiring M1 are integrally formed, an aluminum film or an aluminum alloy film is mainly used so as to fill the contact holes CT1 and CT2 on the main surface of the substrate SUB (that is, on the barrier conductor film BR). When the conductor film (MC3) is formed, a high-temperature / reflow sputtering method or the like can be preferably used.

  Next, as shown in FIG. 60, an insulating film IL3 is formed on the main surface of the substrate SUB, that is, on the insulating film IL2, so as to cover the wiring M1. The insulating film IL3 is made of, for example, a silicon nitride film or a polyimide resin film, and is formed for surface protection (step S12 in FIG. 9).

  Next, the insulating film IL3 is patterned by using a photolithography technique and an etching technique, and an opening OP3 that exposes a part of the wiring M1 is formed in the insulating film IL3, thereby forming a bonding pad (pad electrode). (Step S13 in FIG. 9).

  The source wiring M1S exposed from the opening OP3 of the insulating film IL3 (shown in both FIG. 60 and FIG. 1) serves as a source bonding pad, and the opening OP3 of the insulating film IL3 (FIG. Although not shown, the gate wiring M1G exposed from (shown in FIG. 1) serves as a gate bonding pad.

  Further, a metal layer (not shown) may be further formed by plating or the like on the surface of the wiring M1 exposed from the opening OP3 (that is, the surface of the bonding pad). This metal layer is, for example, a laminated film of a copper (Cu) film, a nickel (Ni) film, and a gold (Au) film formed in order from the bottom, or a titanium (Ti) film formed in order from the bottom. It consists of a laminated film of a nickel (Ni) film and a gold (Au) film. By forming this metal layer, oxidation of the surface of the underlying aluminum (wiring M1) can be suppressed or prevented.

  Next, the back surface of the substrate SUB (the main surface of the substrate SUB opposite to the side where the epitaxial layer EP is formed, that is, the back surface of the substrate body SB opposite to the side where the epitaxial layer EP is formed) is ground or polished. Thus, the thickness of the substrate SUB is reduced. Then, as shown in FIG. 61, a metal layer is deposited on the entire back surface of the substrate SUB (back surface of the substrate body SB) by vapor deposition or the like, thereby forming a back electrode (back surface drain electrode) BE (FIG. 9). Step S14).

  The back electrode BE is electrically connected to the drain of the trench gate type MISFET, and can function as a drain electrode (a drain back electrode). The substrate body SB and the epitaxial layer EP have a function as a drain region of a vertical MISFET having a trench gate structure. The back electrode BE can be formed by, for example, a laminated film of a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer in order from the back surface of the substrate SUB.

  In this way, the semiconductor device of the present embodiment is manufactured. Thereafter, the substrate SUB is divided (separated and cut) by dicing or the like, whereby individual semiconductor chips (semiconductor devices) are obtained from the substrate SUB.

<About study example>
When a trench gate type MISFET is formed on a substrate, a gate electrode is embedded in a groove formed in the substrate. However, the embedded gate electrode needs to be drawn on the substrate and connected to a wiring. One of these methods will be described with reference to FIG. FIG. 62 is a cross-sectional view for explaining a method of drawing a gate electrode embedded in a groove onto a substrate and connecting it to a wiring.

  As shown in FIG. 62, a trench (TR101) is provided in a substrate (semiconductor substrate) SUB101, and a conductive film portion GE101 for gate extraction formed integrally with a gate electrode embedded in the trench TR101 is formed in the trench TR101. It extends also on the external substrate SUB101. Note that the gate electrode is buried in the trench TR101 via the insulating film GI101 for the gate insulating film, and the insulating film GI101 is also interposed between the conductive film portion GE101 for extracting the gate and the substrate SUB101. . Further, in FIG. 62, for simplification, illustration of the semiconductor region formed in the substrate SUB101 is omitted. An insulating film IL102 is formed on the substrate SUB101 so as to cover the gate electrode and the conductive film portion GE101 for extracting the gate. In the insulating film IL102, the contact hole CT102 is formed on the conductive film portion GE101 for extracting the gate. Form and embed plug PG102. Via the plug PG102, the wiring and the conductive film portion GE101 for leading the gate are connected. Thereby, the gate electrode can be drawn out and connected to the wiring.

  However, in the method shown in FIG. 62, the conductive film portion GE101 for extracting the gate extends so as to get over the opening end of the upper portion of the trench TR101. However, the conductive film portion GE101 for extracting the gate electrode and the gate The insulating film GI101 for the gate insulating film formed between the substrate SUB101 (including the inner surface of the trench TR101) is locally thinned at the upper corner (opening end) RG101 of the trench TR101. For this reason, the breakdown voltage (gate breakdown voltage) between the substrate SUB101 and the conductive film portion GE101 for extracting the gate electrode and the gate is reduced at the portion where the insulating film GI101 is locally thin (upper corner portion RG101). End up. This causes an increase in gate leakage current. Further, since the conductive film portion GE101 for extracting the gate extends on the substrate SUB101, the planar dimension of the semiconductor device is increased, which is disadvantageous for downsizing (smaller area) of the semiconductor device.

  Therefore, as another method of pulling out the gate electrode embedded in the groove on the substrate and connecting it to the wiring, there is a method of pulling out directly from the groove. The inventor is examining this technique, and the present embodiment and the following examination examples (FIGS. 63 to 69) belong to this technique.

  Compared with the method of FIG. 62 in which the conductive film portion for extracting the gate is extended on the substrate, the method of extracting the gate electrode embedded in the groove directly above the groove (this embodiment and the following examination example) The gate electrode can be pulled out without going through the upper corner (groove opening end) of the groove where the insulating film for the insulating film is likely to become thin locally, so the gate breakdown voltage does not decrease at the upper corner of the groove. There is an advantage that the gate leakage current can be reduced. In addition, since the planar dimension of the semiconductor device can be reduced as long as the conductive film portion for extracting the gate does not need to extend on the substrate, the semiconductor device can be downsized (smaller in area). Further, if the chip area is the same, the active area area (area of the area where the trench gate type MISFET cells are arranged) can be increased.

  However, as a result of studies by the present inventors, it has been found that various techniques are required to ensure the reliability of the semiconductor device even in the method of pulling out the gate electrode embedded in the groove directly above the groove. . This will be described with reference to a study example studied by the present inventors.

  63 to 69 are cross-sectional views of the main part in the manufacturing process of the semiconductor device of the examination example examined by the present inventors. 63 to 67, a cross section corresponding to FIG. 5 is shown, and FIGS. 68 and 69 show a cross section corresponding to FIG. 63 to 69, a single-layer polysilicon film (doped polysilicon film) CD201 is used instead of the laminated film LM.

  In the manufacturing process of the semiconductor device of the examination example, after obtaining the structure of FIG. 63 corresponding to FIG. 19, the trenches TR201 and TR202 are formed on the main surface (entire main surface) of the substrate SUB201 as shown in FIG. A single-layer polysilicon film (doped polysilicon film) CD201 is formed so as to fill the inside. The substrate SUB201 corresponds to the substrate SUB, the substrate body SB201 corresponds to the substrate body SB, the epitaxial layer EP201 corresponds to the epitaxial layer EP, and the groove TR201 corresponds to the groove 201. It corresponds to TR1, the trench TR202 corresponds to the trench TR2, and the insulating film GI201 corresponds to the insulating film GI.

  Then, as shown in FIG. 65, the polysilicon film CD201 is anisotropically etched (etched back) to remove the polysilicon film CD201 outside the trenches TR201 and TR202, and the polysilicon in the trenches TR201 and TR202 is removed. Leave film CD201. The gate electrode GE201 made of the polysilicon film CD201 is buried in the trench TR201, and the polysilicon film CD201 is buried in the trench TR202. Hereinafter, the polysilicon film CD201 remaining and buried in the trench TR202 is referred to as a polysilicon film CD201a.

Then, as shown in FIG. 66, by ion implantation to form a p-type semiconductor region PR201 corresponding to the p-type semiconductor region PR, also, ^{n +} -type semiconductor region NR201 corresponding to the ^{n +} -type semiconductor region NR Form.

  Then, an insulating film IL202 corresponding to the insulating film IL2 is formed on the main surface of the substrate SUB.

  Then, as shown in FIGS. 67 and 68, a photoresist pattern RP202 corresponding to the photoresist pattern RP2 is formed on the insulating film IL202. The photoresist pattern RP202 has an opening OP201 for forming the contact hole CT201 and an opening OP202 for forming the contact hole CT202.

Then, contact holes CT201 and CT202 are formed by performing anisotropic etching using the photoresist pattern RP202 as an etching mask. The contact hole CT201 corresponds to the contact hole CT1, and the contact hole CT201 passes through the n ⁺ type semiconductor region NR201, and the bottom of the contact hole CT201 is located in the middle of the thickness direction of the p type semiconductor region PR201. Formed as follows. Contact hole CT202 is a contact hole for leading a gate, and is formed at a position enclosed in trench TR202 in plan view.

  After the contact holes CT201 and CT202 are formed, plugs PG201 and PG202 corresponding to the plugs PG1 and PG2 are formed in the contact holes CT201 and CT202 as shown in FIG. Thereafter, the wiring corresponding to the source wiring M1S and the gate wiring M1G, the wiring corresponding to the insulating film IL3, and the wiring corresponding to the back electrode BE are formed, but illustration thereof is omitted here. In this way, the semiconductor device of the study example is manufactured.

  With regard to the manufacturing process of the semiconductor device of such a study example, attention is focused on the contact hole CT201 and CT202 formation process.

In the region where the source contact hole CT201 is to be formed, the contact hole CT201 penetrates through the insulating film IL202 and the insulating film GI201, and then proceeds through the n ⁺ type semiconductor region NR201 to the middle of the p type semiconductor region PR201. Then, the etching is completed when the bottom of the contact hole CT201 is located in the middle of the depth direction of the p-type semiconductor region PR201. That is, the etching time of the contact hole CT201, CT202 formation process is set so that the contact hole CT201 having such a depth is formed.

  On the other hand, in the region where the contact hole CT202 for leading the gate is formed, the polysilicon film CD201a embedded in the trench TR202 is etched after penetrating the insulating film IL202. Since the contact hole CT201 and the contact hole CT202 are formed in the same etching process, the end (termination) of the etching in the contact hole CT202 is determined by the end (termination) of the etching in the contact hole CT201.

Here, in the contact hole CT202 for extracting the gate as compared with the region where the contact hole CT201 is formed, in addition to the absence of the insulating film GI201, the upper surface of the polysilicon film CD201a embedded in the trench TR202 is an n ⁺ type semiconductor. It is at a position lower than the height position of the upper surface of the epitaxial layer EP in the portion that is the region NR201. This is because when the polysilicon film CD201 outside the trenches TR201 and TR202 is removed in order to obtain the structure shown in FIG. 65 from the structure shown in FIG. 64, unnecessary removal of the polysilicon film CD201 is left outside the trenches TR201 and TR202. This is to prevent the occurrence of. Furthermore, doped polysilicon (polysilicon film CD201) has a higher etching rate than single crystal silicon (n ⁺ type semiconductor region NR201 and p type semiconductor region PR201). Therefore, if the source contact hole CT201 and the gate lead contact hole CT202 are formed simultaneously (in the same process), the gate lead contact hole CT201 is etched more than the source contact hole CT201. Will lead. That is, the contact hole CT202 for extracting the gate is excessively etched compared to the contact hole CT201 for the source.

  Compared with the contact hole CT201 for the source, the contact hole CT202 for extracting the gate is excessively etched, which causes the following problems.

  An insulating film GI201 is formed on the inner surface (bottom surface and side surface) of the trench TR202, and this insulating film GI201 is interposed between the inner surface of the trench TR202 and the polysilicon film CD201a embedded in the trench TR202. When the contact holes CT201 and CT202 are formed, if the contact hole CT202 is excessively etched compared to the contact hole CT201, the polysilicon film CD201a is excessively etched in the depth direction at the bottom of the contact hole CT202. End up. As a result, as shown in FIG. 68, the polysilicon film CD201a on the bottom surface of the trench TR202 may be removed and the insulating film GI201 on the bottom surface of the trench TR202 may be exposed.

  Furthermore, even when anisotropic dry etching is used as the etching for forming the contact holes CT201 and CT202, side etching cannot be completely prevented depending on the etching conditions. Therefore, when the contact hole CT202 is formed, the polysilicon film CD201a exposed from the contact hole CT202 is side-etched (etched in the lateral direction), so that the trench TR202 is formed as shown in FIG. There is a possibility that the polysilicon film CD201a on the side surface is removed and the insulating film GI201 on the side surface of the trench TR202 is exposed.

  That is, in the etching process for forming the contact hole CT202, the insulating film GI201 on the bottom surface of the trench TR202 may be exposed from the contact hole CT202, and the insulating film GI201 on the side surface of the trench TR202 may be exposed. That is, in the etching process for forming the contact hole CT202, the etching proceeds with a certain amount of variation not only in the depth direction (direction toward the bottom surface of the trench TR202) but also in the lateral direction (direction toward the side surface of the trench TR202). A part of the insulating film GI201 on the inner surface of the trench TR202 is exposed and suffers from etching damage. In FIGS. 68 and 69, the etching damage received by the insulating film GI201 by the etching at the time of forming the contact hole CT202 is schematically shown by x marks.

  In the etching process for forming the contact hole CT202, if the insulating film GI201 on the inner surface of the trench TR202 is exposed from the contact hole CT202 and is subjected to etching damage, the reliability of the semiconductor device is lowered. For example, the breakdown voltage between the gate and the drain may be reduced.

  The breakdown voltage between the gate and the drain is lowered for the following reason.

  That is, when the insulating film GI201 on the inner surface of the trench TR202 exposed from the contact hole CT202 is subjected to etching damage, and the plug PG202 is embedded in the contact hole CT202, the plug PG202 passes through the insulating film GI201 that has been subjected to etching damage. It is adjacent to the epitaxial layer EP201 (including the portion that becomes the p-type semiconductor region PR201). Since the trench TR202 is connected to the trench TR201, and the polysilicon film CD201 is integrally formed continuously from the trench 201 to the trench TR202, the plug PG202 is a gate embedded in the trench TR201 through the polysilicon film CD201. The electrode GE201 is electrically connected. For this reason, the insulating film GI201 interposed between the plug PG202 and the epitaxial layer EP201 (including the portion serving as the p-type semiconductor region PR201) is subjected to etching damage, so that it is electrically connected to the gate electrode GE201. The breakdown voltage between the formed plug PG202 and the epitaxial layer EP201 is lowered. Accordingly, the breakdown voltage between the gate and drain of the trench gate type MISFET is lowered. This causes an increase in gate leakage current.

  Further, in the etching process for forming the contact hole CT202, when the insulating film GI201 on the inner surface of the trench TR202 is exposed from the contact hole CT202, the plug PG202 and the polysilicon film CD201 are in contact with the insulating film GI201. The contact area with is reduced. This may increase the connection resistance between the plug PG202 filling the contact hole CT202 and the polysilicon film CD201. This can also be a factor that reduces the reliability of the semiconductor device.

  Further, when the width of the trench TR202 is increased to increase the difference between the width of the opening OP202 of the photoresist pattern RP202 (this becomes the width of the contact hole CT202) and the width of the trench TR202, the contact hole CT202 is formed. At this time, even if side etching occurs, the insulating film GI201 on the side surface of the trench TR202 is hardly exposed. However, increasing the width of the trench TR202 leads to an increase in the planar size of the semiconductor device, which is disadvantageous for downsizing (smaller area) of the semiconductor device.

<Main features and effects of the present embodiment>
In the present embodiment, a single-layer film such as the polysilicon film CD201 is not used to fill the trenches TR1 and TR2, but the conductive film CD1, the material film MT on the conductive film CD1, and the material film MT. A laminated film (first film) LM having the upper conductive film CD2 is used. That is, in step S4, a laminated film (including a conductive film CD1, a material film MT on the conductive film CD1, and a conductive film CD2 on the material film MT so as to fill the trenches TR1 and TR2 on the substrate SUB ( First film) LM is formed. In step S9, a contact hole CT2 that penetrates the insulating film IL2 and exposes the conductive film CD1 of the stacked film LM (that is, the stacked film LM2) embedded in the trench TR2 is formed by etching.

  In the present embodiment, the contact hole CT2 is formed in a state where the trench TR2 is embedded with the laminated film LM2 (LM) including the conductive film CD1, the material film MT, and the conductive film CD2, and thus the etching for forming the contact hole CT2 is performed. In the process, the material film MT in the laminated film LM2 (LM) embedded in the trench TR2 can function as an etching stopper film. That is, in the contact hole CT2 formation step, when the conductive film CD2 exposed from the contact hole CT2 is etched, the conductive film CD2 is more easily etched than the material film MT (in other words, the material film MT than the conductive film CD2). Etching is performed under the condition that etching is difficult. This can prevent the conductive film CD1 from being etched and the insulating film GI on the inner surface (side surface and bottom surface) of the trench TR2 from being exposed in the contact hole CT2 formation step. That is, even when the contact hole CT2 is formed, it is possible to maintain the state where the insulating film GI on the inner surface (side surface and bottom surface) of the trench TR2 is covered with the conductive film CD1. For this reason, in the etching process for forming the contact hole CT2, it is possible to prevent the insulating film GI on the inner surface of the trench TR2 from being exposed from the contact hole CT2 and receiving etching damage. Therefore, the reliability of the manufactured semiconductor device can be improved. In addition, the performance of the manufactured semiconductor device can be improved. For example, the breakdown voltage between the gate and the drain can be improved. In addition, gate leakage current can be suppressed.

  That is, as described in the examination examples of FIGS. 63 to 69, the contact holes CT202 and CT2 for leading the gate lead out the etching rather than the contact holes CT201 and CT1 for the source. However, in the present embodiment, the inner surface (bottom surface and side surface) of trench TR2 is covered with conductive film CD1 (here, a doped polysilicon film) having a substantially uniform thickness, and the surface (conductive film CD1). Is provided with a material film MT (here, a silicon oxide film) as an etching stopper film (etching mask). Therefore, in the present embodiment, this material film MT suppresses the preceding etching of the contact hole CT2 not only in the depth direction of the trench TR2 but also in the side surface direction of the trench TR2. As a result, the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not exposed from the bottom surface and side surface of the contact hole CT2 for leading the gate, and the insulating film GI on the inner surface (bottom surface and side surface) of the trench TR2 is not exposed. No more etching damage. Therefore, the reliability of the manufactured semiconductor device can be improved. In addition, the performance of the manufactured semiconductor device can be improved. For example, the breakdown voltage between the gate and the drain can be improved. In addition, gate leakage current can be suppressed.

  In the present embodiment, since the insulating film GI on the inner surface of the trench TR2 can be prevented from being exposed from the contact hole CT2 in the etching process for forming the contact hole CT2, the plug PG2 is prevented from contacting the insulating film GI. Can be prevented. Since the plug PG2 does not contact the insulating film GI, the area of the plug PG in contact with the insulating film can be reduced, so that the contact resistance of the plug PG2 can be reduced. Therefore, the reliability of the manufactured semiconductor device can be improved. In addition, the performance of the manufactured semiconductor device can be improved.

  In the present embodiment, the inner surface (bottom surface and side surface) of the trench TR2 for extracting the gate is covered with the conductive film CD1 having a substantially uniform thickness, and the trench TR2 covered with the conductive film CD1 constitutes the plug PG2. The conductive film (here, the barrier conductor film BR and the main conductor film MC1) is filled. Therefore, a large contact area can be ensured between the conductive film constituting the plug PG2 and the conductive film (conductive film CD1) formed integrally with the gate electrode GE. Therefore, the contact resistance of the plug PG2 can be reduced, and the good contact property of the plug PG2 can be obtained.

  In the present embodiment, it is possible to prevent the insulating film GI on the inner surface of the trench TR2 from being exposed from the contact hole CT2 in the etching process for forming the contact hole CT2 without increasing the width W2 of the trench TR2. it can. That is, the width W2 of the trench TR2 can be reduced while preventing the insulating film GI on the inner surface of the trench TR2 from being exposed from the contact hole CT2. For this reason, since the width of the trench TR2 can be suppressed, the semiconductor device can be reduced in size (reduced area). In the present embodiment, the width W2 of the trench TR2 for pulling out the gate can be less than twice the width W1 of the trench TR1 for trench gate (that is, W2 ≦ W1 × 2). In the etching process for forming the contact hole CT2, it is possible to prevent the insulating film GI on the inner surface of the trench TR2 from being exposed from the contact hole CT2. As a result, the reliability of the semiconductor device can be improved and the semiconductor device can be made smaller (smaller in area). Therefore, in the present embodiment, when the width W2 of the gate lead-out trench TR2 is suppressed, in particular, the width W2 of the gate lead-out trench TR2 is set to be not more than twice the width W1 of the trench gate trench TR1 (that is, If applied to the case of W2 ≦ W1 × 2), the effect is extremely large.

  63 to 69, if the side surface of the trench TR202 has a taper, the contact hole CT202 is formed in the etching process for forming the contact hole CT202 due to the variation (variation) in the taper angle. In some cases, the insulating film GI201 on the inner surface of the trench TR202 is likely to be exposed from the CT202. On the other hand, in this embodiment, even if the taper angle of the side surface of the trench TR2 fluctuates (varies), the insulating film on the inner surface of the trench TR2 from the contact hole CT2 in the etching process for forming the contact hole CT2 is used. It is possible to prevent GI from being exposed. For this reason, if this embodiment is applied when the side surface of the trench TR2 has a taper, the effect is great. Further, since the side surface of the trench TR2 is tapered, the embedding property of the conductive film for the plug PG2 (here, the barrier conductor film BR and the main conductor film MC1) in the trench TR2 can be improved.

  Unlike the present embodiment, the trench TR202 is filled with the polysilicon film CD201a not including the etching stopper film as shown in FIGS. 63 to 65 to obtain the structure shown in FIG. 65, and then buried in the trench TR202. Assume that a film for an etching stopper is formed on the polysilicon film CD201a. However, in this case, the etching stopper film does not exist in the trench TR202, that is, the etching stopper film does not exist in the buried film (here, the polysilicon film CD201a) embedded in the trench TR202. The etching stopper film does not exist at a position facing the side surface of the trench TR201. In this case, since there is no etching stopper film at a position facing the side surface of the trench TR201, if side etching of the buried film (here, the polysilicon film CD201a) occurs when forming the contact hole, the side surface of the trench TR202 The insulating film GI201 is exposed. Therefore, it is difficult to completely prevent the insulating film GI201 from being exposed on the side surface of the trench TR202.

  Therefore, in order to reliably prevent the insulating film GI from being exposed on the side surface of the trench TR2 when forming the contact hole, the etching stopper film (here, the material film MT) is formed in the trench TR2 as in the present embodiment. That is, it is important that the etching stopper film (here, the material film MT) exists in the buried film (here, the laminated film LM2) buried in the trench TR2. In the present embodiment, the conductive film CD1 is conformally formed with a substantially uniform thickness on the inner surface (side surface and bottom surface) of the trench TR2, and the surface of the conductive film CD1 (the side opposite to the side in contact with the insulating film GI) is formed. The material film MT is formed on the surface. By doing so, an etching stopper film (in this case, the material film MT) exists opposite to the side surface of the trench TR2, and this functions as an etching stopper film when forming the contact hole. Therefore, side etching toward the side surface of the trench TR2 is performed. Can be suppressed or prevented. Thereby, it is possible to prevent the insulating film GI from being exposed at the time of forming the contact hole, not only on the bottom surface of the trench TR2. For this reason, it is possible to prevent the insulating film GI from being exposed to etching damage not only on the bottom surface but also on the side surface of the trench TR2 when the contact hole is formed. Therefore, the reliability of the manufactured semiconductor device can be improved accurately. In addition, the performance of the manufactured semiconductor device can be improved accurately. For example, the breakdown voltage between the gate and the drain can be improved accurately. In addition, the gate leakage current can be accurately suppressed.

  In the present embodiment, the gate lead trench TR2 is filled with the laminated film LM having the conductive film CD1, the etching stopper material film MT thereon, and the conductive film CD2 thereon. Therefore, a film (in this case, the material film MT) that serves as an etching stopper when forming the contact hole can be formed in a self-aligned manner with respect to the trench TR (TR1, TR2).

  In addition, when doped polysilicon films are used as the conductive films CD1 and CD2 and a silicon oxide film is used as the material film MT, supply / stop of oxygen gas is performed during the CVD film forming process of the polysilicon film. Only by this, the laminated film LM for filling the trench TR can be formed. Thereby, the etching stopper film (material film MT) can be provided in the film for filling the trench TR (laminated film LM) without increasing the number of manufacturing steps.

  Unlike the present embodiment, when the contact hole CT2 is formed in step S9a, the conductive film CD1 of the stacked film LM2 embedded in the trench TR2 at the bottom of the contact hole CT2 that penetrates the insulating film IL2. Suppose also exposed. In this case, the conductive film CD1 in the trench TR2 is also etched in step S9b. However, if side etching occurs at that time, the insulating film GI is exposed on the side surface of the trench TR2. On the other hand, in this embodiment, the contact hole CT2 is formed so as to penetrate the insulating film IL2 in step S9a. At this time, the trench TR2 is buried at the bottom of the contact hole CT2 that penetrates the insulating film IL2. Of the laminated film LM2, the conductive film CD2 is exposed, but the conductive film CD1 is not exposed. Thereby, in step S9b, the conductive film CD2 of the laminated film LM2 embedded in the trench TR2 is etched, and the material film MT functions as an etching stopper, thereby preventing the conductive film CD1 from being etched. For this reason, it is possible to accurately prevent the insulating film GI from being exposed on the side surface of the trench TR2 when the contact hole is formed.

  In the present embodiment, the width W4 of the conductive film CD2 in the stacked film LM2 embedded in the trench TR2 is slightly larger than the width (opening width) W3 of the contact hole CT2 in the portion formed in the insulating film IL2. (Ie, W4> W3), even a slight pattern shift (position shift of the opening OP2 of the photoresist pattern RP2) is acceptable. That is, even if there is a slight pattern shift, the conductive film CD2 is exposed in the laminated film LM2 embedded in the trench TR2 at the bottom of the contact hole CT2 formed in the insulating film IL2 in step S9a. CD1 can be prevented from being exposed. As a result, the semiconductor device can be easily manufactured. As the difference between the width W4 and the width W3, for example, about 120 nm to 240 nm can be suitably used.

  Here, the width W3 of the contact hole CT2 is shown in FIG. 46, which is the width of the contact hole CT2 on the lower surface of the insulating film IL2, and is parallel to the main surface of the substrate SUB (and hence the main surface of the epitaxial layer EP). It corresponds to the width (dimension) in the direction perpendicular to the extending direction of the trench TR2. Further, the width W4 of the conductive film CD2 in the laminated film LM2 embedded in the trench TR2 is the width of the conductive film CD2 on the upper surface (corresponding to the upper surface UPS2 in FIG. 28) embedded in the trench TR2. This corresponds to the width (dimension) in the direction parallel to the main surface of the SUB (and hence the main surface of the epitaxial layer EP) and perpendicular to the extending direction of the trench TR2. For this reason, the direction of the width W2 of the trench TR2, the direction of the width W3 of the contact hole CT2, and the direction of the width W4 of the conductive film CD2 are the same. When the side surface of the contact hole CT2 in the insulating film IL2 is not tapered or is small even if there is a taper, the width W3 of the contact hole CT2 is equal to the opening OP2 for forming the contact hole CT in the photoresist pattern RP2. It is approximately equal to the width W3a (W3 = W3a). Here, similarly to the width W3 of the contact hole CT2, the width W3a of the opening OP2 of the photoresist pattern RP2 (the width W3a is shown in FIG. 43) is also the main surface of the substrate SUB (therefore, the main surface of the epitaxial layer EP). ) And a width (dimension) in a direction perpendicular to the extending direction of the trench TR2.

  In this embodiment, the case where an n-channel trench gate type MISFET is formed on the substrate SUB has been described. As another form, the n-type and p-type conductivity types can be reversed. In this case, a p-channel type trench gate type MISFET is formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BE Back electrode BR Barrier conductor film CD1, CD2 Conductive film CD201, CD201a Polysilicon film CE Transistor cell region CP Semiconductor device CT, CT1, CT2, CT102, CT201, CT202 Contact hole EP, EP201 Epitaxial layer EP1 Insular part GE, GE201 Gate electrode GE101 Conductive film portion GI, GI101, GI201 Insulating film IL1, IL2, IL3, IL102, IL202 Insulating film LM, LM1, LM2 Laminated film M1 Wiring M1G Gate wiring M1S Source wiring MC1 Main conductor film MC2, MC3 Conductor Film MT Material film NR, NR201 n ⁺ type semiconductor regions OP1, OP2, OP3, OP201, OP202 Openings PG, PG1, PG2, PG102, PG201, PG202 Plugs PR, PR201 p Type semiconductor region RG1, RG2, RG3 region RG101 Upper corner portion RP1, RP2, RP202 Photoresist pattern (resist pattern, mask layer)
RS1, RS2 recess (recess, groove)
SB, SB201 Substrate body SN1 Silicon nitride film SO1 Silicon oxide film SUB, SUB101, SUB201 Substrate (semiconductor substrate)
SW1, SW2 Side surface T1, T2, T3 Film thickness TR, TR1, TR2, TR101, TR201, TR202 Groove UPS1, UPS2, UPS3 Top surface W1, W2, W3, W3a, W4 Width

Claims (19)

A method of manufacturing a semiconductor device having a trench gate type field effect transistor formed on a semiconductor substrate,
(A) preparing the semiconductor substrate;
(B) after the step (a), forming a first groove and a second groove connected to each other on the semiconductor substrate;
(C) a step of forming a first insulating film for a gate insulating film on the inner surfaces of the first and second grooves after the step (b);
(D) After the step (c), a first conductive film, a first material film on the first conductive film, and the first conductive film so as to fill the first and second grooves on the semiconductor substrate substrate, Forming a first film having a second conductive film on the first material film;
(E) after the step (d), leaving the first film in the first and second grooves and removing the first film outside the first and second grooves;
(F) After the step (e), a step of forming a second insulating film on the semiconductor substrate;
(G) After the step (f), a first contact hole that penetrates the second insulating film and exposes the first conductive film of the first film embedded in the second groove is formed by etching. The process of
(H) a step of filling the first contact hole with a third conductive film after the step (g);
Have
A gate electrode is formed by the first film embedded in the first trench,
The first material film is made of a material different from the first conductive film and the second conductive film,
The step (g)
(G1) The second insulating film is etched to form the first contact hole in the second insulating film, and the first film embedded in the second groove at the bottom of the first contact hole is formed. Exposing the second conductive film;
(G2) After the step (g1), the second conductive film of the first film exposed from the first contact hole is etched to remove the first material film of the first film from the first contact hole. Exposing,
(G3) After the step (g2), the first material film of the first film exposed from the first contact hole is etched to remove the first conductive film of the first film from the first contact hole. Exposing,
Have
The first material film is made of a material different from the first conductive film and the second conductive film,
In the step (g2), a method of manufacturing a semiconductor device, wherein etching is performed under a condition that the second conductive film is more easily etched than the first material film. In the manufacturing method of the semiconductor device according to claim 1,
In the step (g1), the second conductive film of the first film embedded in the second groove is exposed at the bottom of the first contact hole, but the second conductive film is embedded in the second groove. A method of manufacturing a semiconductor device, wherein the first conductive film of the first film is not exposed. The method of manufacturing a semiconductor device according to claim 2.
In the step (g), a second contact hole is also formed,
The method for manufacturing a semiconductor device, wherein the second contact hole is formed in a region adjacent to the first groove in the semiconductor substrate and spaced from the first groove. In the manufacturing method of the semiconductor device according to claim 3,
The semiconductor substrate is of a first conductivity type;
After the step (e) and before the step (f),
In a region adjacent to the first groove in the semiconductor substrate, a first semiconductor region of a first conductivity type for a source, and a first semiconductor region located below the first semiconductor region and opposite to the first conductivity type Forming a second conductivity type second semiconductor region;
Have
In the step (g), the second contact hole is formed so as to penetrate the second insulating film and the first semiconductor region and reach the second semiconductor region. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the first film remaining in the second trench in the step (e) is connected to the gate electrode. In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the third conductive film is electrically connected to the gate electrode through the first conductive film. The method of manufacturing a semiconductor device according to claim 6.
The method of manufacturing a semiconductor device, wherein an upper surface of the first film remaining in the second groove in the step (e) is lower than an upper surface of the semiconductor substrate outside the second groove. The method of manufacturing a semiconductor device according to claim 7.
A method of manufacturing a semiconductor device, wherein a film formed integrally with the gate electrode does not extend on an upper surface of the semiconductor substrate outside the first and second grooves. The method of manufacturing a semiconductor device according to claim 8.
In the step (g3), a method of manufacturing a semiconductor device, wherein the first material film is etched more easily than the first conductive film. In the manufacturing method of the semiconductor device according to claim 9,
In the step (g1) and the step (g2), dry etching is performed.
In the step (g3), wet etching is performed. The method of manufacturing a semiconductor device according to claim 10.
The first conductive film and the second conductive film are made of polysilicon,
The method of manufacturing a semiconductor device, wherein the first material film is made of silicon oxide or silicon nitride. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the step (g3) is performed continuously from the step (g2). In the manufacturing method of the semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein dry etching is performed in the step (g1), the step (g2), and the step (g3). In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the width of the second groove is 1 to 2 times the width of the first groove. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein a side surface of the second groove formed in the step (b) has a taper. In the manufacturing method of the semiconductor device according to claim 1,
The first conductive film and the second conductive film are made of polysilicon,
The first material film is made of silicon oxide,
In the step (d), the first conductive film, the first material film, and the second conductive film are continuously formed by the same film forming apparatus. A semiconductor device having a trench gate type field effect transistor formed on a semiconductor substrate,
A first groove and a second groove formed in the semiconductor substrate and connected to each other;
A gate electrode for the trench gate type field effect transistor formed in the first trench via a first insulating film for a gate insulating film;
A first conductive film formed on the inner surface of the second groove via the first insulating film;
An interlayer insulating film formed on the semiconductor substrate so as to cover the gate electrode;
A first contact hole penetrating the interlayer insulating film on the second groove and exposing the first conductive film in the second groove;
A first connecting conductor portion embedded in the first contact hole and electrically connected to the first conductive film in the second groove;
Have
The gate electrode includes: the first conductive film formed on the inner surface of the first groove so as to be in contact with the first insulating film; a first material film on the first conductive film; and the first material film The second conductive film,
The first conductive film and the second conductive film are formed of the same material,
The first material film is formed of a material different from the first and second conductive films,
The semiconductor device, wherein the first conductive film in the first groove and the first conductive film in the second groove are integrally formed. The semiconductor device according to claim 17.
The first conductive film and the second conductive film are made of polysilicon,
The semiconductor device, wherein the first material film is made of silicon oxide or silicon nitride. The semiconductor device according to claim 18.
In a region adjacent to the first groove in the semiconductor substrate, a first semiconductor region of a first conductivity type for a source and a second opposite to the first conductivity type and located under the first semiconductor region. A conductive second semiconductor region is formed,
A second contact hole penetrating the interlayer insulating film and the first semiconductor region and reaching the second semiconductor region;
A second connecting conductor portion embedded in the second contact hole and electrically connected to the first and second semiconductor regions;
A semiconductor device.

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