JP2014026409A - Method of synchronizing information terminal device and information terminal device - Google Patents

Abstract

A source device and a sleep target device are synchronized in real time.
A target device receives a synchronization signal from a source device during a sleep state (352). The target device transitions from the sleep state to the power-on state in response to receiving the synchronization signal (361). When it is detected that the target device has been accessed illegally during the transition to the power-on state, the synchronization is stopped (359). If there is no injustice, the synchronization data is received from the source device after transitioning to the power-on state (364).
[Selection] Figure 5

Description

  The present invention relates to a technique for synchronizing information terminal apparatuses in a sleep state, and further relates to a technique for synchronizing while ensuring security of an information terminal apparatus in a sleep state.

  In recent years, a single user often has a plurality of information terminal devices such as a desktop personal computer (desktop PC), a notebook personal computer (notebook PC), a tablet terminal device, and a smartphone. Then, there are cases where data is edited using a highly functional desktop PC that is easy to input in the office, and the edited data is desired to be continuously used on a notebook PC or tablet terminal when away from home. In this case, data synchronization is required between the information terminal devices.

  Patent Document 1 discloses an invention of an information communication apparatus that can perform data synchronization without the user being aware of it. The PDA that receives the synchronization data operates only in the wireless communication unit even when the power is turned off. When the personal computer whose data has been changed transmits synchronization data to the PDA, the PDA temporarily stores the synchronization data in the RAM of the wireless communication unit until the main body or schedule management software is activated.

  Thereafter, when the main body and the schedule management software are in an operating state, the PDA retrieves data from the RAM and executes synchronization. The document also inquires whether there is data to be updated in the PDA when there is no data to be updated by the personal computer. Is described in this document.

  Patent Document 2 discloses a technique for synchronizing a data base of an application server and a data base of an information terminal that is not always turned on. The data sent from the application server to the information terminal that is not powered on is temporarily stored in the data buffer of the packet communication device. The data stored in the buffer is sent after the information terminal is turned on. Patent Document 3 discloses a technique for setting an HDD password in a magnetic disk device.

JP 2002-190845 A JP 2002-182961 A JP 2008-52704 A

  When the data edited by the user on the desktop PC is synchronized with the notebook PC, the desktop PC becomes the source device and the notebook PC becomes the target device for the movement of the synchronization data. The target device is housed in a bag, for example, and transitions to a sleep state during synchronization. Since synchronization needs to be performed in the power-on state for both the transfer source and the transfer destination information terminal device, the notebook PC is taken out of the bag for the synchronization and is temporarily switched to the power-on state, and then returned to the sleep state again. This operation is necessary and cumbersome.

  There is a method of transferring synchronous data to a target device that is in a sleep state using the invention of Patent Document 1 or Patent Document 2. In the inventions of Patent Document 1 and Patent Document 2, when the power of the target device is stopped and cannot be synchronized, the data is temporarily stored in the buffer and the synchronization is performed after the power of the target device is activated. Is called. However, in such a method, when the size of the synchronization data increases, it is necessary to prepare a buffer corresponding to the size of the synchronization data. Therefore, the cost of the buffer increases particularly when transferring a large file such as an image or audio data. Furthermore, if the process of writing the buffer data to the disk drive at the timing of booting the notebook PC, the use of the processor or the disk drive competes with the boot process, resulting in a problem that the boot time of the target device is delayed.

  Therefore, the source device automatically transitions the target device from the sleep state to the power-on state, transfers the synchronization data, and transfers the synchronization data by performing a single transfer operation for transferring the synchronization data. It would be convenient if the target device could transition to the sleep state after the end. However, a further problem remains in order to automatically synchronize without performing an operation on the sleep target device.

  Since a portable target device such as a notebook PC is particularly likely to be stolen, the user usually sets a password in the disk drive. At this time, when the target device transitions to the power-on state by the synchronization signal received from the source device, the BIOS requires the user to input a password, and thus the target device must be operated.

  In order to avoid this, there is a method in which the BIOS automatically transmits the password stored in the secure area on behalf of the user to the disk drive. However, when the target device and the source device are connected wirelessly, it is necessary to assume that the target device is not under user supervision. A malicious third party attaches an eavesdropping device to the interface circuit of the disk drive and then activates the power supply by impersonating a synchronization signal so that the password sent from the BIOS to the disk drive can be eavesdropped. There is also a possibility that the synchronization data may be wiretapped by illegally attaching a USB memory or an external disk drive to the target device.

Accordingly, an object of the present invention is to provide a method for synchronizing a source device and a sleep target device in real time. It is a further object of the present invention to provide a method for synchronizing without operating a target device.
It is a further object of the present invention to provide a method for synchronizing while ensuring the security of the target device. It is a further object of the present invention to provide a method for synchronizing in a short time. A further object of the present invention is to provide a computer program and an information terminal device that realize such a method.

  One aspect of the invention provides a method in which a target device comprising a non-volatile storage is synchronized to a source device. The target device includes a nonvolatile storage device. The target device receives a synchronization signal from the source device during the sleep state. In response to the reception of the synchronization signal, the target device is activated and transitions to a power-on state. The target device receives synchronization data from the source device after transitioning to the power on state. The target device stores the received synchronization data in the storage device. According to such a configuration, the sleep target device can be synchronized in real time. Further, the user does not need to perform an operation for synchronization with respect to the target device.

  If the source device and target device have a direct wireless connection that does not go through a wireless access point connected to the backbone network, the target device may receive synchronization signals and data over the direct wireless connection. it can. By adopting such a configuration, it is possible to synchronize with a place where the backbone network cannot be used or a device which cannot participate in the backbone network.

  The synchronization signal can be included in a beacon frame transmitted by the source device. When a synchronization signal is transmitted using a beacon frame, the authentication and association procedures by the wireless module and the boot procedure can be performed in parallel, so that the synchronization processing time can be shortened. The synchronization signal can be included in a connection request frame transmitted by the source device. If the target device transmits a connection response frame in response to the connection request frame and starts the power supply after the association is completed, the target device can be booted with the confirmed synchronization signal from the target device.

  The target device can determine whether there is unauthorized access during booting. When entering the power-on state, when it is determined that there is no unauthorized access, the user's password input to the storage device to which the password is set is skipped, and when it is determined that there is unauthorized access, the power-on state The transition to can be stopped. Therefore, it is possible to synchronize the target device while ensuring the security of the target device while omitting a user operation on the target device.

  Whether or not there is an unauthorized access can be determined by whether or not the storage device has been removed from the target device between the previous boot and the current boot. Alternatively, the presence or absence of unauthorized access can also be determined by whether or not the boot device has been changed since the previous boot. At the time of transition to the power-on state, initialization of a device that is not required for synchronization can be skipped to shorten the time for synchronization processing.

  When transitioning to the power-on state, the interface controller for the output device connectable to the target device can be disabled. As a result, it can be prevented that the output device is illegally connected and the synchronization data is wiretapped. The target device can transition to the sleep state in response to the end of storing the synchronization data. Therefore, the target device can be returned to the original sleep state without performing any operation between the start and end of synchronization.

  In another aspect of the invention, a method is provided for a source device to synchronize a target device whose processor is stopped. The source device generates synchronization data. In response to the synchronization start operation, the source device transmits a synchronization signal for operating the processor to the target device. In response to the processor operating, the source device sends synchronization data to the target device. The synchronization signal can be transmitted when the source device searches for the target device using an active scanning scheme of wireless communication.

  According to the present invention, it is possible to provide a method for synchronizing a source device and a sleeping target device in real time. Furthermore, according to the present invention, it is possible to provide a method of synchronizing without operating the target device. Furthermore, according to the present invention, it is possible to provide a method of synchronizing while ensuring the security of the target device. Furthermore, according to the present invention, a method for synchronizing in a short time could be provided. Further, according to the present invention, it is possible to provide a computer program and an information terminal device that realize such a method.

It is a figure explaining the outline | summary of the synchronous process concerning this Embodiment. It is a functional block diagram which shows the main structures of the notebook PC 100 concerning this Embodiment. It is a truth table which judges the presence or absence of fraud with respect to SSD123. It is a figure which shows the data structure of BIOS_ROM125. It is a flowchart which shows the procedure of a synchronous process. It is a flowchart which shows the procedure of the boot process in a target device. It is a flowchart which shows the procedure of the boot process in a target device. It is a flowchart which shows the other procedure of a synchronous process.

[Overview of synchronization processing]
FIG. 1 is a diagram for explaining the outline of the synchronization processing according to the present embodiment. As an example, FIG. 1 shows a state in which information terminal devices such as a desktop PC 11, a notebook PC 13, a tablet terminal 15, a PDA 17, and a smartphone 19 are directly connected to each other by wireless to form a network. The desktop PC 11 and other information terminal devices are directly connected to each other wirelessly without going through a WLAN access point (AP) 33 connected to the backbone network 31. Such a direct wireless connection method between devices is hereinafter referred to as device-to-device (D2D) connection. The ad hoc mode defined in IEEE 802.11 is a typical example of D2D connection.

  The D2D connection enables synchronization processing in an environment where no WLAN exists, and synchronization processing in a group including information terminal devices that cannot participate in the WLAN. However, it will be apparent from the following description that the present invention can be applied to a case where information terminal devices are connected to each other by wire or a case where they are connected via a WLAN network via the AP 33. These information terminal devices, for example, are owned by the same user or constitute specific members to establish a mutual trust relationship.

  In one example, the desktop PC 11 includes a keyboard and a large display, and has an advanced editing function. The user edits data on the desktop PC 11 and tries to synchronize other information terminal devices with newly created synchronization data or synchronization data related to a difference from the previous synchronization. Hereinafter, the desktop PC 11 that is the transfer source of the synchronization data is referred to as a source device. On the other hand, the notebook PC 13, the tablet terminal 15, the PDA 17, and the smartphone 19 serve as transfer destinations of the synchronization data, and are hereinafter collectively referred to as target devices.

  The relationship between the source device and the target device need not be fixed, and any device that has edited data can be a source device. The source device and the target device both implement the same or compatible application program (application). The target device transitions to a sleep state described later at least when synchronous data is transferred.

  The user operates on the source device for synchronization but does not need to operate on the target device. The target device transitions from the sleep state to the power-on state in response to an operation on the source device, and returns to the original sleep state when synchronization is completed. The target device transitions from the sleep state to the power-on state while ensuring security.

[Information terminal equipment and power state]
FIG. 2 is a functional block diagram illustrating a hardware configuration of the notebook PC 100 as an example of the information terminal device. Since many hardware configurations are well known, they will be described here within the scope necessary for the present invention. The notebook PC 100 can be either a source device or a target device. A CPU 111, a main memory 115, a video controller 117, and an I / O control hub (ICH) 121 are connected to the memory control hub (MCH) 113. An LCD 119 is connected to the video controller 117.

  The ICH 121 has various standard interface functions. In FIG. 1, the SSD 123 is typically connected to the SATA, the BIOS_ROM 125 is connected to the SPI, the USB terminal 126 is connected to the USB, and the WLAN module 127 is connected to the PCIe. An embedded controller (EC) 131 and NVRAM 133 are connected to the LPC. Registered in the secure storage area of NVRAM 133 are BIOS passwords such as power-on passwords and SSD passwords, MAC addresses of group members that synchronize data, and special ESSIDs and authentication codes used by group members for synchronization. Has been.

  A keyboard 129 and a power controller 135 are connected to the EC 131. A control circuit of the DC / DC converter 139 and a power button 145 are connected to the power controller 135. The power controller 135 is further connected to the SSD 123 by a tamper detection line 141 and is connected to the WLAN module 127 by a synchronization event line 143.

  The notebook PC 100 supports ACPI (Advanced Configuration and Power Interface) power saving function and plug and play. ACPI defines four sleeping states (sleep state), S0 state (power-on state), and S5 state (power-off state) from the S1 state to the S4 state. The notebook PC 100 defines only the S3 state and the S4 state in the ACPI sleep state.

  The S3 state is referred to as a so-called suspend state, in which the storage of the main memory 115 is retained, and the power supply that is not necessary for the retention of the main memory 115 is stopped. When entering the S3 state, the operating system (OS) saves the system context held by the device whose power is stopped to the main memory 115, and returns to each device when the power is restored.

  The S4 state is a power state that takes the longest time to return among sleep states supported by ACPI, and is called a hibernation state. When the notebook PC 100 transitions from the S0 state to the S4 state, if the OS stores the system context immediately before the notebook PC 100 including the stored contents of the main memory 115 in the SSD 123, the EC 131 may be the power controller 135 or the lid sensor. The power supply to devices other than the minimum device necessary for starting the power supply (not shown) is stopped.

  The S5 state is a so-called soft-off power state and basically has the same device range as the S4 state except that the OS does not save the context to the SSD 123. Hereinafter, the S3 state, the S4 state, and the S5 state are collectively referred to as the Sx state. In contrast to the Sx state, the S0 state is a state in which power is supplied to all devices necessary for the notebook PC 100 to operate and the boot or resume is completed. The operation of transition from the Sx state to the S0 state is referred to as wakeup as appropriate.

  In the present invention, the S34 state is further defined based on the viewpoint of whether the execution subject on software when the power state is changed is the OS or the BIOS. The S34 state is a state in which the OS changes from the S0 state to the S3 state, and then the BIOS automatically changes from the S3 state to the S4 state. Since the OS performs the process of shifting from the S0 state to the Sx state, in principle, the power state recognized by the OS matches the actual power state. In contrast, in the S34 state, the OS recognizes that the transition destination is the S3 state, but the power supply state and the data state substantially correspond to the S4 state.

  When the OS transitions to the S3 state, the system context includes a code for returning from the S3 state to the S0 state, and thus cannot directly return from the S34 state to the S0 state. When returning from the S34 state to the S0 state, it is necessary for the OS that has taken over the control right from the BIOS after the BIOS temporarily returns the system from the S34 state to the S3 state to return from the S3 state to the S0 state.

  On the other hand, when transitioning to the S4 state, after the OS writes the system context into the main memory 115, the OS saves the data stored in the main memory 115 to the SSD 123. Since the OS includes a code for returning from the S4 state to the S0 state in the system context, the system can directly return the system from the S4 state to the S0 state. When the state transitions from the S0 state to the S34 state, the time that remains temporarily in the S3 state is referred to as S34 time. In this specification, the S34 state is described as being included in the sleep state and the Sx state.

  When transitioning from the Sx state to the S0 state, the BIOS executes POST (Power On Self Test) for the reset device. The POST can use the code stored in the BIOS_ROM 125 after setting the reset signal to the CPU 111 and starting the loading of the OS by setting parameters in the controller and peripheral devices of the chip sets 113 and 121. Refers to the work to make a state. POST is all processing performed by the BIOS code from when the CPU 111 is reset to when the OS starts loading, or processing other than initialization for basic devices such as the CPU 111 and the main memory 115 from among them. It may be processing without the.

  The ICH 121 includes an RTC (Real Time Clock) and an RTC memory 151 (not shown). The RTC and RTC memory 151 can receive power from the button battery when the power of the AC / DC adapter and the battery pack is stopped and power is not supplied from the DC / DC converter 139 to the ICH 121. The RTC memory 151 is a volatile memory that stores BIOS setup data, time information generated by the RTC, and the like. The RTC memory 151 stores an S34 flag and an S34 time that the BIOS refers to when making a transition to the S3 state. The S34 flag and S34 time are set in the RTC memory 151 when the BIOS set-up code 233 (see FIG. 4) sets S34 enable in the data area 283 of the BIOS_ROM 125.

  The S34 flag instructs the BIOS to perform the process of transitioning to the S34 state when the OS transitions the notebook PC 10 to the S3 state, or the BIOS detects unauthorized access to the SSD 123 and determines the execution path. It is information to do. The S34 time is the time from when the OS changes the system to the S3 state until the BIOS automatically changes to the S34 state.

  The ICH 121 includes a register 153 defined by ACPI and registers 155 and 157. The registers 153, 155, and 157 are maintained in the Sx state. The register 153 corresponds to an SLP_TYP register and an SLP_EN register defined in ACPI. When the register 153 transits from the S0 state to the Sx state, the transition destination power state is set by the OS. In the register 155, a time-up bit is set by the RTC when S34 time has elapsed since the transition to the S3 state. A synchronization bit is set in the register 157 when the WLAN module 127 outputs a synchronization event.

  The SSD 123 is an example of a disk drive, and is a large-capacity storage device having a storage area composed of a flash memory for storing an OS, a device driver, an application, a utility program, user data, and the like. A user can set a password in the SSD 123 through an interface provided by the authentication code 211. The notebook PC 100 may be equipped with a hard disk drive or other nonvolatile storage device instead of the SSD 123. The SSD 123 stores an editing application 191, a synchronization utility 193, and synchronization data 195 that are directly related to the synchronization processing of the present embodiment.

  The editing application 191 can be a program that creates data such as documents, images, and videos. The synchronization utility 193 is a program that performs processing for authentication and data transmission / reception for synchronization. The synchronization data 195 corresponds to data created by the user through the editing application 191 when the notebook PC 100 operates as a source device, and the editing application received from the source device when the notebook PC 100 operates as a target device. 191 corresponds to the data associated with 191. The SSD 123 stores a boot image that is loaded when the notebook PC 100 starts up as a boot device. The storage area of the SSD 123 is divided into a system area and a user area.

  The system area stores the firmware of the SSD 123 and is an area in which access for data writing or reading by the user is prohibited. When the BIOS sends the SSD password and the lock command to the SSD 123, the firmware sets the SSD password and stores the set SSD password in the system area. When the BIOS sends the SSD password and a lock release command to the SSD 123 in which the SSD password is set, the firmware authenticates and releases the lock, and permits access from the system to the user area. Note that the SSD 123 with the password set is automatically locked again when the power is stopped or a reset signal is supplied even if the lock is once released. The data structure of the BIOS_ROM 125 will be described later with reference to FIG. The WLAN module 127 that performs D2D communication will also be described later.

  The EC 131 is a microcomputer composed of a CPU, ROM, RAM, and the like, and further includes a plurality of channels of A / D input terminals, D / A output terminals, timers, and digital input / output terminals. The EC 131 can execute a program related to management of the operating environment inside the notebook PC 10 independently of the CPU 111. The EC 131 includes a keyboard controller.

  The power controller 135 is a wired logic digital control circuit (ASIC) that controls the DC / DC converter 139 based on an instruction from the EC 131. The power controller 135 includes registers 181, 183, and 185. The power supply of the power controller 135 is maintained even in the Sx state. The DC / DC converter 139 converts a DC voltage supplied from an AC / DC adapter (not shown) or a battery pack into a plurality of voltages necessary for operating the notebook PC 100, and is defined according to the power state. Power is supplied to each device based on the power supply category.

  When the power controller 135 receives a synchronization event from the WLAN module 127 through the synchronization event line 143, the power controller 135 causes the DC / DC converter 139 to supply power to all devices operating in the power-on state. Control. When the power controller 135 receives a synchronization event from the WLAN card 127 through the synchronization event line 143, the power controller 135 sets the register 185 to a logical value 1 (synchronization bit). The EC 131 writes the synchronization bit of the register 185 to the register 157 of the ICH 121. The WLAN module 127 can also send a synchronization event to the power controller 135 through the ICH 121 and the EC 131. In this case, it is necessary to supply power to the circuit that processes the synchronization event of the ICH 121 and the EC 131 during the transition to the sleeping state.

  The tamper detection line 141 is pulled up by the same power source as the power controller 135. The SSD 123 maintains the potential of the tamper detection line 141 at the ground level while being mounted on the notebook PC 100. When the SSD 123 is removed from the notebook PC 100, the potential of the tamper detection line 141 rises. When the logic circuit of the power controller 135 detects the leading edge when the potential of the tamper detection line 141 rises, it sets the register 181 to the logic value 1 (tamper bit).

  The BIOS sets the register 183 to the logical value 1 (power bit) and sets the register 181 to the logical value 0 when the boot is successful after completing the authentication of the power-on password or the SSD password. When waking up from the Sx state, the BIOS determines whether the SSD 123 is removed from the ICH 121 during the Sx state in the truth table shown in FIG.

  If the SSD 123 is removed from the ICH 121 and reattached during the sleep state, the potential of the tamper detection line 141 once rises to zero. The logic circuit of the power controller 135 detects the leading edge of the potential of the tamper detection line 141 and sets the tamper bit of the register 181 to the logic value 1. If the power of the power controller 135 is stopped during the sleep state, the tamper bit of the register 181 is cleared to a logical value of 0, but at the same time, the power bit of the register 183 is also cleared to a logical value. 0.

  Such a situation also occurs when an eavesdropping device is inserted between the SSD 123 and the ICH 21, so that the BIOS can determine that unauthorized access to the SSD 123 has occurred using the truth table. As described above, when the SSD 123 is removed from the notebook PC 100 between the previous boot and the current boot, the BIOS can be updated regardless of whether the same SSD 123 is remounted or a new SSD is remounted. It can be detected at boot time.

[D2D communication]
The D2D communication can be performed jointly by the device driver and OS and the WLAN module 127. The WLAN module 127 may be configured to connect to the backbone network 31 and perform wireless communication in the infrastructure / rature mode simultaneously with or by switching the D2D communication. The WLAN module 127 may be configured to connect only to one or a plurality of information terminal devices in the ad hoc mode when performing D2D communication. Alternatively, the WLAN module 127 may be configured to connect to a plurality of information terminal devices using a technique called “Soft AP”.

  For D2D communication, Windows 7 (registered trademark) equipped with a function such as "Virtual WiFi" that virtualizes one wireless controller to make it appear to multiple wireless controllers and a "Soft AP" function that emulates the function of an AP is adopted. can do. Alternatively, Intel (Intel is a registered trademark) My WiFi Technology can be used. In the present embodiment, a communication technology called WiFi Direct established by the WiFi Alliance will be described as an example. When WiFi Direct is adopted, one information terminal device functions as a Soft AP to enable connection of a plurality of information terminal devices, and D2D communication that does not use an AP or router with information terminal devices that form a group Can do.

[Configuration of BIOS_ROM]
FIG. 4 shows the data structure of the BIOS_ROM 125. As shown in FIG. The BIOS code stored in the BIOS_ROM 125 is configured by UEFI firmware as an example. The BIOS_ROM 125 includes a BIOS area 281 for storing the BIOS code and a data area 283 used by the BIOS code. The BIOS_ROM 125 employs a boot block method in order to reduce the risk associated with rewriting the BIOS code. The BIOS area 281 is divided into a boot block 285 and a system block 287. The boot block 285 is a storage area that is write-protected, and the program stored here is treated as a CRTM (Core Root of Trust for Measurement) defined in the TPM (Trusted Platform Module) specification and has no special authority. It cannot be rewritten.

  In the boot block 285, the basic device initialization code 201, the consistency authentication code 203, the POST selection code 205, and the save code 207 are stored as CRTM. The CRTM is configured as a consistent part in the BIOS code and is always executed first when the notebook PC 100 boots. The basic device initialization code 201 is stored in the CPU 111, the main memory 115, and the main memory 115, which are necessary for processing from loading the BIOS code to the main memory 115 and starting execution when the notebook PC 100 is powered on and wakes up. Other basic device detection, inspection, and initialization are performed to the minimum extent. The consistency authentication code 203 measures all the consistency regarding the platform of the notebook PC 100.

  The POST selection code 205 refers to the registers 153 and 157 of the ICH 121, the S34 flag of the RTC memory 151, and the registers 181 and 183 of the power controller 135, and either the basic POST code 209, the simple POST code 213 or the S3 POST code 215 is selected. The execution path is controlled by determining whether to execute. When the power source is activated due to a synchronization event generated by the WLAN module 127, the POST selection code 205 continues booting only when the transition source is any of the S3 state, the S34 state, and the S4 state.

  The POST selection code 205 selects the simple POST code 213 when waking up from the S34 state or the S4 state due to a synchronization event generated by the WLAN module 127. The POST selection code 205 selects the S3 POST code 215 when waking up from the S3 state due to a synchronization event generated by the WLAN module 127.

  The POST selection code 205 interrupts the wake-up and forcibly shuts down when it detects an unauthorized access to the SSD 123 performed during the sleep state or when the boot device is changed. The save code 207 transfers the state of the main memory 115 in the S3 state to the SSD 123 when transitioning from the S0 state to the S34 state. Unlike the OS, the save code 207 does not recognize the data structure of the storage area of the main memory 115. Therefore, in principle, the save code 207 indicates the storage state of the entire address of the main memory 115 from the start address to the end address of the storage area. Copy exactly to SSD123.

  The basic POST code 209 is detected and inspected for all internal devices when waking up from the S4 state or S5 state for reasons other than the synchronization event generated by the WLAN module 127, such as pressing the power button 145. , And complete POST processing such as initialization. The basic POST code 209 outputs an error due to a beep sound or a screen display when a predetermined device cannot be detected or when it is determined that the device does not operate normally as a result of the inspection. The basic POST code 209 acquires parameters from peripheral devices connected to the MCH 113 and the ICH 121, selects the optimum parameters in the current system, and sets them in the controller included in the MCH 113 and the ICH 121.

  In this way, inspecting the internal device and setting the optimal parameter selected based on the information obtained from it in the controller is called initialization, and the parameter set in the past saved in one of the locations is called initialization. Setting to the corresponding controller is called restoration. The restoration can be completed in a shorter time than the initialization because the processing for detecting the internal device, inspecting, and selecting the optimum parameter is omitted.

  The authentication code 211 displays a prompt for setting a BIOS password such as a power-on password, an SSD password, and an administrator password on the LCD 119, sends the input power-on password to the system, or The SSD password is sent to the SSD 123 to release the lock. When any BIOS password is set, the authentication code 211 is always executed when the basic POST code 209 is being executed or when it is terminated. If no BIOS password is set, the authentication code 211 is not executed even if the control right is transferred.

  The simple POST code 213 completes booting in a shorter time than the basic POST code 209 by omitting POST processing such as detection of some devices, inspection, and selection of optimum parameters when waking up. The simple POST code 213 omits POST processing for devices such as USB devices, keyboards 129 and the like that are not necessary for synchronization processing, and devices that do not have any problem even if the OS is initialized from the timing of operation. Can do.

  The simple POST code 213 stores the optimum parameters set by the basic POST code 209 when booting from the S4 state or the S5 state, the device information at that time, etc. in the data area 283 of the BIOS_ROM 125 or the NVRAM 133 and boots. Sometimes the POST time can be shortened by restoring the stored parameters except for the basic device.

  The simple POST code 213 is configured for the purpose of shortening the recovery time as compared with the basic POST code 209, and therefore does not require the user to input a power-on password and an SSD password. The simple POST code 213 automatically sends the power-on password and SSD password stored in the NVRAM 133 on behalf of the user to the system and the SSD 123 to release the lock. The simple POST code 213 can disable the interface controller for an external output device such as ESTA or USB of the ICH 121.

  The S3POST code 215 is called and executed by the SMI handler when transitioning from the S3 state to the S0 state. The S3 POST code 215 completes the POST process in a shorter time than the simple POST code 213. The parameters set by the basic POST code 209 when booting from the S4 state or the S5 state are stored in the main memory 115 in the S0 state. When suspending from the S0 state to the S3 state, the parameters stored in the main memory 115 and the storage of the S3 POST code 215 are maintained. The S3 POST code 215 can complete the controller setting in a short time by restoring the parameters stored in the main memory 115.

  Similar to the simple POST code 213, the S3 POST code 215 automatically sends the power-on password and the SSD password instead of the user input to release the lock. Similar to the simple POST code 213, the S3 POST code 215 can disable the interface controller for an external output device such as ESTA of the ICH 121 or USB.

  The I / O code 231 provides an input / output interface for accessing peripheral devices when the CPU 111 operates in the real mode. The BIOS setup code 233 provides an interface for the user to customize settings for internal devices such as boot drive selection, enable / disable features of each device, enable / disable security, etc. . When booting, if a predetermined key is operated before the OS is loaded, the BIOS setup code 233 is executed, and the BIOS setup screen is displayed on the LCD 119.

  Most of the setup data set by the user is stored in the RTC memory 151 in the ICH 121. The CPU 111 refers to the setup data stored in the RTC memory 151 when executing the basic POST code 209, the simple POST code 213, or the S3 POST code 215. The user can set the boot device order through the BIOS setup code 233.

  For example, the external USB memory, ODD, and SSD 123 can be set in this order. In this case, if an external USB memory is not connected to the USB terminal 126 and no bootable medium is attached to the ODD, the SSD 123 is booted. However, when an external USB memory that can be a boot device is illegally connected to the USB terminal 126 when waking up for synchronization, there is a possibility that the USB memory boots and the synchronization data is wiretapped. . In the present embodiment, measures against such an action are also taken as described later.

  The user can enable or disable the use of the S34 state through the BIOS setup screen. Further, when the use of the S34 state is enabled, the S34 time can be set. The set S34 enable flag and S34 time are stored in the data area 283. The BIOS set-up code 233 sets the S34 flag and the S34 time in the RTC memory 151 at the same time when the S34 state is set to enable.

  The environmental utility code 235 controls the temperature and power of the notebook PC 100. Each BIOS code does not need to be composed of independent codes as shown in FIG. 4, but may be configured to control an execution path so that a part of the code is shared and each function is performed. The present invention can also be applied to a BIOS_ROM that does not employ a boot block method, or a BIOS_ROM in which the entire BIOS area is a boot block.

[Overall synchronization steps]
FIG. 5 is a flowchart showing an operation procedure when the source device and the target device are synchronized. Both the source device and the target device will be described using the notebook PC 100 as an example. When it is necessary to distinguish between the components of the source device and the target device, the reference numbers shown in FIG. 2 and FIG. 4 are distinguished by adding S for the source device and T for the target device. I will do it. Although the description will focus on the case where only one target device exists, the procedure for synchronizing a plurality of target devices is also understood in this description.

  Compatible editing applications 191S and 191T and synchronization utilities 193S and 193T are installed in the source device and the target device. The source device and the target device store the ESSID, MAC address, authentication code, and the like used for synchronization in advance in the NVRAM 133S, 133T in order to form a synchronizable group.

  Blocks 301 to 311 show the operation of the source device, and blocks 351 to 367 show the operation of the target device. In block 301, the source device is powered on, and the user creates or edits data through the editing application 191S and updates the synchronization data 195 stored in the SSD 123S. In block 351, the target device has transitioned to one of the sleep states (S3, S34, S4).

  In any sleep state, the target device is supplied with power to at least the WLAN module 127T and the power controller 135T. The WLAN module 127T mounted on the target device in the sleep state may operate in a power save mode in which radio waves can be scanned so as to be able to wake up when synchronization is requested. Note that the target device may be able to wake up and synchronize even in the S5 state.

  In block 303, the user accesses the synchronization utility 193S and clicks an icon displayed on the LCD 119 to perform an operation for starting synchronization. Alternatively, synchronization may be automatically started by using an update of a file to be synchronized on the source device or a power control event such as sleep or shutdown as a trigger. In block 305, the WLAN module 127S broadcasts a probe request frame including a special ESSID used for synchronization and the MAC address of the other party to search for a target device using an active scanning method. The WLAN module 127T of the target device sends back a probe response frame to the target device when the received ESSID and MAC address match the pre-registered data. After that, authentication and association are performed between the two to establish a connection. In block 352, the target device recognizes that the synchronization signal has been received because the connection has been established.

  At block 353, in response to the synchronization signal, the WLAN module 127T sends a synchronization event to the power controller 135T. Receiving the synchronization event, the power controller 135T sets the synchronization bit in the register 185 and controls the DC / DC converter 139T to supply power to the device operating in the S0 state. At this time, since the synchronization event is generated after the authentication is performed in blocks 305 and 352, it is possible to prevent the power source from being activated by the information terminal device impersonating the ESSID and the MAC address. The EC 131T refers to the register 185T and sets a synchronization bit in the register 157T. At block 355, execution of the BIOS CRTM (FIG. 4) begins. In block 357, the BIOS checks for the presence of fraud on the target device that may have occurred between the previous wakeup and the current wakeup.

  The presence / absence of fraud is determined by whether the SSD 123 has been removed or the boot device has been changed. If there is a fraud, the target device shuts down autonomously at block 359 to stop accepting synchronization data. The shutdown is an example of an operation for stopping synchronization, and the boot may be stopped at that time. If there is no fraud, the OS and synchronization utility 193T are loaded at block 361, the boot is completed, and the state transitions to the S0 state.

  The BIOS notifies the executing synchronization utility 193T that the synchronization bit is set in the register 157T. The synchronization utility 193T notifies the source device that preparation for synchronization has been completed. In blocks 307 and 363, mutual authentication is performed between the synchronization utility 193S of the source device and the synchronization utility 193T of the target device. The source device authenticates the target device with the authentication code received from the target device and confirms that it is a partner to which synchronization data can be sent.

  Similarly, the target device authenticates the source device with the authentication code received from the source device, and confirms that the target device can receive synchronization data. Note that authentication of the source device by the target device may be omitted. In block 309, the synchronization utility 193S transfers the synchronization data 195T related to the difference of the editing application 191S from the previous synchronization and the identifier of the editing application 193S to the target device.

  In the target device that received the synchronization data and the identifier in block 364, the editing application 193T corresponding to the editing application 193S is activated. Then, the synchronization data 195S is written to the SSD 123T in association with the application 193T. When the synchronization is successful, the synchronization utility 193T notifies the synchronization utility 193S of this in block 365. The synchronization utility 193S can retransmit the synchronization data 195S when it does not receive a notification of successful synchronization even after a predetermined time has elapsed since the transmission of the synchronization data 195S.

  In block 311, the synchronization utility 193 </ b> S ends the synchronization in block 311 and notifies the synchronization utility 193 </ b> T when the synchronization success notification is received or if the synchronization success notification is not received after a predetermined time elapses. To do. Recognizing the end of synchronization in block 367, the synchronization utility 193T causes the target device to transition to the same sleep state as block 351 through the OS. When there are a plurality of target devices, the procedures of blocks 305 to 311 and blocks 352 to 367 are performed for each target device. During the synchronization process, the user only has to start the synchronization through the connection utility after editing on the target device, and does not need to perform any operation on the target device.

[BIOS Processing Procedure for Wake-up]
Next, a boot procedure executed by the BIOS in blocks 352 to 361 in FIG. 5 will be described with reference to FIG. In block 501, it is assumed that an unauthorized operation is performed on the target device that is transitioning to the sleep state. In block 503, the synchronization signal received from the source device powers up the target device. In block 505, the CPU 111 executes the POST selection code 205T. In block 507, the POST selection code 205T determines whether the synchronization bit is set in the register 157T. When the synchronization bit is set, the process proceeds to block 511, and when the synchronization bit is not set, the process proceeds to block 509. In block 509, since the CPU 111 is reset for a reason other than synchronization, another procedure is executed.

  In block 511, the POST selection code 205T determines whether an SSD password is set in the SSD 123T. If the SSD password has been set, the process proceeds to block 513, and if not, the process proceeds to block 515. In blocks 513 and 515, the POST selection code 205T determines whether or not there is unauthorized access to the SSD 123T with reference to the truth table of FIG. In block 513, the POST selection code 205T refers to the register 183T to confirm the power bit. When the power bit is set, the process proceeds to block 515, and when the power bit is cleared, the process proceeds to block 517 because it corresponds to a case where fraud is detected.

  In block 515, the POST selection code 205T confirms the tamper bit with reference to the register 181T. When the tamper bit is set, this corresponds to the detection of unauthorized access to the SSD 123T, and the process proceeds to block 517. When the tamper bit is not set, this corresponds to the detection of unauthorized access to the SSD 123T, and the process proceeds to block 515.

  In block 515, the POST selection code 205T determines whether the boot device has been changed between the previous boot and the current boot. A case where the boot device is changed is, for example, a case where the USB memory is illegally connected in this boot as a boot device having a higher selection order that has not been used in the previous boot. In order for a genuine user to use the USB memory as a boot device, it is necessary to start with the power button 145T instead of the synchronization signal.

  When the boot device has been changed, the process proceeds to block 517. When the boot device has not been changed, it is determined that there has been no fraud, and the process proceeds to block 551 in FIG. In block 517, the POST selection code 205T stops booting and forcibly shuts down the target device through the EC 131. At this time, the POST selection code 205T may notify the user that the boot is stopped by a beep sound.

  In block 551 in FIG. 7, the POST selection code 205T determines whether or not the S3 bit is set in the register 153T. When the S3 bit is not set, it is determined that the transition is from the S4 state, and the process proceeds to block 555. When the S3 bit is set, in block 553, the POST selection code 205T refers to the RTC memory 151T and determines whether or not the S34 flag is set. When the S34 flag is set, it is determined that the transition is from the S34 state, and the process proceeds to block 555.

  In block 555, control is transferred from the POST selection code 205T to the simple POST code 213T. The simple POST code 213T automatically sends the SSD password to the SSD 123T at block 557, and automatically sends the password to the system if a power-on password is set. In block 559, the simple POST code 213T omits POST of devices unnecessary for synchronization, and disables the interface controller for externally connected output devices such as USB memory and SSD that may be illegally connected in block 561. Set.

  In block 563, the process after POST ends differs depending on whether the transition source is the S34 state or the S4 state. In the transition from the S34 state, the simple POST code 213T returns the storage state of the main memory 115 saved to the SSD 123T in the S34 state to the main memory 115. The simple POST code 213T clears the S34 flag of the RTC memory 151. At this time, the data state of the target device is the S3 state, but the power supply state is the S0 state.

  When the data transfer to the main memory 115 is completed, the simple POST code 213T transfers the control right to the OS. The OS recognizes that the power state of the transition source is the S3 state by referring to the register 153, and changes the system context in cooperation with the device driver and the BIOS as necessary in order to transition to the S0 state. Return to the register of each reset device. At the time of transition from the S4 state, the system state in which the OS transferred from the simple POST code 213T has been saved in the SSD 123T is restored to the main memory 115T and the register.

  In block 573, control is transferred from the POST selection code 205T to the S3 POST code 215T. The procedure from block 575 to 579 is almost the same as the procedure from block 555 to block 561, but the processing of the S3 POST code 215T can be completed in a shorter time than the simple POST code 213T. In block 563, the OS returns the system context stored in the main memory 115 to each device.

  The target device can synchronize in real time even if the BIOS password is set by the above procedure. In addition, the target device that receives the synchronization signal autonomously stops synchronization if there is a fraud, and if there is no fraud, disables the controller of the I / O device to ensure safety from eavesdropping associated with the synchronization. Secured. If there is no fraud, the unnecessary device POST is omitted, and the synchronization process is completed in a shorter time than when the basic POST code 209T is executed.

[Other methods of searching for target devices]
The AP 33 of the backbone network 31 constantly transmits a beacon frame in order to inform the surrounding information terminal device of the location. A method in which an information terminal device that desires connection to the backbone network 31 monitors a beacon frame and searches for a connection destination is called a passive scanning method. In the present embodiment, a source device that desires connection transmits a beacon frame to search for a target device that is a connection destination. The use of such a beacon frame can be included in the category of active scanning schemes.

  FIG. 8 is a diagram illustrating a method in which a source device searches for a target device by transmitting a beacon frame. The same procedures as those in FIG. 5 are denoted by the same reference numerals, description thereof is omitted, and only different portions are described. In block 601, the WLAN module 127S operates as a soft AP and transmits a beacon frame including a special ESSID. When the target device recognizes the special ESSID of the beacon frame as an activation signal at block 651, it immediately generates a synchronization event and activates the power supply to proceed with the procedure from block 355 onward.

  In block 603 and block 653, the WLAN module 127S and the WLAN module 127T perform authentication and association to establish a connection. Since the procedure in block 653 is performed in parallel with the procedure in and after block 651, it is possible to make a transition to the S0 state in a shorter time than waiting for establishment of a connection and starting the power supply as in the procedure in FIG. In addition, when there are a plurality of target devices, each target device that detects the beacon frame immediately starts a power source, so that the overall synchronization time can be shortened.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

100 notebook PC
125 BIOS_ROM

Claims (20)

A method in which a target device with non-volatile storage is synchronized to a source device, comprising:
Receiving a synchronization signal from the source device during a sleep state;
Activating a power source in response to receiving the synchronization signal and transitioning to a power-on state;
Receiving synchronization data from the source device after transitioning to the power on state;
Storing the synchronization data in the storage device.   2. The direct wireless connection between the source device and the target device is possible without going through a wireless access point connected to a backbone network, and the synchronization signal and the synchronization data are received over the direct wireless connection. The method described.   The method of claim 2, wherein the synchronization signal is included in a beacon frame transmitted by the source device.   The method according to claim 2 or 3, wherein the synchronization signal is included in a connection request frame transmitted by the source device. The target device has a step of determining whether there is unauthorized access during booting;
The step of transitioning to the power-on state skips the user's password input to the storage device to which a password has been set when it is determined that there is no unauthorized access, and the power The method according to any one of claims 1 to 4, further comprising the step of stopping the transition to the on state.   The method according to claim 5, wherein the step of determining whether or not there is an unauthorized access includes a step of determining whether or not the storage device has been removed from the target device between a previous boot and a current boot.   The method according to claim 5 or 6, wherein the step of determining whether or not there is an unauthorized access includes a step of determining whether or not a boot device has been changed since the previous boot.   The method according to any one of claims 1 to 7, wherein the step of transitioning to the power-on state includes the step of skipping device initialization that is not required for synchronization.   9. A method according to any preceding claim, wherein transitioning to the power on state comprises disabling an interface controller for an output device connectable to the target device.   The method according to claim 1, further comprising the step of transitioning the target device to the sleep state in response to the end of storing the synchronization data. A method in which a source device synchronizes a target device whose processor operation has stopped,
The source device generates synchronization data in response to a synchronization start operation;
The source device transmitting a synchronization signal for operating the processor to the target device;
The source device transmitting the synchronization data to the target device in response to the processor operating.   The method of claim 11, wherein transmitting the synchronization signal comprises the source device searching for the target device in an active scanning manner for wireless communications. An information terminal device that can be synchronized with a source device,
A wireless module in wireless communication with the source device;
A power controller that activates a power supply in response to a synchronization signal received by the wireless module from the source device during a sleep state;
An information terminal device comprising: a non-volatile storage device that stores synchronization data received from the source device via the wireless module after transitioning to a power-on state.   The information terminal apparatus according to claim 13, wherein the wireless module directly communicates with the wireless module of the source device to receive the synchronization signal and the synchronization data. A boot processing unit that processes a boot from when the power source is started until the power-on state is entered;
The boot processing unit determines whether or not there is unauthorized access to the information terminal device, and when it is determined that there is no unauthorized access, skips the user's password input to the storage device in which a password is set, and there is unauthorized access The information terminal device according to claim 13 or 14, wherein the boot is stopped when the determination is made. The sleep state is a suspend state or a hibernation state defined in ACPI.
The boot processing unit performs a simplified initialization than when transitioning from the soft-off state defined in ACPI to the power-on state and transitions from the sleep state to the power-on state. The information terminal device according to claim 15. To the information terminal device that can be synchronized with the source device,
Determining the cause of power activation received during sleep;
Determining the presence or absence of unauthorized access to the information terminal device since the last boot when determining that the activation cause is a synchronization signal for synchronizing with the source device;
A computer program for executing a process including a step of stopping a synchronization process when it is determined that there has been an unauthorized access. The information terminal device has a nonvolatile storage device that records synchronization data,
The computer program according to claim 17, wherein the presence or absence of unauthorized access determines whether or not the storage device is attached between the previous boot and the current boot.   19. The computer program product according to claim 17, further comprising a step of skipping input of a BIOS password by a user and transitioning to a power-on state when it is determined that there is no unauthorized access. Determining the type of sleep state when determining that there is no unauthorized access;
The computer program according to any one of claims 17 to 19, further comprising a step of changing to a power-on state by changing a degree of initialization in accordance with a type of the sleep state.

Images