JP2014022381A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device and a semiconductor device capable of ensuring a large area of an upper surface of a contact plug serving as a contact surface with an object to be connected are provided.
A step of forming a first conductive film, a step of forming a plurality of protective films formed on an upper surface of the first conductive film, and a protective film facing in a second direction D2 Forming a first side wall protective film 14 covering the side walls of twelve, and removing the plurality of protective films 12 and the first conductive film 9 exposed from the first side wall protective film 14, thereby Forming the wiring 15, forming the plurality of wirings 15, removing the first sidewall protection film 14, removing the first sidewall protection film 14, and then connecting the plurality of wirings 15. Forming a contact plug 22 by filling a space between the protective films 12 with a second conductive film.
[Selection] Figure 9

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Japanese Patent Laying-Open No. 2011-129566 (Patent Document 1) discloses a method of manufacturing a semiconductor device including a DRAM including a buried gate (word line) type transistor and a bit line formed thereabove. .

  In the prior art disclosed in Patent Document 1, after a plurality of bit lines extending in a predetermined direction are formed, contact plugs are formed in a self-aligning manner between the plurality of bit lines.

JP 2011-129666 A

  However, in the prior art of Patent Document 1, since the width dimension of the upper surface of the contact plug that becomes the contact surface with the connection object (capacitor) is determined by the interval between the bit lines, the width dimension of the upper surface of the contact plug is set to a predetermined value. It may be difficult to widen beyond the value. In this case, a large area of the upper surface (contact surface) of the contact plug cannot be secured, and there is a concern about an increase in contact resistance between the contact plug and the connection object. This tendency becomes more remarkable as the semiconductor device is downsized.

  Therefore, the present invention solves the conventional problem, that is, the object of the present invention is to ensure a large area of the upper surface of the contact plug that is a contact surface with the connection object. A semiconductor device manufacturing method and a semiconductor device are provided.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive film, a first conductive film formed on the upper surface of the first conductive film, and extending in a first direction along the substrate surface, and Forming a plurality of protective films spaced apart from each other in a second direction intersecting the first direction along the substrate surface, and sidewalls of the protective film facing the second direction Forming a first sidewall protective film covering the first protective film, and removing the plurality of protective films and a portion of the first conductive film exposed from the first sidewall protective film in the first direction. Forming a plurality of wirings extending along the second direction and spaced apart from each other in the second direction, and removing the first sidewall protective film after forming the plurality of wirings And after removing the first sidewall protective film, between the plurality of wirings and the plurality of protections Forming a contact plug between filled with the second conductive film by having, in which to solve the problems described above.

  The semiconductor device of the present invention includes a substrate and a second direction that extends in a first direction along the main surface of the substrate and intersects the first direction along the main surface of the substrate. A plurality of wirings spaced apart from each other, a plurality of protective films respectively disposed on the top surface of the wiring, and a second conductive film embedded between the plurality of wirings and between the plurality of protective films And the width dimension in the second direction between the plurality of protective films is larger than the width dimension in the second direction between the plurality of wirings. It is a thing.

  In the present invention, at the time of forming the contact plug by filling the wiring and the protective film with the second conductive film, the width dimension of the upper surface of the protective film is made smaller than the width dimension of the wiring in advance. Since it is possible to secure a large area of the upper surface of the contact plug that becomes the contact surface with the object, the contact area between the contact plug and the connection object is enlarged, and the contact plug and the connection object are The contact resistance between them can be reduced.

It is explanatory drawing which shows the semiconductor device which is 1st Embodiment of this invention, (a) is a top view of the semiconductor device which abbreviate | omits a capacitor, (b) is sectional drawing along XX. is there. It is explanatory drawing which shows the manufacturing process 1 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 2 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 3 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 4 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 5 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 6 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 7 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 8 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 9 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 10 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 11 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 12 of the semiconductor device of 1st Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 13 of the semiconductor device of 1st Embodiment, (a) is sectional drawing corresponding to the XX line of Fig.13 (a), (b) is FIG.13 (a). It is sectional drawing corresponding to an AA line, (c) is sectional drawing corresponding to the BB line of Fig.13 (a). It is explanatory drawing which shows the semiconductor device which is 2nd Embodiment of this invention, (a) is a top view of the semiconductor device which abbreviate | omits a capacitor, (b) is sectional drawing along XX. is there. It is explanatory drawing which shows the manufacturing process 5 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 6 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 7 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 8 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 10 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 12 of the semiconductor device of 2nd Embodiment, (a) is a top view, (b) is sectional drawing along XX, (c) is AA. It is sectional drawing along a line, (d) is sectional drawing along a BB line. It is explanatory drawing which shows the manufacturing process 13 of the semiconductor device of 2nd Embodiment, (a) is sectional drawing corresponding to the XX line of Fig.21 (a), (b) is FIG.21 (a). It is sectional drawing corresponding to an AA line, (c) is sectional drawing along the BB line of Fig.13 (a). It is explanatory drawing which shows the semiconductor which is 3rd Embodiment of this invention. It is explanatory drawing which shows the semiconductor which is 4th Embodiment of this invention, and is a top view which abbreviate | omits a capacitor and shows a semiconductor device. It is explanatory drawing which shows the semiconductor which is 6th Embodiment of this invention, (a) is a top view, (b) is sectional drawing along the BB line. It is explanatory drawing which shows the semiconductor which is 7th Embodiment of this invention, (a) is a top view, (b) is sectional drawing along the BB line. It is explanatory drawing which shows the semiconductor which is 8th Embodiment of this invention, (a) is a top view, (b) is sectional drawing along the BB line.

  Hereinafter, a plurality of embodiments of a semiconductor device of the present invention will be described with reference to the drawings. Hereinafter, a case where the present invention is applied to a DRAM (Dynamic Random Access Memory) as a semiconductor device will be described as an example. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

  In the following description of the embodiments, one direction along the substrate surface (main surface) of the substrate 1 is defined as the first direction D1 and along the substrate surface (main surface) of the substrate 1 as the first direction D1. The intersecting direction is defined as the second direction D2, and the direction perpendicular to the substrate 1 is defined as the third direction D3.

  Hereinafter, a semiconductor device (DRAM) according to a first embodiment of the present invention will be described with reference to the drawings.

  First, the configuration of the semiconductor device of the first embodiment will be described.

  The semiconductor device includes a memory cell region shown in FIG. 1 and a peripheral circuit region (not shown).

  In the memory cell region of the semiconductor device, a plurality of active regions 2 surrounded by element isolation regions 3 are formed at predetermined intervals. Also, a plurality of embedded word lines 7 are embedded and formed so as to extend along the second direction D2 and are spaced apart from each other in the first direction D1 so as to cut the active region 2 vertically. Further, a plurality of bit lines 15 are formed in a state of extending along the first direction D1 and being separated from each other in the second direction D2. Memory cells are respectively formed in regions where the buried word line 7 and the active region 2 intersect.

  Next, a memory cell constituting the semiconductor device of this embodiment will be described. The memory cell according to the present embodiment is a stacked structure including a buried gate type transistor in which the buried word line 7 is completely buried in the substrate 1, a capacitor 23, and the like.

  As shown in FIG. 1, the buried gate type transistor includes a substrate 1, an active region 2, an element isolation region 3 that partitions the active region 2, a buried word line 7 buried in the substrate 1, and a buried word line. 7, an insulating film 8 that protects the upper surface of the embedded word line 7, a bit line 15 formed above the substrate 1, and a protective film 12 that partially covers the upper surface of the bit line 15. Are connected to the bit line 15, the sidewall spacer 17 covering the side walls of the bit line 15 and the protective film 12, the interlayer insulating film 18 formed between the bit lines 15, the contact plug 22 connected to the capacitor 23, and the bit line 15. A bit line diffusion layer 4 a and a contact diffusion layer 4 b connected to the contact plug 22.

  A capacitor 23 having a cylindrical lower electrode 24, an upper electrode 25, a plate electrode 26, and a dielectric film 27 is provided above the buried gate type transistor, as shown in FIG.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

  First, in the manufacturing process 1, as shown in FIG. 2, an element isolation region 3 that partitions the active region 2 is formed on the substrate 1 using a known STI (Shallow Trench Isolation) method and the upper surface of the substrate 1. Then, a diffusion layer 4 (later bit line diffusion layer 4a, contact diffusion layer 4b) is formed by implanting ions.

  Next, in the manufacturing process 2, as shown in FIG. 3, a plurality of buried word line (gate electrode) trenches 5 extending in the second direction D2 are formed in the substrate 1 by photolithography and dry etching.

  Next, in the manufacturing process 3, as shown in FIG. 4, a gate insulating film 6 made of a thermal oxide film or the like is formed so as to cover the inner wall surface of the word line trench 5 and the upper surface of the substrate 1. Subsequently, a buried word line 7 is formed at the bottom of the word line trench 5 by depositing a conductive film such as a titanium nitride film, a tungsten film, or a polysilicon film. Subsequently, an insulating film 8 such as a CVD silicon oxide film is formed on the substrate 1 and the buried word line 7.

  Next, in the manufacturing process 4, as shown in FIG. 5, a conductive film (first conductive film) 9 is formed on the upper side of the substrate 1 using a polysilicon film, a tungsten film, a tungsten nitride film, or the like, An insulating film 10 for a bit line hard mask such as a silicon nitride film is formed on the upper surface of the conductive film 9.

  Next, in the manufacturing process 5, as shown in FIG. 6, a photoresist 11 is applied to the upper surface of the insulating film 10, and the insulating film 10 is dry-etched using the photoresist 11 as a mask, so that the first direction D1 is obtained. A plurality of protective films 12 extending along the second direction and spaced apart from each other in the second direction D2 are formed. The photoresist 11 is removed after the protective film 12 is formed.

Here, in the manufacturing process 5, as shown in FIG. 6, the width dimension Wp of the protective film 12 in the second direction D2 is set to be smaller than the width dimension Wb of the upper surface and the lower surface of the desired bit line 15.
In the present embodiment, as shown in FIG. 6, the width dimension Wp of the protective film 12 is set to the desired bit line 15 by setting the width dimension of the photoresist 11 to be smaller than the width dimension Wb of the desired bit line 15. It was set to be smaller than the width dimension Wb. However, the method for making the width dimension Wp of the protective film 12 smaller than the desired width dimension Wb of the bit line 15 is not limited to the above. For example, after the protective film 12 is formed with the width dimension Wb, wet etching or the like is performed. Thus, the width dimension Wp of the protective film 12 may be made smaller than the width dimension Wb of the desired bit line 15 by slimming the protective film 12.

  Next, in the manufacturing process 6, as shown in FIG. 7, the exposed upper surface of the conductive film 9, the upper surfaces of the plurality of protective films 12, and both side walls of the protective film 12 facing the second direction D2 are covered. Thus, the insulating film 13 is formed with a uniform thickness.

  Here, the material of the insulating film 13 may be any material that can be removed at a higher etching rate than the protective film 12 (insulating film 10) in the first etching described later (see manufacturing process 8). In the embodiment, for example, silicon oxide is used. Further, as shown in FIG. 7, the film thickness of the insulating film 13 is set to a dimension that is half the value obtained by subtracting the width dimension Wp of the protective film 12 from the width dimension Wb of the desired bit line 15. The thickness of the insulating film 13 is preferably 1 nm or more.

  Next, in the manufacturing process 7, as shown in FIG. 8, the insulating film 13 located on the upper surface of the conductive film 9 and the upper surface of the protective film 12 is etched back and removed, so that the second direction D2 is obtained. A sacrificial sidewall spacer (first sidewall protective film) 14 is formed to cover both side walls of the protective film 12 facing. Here, the width dimension of the protective film 12 and the pair of sacrificial sidewall spacers 14 in the second direction D2 matches the desired width dimension Wb of the bit line 15.

  Next, in the manufacturing process 8, as shown in FIG. 9, the conductive film 9 is dry-etched using the protective film 12 and the sacrificial sidewall spacer 14 as a mask, thereby extending along the first direction D1. A plurality of bit lines 15 are formed apart from each other in the second direction D2. The sacrificial sidewall spacer 14 is removed by wet etching (first etching) after the bit line 15 is formed.

  Next, in the manufacturing process 9, as shown in FIG. 10, the upper side of the substrate 1, that is, the exposed upper surface of the insulating film 8, the both side walls of the bit line 15 facing the second direction D2, and the second An insulating film 16 such as a silicon nitride film is formed so as to cover both side walls of the protective film 12 facing the direction D2 and the upper surface of the protective film 12.

  Next, in the manufacturing process 10, as shown in FIG. 11, the insulating film 16 located on the upper surfaces of the insulating film 8 and the protective film 12 is etched back and removed, so that the bit facing the second direction D <b> 2. Side wall spacers 17 that cover both the side walls of the line 15 and the protective film 12 are formed with a uniform thickness. Subsequently, a CVD silicon oxide film or the like is formed between the set of the bit line 15 and the protective film 12 and the side wall spacer 17 that are spaced apart in the second direction D2, and is flattened by etch back, CMP, or the like. Thus, the interlayer insulating film 18 is formed.

  Next, in the manufacturing process 11, as shown in FIG. 12, a plurality of photoresists 19 extending in the second direction D2 and spaced apart from each other in the first direction D1 are applied on the upper side of the substrate 1, The interlayer insulating film 18 is dry-etched using the resist 19 as a mask, so that a gap space 20 is formed between the pair of the bit line 15 and the protective film 12 and the side wall spacers 17 that are spaced apart in the second direction D2. Form. As shown in FIG. 12, a plurality of the gap spaces 20 are formed apart from each other in the first direction D1, and a plurality are formed apart from each other in the second direction D2, in other words, the third direction. When viewed in D3, it is formed in a lattice shape (grid shape). The photoresist 19 is removed after the gap space 20 is formed.

  Next, in the manufacturing process 12, as shown in FIG. 13, the sidewall spacer 21 is formed so as to cover the sidewall of the sidewall spacer 17 facing the gap space 20, the sidewall of the interlayer insulating film 18, and the sidewall of the insulating film 8. Form. Subsequently, a conductive film (second conductive film) such as a polysilicon film, a tungsten film, a tungsten nitride film, or a metal silicide film is deposited in the gap space 20 and etched back to thereby form a plurality of contact plugs 22. Form.

  Here, in the manufacturing process 12, as shown in FIG. 13, when the contact plug 22 is formed by filling the gap space 20 formed between the bit lines 15 and between the protective films 12 with the second conductive film, Since the width dimension Wp of the protective film 12 is smaller than the width dimension Wb of the bit line 15, the width dimension Wcu of the upper surface of the contact plug 22 in the second direction D2 is the width dimension of the lower surface of the contact plug 22 in the second direction D2. Since it is larger than Wcd, a large area of the upper surface of the contact plug 22 which is a contact surface with the capacitor 23 which is a connection object is secured.

  Next, in the manufacturing process 13, as shown in FIG. 14, the capacitor 23 is formed on the upper side of the transistor by a known method so that the lower electrode 24 of the capacitor 23 is in contact with the upper surface of the contact plug 22. Note that reference numeral 28 shown in FIG. 14 is an etch stopper film used when the capacitor 23 is formed.

  The width dimension of the upper surface of the protective film 12 is formed when the contact plug 22 is formed by filling the gap space 20 formed between the bit lines 15 and the protective film 12 thus obtained with the second conductive film. By making Wp smaller than the width dimension Wb of the bit line 15 in advance, it is possible to secure a large area of the upper surface of the contact plug 22 that serves as a contact surface with the capacitor 23. The contact area between the contact plug 22 and the capacitor 23 can be reduced.

  Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the configuration of the protective film 12 and the sacrificial sidewall spacer 14 is mainly different from the configuration of the first embodiment, and only the differences from the first embodiment will be described below.

  First, the configuration of the semiconductor device according to the second embodiment will be described below.

  In the second embodiment, as shown in FIG. 15, the protective film 12 includes a lower layer portion 12a disposed on the upper surface of the bit line 15 (conductive film 9) and an upper layer portion disposed on the upper surface of the lower layer portion 12a. 12b. Both end portions of the lower layer portion 12a in the second direction D2 protrude from the both side walls of the upper layer portion 12b facing the second direction D2 to the outside in the second direction D2, and thus in the second direction D2. A step is formed on the side wall of the protective film 12 facing.

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

  First, since the manufacturing steps 1 to 4 are the same as the manufacturing steps 1 to 4 of the first embodiment described above, description thereof is omitted.

  Next, in the manufacturing process 5, as shown in FIG. 16, a plurality of photoresists 11 extending along the first direction D1 and spaced apart from each other in the second direction D2 are applied to the upper surface of the insulating film 10. Then, the insulating film 10 is dry-etched from the upper surface side to the middle in the third direction D3 using the photoresist 11 as a mask. As a result, as shown in FIG. 16, the lower layer portion 12a disposed on the entire upper surface of the conductive film 9 (in a state after the manufacturing process 5), and the first direction disposed on the upper surface of the lower layer portion 12a. A protective film 12 having a plurality of upper layer portions 12b extending along D1 and spaced apart from each other in the second direction D2 is formed.

  Here, in the manufacturing process 5, as shown in FIG. 16, the width dimension Wp of the upper layer portion 12b of the protective film 12 in the second direction D2 is set smaller than the width dimension Wb of the upper surface and the lower surface of the desired bit line 15. Is done.

  Next, in the manufacturing process 6, as shown in FIG. 17, the exposed upper surface of the lower layer portion 12a of the protective film 12, the upper surface of the upper layer portion 12b of the protective film 12, and the upper layer portion 12b facing the second direction D2. The insulating film 13 is formed with a uniform thickness so as to cover both side walls. Here, as shown in FIG. 17, the film thickness of the insulating film 13 is set to a half of the value obtained by subtracting the width dimension Wp of the upper layer portion 12b from the width dimension Wb of the desired bit line 15. The thickness of the insulating film 13 is preferably 1 nm or more.

  Next, in the manufacturing process 7, as shown in FIG. 18, the insulating film 13 located on the upper surface of the upper layer portion 12b and the upper surface of the lower layer portion 12a is etched back to be removed in the second direction D2. A sacrificial sidewall spacer (first sidewall protective film) 14 is formed to cover both side walls of the facing upper layer portion 12b. Subsequently, as shown in FIG. 18, the upper layer portion 12b and the portion of the lower layer portion 12a not covered by the sacrificial sidewall spacer 14 are etched back. Here, the width dimension of the upper layer part 12b and the pair of sacrificial sidewall spacers 14 in the second direction D2 and the width dimension of the lower layer part 12a coincide with the desired width dimension Wb of the bit line 15.

  Next, in the manufacturing process 8, as shown in FIG. 19, the conductive film 9 is dry-etched using the protective film 12 and the sacrificial sidewall spacer 14 as a mask, thereby extending along the first direction D1, respectively. A plurality of bit lines 15 are formed apart from each other in the second direction D2. The sacrificial sidewall spacer 14 is removed by wet etching after the bit line 15 is formed.

  Next, in the manufacturing process 9, the upper side of the substrate 1, that is, the exposed upper surface of the insulating film 8, the both side walls of the bit line 15 facing the second direction D2, and the protective film facing the second direction D2. An insulating film 16 such as a silicon nitride film is formed with a uniform thickness so as to cover both side walls of the film 12 and the upper surface of the protective film 12.

  Next, in the manufacturing process 10, as shown in FIG. 20, the insulating film 16 located on the upper surfaces of the insulating film 8 and the protective film 12 is etched back and removed, so that the bit facing the second direction D2 is obtained. Side wall spacers 17 that cover both the side walls of the line 15 and the protective film 12 are formed with a uniform thickness. Subsequently, a CVD silicon oxide film or the like is formed between the set of the bit line 15 and the protective film 12 and the side wall spacer 17 that are spaced apart in the second direction D2, and is flattened by etch back, CMP, or the like. Thus, the interlayer insulating film 18 is formed.

  Next, in the manufacturing process 11, a plurality of photoresists 19 extending in the second direction D2 and spaced apart from each other in the first direction D1 are applied on the upper side of the substrate 1, and interlayer insulation is performed using the photoresist 19 as a mask. By subjecting the film 18 to dry etching, a gap space 20 is formed between the pair of the bit line 15, the protective film 12, and the side wall spacers 17 that are spaced apart in the second direction D 2. The photoresist 19 is removed after the gap space 20 is formed.

  Next, in the manufacturing process 12, as shown in FIG. 21, the side wall spacer 21 is covered so as to cover the side wall of the side wall spacer 17 facing the gap space 20, the side wall of the interlayer insulating film 18, and the side wall of the insulating film 8. Form. Subsequently, a conductive film (second conductive film) such as a polysilicon film, a tungsten film, a tungsten nitride film, or a metal silicide film is deposited in the gap space 20 and etched back to thereby form a plurality of contact plugs 22. Form.

  Here, in the manufacturing process 12, as shown in FIG. 21, when the contact plug 22 is formed by filling the gap space 20 formed between the bit lines 15 and between the protective films 12 with the second conductive film, Since the width dimension Wp of the protective film 12 is smaller than the width dimension Wb of the bit line 15, the width dimension Wcu of the upper surface of the contact plug 22 in the second direction D2 is the width dimension of the lower surface of the contact plug 22 in the second direction D2. Since it is larger than Wcd, a large area of the upper surface of the contact plug 22 which is a contact surface with the capacitor 23 which is a connection object is secured.

  Next, in the manufacturing process 13, as shown in FIG. 22, the capacitor 23 is formed on the upper side of the transistor by a known method so that the lower electrode 24 of the capacitor 23 is in contact with the upper surface of the contact plug 22. Note that reference numeral 28 shown in FIG. 22 is an etch stopper film used when the capacitor 23 is formed.

  In the semiconductor device of the second embodiment obtained in this way, in addition to the effects of the first embodiment, as shown in the region indicated by the symbol K in FIG. 21, the protective film 12 includes the upper layer portion 12b and the upper layer portion. The lower layer portion 12a is disposed on the lower surface of 12b and protrudes from the both side walls of the upper layer portion 12b facing the second direction D2 to the outside in the second direction D2, and the side walls of the upper layer portion 12b and the lower layer portion 12a are formed. By adopting the configuration of covering with the sidewall spacers 17, it is possible to reduce the risk of a short circuit between the contact plug 22 and the bit line 15.

  Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, since only the arrangement mode of the contact pads 29 of the capacitor 23 is different from the first embodiment or the second embodiment, only the differences from the first embodiment or the second embodiment are provided. Is described below.

  In the third embodiment, as shown in FIG. 23, a plurality of rows of contact pads 29 arranged along the second direction D2 are arranged with respect to a row h of contact pads 29 adjacent in the first direction D1. , They are arranged shifted in the second direction D2.

  Also in the third embodiment, similarly to the first embodiment or the second embodiment described above, the width dimension Wcu of the upper surface of the contact plug 22 in the second direction D2 is formed larger than the width dimension Wcd of the lower surface, In other words, since the upper surface of the contact plug 22 is enlarged only in the second direction D2, the contact pad 29 is secured in the second direction D2 while ensuring a contact area between the contact plug 22 and the contact pad 29. Can be shifted.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. Note that in the fourth embodiment, only the pitch P of the contact plugs 22 is different from the above-described embodiment, and only the differences from the above-described embodiment will be described below.

  In the fourth embodiment, the pitch P in the first direction D1 between the row i of the contact plugs 22 arranged in the second direction D2 and the row i of the adjacent contact plugs 22 is equal. It is not formed with a pitch.

Here, when the pitch P is formed not at an equal pitch, if the upper surface of the contact plug 22 is enlarged in both the first direction D1 and the second direction D2, it is adjacent in the first direction D1. There is a concern that the distance between the contact plugs 22 is narrowed and a short circuit occurs between the contact plugs 22.
However, in this embodiment, since the upper surface of the contact plug 22 is enlarged only in the second direction D2 as in the above-described embodiment, the pitch P of the contact plug 22 in the first direction D1 is set to an equal pitch. Even if it is formed instead, there is no concern that a short circuit will occur between the contact plugs 22 adjacent in the first direction D1.

  Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, only the material surface relationship between the protective film 12 and the sidewall spacer 17 is different from the above-described embodiment, and only the differences from the above-described embodiment will be described below. .

  In the fifth embodiment, the sidewall spacer 17 is formed of a material having a lower dielectric constant than that of the protective film 12. Thereby, the capacity between the bit line 15 and the contact plug 22 can be reduced. For example, comparing the case where the sidewall spacer 17 is formed of a nitride film and the case where the sidewall spacer 17 is formed of an oxynitride film, the capacitance between the bit line 15 and the contact plug 22 is reduced to about 85%. Is possible.

  Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, only the configuration of the contact plug 22 is different from the above-described embodiment, and only the differences from the above-described embodiment will be described below.

  In the sixth embodiment, as shown in FIG. 25, the contact plug 22 is composed of a lower layer portion 22a and an upper layer portion 22b made of different materials. The upper layer portion 22b is embedded on the upper surface side of the lower layer portion 22a. As a method for forming such a contact plug 22, there is a method in which the lower layer portion 22 a is formed by CVD, the upper layer portion 22 b is formed by PVD or CVD, and then planarized by CMP.

  In the above description, the contact plug 22 is formed of two materials. However, the number of materials constituting the contact plug 22 may be any number such as three or four.

  Next, a seventh embodiment of the present invention will be described with reference to FIG. In the seventh embodiment, only the configuration and the manufacturing method of the contact plug 22 are different from the sixth embodiment described above, and only the differences from the sixth embodiment described above will be described below.

  In the seventh embodiment, the upper layer portion 22b is formed over the entire upper surface of the lower layer portion 22a.

  As a manufacturing method of the contact plug 22 of 7th Embodiment, the two manufacturing methods demonstrated below are mentioned, for example.

  The first manufacturing method is a method in which after the lower layer portion 22a is formed by CVD, the lower layer portion 22a is dry-etched back, the upper layer portion 22b is formed by PCD or CVD, and then planarized by CMP. is there.

  In the second manufacturing method, after the lower layer portion 22a is formed by CVD, the upper layer portion 22b is formed by PCD or CVD, the material of the lower layer portion 22a is dry-etched back, and the upper layer portion 22b is again PCD. Alternatively, it is a method of forming by CVD and then performing planarization by CMP.

  In the semiconductor device of the seventh embodiment, the area of the upper surface of the upper layer portion 22b is increased as compared with the sixth embodiment, so that the contact resistance with the capacitor 23 can be further reduced.

  Next, an eighth embodiment of the present invention will be described with reference to FIG. In the eighth embodiment, since only the configuration of the protective film 12 is different from the above-described embodiment, only the differences from the above-described embodiment will be described below.

  In the eighth embodiment, as shown in FIG. 27, the protective film 12 includes a lower layer portion 12a disposed on the upper surface of the bit line 15 (conductive film 9) and an upper layer portion disposed on the upper surface of the lower layer portion 12a. 12b.

  In the eighth embodiment, the lower layer portion 12a and the upper layer portion 12b are formed of different materials, in particular, materials that can ensure etching selectivity with each other.

  In the eighth embodiment thus obtained, the lower layer portion 12a and the upper layer portion 12b are formed of different materials, so that the insulating film 10 is formed in the manufacturing process 5 (FIG. 16) of the second embodiment described above. When the (protective film 12) is etched, it is possible to etch from the upper surface side of the insulating film 10 to the middle of the third direction D3 by etching only the upper layer portion 12b. Becomes easier.

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Active region 3 ... Element isolation region 4 ... Diffusion layer 4a ... Bit line diffusion layer 4b ... Contact diffusion layer 5 ... Word line trench 6・ ・ ・ Gate insulating film 7 ・ ・ ・ Embedded word line 8 ・ ・ ・ Insulating film 9 ・ ・ ・ Conductive film (first conductive film)
DESCRIPTION OF SYMBOLS 10 ... Insulating film for bit line hard mask 11 ... Photoresist 12 ... Protective film 12a ... Lower layer part 12b ... Upper layer part 13 ... Insulating film 14 ... Sacrificial sidewall spacer (First sidewall protective film)
15 ... Bit line (wiring)
16 ... Insulating film 17 ... Side wall spacer (second side wall protective film)
DESCRIPTION OF SYMBOLS 18 ... Interlayer insulation film 19 ... Photoresist 20 ... Gap space 21 ... Side wall spacer 22 ... Contact plug (2nd electrically conductive film)
22a ... Lower layer part 22b ... Upper layer part 23 ... Capacitor 24 ... Lower electrode 25 ... Upper electrode 26 ... Plate electrode 27 ... Dielectric film 28 ... Etch stopper film 29 .. Contact pad D1... First direction D2... Second direction D3... Third direction Wb... Bit line width dimension Wp... Protective film width dimension Wcu. Contact plug upper surface width dimension Wcd ... Contact plug lower surface width dimension P ... Contact plug pitch

Claims (14)

Forming a first conductive film;
Formed on the top surface of the first conductive film, each extending in a first direction along the substrate surface, and mutually in a second direction intersecting the first direction along the substrate surface Forming a plurality of protective films spaced apart; and
Forming a first sidewall protective film covering the sidewall of the protective film facing the second direction;
By removing the portions of the first conductive film exposed from the plurality of protective films and the first sidewall protective film, the first conductive film extends along the first direction and extends in the second direction. Forming a plurality of wirings spaced apart from each other;
Removing the first sidewall protective film after forming the plurality of wirings;
Removing the first sidewall protective film, and then filling a space between the plurality of wirings and the plurality of protective films with a second conductive film to form a contact plug;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first sidewall protective film is formed on both side walls of the protective film facing in the second direction.   The first sidewall protective film is formed of a material that is removed at a higher etching rate than the protective film in the first etching, and the first etching is used in the step of removing the first sidewall protective film. 3. A method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device.   After removing the first side wall protective film and before forming the contact plug, the second side wall protective film covering the side wall of the wiring facing the second direction and the side wall of the protective film The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming the semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the second sidewall protective film is formed of a material having a dielectric constant lower than that of the protective film.   The first side wall protective film is formed so as to cover the side wall of the protective film from the upper surface side to the lower surface side of the protective film. 2. A method for manufacturing a semiconductor device according to item 1. The step of forming the first sidewall protective film includes:
Forming an insulating film from the upper surface of the first conductive film exposed from the plurality of protective films across the upper surface of the plurality of protective films and the sidewalls;
By removing the insulating film located on the upper surface of the first conductive film and on the upper surface of the protective film, the first sidewall protective film made of the insulating film is formed on the sidewall of the protective film. The method of manufacturing a semiconductor device according to claim 6, further comprising: The protective film has a lower layer portion disposed on the upper surface of the first conductive film, and an upper layer portion disposed on the upper surface of the lower layer portion,
An end portion of the lower layer portion in the second direction protrudes outward from the side wall of the upper layer portion facing the second direction in the second direction,
6. The method of manufacturing a semiconductor device according to claim 1, wherein the first sidewall protective film is formed to cover the sidewall of the upper layer portion. Forming the protective film and the first sidewall protective film,
A lower layer disposed on the upper surface of the first conductive film, and projects upward from the upper surface of the lower layer, extends along the first direction, and is spaced apart from each other in the second direction. A step of forming an insulating film including a plurality of upper layer portions arranged in a manner;
Forming an insulating film covering the exposed upper surface of the lower layer portion, the upper surface of the upper layer portion, and the sidewall of the upper layer portion;
By removing the insulating film located above the upper surface of the upper layer part and the insulating film and the lower layer part corresponding to the space between the upper layer parts, the first side wall is formed on the side wall of the upper layer part. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of dividing the lower layer portion of the insulating film into a plurality while leaving a protective film. A substrate,
A plurality of first and second extending in a first direction along the main surface of the substrate and spaced apart from each other in a second direction intersecting the first direction along the main surface of the substrate; Wiring and
A plurality of protective films respectively disposed on the upper surface of the wiring;
A contact plug made of a second conductive film embedded between the plurality of wirings and between the plurality of protective films;
A width of the plurality of protective films in the second direction in the second direction is larger than a width dimension in the second direction between the plurality of wirings.   The semiconductor device according to claim 10, further comprising a sidewall protective film that covers a sidewall of the wiring facing the second direction and a sidewall of the protective film.   The semiconductor device according to claim 11, wherein the sidewall protective film is made of a material having a lower dielectric constant than the protective film.   The width of the protective film in the second direction is the same from the upper surface side to the lower surface side of the protective film. A semiconductor device according to 1. The protective film has a lower layer portion disposed on the upper surface of the wiring, and an upper layer portion disposed on the upper surface of the lower layer portion,
The end portion of the lower layer portion in the second direction projects outward from the side wall of the upper layer portion facing the second direction in the second direction. 13. The semiconductor device according to any one of 12 above.

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