JP2014017778A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of reducing current consumption is provided.
A semiconductor integrated circuit converts a digital input signal Din into complementary analog currents Io and Iox, and outputs a current DAC10 that outputs the analog currents Io and Iox from a first output terminal Po1 and a second output terminal Po2, respectively. Have. The semiconductor integrated circuit 1 also includes a linear regulator 20 that generates an output voltage Vo from the power supply voltage AVD and supplies the output voltage Vo to the load from the output terminal Po3 connected to the second output terminal Po2. When the output voltage Vo becomes higher than a predetermined voltage, the semiconductor integrated circuit 1 protects the load from an overvoltage of the output voltage Vo by flowing a part of the operating current IRL0 flowing through the output terminal Po3 to the ground. An overvoltage protection circuit 30 is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit.

2. Description of the Related Art Conventionally, a semiconductor integrated circuit in which a current digital analog converter (current DAC) and a power supply circuit such as a linear regulator are mounted together is known.
8 and 9 show an example of a conventional single-ended output type current DAC. As shown in FIG. 8, n + 1-bit digital input signals D0 to Dn are input to the single-end output type current DAC50. The current DAC 50 supplies an analog current Io corresponding to the digital input signals D0 to Dn to the load RL1. For example, in the current DAC 50, as shown in FIG. 9, the differential transistors in the differential pairs B1 to Bn are turned on and off by the digital input signals D0 to Dn and the input signals XD0 to XDn at their inverted levels. Thereby, the current I1 to In of the current sources A1 to An is switched to flow to the first output terminal Po1 or to the second output terminal Po2. Then, the analog current Io output from the first output terminal Po1 flows to the load RL1, and an analog voltage corresponding to the input signals D0 to Dn is generated at the load RL1. On the other hand, the analog current Iox output from the second output terminal Po2 flows to the ground (ground line) to which the ground voltage AVS is supplied.

  As described above, in the current DAC 50, the currents I1 to In from the current sources A1 to An are always supplied by flowing the currents I1 to In of the current sources A1 to An to either the first output terminal Po1 or the second output terminal Po2. Can be maintained at a constant set current. Thereby, supply / stop of the currents I1 to In maintained at a desired set current to the first output terminal Po1 can be switched at high speed and stably, and the current DAC 50 can be operated at high speed and stably.

  FIG. 10 shows an example of a conventional linear regulator. As shown in FIG. 10, the linear regulator 60 includes an operational amplifier 61, resistors R11 and R12, a P-channel MOS transistor T61, an output resistor Ro, and an output capacitor Co. The operational amplifier 61 drives the gate of the transistor T61 with reference to a reference voltage Vr1 obtained by dividing the high potential power supply voltage (input voltage) AVD by the resistors R11 and R12. The transistor T61 causes a drive current Ir corresponding to the gate voltage to flow through the output resistor Ro. As a result, an output voltage Vo corresponding to the current flowing through the output resistor Ro and the resistance value of the output resistor Ro is generated at the output terminal Po. This output voltage Vo is fed back to the inverting input terminal of the operational amplifier 61. The operational amplifier 61 controls the transistor T61 so that the output voltage Vo supplied to the inverting input terminal is equal to the reference voltage Vr1. Accordingly, a stable output voltage Vo {= Vr1 = AVD × R12 / (R11 + R12)} is generated at the output terminal Po based on the power supply voltage AVD.

  In such a linear regulator 60, the drain current (driving current Ir) is always supplied to the transistor T61, thereby realizing a high-speed operation of the transistor T61 and a high-speed feedback operation by the operational amplifier 61, the transistor T61, and the like. As a result, a stable output voltage Vo can be generated even when the current supplied from the output terminal Po with respect to the load connected to the output terminal Po varies as the load varies. .

  For example, Patent Document 1 is known as a prior art related to the above prior art.

International Publication No. 2008/012955

  However, in the current DAC 50, when the currents I1 to In from the current sources A1 to An are output to the second output terminal Po2, the currents I1 to In are not converted into analog voltages (consumed by the load RL1). Flow) to the ground. That is, in the current DAC 50, the current output to the second output terminal Po2 for the high-speed operation of the current DAC 50 flows to the ground as an unnecessary current. In the linear regulator 60, since the drive current Ir always flows through the transistor T61 regardless of the state of the load connected to the output terminal Po, when the load is unloaded, an unnecessary current is output from the transistor T61 to the output resistor Ro. It will flow. For this reason, in the semiconductor integrated circuit in which the current DAC 50 and the linear regulator 60 are mixedly mounted, the current consumption of the entire circuit increases due to an unnecessary current generated in the current DAC 50 and an unnecessary current generated in the linear regulator 60. Occur.

  According to one aspect of the present invention, a current DA converter that converts a digital input signal into a complementary analog current and outputs the complementary analog current from the first output terminal and the second output terminal, and an output voltage from the input voltage. A power supply circuit for generating and supplying the output voltage to a load from a third output terminal connected to the second output terminal; and a protection connected to the third output terminal for protecting the load from an overvoltage of the output voltage A circuit.

  According to one aspect of the present invention, it is possible to reduce current consumption.

1 is a block circuit diagram showing a semiconductor integrated circuit according to an embodiment. FIG. 3 is a circuit diagram illustrating an example of an internal configuration of a current DAC according to an embodiment. 1 is a circuit diagram showing an example of an internal configuration of an overvoltage protection circuit according to an embodiment. 1 is a block diagram showing a semiconductor integrated circuit according to an embodiment. The wave form diagram for demonstrating the effect | action of the electric current DAC and linear regulator of one Embodiment. The wave form diagram which shows the operation | movement of the overvoltage protection circuit of one Embodiment. The wave form diagram which shows the operation | movement of the overvoltage protection circuit of one Embodiment. The block diagram which shows the conventional electric current DAC. The circuit diagram which shows the example of an internal structure of the conventional electric current DAC. The circuit diagram which shows the internal structural example of the conventional linear regulator.

(One embodiment)
Hereinafter, an embodiment will be described with reference to FIGS.
As shown in FIG. 4, the semiconductor integrated circuit 1 includes a current digital-to-analog converter (current DAC) 10, a linear regulator 20 connected to the current DAC 10, and a load RL0 to which an output voltage Vo of the linear regulator 20 is supplied. And an overvoltage protection circuit 30 that protects the load RL0 from an overvoltage of the output voltage Vo.

  A plurality of bits (here, 4 bits) digital input signals (input signals) D0 to D3 are input to the current DAC10. A high potential power supply voltage (power supply voltage) AVD is supplied to the current DAC10. The first output terminal Po1 of the current DAC10 is connected to the load RL1, and the second output terminal Po2 of the current DAC10 is connected to the linear regulator 20. The current DAC10 outputs complementary (reverse phase) analog currents Io and Iox corresponding to the 4-bit input signals D0 to D3. That is, the current DAC 10 is a 4-bit current DAC that outputs analog currents Io and Iox having 16 gradations with respect to the 4-bit digital input signals D0 to D3. For example, the current DAC 10 supplies an analog current Io corresponding to the 4-bit input signals D0 to D3 to the load RL1, and supplies an analog current Iox at an inversion level of the analog current Io to the linear regulator 20. In the following description, the input signals D0 to D3 may be collectively referred to as “input signal Din”.

  The linear regulator 20 is supplied with the power supply voltage AVD as an input voltage. The output terminal Po3 of the linear regulator 20 is connected to the load RL0. The linear regulator 20 generates a stable output voltage Vo from the power supply voltage AVD and supplies the output voltage Vo to the load RL0. The linear regulator 20 supplies an operating current IRL0 corresponding to the analog current Iox output from the second output terminal Po2 of the current DAC10 to the load RL0. The analog current Iox is also used for generating the output voltage Vo.

  The overvoltage protection circuit 30 is supplied with 4-bit digital input signals D0 to D3 input to the current DAC10. The overvoltage protection circuit 30 controls the operating current IRL0 (analog current Iox) flowing through the output terminal Po3 of the linear regulator 20 when the output voltage Vo becomes higher than a predetermined voltage, whereby the output voltage Vo is set to a desired value. Suppresses the voltage value from rising.

  As shown in FIG. 1, the linear regulator 20 includes resistors R1 and R2, an operational amplifier 21, an output capacitor Co, a P-channel MOS transistor T21, and an output resistor Ro.

  A power supply voltage AVD is supplied to the high potential power supply terminal of the operational amplifier 21, and a low potential power supply voltage (here, ground voltage) AVS lower than the high potential power supply voltage is supplied to the low potential power supply terminal of the operational amplifier 21. . A reference voltage Vr corresponding to the power supply voltage AVD is supplied to the non-inverting input terminal of the operational amplifier 21. In this example, the reference voltage Vr generated by the resistors R1 and R2 is supplied to the non-inverting input terminal of the operational amplifier 21. Specifically, a power supply line to which the power supply voltage AVD is supplied is connected to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to a power supply line (hereinafter also referred to as ground) to which the ground voltage AVS is supplied. Yes. A node N21 between the resistors R1 and R2 is connected to the non-inverting input terminal of the operational amplifier 21. Here, the resistors R1 and R2 generate a reference voltage Vr obtained by dividing the power supply voltage AVD according to the respective resistance values. The value of the reference voltage Vr corresponds to the resistance value ratio between the resistors R1 and R2 and the potential difference between the power supply voltage AVD and the ground voltage AVS. Therefore, the reference voltage Vr {= AVD × R2 / (R1 + R2)} proportional to the power supply voltage AVD is supplied to the non-inverting input terminal of the operational amplifier 21.

  The output terminal of the operational amplifier 21 is connected to the gate of the transistor T21. The source of the transistor T21 is supplied with the power supply voltage AVD, and the drain of the transistor T21 is connected to the first terminal of the output resistor Ro. The second terminal of the output resistor Ro is connected to the ground. A connection point between the transistor T21 and the output resistor Ro is connected to the output terminal Po3 of the linear regulator 20 and the first terminal of the output capacitor Co. The second terminal of the output capacitor Co is connected to the ground.

  The operational amplifier 21 drives the gate of the transistor T21 based on the reference voltage Vr obtained by dividing the power supply voltage AVD by the resistors R1 and R2. The transistor T21 causes the drive current Ir corresponding to the gate voltage to flow through the output resistor Ro. Thereby, a potential difference corresponding to the current flowing through the output resistor Ro and the resistance value of the output resistor Ro is generated between both terminals of the output resistor Ro. The voltage at the first terminal of the output resistor Ro is output from the output terminal Po3 as the output voltage Vo.

  The output terminal Po3 (the first terminal of the output resistor Ro) is connected to the inverting input terminal of the operational amplifier 21. Therefore, the output voltage Vo generated at the output terminal Po3 is fed back to the inverting input terminal of the operational amplifier 21. The operational amplifier 21 controls the transistor T21 so that the output voltage Vo supplied to the inverting input terminal is equal to the reference voltage Vr. As a result, a stable output voltage Vo {= Vr = AVD × R2 / (R1 + R2)} is generated at the output terminal Po3 based on the power supply voltage AVD. The output capacitor Co functions to suppress fluctuations in the output voltage Vo due to the load RL0 (see FIG. 4) connected to the output terminal Po3.

  The output terminal Po3 (the first terminal of the output resistor Ro) is connected to the second output terminal Po2 of the current DAC10. For this reason, the load RL0 (see FIG. 4) connected to the output terminal Po3 has an operating current corresponding to the drive current Ir flowing through the transistor T21 and the analog current Iox output from the second output terminal Po2 of the current DAC10. IRL0 is supplied. That is, by connecting the second output terminal Po2 of the current DAC10 to the output terminal Po3 of the linear regulator 20, the analog current Iox output from the current DAC10 is used as part of the operating current of the linear regulator 20. The output resistor Ro is supplied with a current (= Ir−IRL0 + Iox) corresponding to the drive current Ir, the analog current Iox, and the operating current IRL0.

  Further, an overvoltage protection circuit 30 is connected to the output terminal Po3. When the output voltage Vo becomes higher than a predetermined voltage, the overvoltage protection circuit 30 extracts a part of the operation current IRL0 (analog current Iox) to the ground (ground line) according to the input signals D0 to D3. This suppresses the output voltage Vo from becoming higher than the predetermined voltage.

Next, an internal configuration example of the current DAC 10 will be described with reference to FIG.
The current DAC 10 is a current source 11 through which currents I1, I2, I3, and I4 having current values weighted at a predetermined ratio, specifically, a binary (power of 2) ratio (1: 2: 4: 8). 14 and differential pairs 15 to 18 connected to the current sources 11 to 14, respectively. In the following description, as shown in the figure, the current values of the currents I1, I2, I3, and I4 are denoted as 1I, 2I, 4I, and 8I, respectively. “I” at this time means a unit current value.

  A power supply voltage AVD is supplied to the first terminal of the current source 11. A second terminal of the current source 11 is connected to the differential pair 15. The differential pair 15 has a pair of differential transistors T11 and T12 to which complementary input signals D0 and XD0 are supplied, respectively. Here, the input signal D0 is the first bit (least significant bit) of the input signal Din, and the input signal XD0 is a signal generated by logically inverting the input signal D0. As described above, the current I1 having the current value of 1I is supplied to the differential pair 15 that receives the input signals D0 and XD0 corresponding to the least significant bit of the input signal Din.

  The differential transistors T11 and T12 are, for example, P channel MOS transistors. The differential transistors T11 and T12 have the same electrical characteristics. The sources of the differential transistors T11 and T12 are connected to each other and to the second terminal of the current source 11. The inversion level of the input signal D0 is supplied to the gate of the differential transistor T11. The drain of the differential transistor T11 is connected to the first output terminal Po1. On the other hand, the inverted level of the input signal XD0 is supplied to the gate of the differential transistor T12. The drain of the differential transistor T12 is connected to the second output terminal Po2.

As described above, the first output terminal Po1 is connected to the load RL1, and the second output terminal Po2 is connected to the output terminal Po3 of the linear regulator 20.
A power supply voltage AVD is supplied to the first terminal of the current source 12. A differential pair 16 is connected to the second terminal of the current source 12. The differential pair 16 has a pair of differential transistors T13 and T14 to which complementary input signals D1 and XD1 are supplied, respectively. Here, the input signal D1 is the second bit (second lower bit) of the input signal Din, and the input signal XD1 is a signal generated by logically inverting the input signal D1. As described above, the current I2 having the current value 2I is supplied to the differential pair 16 that receives the input signals D1 and XD1 corresponding to the second bit of the input signal Din.

  The differential transistors T13 and T14 are, for example, P channel MOS transistors. The differential transistors T13 and T14 have the same electrical characteristics. The sources of the differential transistors T13 and T14 are connected to each other and to the second terminal of the current source 12. The inverted level of the input signal D1 is supplied to the gate of the differential transistor T13. The drain of the differential transistor T13 is connected to the first output terminal Po1. On the other hand, the inverted level of the input signal XD1 is supplied to the gate of the differential transistor T14. The drain of the differential transistor T14 is connected to the second output terminal Po2.

  A power supply voltage AVD is supplied to the first terminal of the current source 13. A differential pair 17 is connected to the second terminal of the current source 13. The differential pair 17 includes a pair of differential transistors T15 and T16 to which complementary input signals D2 and XD2 are supplied, respectively. Here, the input signal D2 is the third bit (third lower bit) of the input signal Din, and the input signal XD2 is a signal generated by logically inverting the input signal D2. As described above, the current I4 having the current value 4I is supplied to the differential pair 17 that receives the input signals D2 and XD2 corresponding to the third bit of the input signal Din.

  The differential transistors T15 and T16 are, for example, P channel MOS transistors. The differential transistors T15 and T16 have the same electrical characteristics. The sources of the differential transistors T15 and T16 are connected to each other and to the second terminal of the current source 13. The inverted level of the input signal D2 is supplied to the gate of the differential transistor T15. The drain of the differential transistor T15 is connected to the first output terminal Po1. On the other hand, the inverted level of the input signal XD2 is supplied to the gate of the differential transistor T16. The drain of the differential transistor T16 is connected to the second output terminal Po2.

  A power supply voltage AVD is supplied to the first terminal of the current source 14. A differential pair 18 is connected to the second terminal of the current source 14. The differential pair 18 has a pair of differential transistors T17 and T18 to which complementary input signals D3 and XD3 are respectively supplied. Here, the input signal D3 is the fourth bit (most significant bit) of the input signal Din, and the input signal XD3 is a signal generated by logically inverting the input signal D3. In this manner, the current I4 having the current value 8I is supplied to the differential pair 18 that receives the input signals D3 and XD3 corresponding to the most significant bit of the input signal Din.

  The differential transistors T17 and T18 are, for example, P channel MOS transistors. The differential transistors T17 and T18 have the same electrical characteristics. The sources of the differential transistors T17 and T18 are connected to each other and to the second terminal of the current source 14. The inverted level of the input signal D3 is supplied to the gate of the differential transistor T17. The drain of the differential transistor T17 is connected to the first output terminal Po1. On the other hand, the inverted level of the input signal XD3 is supplied to the gate of the differential transistor T18. The drain of the differential transistor T18 is connected to the second output terminal Po2.

  In such a current DAC10, the differential transistors T11 to T18 are turned on / off in response to the input signals D0 to D3, XD0 to XD3, and the currents I1 to I4 of the current sources 11 to 14 are supplied to the first output terminal Po1. Switching between the two output terminals Po2 is switched. For example, when the input signal D0 is “0 (logic L level)”, the input signal D1 is “1 (logic H level)”, the input signal D2 is “1”, and the input signal D3 is “1”, that is, the input signal Din is A case of “1110” will be described. In this case, the input signals XD0 to XD3 are “1”, “0”, “0”, and “0”, respectively. In response to the input signals D0 to D3 and the input signals XD0 to XD3, the differential transistors T12, T13, T15, and T17 are turned on, and the differential transistors T11, T14, T16, and T18 are turned off. For this reason, the current I1 of the current source 11 flows to the second output terminal Po2, while the currents I2 to I4 of the current sources 12 to 14 flow to the first output terminal Po1. Therefore, the current value of the analog current Io output from the first output terminal Po1 becomes “14I (= 2I + 4I + 8I)” corresponding to the input signals D0 to D3, and the current of the analog current Iox output from the second output terminal Po2 The value is “1I”. Note that the total amount of the analog current Io and the analog current Iox output from the current DAC 10 is always “15I” regardless of the signal levels of the input signals D0 to D3.

Next, an internal configuration example of the overvoltage protection circuit 30 will be described.
As shown in FIG. 3, the overvoltage protection circuit 30 includes a comparator 31, a number of NOR circuits 32 to 35 corresponding to the number of bits of the input signal Din (here, four), and the NOR circuits 32 to 35. N-channel MOS transistors T31 to T34 each having a gate connected to each output terminal. Each of the transistors T31 to T34 has a number of N-channel MOS transistors T31 to T34 (switch circuits) weighted by a binary ratio (1: 2: 4: 8) corresponding to each bit of the digital input signal Din. ing. That is, the transistor T31 is one N-channel MOS transistor T31, and the transistor T32 is an N-channel MOS transistor T32 connected in parallel (= 2 ¹ ). The transistor T33 is an N-channel MOS transistor T33 connected in parallel with 4 (= 2 ² ) transistors, and the transistor T34 is an N-channel MOS transistor T34 connected in parallel with 8 (= 2 ³ ) transistors. All these transistors T31 to T34 have the same electrical characteristics.

  The power supply voltage AVD is supplied to the high potential side power supply terminal of the comparator 31, and the ground voltage AVS is supplied to the low potential side power supply terminal of the comparator 31. The output terminal Po3 of the linear regulator 20 is connected to the inverting input terminal of the comparator 31, and the output voltage Vo of the linear regulator 20 is supplied. The set voltage Vs set to a predetermined voltage value is supplied to the non-inverting input terminal of the comparator 31.

  Here, the voltage value of the set voltage Vs is set according to the target voltage of the output voltage Vo of the linear regulator 20, for example. In this case, for example, the node N21 shown in FIG. 1 may be connected to the non-inverting input terminal of the comparator 31, and the set voltage Vs may be set to the same potential as the reference voltage Vr. As a result, the linear regulator 20 can generate the output voltage Vo with a small fluctuation amount (that is, a ripple voltage is small). Further, the voltage value of the set voltage Vs may be set according to the withstand voltage Vt of an element using the output voltage Vo of the linear regulator 20 as a power supply voltage, for example. As a result, it is possible to suppress the destruction of the element whose output voltage Vo is the power supply voltage. From the above, it is preferable to set the voltage value of the set voltage Vs in the following range.

Vr ≦ Vs <Vt
The comparator 31 compares the output voltage Vo and the set voltage Vs, and generates a comparison signal Vc corresponding to the comparison result. For example, the comparator 31 generates an H level (power supply voltage AVD level) comparison signal Vc when the output voltage Vo is lower than the set voltage Vs, and L level (ground) when the output voltage Vo is higher than the set voltage Vs. A comparison signal Vc of voltage AVS) is generated. This comparison signal Vc is supplied to the NOR circuits 32-35.

  An input signal D0 is input to the NOR circuit 32. The NOR circuit 32 outputs, to the gate of one transistor T31, an output signal S1 having a result obtained by performing a negative logic operation on the input signal D0 and the comparison signal Vc. The drain (first terminal) of the transistor T31 is connected to the output terminal Po3, and the source (second terminal) of the transistor T31 is connected to the ground (ground line). Thus, the output signal S1 generated from the input signal D0 which is the least significant bit of the input signal Din is supplied to one transistor T31.

  An input signal D1 is input to the NOR circuit 33. The NOR circuit 33 outputs an output signal S2 having a result obtained by performing a negative logic operation on the input signal D1 and the comparison signal Vc to the gates of the two transistors T32. The drain (first terminal) of each transistor T32 is connected to the output terminal Po3, and the source (second terminal) of the transistor T32 is connected to the ground (ground line). As described above, the output signal S2 generated from the input signal D1 which is the second bit of the input signal Din is supplied to the two transistors T32 connected in parallel.

  An input signal D2 is input to the NOR circuit 34. The NOR circuit 34 outputs, to the gates of the four transistors T33, an output signal S3 having a result obtained by performing a negative logic operation on the input signal D2 and the comparison signal Vc. The drain (first terminal) of each transistor T33 is connected to the output terminal Po3, and the source (second terminal) of the transistor T33 is connected to the ground (ground line). As described above, the output signal S3 corresponding to the input signal D2 which is the third bit of the input signal Din is supplied to the four transistors T33 connected in parallel.

  An input signal D3 is input to the NOR circuit 35. The NOR circuit 35 outputs, to the gates of the eight transistors T34, an output signal S4 having a result obtained by performing a negative logic operation on the input signal D3 and the comparison signal Vc. The drain (first terminal) of each transistor T34 is connected to the output terminal Po3, and the source (second terminal) of the transistor T34 is connected to the ground (ground line). As described above, the output signal S4 generated from the input signal D3 which is the most significant bit of the input signal Din is supplied to the eight transistors T34 connected in parallel.

  In such an overvoltage protection circuit 30, when the output voltage Vo is lower than the set voltage Vs, the comparator 31 outputs the H level comparison signal Vc, so that regardless of the signal levels of the input signals D 0 to D 3. The NOR circuits 32 to 35 output L level output signals S1 to S4. For this reason, when the output voltage Vo is lower than the set voltage Vs, the transistors T31 to T34 are all turned off. On the other hand, when the output voltage Vo becomes higher than the set voltage Vs, the L level comparison signal Vc is output from the comparator 31, so that the transistors T31 to T34 are turned on / off according to the input signals D0 to D3. As a result, a current It according to the number of turned-on transistors T31 to T34 flows from the output terminal Po3 to the ground, and a part of the operating current IRL0 (analog current Iox) flowing to the output terminal Po3 is extracted to the ground. An increase in the output voltage Vo is suppressed.

  In the present embodiment, the current DAC 10 is an example of a current DA converter, the linear regulator 20 is an example of a power supply circuit, the overvoltage protection circuit 30 is an example of a protection circuit, and the transistors T31 to T34 are examples of a switch circuit. The output terminal Po3 is an example of the third output terminal, the set voltage Vs is an example of the reference voltage, the operating current IRL0 is an example of the current flowing through the third output terminal, the current It is an example of the first current, and the analog current Iox is the first It is an example of 1 analog current.

  Next, the operation of the current DAC 10 and the linear regulator 20 will be described in comparison with the conventional example. Here, for simplification of description, the operation of the current DAC 10 and the linear regulator 20 when the overvoltage protection circuit 30 does not operate will be described.

FIG. 5 shows the current consumption Id of the current DACs 10 and 50 when the current DACs 10 and 50 are outputting sine waves, the drive current Ir of the linear regulators 20 and 60, and the second output terminal of the current DAC 10 of this embodiment. The analog current Iox output from Po2 is shown. FIG. 5 shows the current DAC 50 and the current consumption Ic2 of the linear regulator 60, and the current DAC 10 and the current consumption Ic of the linear regulator 20 of the present embodiment. As is apparent from FIG. 5, the consumption current Ic2 of the conventional example using the current DAC 50 and the linear regulator 60 individually is
Ic2 = Ir + Id
(Refer to the alternate long and short dash line).

In contrast, in this embodiment, the second output terminal Po2 of the current DAC10 is connected to the output terminal Po3 of the linear regulator 20, so that the analog current Iox output from the second output terminal Po2 of the current DAC10 is changed to the linear regulator 20. Is added to the operating current IRL0. That is, the analog current Iox that has been supplied to the ground in order to operate the current DAC at high speed is added to the operating current IRL0 of the linear regulator 20. For this reason, the current supplied by the linear regulator 20 is reduced by an amount corresponding to the added analog current Iox. Therefore, the current DAC 10 and the current consumption Ic of the linear regulator 20 of the present embodiment are
Ic = Ir-Iox + Id
It becomes. That is, in the present embodiment, the current consumption Ic in the current DAC 10 and the linear regulator 20 can be reduced by the analog current Iox as compared with the conventional current consumption Ic2 (see the hatched area in FIG. 5). Here, the analog current Iox when the current DAC 10 outputs a sine wave is time-averaged,
Iox = Id / 2
It becomes. For this reason, in this case, the current DAC 10 and the linear regulator 20 of the present embodiment can reduce the current consumption by ½ of the current consumption Id of the current DAC 10 rather than the conventional current consumption Ic2.

Next, the operation of the overvoltage protection circuit 30 will be described.
First, a circuit when only the overvoltage protection circuit 30 is omitted from the semiconductor integrated circuit 1 of the present embodiment (hereinafter referred to as “first circuit”) will be described.

  As a result of diligent research by the present inventor, in order to generate a stable output voltage Vo with the linear regulator 20 in the first circuit, it has been clarified that the following restrictions are imposed on the use conditions of the first circuit. That is, in the first circuit, the drive current (reactive current) Ir0 consumed by the linear regulator 20 when the load RL0 is no load, the minimum operating current IRL0min that the load RL0 can operate, and the second output terminal of the current DAC10 The maximum current (full scale current) Ioxmax of the analog current Iox output from Po2 needs to satisfy the following relationship.

Ir0 + IRL0min> Ioxmax
The reason why the above restrictions are required will be described in detail below.
When the linear regulator 20 is used in a steady state independently of the current DAC 10, the output voltage Vrgo generated by the linear regulator 20 is
Vrgo = Ir0 × Ro (1)
Can be expressed as At this time, when the second output terminal Po2 of the current DAC 10 is connected to the output terminal Po3 of the linear regulator 20 as shown in FIG. 1, the current flowing into the output resistor Ro increases by the analog current Iox. Therefore, from the relationship between the drive current Ir of the linear regulator 20, the analog current Iox, and the operating current IRL0 of the load RL0, the output voltage Vo of the linear regulator 20 is
Vo = (Ir−IRL0 + Iox) × Ro (2)
It becomes. Here, in order to make the output voltage Vrgo and the output voltage Vo equal, from the above formulas 1 and 2,
Ir0 = Ir-IRL0 + Iox (3)
It is necessary to satisfy the relationship. The analog current Iox has different current values depending on the digital input signals D0 to D3 (input codes) input to the current DAC10. Specifically, the range of the current value of the analog current Iox is from 0 to the maximum current Ioxmax as shown in the following equation.

0 ≦ Iox ≦ Ioxmax
In the linear regulator 20, the operational amplifier 21 controls the gate voltage of the transistor T 21 to adjust the current value of the drive current Ir so that Equation 3 is satisfied by feedback control, thereby controlling the output voltage Vo. For example, when the analog current Iox supplied from the current DAC 10 decreases, the gate voltage of the transistor T21 is controlled so as to increase the drive current Ir. On the other hand, when the analog current Iox supplied from the current DAC10 increases, the gate voltage of the transistor T21 is controlled so as to decrease the drive current Ir. Therefore, when the analog current Iox is the maximum current Ioxmax, the lower limit value Vo_limit of the output voltage Vo that can be controlled by the linear regulator 20 is output when the drive current Ir is 0 A and the operating current IRL0 of the load RL0 is the minimum operating current IRL0min. Since the voltage is Vo,
Vo_limit = (Ioxmax−IRL0min) × Ro (4)
It becomes. At this time, if the lower limit value Vo_limit is not lower than the output voltage Vrgo (that is, the output voltage when the linear regulator 20 is used alone), the desired output voltage Vo is obtained by the feedback control in the linear regulator 20. Can not be. For this reason, in the first circuit in which the overvoltage protection circuit 30 is omitted, in order to generate the desired output voltage Vo in the linear regulator 20,
Vrgo> Vo_limit (5)
It is necessary to satisfy. Further, from this formula 5 and the above formulas 1 and 4, in the first circuit, in order to generate the desired output voltage Vo in the linear regulator 20,
Ir0 + IRL0min> Ioxmax (6)
It is understood that it is necessary to satisfy the relationship (constraint condition).

  Here, in the first circuit in which the overvoltage protection circuit 30 is omitted, when the above constraint is not satisfied, the output voltage Vo of the linear regulator 20 rises higher than a desired voltage value, and the stable output voltage Vo. Cannot be generated. When the increased output voltage Vo exceeds the withstand voltage of an element using the output voltage Vo as a power supply voltage, there is a problem that the element is destroyed.

  On the other hand, in the semiconductor integrated circuit 1 of the present embodiment, the overvoltage protection circuit 30 that suppresses the output voltage Vo of the linear regulator 20 from becoming higher than the set voltage Vs is provided. When the output voltage Vo becomes higher than the set voltage Vs, the overvoltage protection circuit 30 draws a part of the operating current IRL0 (analog current Iox) of the linear regulator 20 to the ground in accordance with the digital input signal Din. The rise of Vo is suppressed. Thereby, it can suppress that the element in load RL0 is destroyed by the overvoltage of output voltage Vo.

  Next, the operation of the overvoltage protection circuit 30 will be described in detail with reference to FIGS. 6 and 7, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  First, the case where the input signal Din is “1110” will be described with reference to FIG. In this case, as described above, the current value of the analog current Io output from the first output terminal Po1 of the current DAC10 is “14I”, and the current value of the analog current Iox output from the second output terminal Po2 is “1I”. That is, the analog current Iox having a current amount of 1/15 of the total current amount (= 15I) of the analog currents Io and Iox output from the current DAC 10 is supplied to the linear regulator 20.

  When the output voltage Vo becomes higher than the set voltage Vs at time t1 shown in FIG. 6, an L level comparison signal Vc is output from the comparator. In response to the L level comparison signal Vc, the NOR circuits 32 to 35 output signal level output signals S1 to S4 corresponding to the digital input signals D0 to D3. Specifically, when the delay time by the NOR circuits 32 to 35 elapses from the time t1 (time t2), only the NOR circuit 32 to which the input signal D0 having the signal level “0” is input is the H level output signal S1. Is output. Note that the L level output signals S2 to S4 are continuously output from the NOR circuits 33 to 35 to which the input signals D1 to D3 having the signal level “1” are input.

In response to the H level output signal S1, one transistor T31 is turned on, and in response to the L level output signals S2 to S4, the transistors T32 to T34 are turned off. At this time, the potential difference between the source and drain of the transistor T31 that is turned on becomes the voltage value Vs1 of the output voltage Vo at time t2. For this reason, the current It1 at time t2 that is pulled out from the output terminal Po3 to the ground by the overvoltage protection circuit 30 is Ron when one on-resistance of each transistor T31 to T34 is Ron.
It1 = 1 × Vs1 / Ron
It becomes.

The voltage value Vs1 is the output voltage Vo after the elapse of the delay time (that is, the delay time by the NOR circuit 32) from the time t1 until the transistor T31 is turned on. However, although the delay time is shown in an enlarged manner in FIG. 6, the delay time is actually sufficiently short with respect to the fluctuation of the output voltage Vo adjusted by the feedback control of the operational amplifier 21 shown in FIG. . Therefore, the voltage value Vs1 is
Vs1≈Vs
Can be expressed as

  As described above, when a part of the operating current IRLO is drawn from the output terminal Po3 to the ground by the overvoltage protection circuit 30, the output voltage Vo of the linear regulator 20 gradually decreases. When the output voltage Vo becomes lower than the set voltage Vs, the comparator 31 outputs an H level comparison signal Vc (time t3). In response to the H level comparison signal Vc, L level output signals S1 to S4 are output from all NOR circuits 32 to 35. Specifically, when the delay time by the NOR circuits 32 to 35 elapses from the time t3 (time t4), L level output signals S1 to S4 are output from all the NOR circuits 32 to 35. In response to these L level output signals S1 to S4, all the transistors T31 to T34 are turned off, and the current It drawn from the output terminal Po3 to the ground becomes 0A.

Thereafter, a series of operations from time t1 to time t4 is repeatedly performed, and the output voltage Vo of the linear regulator 20 gradually converges to the set voltage Vs.
At the time t2, the ratio of the analog current Iox1 output from the second output terminal Po2 of the current DAC 10 to the linear regulator 20 and the current It1 drawn to the ground by the overvoltage protection circuit 30 is
Iox1: It1 = 1 × I: 1 × Vs1 / Ron
Iox1: It1 = I: Vs1 / Ron (7)
It becomes.

  Next, the case where the input signal Din is “0001” will be described with reference to FIG. In this case, the current value of the analog current Io output from the first output terminal Po1 of the current DAC10 is “1I”, and the current value of the analog current Iox output from the second output terminal Po2 is “14I”. . That is, the analog current Iox having a current amount of 14/15 out of the total current amount (= 15I) of the analog currents Io and Iox output from the current DAC 10 is supplied to the linear regulator 20.

At time t5 shown in FIG. 7, when the output voltage Vo becomes higher than the set voltage Vs, the comparator 31 outputs an L level comparison signal Vc. In response to the L level comparison signal Vc, the NOR circuits 33 to 35 output the H level output signals S2 to S4, and the NOR circuit 32 outputs the L level output signal S1 (time t6). In response to the H level output signal S2, the two transistors T32 are turned on, in response to the H level output signal S3, the four transistors T33 are turned on, and in response to the H level output signal S4, eight transistors. The transistor T34 is turned on. Also, one transistor T31 is turned off in response to the L level output signal S1. At this time, the potential difference between the source and drain of each of the turned on transistors T32 to T34 becomes the voltage value Vs1 of the output voltage Vo at time t6. For this reason, the current It2 at time t6 that is pulled out from the output terminal Po3 to the ground by the overvoltage protection circuit 30 is represented by Ron as one on-resistance of each of the transistors T32 to T34
It2 = Vs1 / (Ron / 14) = 14 × Vs1 / Ron
It becomes.

  As described above, when part of the operating current IRL0 (analog current Iox) flowing through the output terminal Po3 is drawn to the ground, the output voltage Vo of the linear regulator 20 gradually decreases. When the output voltage Vo becomes lower than the set voltage Vs, the comparator 31 outputs an H level comparison signal Vc (time t7). In response to the H level comparison signal Vc, L level output signals S1 to S4 are output from all the NOR circuits 32 to 35 (time t8). In response to these L level output signals S1 to S4, all the transistors T31 to T34 are turned off, and the current It drawn from the output terminal Po3 to the ground becomes 0A.

Thereafter, a series of operations from time t5 to time t8 is repeatedly performed, and the output voltage Vo of the linear regulator 20 gradually converges to the set voltage Vs.
At the time t6 described above, the ratio between the analog current Iox2 output from the second output terminal Po2 of the current DAC 10 to the linear regulator 20 and the current It2 drawn to the ground by the overvoltage protection circuit 30 is:
Iox2: It2 = 14 × I: 14 × Vs1 / Ron
Iox2: It2 = I: Vs1 / Ron (8)
It becomes.

  As is clear from Equation 8 and Equation 7 above, when the overvoltage protection circuit 30 operates, the ratio between the analog current Iox output from the second output terminal Po2 and the current It drawn to the ground by the overvoltage protection circuit 30. Is always constant (see formula below).

Iox: It = I: Vs1 / Ron
As described above, the ratio of the analog current Iox to the current It is always constant because the current It drawn from the output terminal Po3 to the ground according to the digital input signals D0 to D3 that determine the amount of the analog current Iox. This is because the amount of current is determined. Further, the number of transistors T31 to T34 that are turned on / off according to the input signals D0 to D3 is weighted by a binary ratio corresponding to each bit of the digital input signal Din, and the electrical characteristics of all the transistors T31 to T34 are determined. This is because they are identical.

At this time, the current It drawn to the ground in order to reduce the output voltage Vo is based on the relationship between the analog current Iox and the reactive current Ir0 consumed by the linear regulator 20 when the load RL0 is unloaded.
Iox−Ir0 ≦ It (9)
It is necessary to satisfy the relationship. That is, the output voltage Vo can be lowered by drawing to the ground a current It that is equal to or larger than the differential current obtained by subtracting the reactive current Ir0 from the analog current Iox.

In addition, if all of the analog current Iox is drawn to the ground in the overvoltage protection circuit 30, the analog current Iox cannot be used to generate the output voltage Vo of the linear regulator 20. Therefore, in order to always use the analog current Iox for generating the output voltage Vo of the linear regulator 20, the current It drawn to the ground is
It <Iox (10)
It is necessary to satisfy the relationship. Therefore, the current range of the current It for always using the analog current Iox to generate the output voltage Vo is
Iox−Ir0 ≦ It <Iox (11)
It becomes. From these equations 9 to 11, one on-resistance Ron of each of the transistors T31 to T34 is
Vs1 / Iox <Ron ≦ Vs1 / (Iox−Ir0)
By setting to this range, the current It can be efficiently extracted to the ground without excess or deficiency with respect to the change in the analog current Iox of the current DAC 10. That is, by setting the on-resistance Ron of each of the transistors T31 to T34 within the above range, the output voltage Vo can be reduced by drawing the current It according to the on-resistance Ron to the ground, and the analog current Iox. Can always be used to generate the output voltage Vo.

Next, current consumption that can be reduced when the overvoltage protection circuit 30 operates will be described.
When the overvoltage protection circuit 30 operates, the consumption current Ic1 consumed for generating the output voltage Vo in the semiconductor integrated circuit 1 is:
Ic1 = Iox−Ir0−It
It becomes. At this time, if the current It satisfies the relationship of Equation 10 above,
−Ir0 <Iox−Ir0 = Ic1
When the current It satisfies the relationship of the above equation 11,
Ic1 = Iox−Ir0−It ≦ 0
It becomes. For this reason, the range of the consumption current Ic1 is as follows.
0 ≦ −Ic1 <Ir0
It becomes.

Here, when the consumption current Ic1 is subtracted from the consumption current Ic3 (≧ Ir0) consumed for generating the output voltage Vo of the linear regulator 60 in the conventional semiconductor integrated circuit,
Ic3 ≦ Ic3−Ic1 <Ic3 + Ir0
Ir0 ≦ Ic3 ≦ Ic3-Ic1 <2Ir0 ≦ Ic3 + Ir0
Ir0 ≦ Ic3-Ic1 <2Ir0
It becomes. Therefore, when the overvoltage protection circuit 30 operates, the semiconductor integrated circuit 1 can reduce the current consumption by at least the reactive current Ir0 of the linear regulator 20 as compared with the current consumption Ic3 of the conventional example, and at most twice the reactive current Ir0. Current consumption can be reduced.

  Note that, as described above, the semiconductor integrated circuit 1 when the overvoltage protection circuit 30 does not operate (that is, the period during which the output voltage Vo is lower than the set voltage Vs) is higher than the analog current of the current DAC10 than the current consumption Ic2 of the conventional example. Current consumption can be reduced by Iox. In practice, however, the current consumption that can be reduced is the current obtained by subtracting the current consumed by the comparator 31 in the overvoltage protection circuit 30 from the analog current Iox. However, since the current consumed by the comparator 31 is sufficiently smaller than the reactive current Ir0 of the linear regulator 20 and the maximum current Ioxmax of the analog current Iox, there is no problem even if the current is ignored. Absent.

According to this embodiment described above, the following effects can be obtained.
(1) The second output terminal Po2 from which the analog current Iox of the current DAC10 is output is connected to the output terminal Po3 of the linear regulator 20. That is, the analog current Iox that has been discharged to the ground in the conventional example is added to the operating current IRL0 of the linear regulator 20. Thereby, when the overvoltage protection circuit 30 does not operate, the current supplied by the linear regulator 20 is reduced by the amount of the added analog current Iox. Therefore, when the overvoltage protection circuit 30 does not operate, the current consumption can be reduced by the analog current Iox rather than the current consumption in the conventional semiconductor integrated circuit.

  In the current DAC 10, the currents I1 to I4 of the current sources 11 to 14 are always supplied to one of the first output terminal Po1 and the second output terminal Po2. For this reason, the current DAC 50 can be operated at high speed and stably. Further, in the linear regulator 20, the drive current Ir is always supplied to the transistor T21 regardless of the state of the load RL0 connected to the output terminal Po3. For this reason, the linear regulator 20 can be operated at high speed.

  (2) The overvoltage protection circuit 30 that protects the load RL0 from the overvoltage of the output voltage Vo of the linear regulator 20 is provided. When the output voltage Vo becomes higher than the set voltage Vs, the overvoltage protection circuit 30 removes a part of the operating current IRL0 flowing through the output terminal Po3 of the linear regulator 20 to the ground, thereby increasing the output voltage Vo. Suppressed. Thereby, it can suppress that the element in load RL0 is destroyed by the overvoltage of output voltage Vo.

  Even if the output voltage Vo becomes higher than the set voltage Vs due to the analog current Iox supplied from the current DAC 10, the overvoltage protection circuit 30 suppresses the increase in the output voltage Vo. For this reason, in the semiconductor integrated circuit 1, it is possible to eliminate the constraint condition as shown in the above formula 6.

  By the way, when there is a constraint condition as shown in the above equation 6, the reactive current Ir0 of the linear regulator 20 must be made larger than the analog current Iox. Therefore, in the first circuit in which the overvoltage protection circuit 30 is omitted, if the current consumption required for the linear regulator 20 is smaller than the analog current Iox of the current DAC 10, the current DAC 10 and the linear regulator 20 are used separately. There must be. In such a case, there is a problem that the current consumption of the entire semiconductor integrated circuit 1 cannot be reduced.

  On the other hand, in the semiconductor integrated circuit 1 having the overvoltage protection circuit 30, as described above, it is possible to eliminate the constraint condition expressed by the above equation 6. Therefore, regardless of the specifications (performance) of the current DAC 10 and the linear regulator 20, the current consumption of the entire semiconductor integrated circuit 1 having the current DAC 10 and the linear regulator 20 can be reduced.

  (3) The amount of current It drawn from the output terminal Po3 to the ground is determined in accordance with the digital input signals D0 to D3 that determine the amount of analog current Iox. Thereby, the amount of operating current IRL0 flowing through the output terminal Po3 is controlled according to the amount of analog current Iox supplied to the linear regulator 20, and the output voltage Vo of the linear regulator 20 is controlled. For this reason, even if the overvoltage protection circuit 30 operates, the linear regulator 20 can be operated at high speed.

  (4) Further, when the output voltage Vo becomes higher than the set voltage Vs, the number of transistors T31 to T34 that are turned on / off in response to the digital input signal Din that determines the amount of the analog current Iox is represented by the input signal Din. The binary ratio corresponding to each bit is weighted. Thereby, when the overvoltage protection circuit 30 operates, the ratio between the analog current Iox output from the second output terminal Po2 and the current It drawn to the ground by the overvoltage protection circuit 30 can be made substantially constant. Thereby, even if the signal level (input code) of the input signals D0 to D3 changes, the fluctuation of the output voltage Vo of the linear regulator 20 can be made substantially constant. For this reason, a stable output voltage Vo can be generated.

  (5) The current It drawn from the output terminal Po3 to the ground is set to a current that is equal to or larger than the differential current between the analog current Iox of the current DAC 10 and the reactive current Ir0 of the linear regulator 20, and smaller than the analog current Iox. I made it. As a result, a part of the operating current IRL0 can be efficiently drawn to the ground as the current It without excess or deficiency with respect to the change in the analog current Iox of the current DAC10. That is, it is possible to suitably suppress the output voltage Vo from rising above the set voltage Vs, and the analog current Iox can always be used to generate the output voltage Vo. For this reason, even when the overvoltage protection circuit 30 operates, the current consumption can be reduced by at least the reactive current Ir0 of the linear regulator 20.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In the above embodiment, the current It drawn from the output terminal Po3 to the ground is equal to or larger than the differential current between the analog current Iox of the current DAC 10 and the reactive current Ir0 of the linear regulator 20, and is smaller than the analog current Iox. I set it. However, the current range of the current It is not limited to this. For example, the current It may be equal to the current value of the analog current Iox. In this case, when the overvoltage protection circuit 30 operates, the analog current Iox cannot be used to generate the output voltage Vo. However, even in such a case, the same effects as (1) and (2) of the above embodiment can be obtained.

  In the above embodiment, the current It drawn from the output terminal Po3 to the ground is set according to the digital input signals D0 to D3. For example, when the output voltage Vo becomes higher than the set voltage Vs, a preset constant current It may be drawn to the ground.

  In the above embodiment, the number of transistors T31 to T34 is weighted by a binary ratio corresponding to each bit of the input signal Din. However, the present invention is not limited to this, and weighting may be performed according to the element sizes of the transistors T31 to T34.

  In the above embodiment, the number of transistors T31 to T34 is weighted by a binary ratio corresponding to each bit of the input signal Din. For example, when the current reuse efficiency and the deterioration of the ripple of the output voltage Vo can be tolerated, all the transistors T31 to T34 may be set to the same number. That is, the above weighting in the transistors T31 to T34 may be omitted.

  In the above embodiment, the N channel MOS transistors T31 to T34 are disclosed as an example of the switch circuit, but P channel MOS transistors may be used. A bipolar transistor may be used as the switch circuit.

  -The internal structure of the overvoltage protection circuit 30 in the said embodiment is not specifically limited. For example, the drains (first terminals) of the transistors T31 to T34 may be connected to the second output terminal Po2 of the current DAC10. In this case, when the output voltage Vo becomes higher than the set voltage Vs, at least a part of the current It of the analog current Iox flowing through the second output terminal Po2 is drawn to the ground.

  Alternatively, the overvoltage protection circuit 30 is changed to a circuit that disconnects the connection between the second output terminal Po2 of the current DAC 10 and the output terminal Po3 of the linear regulator 20 when the output voltage Vo becomes higher than the set voltage Vs. Also good.

  The internal configuration of the current DAC 10 in the above embodiment is not particularly limited. That is, the internal configuration of the current DAC 10 is not particularly limited as long as the digital input signal Din can be converted into complementary analog currents Io and Iox.

  -The internal structure of the linear regulator 20 in the said embodiment is not specifically limited. That is, the internal configuration of the linear regulator 20 is not particularly limited as long as it can generate a stable output voltage Vo from the power supply voltage (input voltage) AVD.

  The number of bits of the digital input signal Din in the above embodiment is not particularly limited. That is, the digital input signal Din may be 3 bits or less, or 5 bits or more.

  The overvoltage protection circuit 30 in the above embodiment may be omitted. In this case, the specifications of the current DAC 10 and the linear regulator 20 are limited by the above-described restrictions. If the restrictions are satisfied, the same effects as (1) of the above embodiment are achieved.

1 Semiconductor integrated circuit 10 Current DAC
20 Linear regulator 30 Overvoltage protection circuit 31 Comparator T31 to T34 N-channel MOS transistor RL0 Load

Claims (8)

A current DA converter that converts a digital input signal into a complementary analog current and outputs the complementary analog current from a first output terminal and a second output terminal;
A power supply circuit that generates an output voltage from an input voltage and supplies the output voltage to a load from a third output terminal connected to the second output terminal;
A protection circuit connected to the third output terminal and protecting the load from an overvoltage of the output voltage;
A semiconductor integrated circuit comprising:   2. The protection circuit according to claim 1, wherein when the output voltage becomes higher than a reference voltage, a part of the first current that flows through the third output terminal flows through the ground line when the output voltage is higher than a reference voltage. Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 2, wherein a current value of the first current is set according to the digital input signal. The protection circuit is
A first terminal is connected to the third output terminal, a second terminal is connected to the ground line, and when the output voltage becomes higher than the reference voltage, a plurality of on / off operations based on the digital input signal are performed. 4. The semiconductor integrated circuit according to claim 3, further comprising a switch circuit.   5. The semiconductor integrated circuit according to claim 4, wherein each of the switch circuits includes a number of switch circuits weighted by a binary ratio corresponding to each bit of the digital input signal.   The first current is a current greater than or equal to a difference current between a first analog current supplied from the current DA converter to the power supply circuit and a current consumed by the power supply circuit when the load is unloaded. 6. The semiconductor integrated circuit according to claim 3, wherein the current is smaller than the first analog current.   The semiconductor integrated circuit according to claim 2, wherein the reference voltage is set according to a target voltage of the output voltage.   The semiconductor integrated circuit according to claim 2, wherein the reference voltage is set according to a withstand voltage of the load.