JP2014017550A - Filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AFIR circuit that simply suppresses out-of-band noise of a DAC without adding to the number of analog segments.SOLUTION: An N-tap (N is an integer of two or more) filter circuit 130 includes: N-1 delay elements z-1 connected in series; N signal lines connected to input terminals and output terminals of the delay elements; and an analog segment section including a plurality of capacitive elements 131, 132, 133, 134 connected to M (M is an integer satisfying N>M) signal lines arbitrarily selected from the N signal lines, respectively.

Description

  The present invention relates to an analog FIR (AFIR) circuit, and to an AFIR circuit that suppresses out-of-band noise of an audio D / A converter (DAC) using the analog FIR (AFIR) circuit.

  In order to reduce noise outside the voice band in the DAC, one method is to filter the noise after the DAC. Basically, a switched capacitor filter (SCF) and a smoothing filter are provided after the DAC, and noise shaping characteristics can be canceled and noise can be reduced by using the low-pass filter characteristics of the SCF and smoothing filter. .

  However, in order to completely cancel the noise shaping characteristics with these analog filters, it is necessary to arrange poles in the low band, and the demand for the analog filters becomes severe.

  FIG. 1 illustrates a spectrum of DAC out-of-band noise. Since the zero point of the analog filter is not in the low band, there is a peak of out-of-band noise around 300 kHz.

  FIG. 2 is a block diagram of a conventional DAC. As shown in FIG. 2, the conventional DAC 10 includes a digital delta sigma modulator (ΔΣ) 1, Data weighted averaging (DWA) 2, AFIR 3, SCF 4, and a smoothing filter 5.

  The out-of-band noise may fold back into the band due to modulation and become in-band noise. Therefore, the conventional DAC 10 takes measures to reduce specific frequencies such as fs / 2 and fs / 4 by inserting AFIR3 between DWA2 and SCF4. AFIR3 is an N-tap AFIR having N taps.

FIG. 3 is a diagram schematically showing the configuration of a conventional 4-tap AFIR 20 as a simple example. As shown in FIG. 3, the conventional 4-tap AFIR 20 is different from the conventional 4-tap AFIR 20 in correspondence with three delay elements z ⁻¹ connected in series and each path between the delay elements z ^−1. Sampling capacitors (CAP) 21 to 24. In the 4-tap AFIR 20, the digital data from the DWA2 is input to the first delay element z- ¹ , and the digital data from the DWA2 and the digital data output from each path of each delay element z- ¹ are the sampling CAP21 to 24 is sampled and converted to analog data. Here, the sampling CAPs 21 to 24 also serve as the sampling CAP of the SCF 4 connected to the subsequent stage of the AFIR 3.

David K. Su and Bruce A. Wooley, "A CMOS Oversampling D / A Converter with a Current-Mode Semidigital Reconstruction Filter", IEEE J. Solid-State Circuits, December 1993, vol. 28, p. 1224-1233 .

  For example, in the technique disclosed in Non-Patent Document 1, the number of taps N of N tap AFIR is increased in order to suppress out-of-band noise so that the filter effect is strongly applied.

  However, compared with 1-tap AFIR, N-tap AFIR increases the number of analog segments connected to the latter stage of AFIR by N times. Therefore, when the number of taps N of N tap AFIR is increased as in the technique disclosed in Non-Patent Document 1, an increase in area is inevitable because the analog segment is configured by a switch or the like in addition to sampling CAP.

  Therefore, in view of the above points, an object of the present invention is to provide an AFIR circuit that can easily suppress out-of-band noise of a DAC without increasing the number of analog segments.

  In order to solve the above problems, a filter circuit according to a first aspect of the present invention is an N tap (N is an integer of 2 or more) filter circuit, and N−1 delay elements connected in series. N signal lines connected to the input terminal and output terminal of the delay element, and M signal lines (M is an integer of N> M) arbitrarily selected from the N signal lines. And an analog segment portion including a plurality of capacitive elements connected to each other.

  The filter circuit according to claim 2 of the present invention is a filter circuit of N taps (N is an integer of 2 or more), and uses M taps (M is an integer of N> M) among the N taps. Features.

  A filter circuit according to a third aspect of the present invention is the filter circuit according to the first or second aspect of the present invention, wherein each of the N taps has a weighted impulse coefficient.

  A filter circuit according to a fourth aspect of the present invention is the filter circuit according to the third aspect of the present invention, wherein (N−M) impulse coefficients among the impulse coefficients of each of the N taps are obtained. It is substantially zero.

  The DA converter according to claim 5 of the present invention is a digital delta sigma modulator, the filter circuit according to any one of claims 1 to 4 provided at a subsequent stage of the digital delta sigma modulator, and the filter circuit. And a switched capacitor circuit provided in a subsequent stage.

  According to the present invention, in the N-tap AFIR, by using only M taps out of N taps (N> M), a zero point can be inserted in a lower band, so that the analog area in the subsequent stage It is possible to obtain an AFIR circuit capable of dropping the low frequency without increasing the frequency. That is, by not using the path of (N−M) taps, the number of analog segments becomes the same as that of M tap AFIR, which is a low order, and the analog area can not be increased. As described above, according to the present invention, it is possible to realize the zero point arrangement with the same accuracy as the high-order N-tap AFIR with the number of analog segments of the order of low-order M-tap AFIR.

It is a figure which shows the out-of-band noise spectrum waveform of audio DAC. It is a block diagram of the conventional audio DAC. It is a block diagram of a conventional AFIR circuit. 1 is a block diagram of an audio DAC according to the present invention. It is a block diagram of an AFIR circuit according to the present invention. It is a block diagram of AFIR and SCF concerning the present invention. It is a figure which shows the filter characteristic of the N tap FIR circuit which has a predetermined weighted impulse coefficient. FIG. 8 is a diagram illustrating filter characteristics of a 16-tap FIR circuit according to the present invention having a weighted impulse coefficient different from that of FIG. 7. 1 is a block diagram of a DAC in which FIR circuits according to the present invention are connected in multiple stages.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 4 is a block diagram of the DAC 100 according to the present invention. As shown in FIG. 4, the DAC 100 according to the present invention includes a ΔΣ 110, a DWA 120, an AFIR 130, an SCF 140, and a smoothing filter 150. By inserting the AFIR 130 according to the present invention between the DWA 120 and the SCF 140, a noise peak at a low frequency as shown in FIG. 1 can be dropped, and the demand for the analog filter characteristics in the subsequent stage can be relaxed.

  FIG. 5 is a diagram schematically showing the configuration of the AFIR 130 according to the present invention. In the following, as an exemplary configuration of the AFIR 130 according to the present invention, a configuration of a 16-tap AFIR is shown for simplicity.

As shown in FIG. 5, the AFIR 130 according to the present invention includes 15 delay elements z ⁻¹ connected in series and 4 connected to 4 of the 16 paths P0 to P15. Sampling CAP 131-134. Specifically, the sampling CAP 131 is connected to a path P15 between the delay element z ⁻¹ and the sampling CAP 131, and the sampling CAP 132 is connected to any one of the paths P1 to P14 between the delay elements z ^−1. sampling CAP133 is connected to one of the paths PXX path P1~P14 between each delay element ^{z -1,} the sampling CAP134 is connected to the path P0 between a delay element ^{z -1} and DWA120. The delay element z ⁻¹ can be realized using an FF (flip-flop). By connecting flip-flops in series, a delay line is formed as a shift register.

Digital data from the DWA 120 is input to the delay element z ⁻¹ in the first stage, and the digital data from the DWA 120 and the digital data output from the four paths P0, PXX, PYY, and P15 are sampled to the sampling CAPs 131 to 134. And converted into analog data. Here, the sampling CAPs 131 to 134 also serve as the sampling CAP of the SCF 140 connected to the subsequent stage of the AFIR 130.

FIG. 6 shows an example of a circuit diagram of the AFIR 130 of the present invention and the SCF 140 connected to the subsequent stage. As shown in FIG. 6, the AFIR 130 is connected to 15 delay elements z ⁻¹ connected in series and four paths P0, PXX, PYY, and P15 among the 16 paths P0 to P15. Four sampling CAPs 131 to 134 and four switches SW1 connected to the sampling CAPs 131 to 134, respectively. Sampling units 141 to 144 are configured by the sampling CAPs 131 to 134 and the four switches SW1, respectively. Similarly to the above, the sampling CAPs 131 to 134 also serve as the sampling CAP of the SCF 140 connected to the subsequent stage of the AFIR 130.

  As shown in FIG. 6, the SCF 140 includes sampling units 141 to 144, one sampling switch SW <b> 2, an operational amplifier 145, and a feedback CAP 146. The sampling switch SW2 is connected to the sampling units 141 to 144, the operational amplifier 145 has a negative input terminal connected to the sampling switch SW2, and the feedback CAP 146 has a negative input terminal of the operational amplifier 145 and an output terminal of the operational amplifier 145. And connected in parallel.

  Here, in the AFIR 130 according to the present invention shown in FIGS. 5 and 6 and the like, four of the 16 paths of the 16-tap AFIR are used, but the present invention is not limited to this. , N (N is an integer of 2 or more) tap AFIR, M (M is an integer of N> M) paths can be used. In this case, M paths arbitrarily selected from the N paths connected to the input terminal and the output terminal of the N−1 delay elements are connected to the M sampling units.

In the AFIR 130 shown in FIG. 6, the digital data from the DWA 120 is input to the delay element z ⁻¹ in the first stage, and the digital data from the DWA 120 and the digital data output from the four paths P0, PXX, PYY, and P15 are Each CAP is sampled and converted into analog data.

  The analog segment is composed of sampling units 141 to 144. Actually, since the analog noise is determined by kT / C, the total area of the sampling CAPs 131 to 134 does not change. However, the AFIR 130 according to the present invention taps by using only a few taps of N taps. By reducing the number, the number of switches SW1 in the analog segment can be reduced.

  Also, as shown in FIG. 6, for example, if the impulse train is weighted so that only 4 taps of 16-tap AFIR are used, zero-point arrangement with 16-tap AFIR accuracy is performed with the same number of analog segments as 4 taps. be able to.

  FIG. 7 shows the filter characteristics of the N tap AFIR. FIG. 7 shows a conventional non-weighted 4-tap AFIR filter characteristic, a conventional non-weighted 16-tap AFIR filter characteristic, and an arbitrarily weighted 16-tap AFIR filter characteristic according to the present invention. Yes.

  Here, in FIG. 7, the weighted impulse coefficients are [1/4, 0, 0, 0, 0, 0, 1/4, 0, 0, 1/4, 0, 0, 0, 0, 0, 1/4], but is not limited to this. Making the impulse coefficient substantially zero is equivalent to not using that path. By selecting the weighted impulse coefficients in this way, the band to be dropped (around 300 kHz from FIG. 1) can be cut by about 20 dB. The transfer function T at this time is expressed by the following (Equation 1).

The position of the zero point can be obtained by solving a higher order equation where the transfer function T becomes zero. In this case, there are zeros at the following 15 points.
-1.0000, -0.8660 ± 0.5000i, -0.7660 ± 0.6428i, -0.1736 ± 0.9848i, 0.0000 ± 1.0000i, 0.5000 ± 0.8660i, 0.9397 ± 0.3420i, 0.8660 ± 0.5000i

  By obtaining the zero point position from the transfer function T, an arbitrary frequency band can be filtered.

As for the determination method of the impulse coefficient, the sum of the impulse coefficients may be set to 1 in total so that the DC gain becomes 1. Also, it is better to insert the impulse coefficients as symmetrically as possible. Furthermore, since the term of z ⁻¹⁵ on the transfer function T remains from the equation (1) by always including the impulse coefficient in the final tap, 15 taps can be secured.

  FIG. 8 shows another weighted impulse coefficient [1/4, 0, 0, 1/4, 0, 0, 0, 0, 0, 0, 0, 0, 1/4, 0, 0, 1/4]. The filter characteristic of AFIR which has is shown. As shown in FIG. 8, by selecting the weighted impulse coefficients in this way, it is possible to drop about 20 dB around 1 MHz. As described above, taps having impulse coefficients may be selected according to the band to be dropped, and paths other than those may be used. Of course, you may select 8 taps instead of 4 taps among 16 taps. Thereby, the filter characteristics can be made steeper. When eight taps are selected, the number of paths to be selected and the sampling units connected to the paths are increased to eight. Similarly, M taps can be selected from N taps.

  Further, in digital filter design, a method for obtaining a coefficient from filter characteristics using Matlab (trademark) or the like is general. However, in the AFIR 130 according to the present invention, the coefficient is determined so that the impulse coefficient is zero as much as possible. Just do it.

  FIG. 9 is a block diagram of a DAC in which FIR circuits according to the present invention are connected in multiple stages. FIG. 9 illustrates a DAC 200 including a ΔΣ 210, a DWA 220, a digital FIR 230, an AFIR 130, an SCF 240, and a smoothing filter 250.

  For example, when two stages of FIR circuits having the same transfer function are connected as in the DAC 200 shown in FIG. 9, the number of zeros is doubled, so that steeper filter characteristics can be realized. At that time, the first stage FIR may be constituted by a digital FIR, and the second stage may be constituted by an AFIR 130 according to the present invention. In the case of multi-stage connection, the first and subsequent stages of FIR may be configured by digital FIR, and only the final stage of FIR may be configured by AFIR 130 according to the present invention.

  As the filter characteristics, in addition to the low-pass characteristics, for example, the digital FIR 230 may have a high-pass characteristic and the AFIR 130 may have a low-pass characteristic to realize the band-pass filter characteristic as a whole.

  As described above, the AFIR circuit 130 according to the present invention can insert a zero point in a lower band by using several taps of N taps having a high degree, and lowers the low band noise. be able to. Further, in the AFIR 130 according to the present invention, by not using the path of (N−M) taps, it is equivalent to the M tap AFIR having a low number of analog segments, and the analog area can not be increased. In the AFIR 130 according to the present invention, as a secondary effect, the filter characteristics of the analog filter can be relaxed by dropping the low frequency with AFIR.

  Further, according to the AFIR 130 according to the present invention, the zero point can be shifted by arbitrarily selecting a tap (for M paths) to be used among the N taps. Further, according to the AFIR 130 according to the present invention, the fs / 2 and fs / 4 bands can be reduced as in the case of the conventional AFIR.

1, 110, 210 ΔΣ
2, 120, 220 DWA
3 Conventional AFIR
4, 140, 240 SCF
5, 150, 250 Smoothing filter 10, 100, 200 DAC
20 Conventional 4-tap AFIR
21-24, 131-134 Sampling CAP
130 AFIR of the present invention
141 to 144 Sampling unit 145 Operational amplifier 146 Feedback CAP
230 Digital FIR

Claims (5)

N tap (N is an integer of 2 or more) filter circuit,
N-1 delay elements connected in series;
N signal lines connected to the input terminal and the output terminal of the delay element;
And an analog segment unit including a plurality of capacitive elements respectively connected to M (M is an integer of N> M) signal lines arbitrarily selected from the N signal lines. circuit. N tap (N is an integer of 2 or more) filter circuit,
A filter circuit using M taps (M is an integer of N> M) among the N taps.   The filter circuit according to claim 1, wherein each of the N taps has a weighted impulse coefficient.   4. The filter circuit according to claim 3, wherein (N−M) impulse coefficients among the impulse coefficients included in each of the N taps are substantially zero. 5. A digital delta-sigma modulator,
The filter circuit according to any one of claims 1 to 4, provided at a subsequent stage of the digital delta-sigma modulator;
A switched-capacitor circuit provided at a subsequent stage of the filter circuit.

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