JP2014016925A - Information processing system, data switching method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more properly set determination reference as to whether a hardware failure occurs in an information processing system for switching data when determining that the hardware failure occurs.SOLUTION: A threshold storage part 13 stores a threshold to be used to determine whether to use a preliminary data storage part 12. Thus, determination reference as to whether a hardware failure occurs can be more properly set. For example, a user of an information processing system 1 sets a threshold in data of use having relatively high necessity for performing processing at a high speed so as to make the determination reference as to whether a hardware failure occurs moderate. In addition, the user of the information processing system 1 sets a threshold in data of use having a relatively low necessity for performing processing at a high speed so as to make the determination reference as to whether the hardware failure occurs strict.

Description

  The present invention relates to an information processing system, a data switching method, and a program.

  ECC (Error Correction Code) is known as a countermeasure when an error occurs in a data bit of a memory. In general ECC, a 1-bit error can be corrected, and a 2-bit error can be detected.

In the memory device described in Patent Document 1, when a fixed fault occurs in a SIMM (Single Inline Memory Module) and a copy operation instruction signal is received, the control circuit receives the data portion of the word of the SIMM designated by the address data and the ECC. A copy cycle in which the target data with ECC is read out from the part, the bit error is corrected by the error check / correction circuit, the fixed failure occurrence bit of this data is selected by the alternative data selection circuit, and the value is written in the spare part of the SIMM. This is performed for all the words in the SIMM, whereby the correct data of the fixed failure occurrence bit is copied to the spare part. Thereafter, for read access, the value of the fixed failure occurrence bit of the ECC-added target data read from the SIMM is replaced with the spare part data, and the replaced ECC-added target data is sent to the error check / correction circuit.
Thereby, even if a fixed failure occurs in the memory, the reliability of the access processing is not reduced.

Japanese Patent Laid-Open No. 10-021149

  However, when a hardware failure occurs in a memory using ECC, error detection and correction continue each time access is performed. As a result, the operation load of the memory controller becomes higher than normal, and the memory access speed may be reduced.

  Further, in the memory device described in Patent Document 1, the determination as to whether or not a fixed failure has occurred is not described in detail as being performed by the access source. With regard to this determination, in Patent Document 1, the access source analyzes the status signal returned from the error check / correction circuit for read access and the error bit notification signal F by software or the like, for example, “1 bit error occurs frequently, If the condition that the error bit and its data value are the same every time is satisfied, it can be estimated that a fixed fault such as a stuck-at fault has occurred in one bit of the SIMM. However, Patent Document 1 does not show how often a 1-bit error occurs and whether or not it is determined that a 1-bit error frequently occurs.

  Here, when an error occurs during memory access, it is generally difficult to accurately determine whether or not the error is caused by a hardware failure (fixed failure in Patent Document 1). It is. If the criterion for determining whether or not a hardware failure has occurred is too strict, even if a hardware failure occurs, it may not be determined as a hardware failure. Then, error detection and correction continue every time access is performed, and the operation load of the memory controller becomes higher than normal, which may reduce the memory access speed.

  On the other hand, if the criteria for determining whether or not a hardware failure has occurred is too loose, it is determined that a hardware failure has occurred even though no hardware failure has actually occurred. There is a risk. If a spare bit (a spare part bit in Patent Document 1) is used in this determination, there is a possibility that when a hardware failure is actually detected, there is no spare bit that can be used and it cannot be handled. .

  An object of the present invention is to provide an information processing system, a data switching method, and a program that can solve the above-described problems.

  The present invention has been made to solve the above-described problems, and an information processing system according to an aspect of the present invention includes a main data storage unit that stores data, and a partition that partitions a storage area of the main data storage unit. Whether or not to use the spare data storage unit and the spare data storage unit that stores a part of the data in the partition instead of the main data storage unit in the setting of use. A threshold value storage unit that stores a threshold value used for the determination, and a preliminary data switching determination unit that determines, for each partition, whether to use the backup data storage unit corresponding to the partition using the threshold value. It is characterized by doing.

  Further, in the data switching method according to one aspect of the present invention, the main data storage unit that stores data and the use or non-use are set for each partition that divides the storage area of the main data storage unit. A spare data storage unit that stores part of the data in the partition instead of the main data storage unit, and a threshold storage unit that stores a threshold value used for determining whether to use the spare data storage unit, A data switching method for an information processing system comprising a preliminary data switching determination step for determining whether to use the preliminary data storage unit corresponding to the partition using the threshold value for each partition. It is characterized by.

  Further, the program according to one aspect of the present invention is set to use or non-use for each of the main data storage unit that stores data and the storage area of the main data storage unit. A spare data storage unit that stores part of the data in the partition instead of the main data storage unit; and a threshold storage unit that stores a threshold value used for determining whether to use the spare data storage unit. This is a program for causing an information processing system to execute a preliminary data switching determination step for determining whether or not to use the preliminary data storage unit corresponding to each partition using the threshold value for each partition.

  According to the present invention, it is possible to more appropriately set a criterion for determining whether or not a hardware failure has occurred.

It is a schematic block diagram which shows the function structure of the information processing system in one Embodiment of this invention. It is explanatory drawing which shows the example of switching of the data signal in the information processing system 1 using the DDR memory of the embodiment. It is a schematic block diagram which shows the structural example of the information processing system using the DDR memory in the embodiment. It is a data block diagram which shows the example of a data structure in the storage area of the DDR memory of the embodiment. It is explanatory drawing which shows the data connection before and behind the data selection part in the normal time of the embodiment. It is a data block diagram which shows the structural example of the error count value data which the register function part in the embodiment memorize | stores the frequency | count of the error for every data bit. It is a data block diagram which shows the data structural example of the reserve data assignment register which the register function part in the embodiment memorize | stores. It is explanatory drawing which shows the data connection before and behind the data selection part after switching of the embodiment. It is explanatory drawing which shows the example of the data value in the storage area of the DDR memory after switching of the embodiment. It is a schematic block diagram which shows the structural example of the information processing system in the modification of the embodiment.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a functional configuration of an information processing system according to an embodiment of the present invention. In FIG. 1, the information processing system 1 includes a main data storage unit 11, a backup data storage unit 12, a threshold storage unit 13, and a backup data switching determination unit 21.
The information processing system 1 can be various information processing systems that store data. For example, the information processing system 1 may be a computer system, a personal computer (PC), or a portable information terminal (Personal Digital Assistant).

  Note that the main data storage unit 11, the backup data storage unit 12, the threshold storage unit 13, and the backup data switching determination unit 21 may all be included in a single device, or may be divided into a plurality of devices. It may be. For example, the main data storage unit 11, the spare data storage unit 12, and the threshold storage unit 13 may all be realized by a storage device built in the information device including the backup data switching determination unit 21. It may be realized by an external storage device.

The main data storage unit 11 stores data to be directly stored (hereinafter referred to as “main data”) such as data used when a computer executes an application program.
The spare data storage unit 12 is set to be used or not used for each partition that partitions the storage area of the main data storage unit 11. Then, the spare data storage unit 12 stores a part of the data in the partition in place of the main data storage unit 11 in the use setting (that is, a setting indicating that the spare data storage unit 12 is used).

The threshold storage unit 13 stores a threshold used for determining whether or not to use the spare data storage unit 12.
The spare data switching determination unit 21 determines, for each partition that partitions the storage area of the main data storage unit 11, whether to use the spare data storage unit 12 corresponding to the partition using a threshold value.

Thus, the threshold storage unit 13 stores a threshold used for determining whether or not to use the spare data storage unit 12. As a result, it is possible to more appropriately set a criterion for determining whether or not a hardware failure (hereinafter referred to as “hardware failure”) has occurred.
For example, the user of the information processing system 1 sets a threshold value so that a criterion for determining whether or not a hardware failure has occurred is moderate for data for relatively high usage that requires high-speed processing. Keep it. Based on the threshold value, when a hardware failure occurs, the information processing system 1 is expected to switch the storage unit of the bit in which the failure has occurred from the main data storage unit 11 to the spare data storage unit 12. By this switching, it is possible to avoid a state in which error detection and correction continues every time access is performed, and a decrease in memory access speed can be prevented.

  In addition, the user of the information processing system 1 sets a threshold for data for a use that is relatively less necessary to perform processing at a high speed so that a criterion for determining whether or not a hardware failure has occurred becomes strict. deep. By making the preliminary data switching determination unit 21 perform determination based on the threshold value, it is possible to reduce the risk of determining that a hardware failure has occurred even though a hardware failure has not actually occurred. Therefore, when the spare data switching determination unit 21 actually detects a hardware failure, it is possible to reduce a possibility that there is no spare bit that can be already used and it cannot be handled.

Next, the present embodiment will be described in more detail by taking as an example a case where a DDR (Double Data Rate) memory is used as a storage device for realizing the main data storage unit 11, the spare data storage unit 12, and the threshold storage unit 13.
However, the application range of the present invention is not limited to the DDR memory. The present invention can be applied to various storage devices in which an error caused by a hardware failure and a temporary error (soft error) not caused by a hardware failure can occur.

  FIG. 2 is an explanatory diagram showing an example of data signal switching in the information processing system 1 using a DDR memory. In FIG. 1, the information processing system 1 includes a processor 101 and a plurality of DDR memories 104. The processor 101 includes a processor core 102 and a memory controller 103.

  In the information processing system 1 using the DDR memory described below, the data width is 32 bits and the accompanying ECC is 4 bits on the bus from the processor 101 to the DDR memory 104. However, the present invention does not depend on the data width of the bus between the processor and the memory, the type of error correction bits, and the number of bits. Therefore, the data width of the bus from the processor 101 to the DDR memory 104 is not limited to 32 bits. The number of ECC bits is not limited to 4 bits, and error correction means other than ECC may be used.

In FIG. 2, in the connection between the processor 101 and the DDR memory 104, main data signals DATA [7-0] to DATA [31-24], data strobe signals DQS0 to DQS3, and ECC data In addition to connection of normal data signals such as the signal ECC_DATA [3-0] and the data strobe signal ECC_DQS, connection of a spare data signal (RSB_DATA [3-0] 212) is shown.
Note that [] indicates a bit position. For example, “[7-0]” indicates a series of bits from the 7th bit to the 0th bit.

Since the memory controller 103 has a function of switching access to a data bit to a spare data signal when an error occurs in a specific data bit, it is possible to suppress the occurrence of a continuous error due to a hardware failure. .
For example, when the waveform quality is low and an error occurs at a specific bit due to the design, frequent occurrence of the error can be avoided.

As an error caused by the design, for example, due to wiring on the printed circuit board between the processor and the DDR memory, the quality of the signal waveform at a specific data bit is poor, the temperature change under the environmental conditions as the device and the device Errors that occur due to characteristic variations are considered.
In order to avoid such errors, it is conceivable to design hardware that is sufficiently resistant to environmental changes and device characteristic variations, such as printed circuit board design. However, it is very difficult to foresee errors at the design stage in a DDR memory that requires multi-branch connection due to high capacity, low voltage and high speed.

  On the other hand, as shown in FIG. 2, a data bit in which an error has occurred is not used and switching to spare data avoids a state in which an error continuously occurs, thereby realizing stable memory access. be able to. Therefore, it is possible to avoid an error state without the need for redesign or repair within the range of the preliminary data, and in this respect, the risk at the time of manufacture or design can be reduced.

  FIG. 3 is a schematic configuration diagram illustrating a configuration example of the information processing system 1 using a DDR memory. In FIG. 1, the information processing system 1 includes a processor 101 and a plurality of DDR memories 104. The processor 101 includes a processor core 102 and a memory controller 103. The memory controller 103 includes a data transmission / reception unit 201, an access control unit 202, a register function unit 203, an ECC function unit 204, an internal bus conversion unit 205, and a data selection unit 206.

The processor 101 is hardware that operates software in an information device (for example, a computer, an electric device, an information communication device, or the like).
Here, the present invention does not depend on the type of processor, and the present invention can be applied to various processors. For example, the processor 101 may be a CPU (Central Processing Unit) or an NPU (Network Processing Unit, a processor installed in a network card). Alternatively, the processor 101 may be a DSP (Digital Signal Processor, a microprocessor specialized in digital signal processing). Alternatively, the processor 101 may be a built-in processor of an FPGA (Field-Programmable Gate Array, an integrated circuit whose configuration can be set by a purchaser or designer after manufacture).

The processor core 102 is an arithmetic device that operates software, and has a function of interpreting and executing program instructions.
The memory controller 103 serves as an interface with a peripheral memory (for example, the DDR memory 104) that stores instructions and data for the processor 101 to operate.

  The DDR memory 104 is a non-volatile memory that plays a role of storing instructions and data for operating the processor 101 around the processor 101. As the DDR memory 104, for example, a DDR2 SDRAM (Double-Data-Rate2 Synchronous Dynamic Random Access Memory) may be used. Alternatively, a DDR3 SDRAM (Double-Data-Rate 3 Synchronous Dynamic Random Access Memory) may be used as the DDR memory 104.

  The data transmitting / receiving unit 201 is a functional unit that transmits and receives data signals. In general, in a DDR memory interface, data is processed based on a DQS signal (data strobe signal). The data transmitting / receiving unit 201 adjusts the drive capability and the data input / output timing for the DQS in accordance with the configuration and specifications of the connected memory. The data transmission / reception unit 201 plays a role of latching data and DQS signal output to the DDR memory 104 and data input from the DDR memory 104 with reference to the DQS signal.

The access control unit 202 is a functional unit that adjusts the access control timing in accordance with the configuration and specifications of the connected memory and is responsible for sending control signals, address signals, and clock signals to the DDR memory 104.
The register function unit 203 is a control register in the memory controller 103. The register function unit 203 is a register that sets access timing, drive capability, and the like according to the memory specifications for the data transmitting / receiving unit 201 and the access control unit 202, and a register for checking the error detection state of the ECC function unit 204. Have Further, the register function unit 203 includes a setting register for the data selection unit 206 to perform switching control of data bits in which an error has occurred. For example, the processor core 102 controls each register of the register control unit.

  The ECC function unit 204 has a function of detecting an error in the main data and automatically repairing it by adding the ECC to the main data and storing it in the memory. When the data is read, the ECC function unit 204 detects an error by comparing the code calculated from the read data with the original code (code stored in the memory), and corrects the 1-bit error. I do.

The internal bus conversion unit 205 is a functional unit that performs data transmission / reception of the internal bus 210 between the processor core 102 and the memory controller 103. The internal bus conversion unit 205 acquires write data for access from the processor core 102 to the memory controller 103 via the internal bus 210. Further, the internal bus conversion unit 205 sends the read data from the DDR memory 104 to the processor core 102 via the internal bus 210.
The data selection unit 206 switches the access to the bit in which the error is detected to the spare data bit according to the error occurrence state detected by the ECC function unit 204.

  In the configuration shown in FIG. 3, the data bus width is 64 bits (DATA [63-0]), and the accompanying ECC is 8 bits (ECC [7-0]). Further, the data width of the DDR memory 104 is 16 bits, and one area in one bank is constituted by five memories including those for ECC. Specifically, DDR # 1 to DDR # 4 and ECC & spare DDR # 1 constitute one area in bank 0 and store 64-bit main data. Also, DDR # 5 to DDR # 8 and ECC & spare DDR # 2 form one area in bank 1 and store 64-bit main data.

  However, the scope of application of the present invention is not limited to that shown in FIG. For example, the data bus width, the number of ECC bits, and the data width of the DDR memory are not limited to those shown in FIG. 3. Accordingly, the number of DDR memories 104 constituting one area of one bank is shown in FIG. It is not limited to five. Further, the number of banks in the information processing system 1 is not limited to two shown in FIG. 3 and may be three or more.

In the configuration shown in FIG. 3, the data signal is extended with respect to a general connection between the memory controller 103 and the DDR memory 104. Specifically, 8-bit data signals (RSB_DATA [3-0] and FLG_DATA [3-0]) are added to 64 bits of main data for each area in the bank.
This additional number of bits is because data is handled as one lane in byte (8 bits) units in the DDR memory 104. One DQS signal is paired for each lane, and the 8-bit data in the lane is Transmission / reception is performed based on DQS. A DQS signal (RSB_DQS 211) is added as a reference for the expanded data signal.

  Of the 8 extended data signals, 4 bits are reserved data signals RSB_DATA [3-0] used for switching (redundancy) when an error occurs. The remaining 4 bits are a flag signal FLG_DATA [3-0] for indicating whether or not RSB_DATA [3-0] is used in the accessed address area.

In the configuration shown in FIG. 3, DDR # 1 to DDR # 8 storing main data correspond to an example of a main data storage unit in the present invention. The ECC & spare DDR # 1 for storing spare data RSB_DATA [3-0] corresponds to an example of a spare data storage unit in the present invention.
The register function unit 203 stores a threshold value used for determining whether or not to use the spare data RSB_DATA [3-0]. The register function unit 203 is an example of the threshold value storage unit in the present invention. Applicable.

Further, as described above, the data selection unit 206 switches the access to the bit in which the error is detected to the spare data bit in accordance with the occurrence state of the error detected by the ECC function unit 204. That is, the data selection unit 206 is a functional unit that determines whether or not to use the spare data RSB_DATA [3-0], and corresponds to an example of the spare data switching determination unit in the present invention.
Further, one area in each bank constituted by the five DDR memories 104 corresponds to an example of a partition of the storage area of the main data storage unit in the present invention.

Next, the operation of the information processing system 1 using the DDR memory shown in FIG. 3 will be described.
In the initial sequence for the DDR memory 104, the memory controller 103 performs timing adjustment and initialization for the extended data bits in addition to timing adjustment and initialization of the data bits of the main data and the ECC data bits.

First, the operation of the information processing system 1 in a normal time (a state where no error occurs) will be described.
In a normal state, the data selection unit 206 does not use the extended data bits at the time of writing (Write, writing to the memory) and at the time of reading (Read, reading from the memory).
At the time of write access from the processor core 102 to the DDR memory 104, the data selection unit 206 performs ECC using the data (SEL_DATA [63-0] 209) from the internal bus conversion unit 205 as normal data (DEF_DATA [63-0] 208). Enter in the function section. The ECC function unit 204 calculates the ECC of normal data, and inputs the calculated ECC 8 bits and normal data 64 bits to the data transmitting / receiving unit 201.

  At this timing, the access control unit 202 inputs a write command with a control signal to the memory address area designated by the processor core, and the data transmitting / receiving unit 201 stores the data of 64 bits, ECC data of 8 bits, and the DQS signal. To enter. Data input to the memory is stored in a specified address area. At this time, for the extended data bits, ALL-Zero data (data of all bits 0) is output in accordance with RSB_DQS and stored in the DDR memory 104.

  FIG. 4 is a data configuration diagram showing a data configuration example in the storage area of the DDR memory 104. In the figure, an example in which the information processing system 1 includes a plurality of DDR memories 104 for each bank is shown. As in the case of DDR # 1 to DDR # 4 and ECC & spare DDR # 1 described in FIG. 3, one area is composed of five DDR memories.

The 64-bit normal data written by designating the bank A area of CS0 is stored in DDR # 1 to DDR # 4 that handle data. The ECC data 8 bits are stored in the ECC spare DDR # 1, and ALL-Zero is stored in the extended data area handled by the memory.
At the time of read access from the processor core 102 to the memory, the access control unit 202 inputs a read command to the DDR memory 104. The DDR memory 104 inputs 64 bits of data, 8 bits of ECC, 8 bits of extension data (RSB_DATA [3-0] and FLG_DATA [3-0]) and DQS paired with each data to the memory controller 103.

  The data transmission / reception unit 201 of the memory controller 103 latches 64 bits of data, 8 bits of ECC data, and 8 bits of extension data based on DQS and inputs them to the ECC function unit 204. The ECC function unit 204 checks the value of the extension data 8-bit flag data (FLG [3-0] 214). As described above, 0 (Zero) is stored in the flag data at the normal time.

  When the flag data is 0 (Zero), the ECC function unit 204 performs ECC calculation on 64 bits of normal data and compares it with 8 bits of ECC data read from the DDR memory 104. In the normal state (the state where there is no error), the compared ECCs match each other, and the ECC function unit outputs 64 bits of data and 8 bits of extended data (RSB [3-0], FLG [3-0]) without correction. The data is input to the data selection unit 206.

  The data selection unit 206 confirms the value of the extension data 8-bit flag data (FLG [3-0] 214) input in the same manner as the ECC function unit 204. When the flag data is 0, it indicates that the spare data (RSB [3-0] 207) is not used. Therefore, the data selection unit 206 inputs 64 bits of data to the internal bus conversion unit 205. The internal bus conversion unit outputs the 64-bit data (SEL_DATA [63-0]) from the data selection unit 206 to the processor core 102.

  As described above, 64 bits of data (main data) from the processor core 102 are written to the storage area of the DDR memory 104 and 64 bits of main data are read to the processor 101 during normal operation (the state where no error occurs). Is done. In this normal time, the internal logical data 64 bits coincide with the physical data 64 bits for the DDR memory.

  FIG. 5 is an explanatory diagram showing data connections before and after the data selection unit 206 in a normal state. Normally, as shown in the figure, DATA [63-0] is used as a main data storage area, and the values of spare data RSB_DATA [3-0] and flag data FLG_DATA [3-0] are 0. Yes.

Next, the operation of the information processing system 1 when an error occurs will be described.
When one bit out of 64 bits of main data stored in the DDR memory 104 at the time of writing is incorrect, or when one bit out of the data read by the data transmitting / receiving unit 201 at the time of reading is incorrect, The ECC function unit 204 detects an error.
The ECC function unit 204 detects an error when a mismatch occurs between the ECC calculated by the ECC function unit 204 itself from 64-bit main data and the ECC data read from the DDR memory 104. It is possible to identify a bit causing an error from the mismatched bits of the ECC data, and the ECC function unit 204 corrects the error bit.

Further, the register function unit 203 has an error occurrence count register for storing the number of errors that have occurred in each data bit in order to determine whether or not to switch the data bit in which an error has occurred to spare data.
FIG. 6 is a data configuration diagram illustrating a configuration example of error count value data in which the register function unit 203 stores the number of errors for each data bit. As shown in the figure, the register function unit 203 stores the number of errors (error count value) for each of the 64 bits of data for each bank area. The initial value of each error count value is set to zero.
When an error occurs in any of the bits, the error count value of the corresponding bit is incremented (1 is added to the value).

  Note that the unit in which the register function unit 203 counts errors is not limited to each region. For example, the register function unit 203 may count the number of error occurrences of each bit for each bank so that the bit in which the error has occurred can be switched for each bank. In this case, the register function unit 203 has registers for the number of banks × the number of bits, and counts the number of error occurrences for each bank and for each bit.

Further, the register function unit 203 has an error threshold register for storing a threshold value for determining whether or not to switch access to a data bit in which an error has occurred to spare data.
When the number of error occurrences at a certain bit exceeds the value set in the error threshold register, the data selection unit 206 performs a switching operation to spare data. The user can arbitrarily change the number of error occurrences for switching to spare data by changing the value of the error threshold register.

Next, an operation in which the information processing system 1 performs switching to spare data will be described.
As an example, when the number of error occurrences in the data bit 31 exceeds the threshold in the access to the area A (area constituted by DDR # 1 to # 4 and ECC & spare DDR # 1) of the bank 0 (CS0 bank) Will be described. The ECC function unit 204 sets a value in the data switching flag register of the register function unit 203 to indicate that the access of the data bit 31 has been switched to spare data.

FIG. 7 is a data configuration diagram illustrating a data configuration example of the spare data assignment register stored in the register function unit 203.
The register function unit 203 has a spare data assignment register as a register indicating the value of the data bit to be switched for each bank area and for each of the spare data 4 bits. The register function unit 203 has a spare data enable register as a register for indicating that the spare data is valid.

  The spare data enable register is a flag provided for each bank area and for each of 4 bits of spare data. The initial value of the register (enable bit) is set to 0 indicating that the corresponding spare data is not switched. Setting the enable bit to 1 indicates that the corresponding spare data switching has become effective.

In the example in which the number of error occurrences exceeds the value of the threshold register in the data bit 31 of the area A of the bank 0 (CS0), the ECC function unit 204 stores 31 (in the spare data # 0 assign register corresponding to the area A of the bank 0. 0x1F). Further, the ECC function unit 204 sets 1 to the enable bit of the spare data 0 (RSB [0] 207) of the spare data enable register corresponding to the area A of the bank 0.
By setting 1 in the spare data enable register, the memory controller 103 switches the physical connection of the memory in the bank of CS0 to the spare logical data 0 with respect to the internal logical data bit 31 in the subsequent access.

The write operation and read operation after switching will be described.
At the time of write access from the processor core 102 to the DDR memory 104, the data selection unit 206 checks the status of the spare data enable register and the spare data assignment register of the register function unit 203. Then, the data selection unit 206 substitutes the value of the data bit 31 in the data (SEL_DATA [63-0] 209) from the internal bus conversion unit 205 into the preliminary data 0 and inputs it to the ECC function unit.
The other data bits are input as normal data (DATA [63-32: 30-0] 208) to the ECC function unit. Further, as information indicating that spare data 0 is valid for the memory area to be accessed, the value of flag data 0 (FLG [0] 214) is set to 1 and input to the ECC function unit.

FIG. 8 is an explanatory diagram showing data connections before and after the data selection unit 206 after switching.
The ECC function unit 204 checks the statuses of the spare data enable register and the spare data assignment register of the register function unit 203 as with the data selection unit 206. Then, the ECC function unit 204 calculates the ECC using the spare data 0 instead of the data bit 31 and inputs the calculated ECC data 8 bits to the data transmitting / receiving unit 201. The data transmitting / receiving unit 201 inputs 64 bits of normal data, 4 bits of spare data (RSB_DATA [3-0] 212), and flag data (FLG_DATA [3-0] 213) to the DDR memory 104. Each data input to the DDR memory 104 is stored in a designated address area.

FIG. 9 is an explanatory diagram showing an example of data values in the storage area of the DDR memory 104 after switching.
In the area B of FIG. 8, an example in which the data bit 31 is switched to the spare data 0 is shown. Data of data bit 31 is stored in bit RSB_DATA [0] that handles spare data 0. Further, a value 1 indicating that spare data is used is stored as the value of the flag FLG_DATA [0] corresponding to the spare data 0.
When the number of error occurrences in other data bits exceeds the threshold value, the remaining spare data 1 to 3 are used in the same procedure.

In the area C of FIG. 9, an example in which spare data is used in the data bit 48 in addition to the data bit 31 is shown. As described above, switching to spare data when an error occurs can be controlled for each bank area. In area C, spare data can be assigned to a data bit different from area D.
In the area E, an example in which the data bit 17 is switched to spare data is shown.

  At the time of read access from the processor core 102 to the DDR memory 104, the memory controller 103 determines whether spare data is used for the data in the read area. As described above, in order to switch to spare data in accordance with the error occurrence status, the DDR memory 104 includes a portion where normal data 64 bits are used for each region, a portion where switching to the spare data has occurred, and Are mixed. The register function unit 203 stores a value for the determination in the flag data of the spare data enable register.

When the value of the flag data read from the spare data enable register of the register function unit 203 by the memory controller 103 is 0, it indicates that only normal data is used, and the processing is as described above.
On the other hand, when 1 is set in the read flag data, it indicates that spare data is used. In this case, the ECC function unit 204 confirms which data bit the spare data is based on the value of the spare data assignment register of the register function unit 203. Then, the ECC function unit 204 performs ECC calculation on the 64-bit data using the spare data, and compares it with the 8-bit ECC data read from the DDR memory 104. Further, the data selection unit 206 exchanges data with the internal bus conversion unit 205 using data 64 bits (SEL_DATA [63-0] 209) in which the value of the spare data is the value of the corresponding data bit.

With the above procedure, in the information processing system 1, when an error exceeding a threshold value occurs in a certain bit in accessing the DDR memory 104, the data bit in which the error has occurred is switched to spare data. As a result, it is possible to avoid a state where errors frequently occur with the same bit.
The setting for the spare data switching register of the register function unit 203 can be changed from the processor core 102. For example, if it is known that a certain data bit is disconnected due to a manufacturing defect or the like, the user initializes the register at the time of startup by setting software parameters in advance. Thereby, defects can be avoided from the initial stage of memory access.

In the above, the case where the data bus of the memory is 64 bits and the data width of the connected memory is 16 bits has been described. However, as described above, the scope of application of the present invention is not limited to this. The present invention can also be applied to a memory having a memory bus of 32 bits, a data width of 8 bits, and a configuration having a large number of banks, as in the above example.
In the above description, the ECC function unit 204 performs ECC on 64-bit data. However, the ECC function unit 204 performs error correction or error detection by ECC for expanded data. May be.

  As described above, in the information processing system 1, the data bit in which an error has occurred is not used and is switched to spare data, thereby avoiding a state in which errors frequently occur and ensuring a stable memory access state. obtain. This can prevent the occurrence of simultaneous errors (multi-bit errors) in multiple bits and the load (speed reduction) due to errors in memory access, and reduce the risk of hindering the operation of the device mounting the processor. I can do it.

Further, even if an error due to waveform quality degradation or connection failure occurs in a certain bit during design or manufacturing, an error state can be avoided without requiring redesign or repair within the range of spare data.
In addition, the present invention can be applied by adding signals and adding functions to the memory controller using an existing memory interface. Therefore, the present invention can be applied without increasing the number of memories due to memory multiplexing and without the need for additional peripheral circuits.

Further, the register function unit 203 stores a threshold value used for determining whether or not to use spare data, thereby determining whether or not a hardware failure has occurred as described with reference to FIG. The criteria can be set more appropriately.
For example, the user of the information processing system 1 sets a threshold value so that a criterion for determining whether or not a hardware failure has occurred is moderate for data for relatively high usage that requires high-speed processing. Keep it. When a hardware failure occurs, the information processing system 1 determines, based on the threshold, the storage location of the bit where the failure has occurred from the DDR memory 104 (DDR # 1 to DDR # 8) that stores the main data. Switching to the DDR memory 104 (ECC & spare DDR # 1 to ECC & spare DDR # 2) for storing spare data. By this switching, it is possible to avoid a state in which error detection and correction continues every time access is performed, and a decrease in memory access speed can be prevented.

  In addition, the user of the information processing system 1 sets a threshold for data for a use that is relatively less necessary to perform processing at a high speed so that a criterion for determining whether or not a hardware failure has occurred becomes strict. deep. The information processing system 1 (particularly, the data selection unit 206) may switch data based on the threshold value, and may determine that a hardware failure has occurred even though no hardware failure has actually occurred. Can be reduced. Therefore, when the information processing system 1 actually detects a hardware failure, it is possible to reduce a possibility that there is no spare bit that can be already used and it cannot be handled.

In addition, the register function unit 203 stores a threshold value used for determining whether to use spare data for each section of the storage area of the DDR memory 104 (for each bank area). Then, the information processing system 1 (particularly, the data selection unit 206) uses, for each partition, a threshold corresponding to the partition, and stores DDR memory 104 (ECC & spare DDR #) corresponding to the partition. 1 to ECC & spare DDR # 2) is determined.
As a result, even when the DDR memory 104 stores data corresponding to a plurality of application programs, even when storing data having different needs for processing at a high speed, according to the necessity of performing the processing at a high speed. Thus, it is possible to more appropriately set a criterion for determining whether or not a hardware failure has occurred for each data.

  Note that the register function unit 203 may be realized using a non-volatile storage device, or may be realized using a volatile storage device. When the register function unit 203 is realized using a volatile storage device, switching of bit errors may be managed using a nonvolatile memory. As a result, in a case where the information processing system 1 is restarted, it is possible to switch to the preliminary data immediately after the startup, and it is possible to prevent frequent errors. In addition, when the information processing system 1 is restarted, a new hardware failure occurs before switching to spare data in accordance with a hardware failure that has already occurred. A situation in which the operation of the system 1 cannot be maintained can be prevented.

FIG. 10 is a schematic configuration diagram illustrating a configuration example of an information processing system according to a modification of the present embodiment. In FIG. 1, the information processing system 2 includes a processor 301, a plurality of DDR memories 104, and a nonvolatile memory 702. The processor 301 includes a processor core 102 and a memory controller 103. The memory controller 103 includes a data transmission / reception unit 201, an access control unit 202, a register function unit 203, an ECC function unit 204, an internal bus conversion unit 205, a data selection unit 206, and a nonvolatile memory controller 701. To do.
In the figure, portions having the same functions corresponding to the respective portions in FIG. 1 are denoted by the same reference numerals (102 to 104, 201 to 206), and description thereof is omitted.

The nonvolatile memory 702 is a memory that stores programs and settings necessary for the processor core 102 to operate. In particular, the nonvolatile memory 702 stores data for bit error switching.
The nonvolatile memory controller 701 serves as an interface between the processor core 102 and the nonvolatile memory 702, and manages the switching of bit errors using the nonvolatile memory 702. The nonvolatile memory controller 701 is realized by, for example, extending the function of a ROM (Read Only Memory) controller included in the information processing system 1.

When a single bit error occurs, the processor core 102 stores the error occurrence status in the nonvolatile memory 702 via the nonvolatile memory controller 701.
When the information processing system 2 is restarted, the processor core 102 reads the error occurrence information before the restart from the nonvolatile memory 702 and sets the setting for switching the bit in which the error has occurred to the spare data to the memory controller 103. Do. Thereby, it is possible to prevent an error from occurring at the same bit after the restart.

Note that a program for realizing all or part of the functions of the spare data switching determination unit 21, the processor 101, and the processor 301 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is recorded. The processing of each unit may be performed by being read and executed by a computer system. Here, the “computer system” includes an OS and hardware such as peripheral devices.
Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory in a computer system serving as a server or a client in that case, and a program that holds a program for a certain period of time are also included. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design changes and the like without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Information processing system 11 Main data memory | storage part 12 Reserve data memory | storage part 13 Threshold value memory | storage part 21 Reserve data switching determination part 101, 301 Processor 102 Processor core 103 Memory controller 104 DDR memory 201 Data transmission / reception part 202 Access control part 203 Register function part 204 ECC function unit 205 Internal bus conversion unit 206 Data selection unit 701 Non-volatile memory controller 702 Non-volatile memory

Claims (4)

A main data storage unit for storing data;
Preliminary data storage unit that is set to be used or not used for each partition that partitions the storage area of the main data storage unit, and stores a part of the data in the partition in place of the main data storage unit in the setting of use When,
A threshold value storage unit for storing a threshold value used for determining whether to use the preliminary data storage unit;
For each partition, a preliminary data switching determination unit that determines whether to use the preliminary data storage unit corresponding to the partition using the threshold value;
An information processing system comprising: The threshold storage unit stores the threshold for each partition,
The spare data switching determination unit determines, for each partition, whether to use the spare data storage unit corresponding to the partition using the threshold value corresponding to the partition.
The information processing system according to claim 1. A main data storage unit for storing data;
Preliminary data storage unit that is set to be used or not used for each partition that partitions the storage area of the main data storage unit, and stores a part of the data in the partition in place of the main data storage unit in the setting of use When,
A threshold value storage unit for storing a threshold value used for determining whether to use the preliminary data storage unit;
A data switching method for an information processing system comprising:
A data switching method, comprising: a preliminary data switching determination step for determining whether to use the preliminary data storage unit corresponding to the partition using the threshold value for each partition. A main data storage unit for storing data;
Preliminary data storage unit that is set to be used or not used for each partition that partitions the storage area of the main data storage unit, and stores a part of the data in the partition in place of the main data storage unit in the setting of use When,
A threshold value storage unit for storing a threshold value used for determining whether to use the preliminary data storage unit;
In an information processing system comprising
A program for executing a preliminary data switching determination step for determining whether or not to use the preliminary data storage unit corresponding to the partition by using the threshold value for each partition.

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