JP2014011309A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A TSV and a back bump electrode are effectively integrally formed and embedded in a semiconductor substrate by the same process.
On a back surface 1r of a semiconductor substrate 1, a back surface protection film 5 such as silicon nitride is formed. The back surface bump electrode / TSV 87 in which the TSV and the back surface bump electrode are integrally formed of a dielectric material such as copper is embedded through the seed layer so that the TSV portion and a part of the bump electrode are buried. Are arranged. In other words, the hole in which the back surface bump electrode / TSV 87 is embedded includes a TSV through hole corresponding to the TSV, and a cylindrical step portion (substrate recess portion) continuous with the TSV through hole corresponding to a part of the bump electrode. It consists of The side wall of the TSV through hole portion of the hole is covered with an insulating film, and a TSV side wall insulating ring 61 is formed. Solder 81 is formed by plating on the surface of the bump electrode portion of the back bump electrode / TSV87.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a semiconductor device in which a plurality of semiconductor chips (semiconductor devices) are stacked to realize high functionality, upper and lower semiconductors are formed by through electrodes (Through Silicon Via: TSV) provided so as to penetrate the semiconductor chips and bump electrodes. There is a structure for electrically connecting chips.

  Here, even in the manufacture of each semiconductor chip based on the via last method (circuit element—multilayer wiring—a method in which TSV is formed from the back surface of the substrate after forming the front surface bump), the front surface bump electrode, TSV In general, the back bump electrodes are formed in separate steps (see, for example, the upper terminal 9, the through electrode 15, and the lower electrode 26 in Patent Document 1).

JP 2009-124087 A

  However, if the TSV and the back bump electrode can be integrally formed in the same process, it is preferable because the manufacturing process can be shortened.

  The semiconductor device of the present invention is a backside bump electrode / through electrode in which a semiconductor substrate having a circuit element on a main surface, and a bump electrode and a through electrode on the back side of the semiconductor substrate are integrally molded, On the other hand, the gist of the present invention includes a through-electrode portion and a back-surface bump electrode / through-electrode in which a part of the bump electrode portion is embedded.

  According to the semiconductor device of the present invention, since a part of the back bump electrode portion of the back bump electrode / through electrode is embedded in the semiconductor substrate, the through electrode portion is maintained while ensuring the size of the back bump electrode portion. Even if the diameter is reduced and miniaturized, the mechanical strength of the back bump electrode portion in the assembly process can be ensured. In particular, even when wet etching is performed to remove the exposed seed layer, undercutting to the back bump electrode portion can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the structure of the semiconductor device in one Embodiment of this invention, The figure (b) is a figure which shows the board | substrate back surface side, The figure (a) is shown in the figure (b). It is sectional drawing of A1-A1 part. It is a figure which shows the laminated structure at the time of laminating | stacking multiple semiconductor devices shown in FIG. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the semiconductor device in other embodiment of this invention. It is a figure which shows the example of the variation of the shape of a bump electrode part and a TSV part.

Hereinafter, an example of a semiconductor device to which the present invention is applied and a method for manufacturing the same will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

  FIG. 1 is a diagram for explaining a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a diagram showing a substrate main surface side, and FIG. It is sectional drawing of the A1-A1 part shown to (b).

  First, as shown in FIG. 1B, the semiconductor device 500 includes a through electrode (hereinafter referred to as “TSV” (Through Silicon Via)) region (or bump electrode region) formed longitudinally in the center. And there is an element region extending to the left and right.

  Referring to the cross-sectional view of FIG. 1A, the semiconductor device 500 generally has a structure in which first to fifth interlayer insulating films 2a to 2e are stacked on a semiconductor substrate 1. A wiring layer 23 a and an upper layer wiring 23 b are formed between the first to fifth interlayer insulating films 2 a to 2 e, and they are electrically connected via via plugs 24. Note that some of the wiring layers 23a to be formed are circularly formed in at least the TSV region shown in FIG. 1B, and these correspond to TSV through holes TH described later.

  A circuit element 21 including a gate electrode / gate insulating film, a source / drain (S / D) region, and the like is formed in an element region of the main surface 1f of the semiconductor substrate 1, that is, a circuit formation surface.

  A passivation film (polyimide) 4 that is a resin layer is formed on the element region of the fifth interlayer insulating film 2e. In addition, on the TSV region of the fifth interlayer insulating film 2e, a plurality of front surface bump electrodes (for example, made of copper) connected to the upper layer wiring 23b formed in the fifth interlayer insulating film 2e through the seed layer 32 are provided. ) 3 is formed. A protective film 31 such as a gold film is formed on the upper surface of the front surface bump electrode 3 in order to prevent its oxidation.

  On the other hand, the thickness of the semiconductor substrate 1 is, for example, about 40 μm. On the back surface 1r of the semiconductor substrate 1, a back surface protection film 5 such as silicon nitride is formed. Further, the back surface bump electrode / TSV 87 in which the TSV and the back surface bump electrode are integrally formed of a dielectric material such as copper is interposed through the seed layer 71 so that the TSV portion and a part of the bump electrode are buried. Are disposed on the substrate 1. In other words, the hole in which the back surface bump electrode / TSV 87 is embedded includes a TSV through hole corresponding to the TSV, and a cylindrical step portion (substrate recess portion) continuous with the TSV through hole corresponding to a part of the bump electrode. It consists of The TSV through hole portion is covered with an insulating film from the TSV through hole portion side wall and the cylindrical cut portion to the back surface protective film 5, and a TSV side wall insulating ring 61 is formed on the TSV through hole portion side wall. ing. Also, solder (SnAg alloy) 81 is formed on the surface of the bump electrode portion of the back bump electrode / TSV 87 by plating.

FIG. 2 is a diagram illustrating a stacked structure when a plurality of the semiconductor devices illustrated in FIG. 1 are stacked.
Referring to the drawing, a plurality of semiconductor devices 500a to 500e are stacked on one surface of a package substrate 501. Here, the semiconductor devices 500a to 500d function as core chips, and the semiconductor device 500e functions as an interface chip. Each of the semiconductor devices 500a to 500e is electrically connected to the upper and lower parts through the front surface bump electrode 3 and the rear surface bump electrode / TSV87 to have a laminated structure.

  Further, each of the semiconductor devices 500 a to 500 e is covered with the mold resin 502 and filled in the mold resin 502 by filling the inner space with the underfill 503. A plurality of solder balls 504 are formed on the other surface of the package substrate 501 and are electrically connected to the front bump electrode 3 of the semiconductor device 500e through the through-hole 505 and the rewiring 506. Has been.

  Here, since the semiconductor device 500a is the uppermost semiconductor device having a stacked structure, it is sufficient that a signal or power supplied from a terminal of the semiconductor device 500b can be taken into the own device through the terminal of the own device. It is not necessary to supply the signal supplied from the terminal of the semiconductor device 500b to another semiconductor device. Therefore, the uppermost semiconductor device 500a may not have the back bump electrode / TSV87. As described above, when the back surface bump electrode / TSV87 is not formed on the semiconductor device 500a, it is not necessary to reduce the thickness of the chip to facilitate the formation of the back surface bump electrode / TSV87. Can be thicker. As a result, at the time of manufacturing the laminated structure, the yield can be improved, for example, deformation of the semiconductor device due to thermal stress when the semiconductor devices are stacked can be suppressed.

  In FIG. 2, a structure in which four semiconductor devices 500a to 500d are stacked is taken as an example. However, the present invention can be applied to a stacked structure in which the number of stacked semiconductor devices is two or more. As described above, the above-described configuration can be applied to a stacked structure in which the number of stacked semiconductor devices is other than four. That is, in such a stacked structure, the through electrode and the terminal are not formed in the semiconductor device stacked at the top level, and the thickness of the semiconductor device stacked at the top level is set to be different from that of other semiconductor devices constituting the stacked structure. It is possible to apply a configuration in which the thickness is increased.

  Further, from the standpoint that all the same type of semiconductor devices have the same configuration, the uppermost semiconductor device may have the back bump electrode / TSV like the lower one, and the present invention has such a laminated structure. Is effective as well.

  Next, a method for manufacturing the semiconductor device in one embodiment of the present invention shown in FIG. 1 will be described. 3-13 is a figure for demonstrating the manufacturing method in order, and is sectional drawing in the A1-A1 part of FIG.1 (b).

  Therefore, first, in order to manufacture to the state shown in FIG. 3, the gate electrode / gate insulating film and the source / drain (S / D) region are formed on the main surface 1f of the semiconductor substrate 1, that is, on the circuit forming surface side. The first interlayer insulating film 2a is laminated on the main surface 1f while forming the circuit element 21 made of the like. Next, a wiring layer 23a such as aluminum is formed on the first interlayer insulating film 2a by dry etching using a photoresist (PR) as a mask.

  Next, second to fifth interlayer insulating films 2b to 2e are further stacked on the first interlayer insulating film 2a. In each of the second to fifth interlayer insulating films 2b to 2e, an upper layer wiring (for example, aluminum, copper, etc.) 23b is formed, and these and the wiring layer 23a are electrically connected by the via plug 24. Yes. Next, a passivation film (polyimide) 4 that is a resin layer is formed on the fifth interlayer insulating film 2e. A pad opening is formed in the fifth interlayer insulating film 2e.

  Referring to FIG. 4, next, seed layer 32 is formed by sputtering on fifth interlayer insulating film 2e, on upper wiring 23b of the opening, and on passivation film 4. Next, a photoresist film PR is formed on the seed layer 32. Next, a pattern PT is formed by photolithography.

Referring to FIG. 5, next, O ₂ plasma treatment is performed to improve the wettability in the photoresist PR hole with respect to the subsequent plating solution. Then, a front surface bump electrode (for example, made of copper) 3 connected to the upper layer wiring 23b formed in the fifth interlayer insulating film 2e through the seed layer 32 is formed by a known method such as electroplating. A protective film 31 such as a gold film is formed on the upper surface of the front surface bump electrode 3 in order to prevent its oxidation.

  Referring to FIG. 6, next, the photoresist PR is removed, and further, the exposed seed layer 32 is removed by wet etching.

  Hereinafter, it is a processing step for the back surface 1r of the semiconductor substrate 1. Here, in one embodiment of the method for manufacturing a semiconductor device of the present invention, as described later, the TSV and the back bump electrode are integrally formed, and at that time, special measures are taken.

  That is, from the viewpoint of bump overlay accuracy when forming the stacked structure of the semiconductor device shown in FIG. 2, the diameter of the bump electrode needs to be about 10 μm, but from the viewpoint of integration, the through hole for TSV It is desirable to make them as fine as possible.

  At this time, in the back surface bump electrode / TSV, when the boundary line between the back surface bump electrode and the TSV is flush with the back surface 1r (more precisely, the seed layer) of the substrate 1, in other words, the back surface bump electrode portion is the substrate. If the entire back surface 1r is exposed, the necking strength of the back surface bump electrode / TSV due to assembly in a later process is insufficient due to the difference in the diameter of the TSV portion and the diameter of the bump electrode portion. As a result, a brittle bump electrode is formed. In particular, when wet etching is performed to remove the seed layer from the exposed portion after the formation of the back bump electrode / TSV, there is a weak point that an undercut tends to occur in the seed layer portion at the joint portion between the bump electrode and the back surface 1r of the substrate 1.

  From this point of view, the processing on the back side of the substrate in one embodiment of the method for manufacturing a semiconductor device of the present invention is specifically performed as follows.

  That is, referring to FIG. 7, the back surface 1r of the semiconductor substrate 1 is ground (Back Grind), so that the thickness of the semiconductor substrate 1 is, for example, about 40 μm. Next, a back surface protective film 5 such as silicon nitride is formed on the back surface 1r of the semiconductor substrate 1, and further, holes corresponding to bump electrode portions of a back surface bump electrode / TSV 87 described later (for bump electrodes) are formed thereon. A photoresist (first photoresist) PR having a pattern PT-B for forming a hole) is formed. Then, a plurality of bump electrode holes BH are formed by dry etching using the photoresist PR as a mask.

Referring to FIG. 8, next, the photoresist PR is removed.
Referring to FIG. 9, next, a photoresist PR (second photoresist) PR having a pattern PT-T for forming a TSV through hole corresponding to a TSV portion of a back bump electrode / TSV 87 described later is formed. . Then, a plurality of TSV through holes TH are formed by dry etching using the photoresist PR as a mask.

  Referring to FIG. 10, next, when the photoresist PR is removed, a damascene shape is formed in which spaces corresponding to TSVs and bump electrodes are formed. Thereafter, the insulating film 60 is formed across the remaining surface of the back surface protective film 5 and the bump electrode hole BH and the TSV through hole TH. The insulating film 60 can be composed of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof. At this time, the insulating film 60 covers the side surface and the bottom surface of the cylindrical step (substrate recess portion) for the bump electrode hole BH, and covers the side surface and the bottom surface for the TSV through hole TH. Form.

  For example, in the case of a TSV through hole having an aspect ratio of about 5, by forming the insulating film 60 by a low temperature CVD (LT-CVD) process at a film forming temperature of 200 ° C. or less, the bump electrode hole BH The film thickness of the insulating film 60 on the bottom surface of the cylindrical cut portion is ensured to be 90% or more when the film thickness on the surface of the back surface protective film 5 is 100%. On the other hand, the film thickness of the insulating film 60 on the bottom surface of the TSV through hole TH is about 20 to 30% when the film thickness on the surface of the back surface protective film 5 is 100%.

  Referring to FIG. 11, next, the insulating film on the bottom surface of TSV through hole TH is removed by anisotropic etching (etch back). Thereby, the TSV side wall insulating ring 61 is formed on the side surface of the TSV through hole TH. Note that the TSV side wall insulating ring 61 uses the above-described film thickness distribution of the insulating film 60 from the side surface of the TSV through hole TH to the surface of the bump electrode hole BH (side surface and bottom surface of the cylindrical step). It is possible to form it continuously over the back surface protective film 5.

  Referring to FIG. 12, next, a thin film of seed layer 71 is formed over the entire exposed back surface. The seed layer 71 is composed of titanium, titanium nitride, tantalum, tantalum nitride, or a laminated film thereof, but is not necessarily required.

  Referring to FIG. 13, next, after a photoresist (third photoresist) PR is formed on the seed layer 71 including the bump electrode hole BH and the TSV through hole TH, a photolithography method is used. Then, a pattern PT for integrally molding the back surface bump electrode / TSV87 is formed.

  Referring to FIG. 14, the bump electrode hole BH, the TSV through hole TH, and the hole formed by the pattern PT are formed on the back bump electrode / TSV87 by a known method such as electroplating. (For example, copper) is integrally molded. A protective film 81 such as a gold film is formed on the surface of the back bump electrode / TSV 87 in order to prevent its oxidation.

  Referring to FIG. 15, next, the photoresist PR is removed, and the exposed seed layer 71 is removed by wet etching.

  Thereafter, the structure shown in FIG. 2 is obtained through processes such as known dicing, chip mounting, and assembly.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the back bump electrode portion of the back bump electrode / TSV 87 is partially embedded in the substrate 1. Even if the diameter of the TSV portion is reduced and miniaturized while the size of the portion is secured, the mechanical strength of the back bump electrode portion in the assembly process can be secured. In particular, even when wet etching is performed to remove the exposed seed layer 71, undercutting to the back bump electrode portion can be prevented.

(Modification)
Another embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. As described above, in the method for manufacturing a semiconductor device according to an embodiment of the present invention, the photoresist PR is removed as shown in FIG.
According to the method for manufacturing a semiconductor device according to another embodiment of the present invention, referring to FIG. 16, next, the insulating film 51 extends over the surface of the remaining back surface protective film 5 and the bump electrode hole BH. Form. At this time, the insulating film 51 is formed so that the side surface and the bottom surface of the bump electrode hole BH are entirely covered. As the insulating film 51, it is preferable to use the same film as the insulating film 60 described above.

  Referring to FIG. 17, next, a photoresist PR (second photoresist) PR having a pattern PT-T for forming a TSV through hole corresponding to the TSV portion of the back surface bump electrode / TSV87 is formed. Then, a plurality of TSV through holes TH are formed by dry etching using the photoresist PR as a mask. Thus, by forming the TSV through hole TH together with the insulating film 51, the insulating film 51 can be left in the bump electrode hole BH.

Next, referring to FIG. 18, when the photoresist PR is removed, a damascene shape is formed in which spaces corresponding to the TSVs and the bump electrodes are formed. Thereafter, an insulating film is formed across the surface of the insulating film 51 remaining on the back surface protective film 5 and in the bump electrode hole BH and the TSV through hole TH. Note that this insulating film is preferably the same film as the insulating film 60 described above. At this time, the TSV through hole TH is formed so as to cover the side surface and the bottom surface thereof. Next, the insulating film on the back surface protective film 5, the surface of the bump electrode hole BH, and the bottom surface of the TSV through hole TH is removed by anisotropic etching (etch back). Thereby, the TSV side wall insulating ring 62 is formed on the side surface of the TSV through hole TH. Then, a thin film of the seed layer 71 is formed over the entire exposed surface of the back surface.
The subsequent steps are the same as the steps after FIG.

  In the above-described one embodiment and the other embodiments, the back bump electrode / TSV 87 is described as having a shape in which both the bump electrode portion and the TSV portion of the back bump electrode / TSV 87 are circular in cross section. The shape of the bump electrode part and the TSV part is not limited to this, and various shapes can be adopted from the viewpoint of strength and design. At this time, it is not necessary to match the shape of the bump electrode portion with the shape of the TSV portion. FIG. 19 (formerly FIG. 14) is a diagram illustrating an example of variations in the shapes of the bump electrode portion and the TSV portion. FIG. 4A is a diagram showing a case where the bump electrode portion has a cylindrical shape, and the TSV portion has a circular column and a quadrangular column, respectively. FIG. 2B is a diagram showing a case where the shape of the bump electrode portion is a quadrangular prism and the TSV portion is a cylinder and a quadrangular prism, respectively. FIG. 4C shows a case where the bump electrode portion has a hexagonal column shape, and the TSV portion has a cylindrical column and a quadrangular column, respectively.

  In the above-described one embodiment and other embodiments, the number of bump electrodes is described by showing three rows in the direction perpendicular to the longitudinal direction of the semiconductor substrate. However, the present invention is not limited to this. There is nothing. Further, in the stacked structure of a plurality of semiconductor devices shown in FIG. 2, if the structure has bump electrodes on the main surface and the back surface of the substrate, it is effective to apply the present invention and the semiconductor device constituting the core chip is effective. The structure is not limited to the structure shown in the figure in terms of the stacking direction (face-down or face-up) and the presence or absence of TSV of the uppermost semiconductor device.

  The present invention can be applied to a semiconductor device based on a via last method in which TSV and a back bump electrode are integrally formed by a single electroplating method in the same process.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Interlayer insulating film 21 ... Circuit element 3 ... Front surface bump electrode 31 ... Protective film 32 ... Seed layer 4 ... Passivation film 5 .... Back surface protection film 61 TSV side wall insulating ring 71 seed layer 81 protection film 87 back surface bump electrode / through electrode 500 semiconductor device PT pattern PR photo Resist TH ... Through hole for TSV BH ... Hole for bump electrode

Claims (7)

A semiconductor substrate with circuit elements on the main surface;
A back surface bump electrode / through electrode in which a bump electrode and a through electrode on the back surface side of the semiconductor substrate are integrally molded, wherein the through electrode portion and a part of the bump electrode portion are part of the semiconductor substrate. Buried back bump electrode / through electrode,
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a seed layer in a buried joint portion of the back bump electrode / penetrating electrode with the semiconductor substrate.   2. The semiconductor device according to claim 1, wherein a portion of the bump electrode of the back bump electrode / through electrode has a cylindrical shape and a diameter of 10 μm or more.   4. The semiconductor device according to claim 1, further comprising a front surface bump electrode corresponding to the back surface bump electrode / through electrode on a back surface side of the semiconductor substrate. 5.   The semiconductor device according to claim 4, wherein a plurality of the semiconductor devices are stacked. Forming a first photoresist having a pattern for forming a hole corresponding to the bump electrode portion of the back bump electrode / through electrode on the back side of the semiconductor substrate having a circuit element on the main surface;
Using the first photoresist as a mask, forming a bump electrode hole by dry etching;
Removing the first photoresist from the semiconductor substrate;
Forming a second photoresist having a pattern for forming a through hole for a through electrode corresponding to a through electrode portion of the back bump electrode / through electrode on the back side;
Using the second photoresist as a mask, forming a through hole for the through electrode by dry etching;
Removing the second photoresist from the semiconductor substrate;
Forming a seed layer over the bump electrode hole, the through electrode through hole, and the remaining back surface of the semiconductor substrate;
Forming a third photoresist having a pattern of holes corresponding to the bump electrode holes on the back surface;
A step of integrally molding a back bump electrode / through electrode by electroplating on a hole for a bump electrode, a through hole for a through electrode, and a sidewall of the hole of the third photoresist;
Removing the third photoresist from the semiconductor substrate;
Removing the exposed seed layer by wet etching;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a front bump electrode on a main surface side of the semiconductor substrate.

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