JP2014006564A - Semiconductor integrated circuit design method and design program - Google Patents

Abstract

A design method and a design program for a semiconductor integrated circuit capable of easily performing a design satisfying a timing constraint.
According to one embodiment, a method for designing a semiconductor integrated circuit is described in which a data path between flip-flops 502 and 503 operating in synchronization with different clock signals is synchronized with the same clock signal. A larger timing margin is set for the data path between the operating flip-flops 501 and 502, and logic synthesis is performed.
[Selection] Figure 1

Description

  The present invention relates to a design method and a design program for a semiconductor integrated circuit, for example, a design method and a design program for a semiconductor integrated circuit suitable for a design that satisfies timing constraints.

  A conventional logic synthesis apparatus performs logic synthesis by giving a uniform timing margin to each data path between a plurality of flip-flops without considering layout design. Therefore, in the conventional logic synthesis device, it is difficult to satisfy the timing constraints such as the setup time in the subsequent timing driven layout design (layout design performed while optimizing the timing).

  Related techniques are disclosed in Patent Document 1 and Patent Document 2.

  The method for designing a semiconductor integrated circuit disclosed in Patent Document 1 assumes that clock tree synthesis is performed to optimize timing skew of a clock signal in the placement and routing process, and the logic circuit is optimized during the logic synthesis process. It is characterized by performing.

  A semiconductor integrated circuit design apparatus disclosed in Patent Document 2 is a timing margin setting unit that temporarily sets a timing margin for an operating frequency of a logic circuit in a semiconductor integrated circuit, and a timing margin that is temporarily set in the timing margin setting unit. The logic synthesis unit for determining the logic circuit, the timing margin calculation unit for calculating the timing margin of the logic circuit determined by the logic synthesis unit, and the logic synthesis unit according to the timing margin calculated by the timing margin calculation unit A synthesis constraint creating unit that creates a new constraint on the design value of the determined logic circuit. Thus, this design apparatus designs a desired semiconductor integrated circuit quickly and accurately.

JP 2000-208632 A JP 2001-196458 A

  However, the semiconductor integrated circuit design method disclosed in Patent Document 1 performs logic synthesis assuming clock tree synthesis in layout design, but does not perform logic synthesis considering OCV (On Chip Variation). Therefore, with this semiconductor integrated circuit design method, it is still difficult to satisfy the timing constraints such as the setup time in the subsequent timing driven layout design.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a method for designing a semiconductor integrated circuit includes: a data path between flip-flops operating in synchronization with different clock signals; and data between flip-flops operating in synchronization with the same clock signal. Set a larger timing margin for the path and perform logic synthesis.

  According to another embodiment, a semiconductor integrated circuit design method connects between a first module that is flattened and subjected to logic synthesis and a second module that is flattened and subjected to logic synthesis. A timing margin corresponding to the number of data paths is set for the data path, and logic synthesis is performed.

  Further, according to another embodiment, a semiconductor integrated circuit design program can be used for a data path between flip-flops that operate in synchronization with different clock signals, and flip-flops that operate in synchronization with the same clock signal. The computer is caused to execute a first setting process for setting a larger timing margin than the data path between them and a synthesis process for performing logic synthesis.

  According to the embodiment, it is possible to provide a design method and a design program for a semiconductor integrated circuit capable of easily performing a design satisfying a timing constraint.

1 is a block diagram illustrating a configuration example of a logic synthesis device according to a first exemplary embodiment; 3 is a flowchart illustrating an operation of the logic synthesis device according to the first exemplary embodiment; FIG. 3 is a circuit diagram showing a part of a net list output from the logic synthesis device according to the first exemplary embodiment; 1 is a block diagram illustrating a hardware configuration example of a logic synthesis device according to a first embodiment; FIG. 3 is a block diagram illustrating a configuration example of a logic synthesis device according to a second exemplary embodiment; It is a figure which shows the table of the timing margin set with respect to the data path between modules. 10 is a flowchart illustrating an operation of the logic synthesis device according to the second exemplary embodiment; FIG. 10 is a block diagram illustrating a part of a net list output from a logic synthesis device according to a second exemplary embodiment; FIG. 6 is a block diagram illustrating a configuration example of a logic synthesis device according to a third exemplary embodiment; It is a figure which shows the table of the timing margin set with respect to the data path in a module. 10 is a flowchart illustrating an operation of the logic synthesis device according to the third exemplary embodiment. FIG. 10 is a block diagram illustrating a part of a net list output from a logic synthesis device according to a third exemplary embodiment; FIG. 10 is a block diagram illustrating a configuration example of a logic synthesis device according to a fourth embodiment;

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a block diagram of a configuration example of a logic synthesis device (semiconductor design device) 1 according to the first embodiment. The logic synthesizer 1 according to the present embodiment is provided for a data path between flip-flops operating in synchronization with different clock signals, and for a data path between flip-flops operating in synchronization with the same clock signal. Set a larger timing margin and perform logic synthesis. As a result, the logic synthesis device 1 according to the present embodiment can more easily perform a design that satisfies the timing constraints in the subsequent timing-driven layout design. This will be specifically described below.

  A logic synthesis device 1 shown in FIG. 1 is a device that logically synthesizes a description (structure description) relating to the structure of a circuit such as an RTL description and outputs it as a net list (logic circuit). Specifically, the logic synthesis device 1 includes a logic synthesis unit 11, an FF extraction unit 12, and a margin setting unit 13, and reads the RTL description 14, the timing constraint information 15 and the library 16 of the semiconductor integrated circuit. The net list 17 is output.

  The FF extraction unit 12 extracts a description corresponding to the flip-flop from the RTL description 14.

  The timing constraint information 15 includes, in addition to the timing constraint information used at the time of conventional logic synthesis, timing margin information set for a data path between flip-flops operating in synchronization with different clock signals, and the same clock signal. Timing margin information set for a data path between flip-flops that operate in synchronization with each other.

  The margin setting unit 13 sets the timing margin acquired from the timing constraint information 15 for each data path between the plurality of flip-flops extracted by the FF extraction unit 12.

  Here, the margin setting unit 13 is a data path between flip-flops that operates in synchronization with the same clock signal with respect to a data path between flip-flops that operates in synchronization with different clock signals among the plurality of flip-flops. Set a larger (severe) timing margin than Specific setting contents will be described later.

  The logic synthesis unit 11 logically synthesizes the RTL description 14 according to the timing margin set by the margin setting unit 13 and other timing constraints, and outputs it as a net list 17. Note that the logic synthesis unit 11 performs logic synthesis by reading a library 16 that stores design information of basic logic circuits such as NAND circuits and INV circuits, as in the prior art.

  Next, the operation of the logic synthesis device 1 will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the logic synthesis device 1. First, the logic synthesis device 1 extracts a description corresponding to a flip-flop from the RTL description 14 (S101). Next, the logic synthesis device 1 sets the timing margin acquired from the timing constraint information 15 for each data path between the extracted plurality of flip-flops (S102). Here, the logic synthesizer 1 is configured so that the data paths between the flip-flops operating in synchronization with different clock signals among the plurality of extracted flip-flops are between the flip-flops operating in synchronization with the same clock signal. Set a larger (severe) timing margin than for the data path. Specific setting contents will be described later. Next, the logic synthesizer 1 logically synthesizes the RTL description 14 according to the set timing margin and other timing constraints (S103), and outputs it as a netlist 17 (S104).

  Next, the setting contents of the timing margin for each data path between the plurality of flip-flops will be described using a specific example.

  FIG. 3 is a circuit diagram showing a part of the netlist 17. The netlist 17 includes flip-flops 501 to 503, a PLL 504, and a frequency divider 505. The PLL 504 generates a clock signal CLK1. The frequency divider 505 divides the clock signal CLK1 and outputs it as the clock signal CLK2. That is, the clock signals CLK1 and CLK2 are different clock signals.

  The flip-flop 501 outputs data in synchronization with the clock signal CLK1. The flip-flop 502 takes in and outputs the data output from the flip-flop 501 in synchronization with the clock signal CLK1. The flip-flop 503 captures and outputs the data output from the flip-flop 502 in synchronization with the clock signal CLK2.

  The flip-flops 501 and 502 operate in synchronization with the same clock signal CLK1. Here, a branch point N1 between the clock line of the clock signal input to the flip-flop 501 and the clock line of the clock signal input to the flip-flop 502 is located in the vicinity of the flip-flop 501 on the transmission side. That is, each clock line between the flip-flops 501 and 502 and the branch point N1 is relatively short. Therefore, variation in signal propagation delay due to the influence of OCV is relatively small. In other words, the variation in clock skew between the flip-flops 501 and 502 is relatively small.

  On the other hand, the flip flips 502 and 503 operate in synchronization with different clock signals CLK1 and CLK2, respectively. Here, a branch point N 2 between the clock line of the clock signal input to the flip-flop 502 and the clock line of the clock signal input to the flip-flop 503 is located in the vicinity of the PLL 504. That is, each clock line between the flip-flops 502 and 503 and the branch point N2 is relatively long. Therefore, the variation in signal propagation delay due to the effect of OCV is relatively large. In other words, the variation in clock skew between the flip-flops 502 and 503 is relatively large.

  Therefore, the logic synthesis apparatus 1 according to the present embodiment has flip-flops 502, 502 that operate in synchronization with the same clock signal for data paths between the flip-flops 501, 502 that operate in synchronization with different clock signals. Logic synthesis is performed by setting a larger (stricter) timing margin than the data path between 503.

  For example, a timing margin of 1 ns is set in the data path between the flip-flops 501 and 502 that operate in synchronization with the same clock signal. On the other hand, a timing margin of 2 ns is set in the data path between the flip-flops 502 and 503 operating in synchronization with different clock signals. For example, when the clock cycle is 10 ns and the setup time of each flip-flop is 1 ns, the data propagation time between the flip-flops 501 and 502 operating in synchronization with the same clock signal (after the transmission flip-flop outputs data) The time until the receiving flip-flop captures data) needs to be 8 ns or less. On the other hand, the data propagation time between flip-flops operating in synchronization with different clock signals needs to be 7 ns or less.

  As described above, the logic synthesis device 1 according to the present embodiment performs logic synthesis by setting a strict timing margin for a data path between flip-flops operating in synchronization with different clock signals. As a result, the logic synthesis device 1 according to the present embodiment can more easily perform a design that satisfies the timing constraints in the subsequent timing-driven layout design. As a result, the occurrence of timing errors such as setup time violations is suppressed in static timing analysis (STA) performed after timing-driven layout design.

  Furthermore, the logic synthesis device 1 according to the present embodiment can output a net list 17 whose timing, circuit scale, and power consumption are relatively close to the net list after the actual layout design. Note that the logic synthesis apparatus 1 according to the present embodiment maps a high-speed circuit in advance to a location where it is difficult to satisfy timing constraints, for example.

  The logic synthesis device 1 according to the present embodiment can be realized by, for example, a general-purpose computer system. Hereinafter, it will be briefly described with reference to FIG.

  FIG. 4 is a block diagram illustrating an example of a hardware configuration of the logic synthesis device 1 according to the present embodiment. The computer 100 includes, for example, a central processing unit (CPU) 101 that is a control device, a random access memory (RAM) 102, a read only memory (ROM) 103, and an IF (inter face) 104 that is an interface with the outside. HDD (Hard Disk Drive) 105, which is an example of a nonvolatile storage device. The computer 100 may include an input device such as a keyboard and a mouse and a display device such as a display as other components not shown.

  The HDD 105 stores an OS (Operating System) (not shown), structure description information 106, logic circuit information 107, and a logic synthesis program 108. The structure description information 106 is information relating to the structure of the circuit, and corresponds to the RTL description 14 in FIG. The logic circuit information 107 is design information for realizing the logic circuit, and corresponds to the net list 17 in FIG. The logic synthesis program 108 is a computer program in which the logic synthesis processing according to the present embodiment is implemented.

  The CPU 101 controls various processes in the computer 100, access to the RAM 102, ROM 103, IF 104, and HDD 105, and the like. In the computer 100, the CPU 101 reads and executes the OS and the logic synthesis program 108 stored in the HDD 105. Thereby, the computer 100 implement | achieves the logic synthesis apparatus 1 concerning this Embodiment.

<Embodiment 2>
FIG. 5 is a block diagram of a configuration example of the logic synthesis device (semiconductor design device) 2 according to the second embodiment. The logic synthesis device 2 according to the present embodiment corresponds to the number of data paths (number of wirings) connecting the modules (first and second modules) and the frequency of the clock signal corresponding to the data path. A timing margin is set for the data path, and logic synthesis is performed. As a result, the logic synthesis device 2 according to the present embodiment can more easily perform design that satisfies the timing constraint in the subsequent timing-driven layout design. This will be specifically described below.

  A logic synthesis device 2 shown in FIG. 5 is a device that logically synthesizes a description (structure description) relating to the structure of a circuit such as an RTL description and outputs it as a net list (logic circuit). Specifically, the logic synthesis device 2 includes a logic synthesis unit 21, an intermodule wiring number extraction unit 22, and a margin setting unit 23, and includes an RTL description 24, timing constraint information 25, and a library 26 of the semiconductor integrated circuit. And the net list 27 is output.

  The inter-module wiring number extraction unit 22 extracts the number of data paths connecting the modules from the RTL description 24. Note that a module is a circuit block that realizes a certain function, but here, in particular, refers to a circuit block of a minimum unit that performs logic synthesis by flattening a lower hierarchy.

  The timing constraint information 25 includes timing margin information corresponding to the number of data paths connecting between modules and the frequency of the clock signal corresponding to the data path, in addition to the timing constraint information used in conventional logic synthesis. It is included. Note that the clock signal corresponding to the data path is a clock signal supplied to a flip-flop that transmits and receives a signal through the data path.

  FIG. 6 is a diagram showing a table of timing margins set for data paths connecting modules. As shown in FIG. 6, the number 1 to q of data paths connecting the modules (q is an integer of 2 or more) and the frequency F1 to Fp of the clock signal corresponding to the data path (p is an integer of 2 or more). And timing margins MB11 to MBpq are defined. Note that the timing margins MB11 to MBpq may be coefficients for the basic margin. The timing constraint information 25 includes such timing margin information.

  Returning to FIG. 5, the margin setting unit 23 acquires a timing margin according to the number of data paths connecting between modules and the frequency of the clock signal corresponding to the data path from the timing constraint information 25, and the data Set for the path.

  Here, the margin setting unit 23 sets a larger (stricter) timing margin for the data path when the number of data paths connecting the modules is small than when the number is large. For example, the margin setting unit 23 sets a timing margin larger than the reference margin when the number of data paths connecting the modules is smaller than the reference number. The margin setting unit 23 sets a larger (stricter) timing margin for the data path when the frequency of the clock signal corresponding to the data path connecting the modules is lower than when the frequency is high. For example, the margin setting unit 23 sets a timing margin larger than the reference margin when the frequency of the clock signal corresponding to the data path connecting the modules is lower than the reference frequency. Specific setting contents will be described later.

  The logic synthesis unit 21 logically synthesizes the RTL description 24 according to the timing margin set by the margin setting unit 23 and other timing constraints, and outputs it as a net list 27. Note that the logic synthesis unit 21 performs logic synthesis by reading a library 26 that stores design information of basic logic circuits such as NAND circuits and INV circuits, as in the prior art.

  Next, the operation of the logic synthesis device 2 will be described with reference to FIG. FIG. 7 is a flowchart showing the operation of the logic synthesis device 2. First, the logic synthesis device 2 extracts the number of data paths connecting the modules from the RTL description 24 (S201). Next, the logic synthesis device 2 acquires a timing margin corresponding to the number of data paths connecting the modules and the frequency of the clock signal corresponding to the data path from the timing constraint information 25, and stores the data in the data path. It sets for (S202). Here, the logic synthesis device 2 sets a larger (severe) timing margin for the data path when the number of data paths connecting the modules is small than when the number is large. Further, when the frequency of the clock signal corresponding to the data path connecting the modules is low, the logic synthesis device 2 sets a larger (stricter) timing margin for the data path than when the frequency is high. Specific setting contents will be described later. Next, the logic synthesizer 2 logically synthesizes the RTL description 24 according to the set timing margin and other timing constraints (S203), and outputs it as a netlist 27 (S204).

  Next, the setting contents of the timing margin for the data paths connecting the modules will be described using a specific example.

  FIG. 8 is a circuit diagram showing a part of the netlist 27. The netlist 27 has modules 601 to 604.

  Here, the number of data paths connecting the modules 601 and 602 is relatively large. The frequency of the clock signal corresponding to these data paths is relatively high. Therefore, data path wiring is likely to be congested, and setup time violations are likely to occur. In order to avoid this, in the timing driven layout design, the modules 601 and 602 are likely to be automatically arranged relatively close to each other. Therefore, in the timing driven layout design, the design that satisfies the timing constraint is relatively easy.

  On the other hand, the number of data paths connecting the modules 603 and 604 is relatively small. The frequency of the clock signal corresponding to these data paths is relatively low. Therefore, the data path wiring is less likely to be congested and the setup time violation is less likely to occur. Therefore, in the timing driven layout design, the modules 603 and 604 are likely to be automatically arranged relatively far apart. As a result, in the timing driven layout design, it may be difficult to satisfy the timing constraint than expected.

  Therefore, the logic synthesis device 2 according to the present embodiment has a relatively small number of data paths connecting the modules, and data between the modules 603 and 604 having a relatively low frequency of the clock signal corresponding to the data paths. For the path, a larger (stricter) timing margin than that for the data path between the modules 601 and 602 is set, and logic synthesis is performed.

  As described above, the logic synthesis device 2 according to the present embodiment provides a timing margin corresponding to the number of data paths connecting the modules and the frequency of the clock signal corresponding to the data path to the data path. Set and perform logic synthesis. As a result, the logic synthesis device 2 according to the present embodiment can more easily perform a design that satisfies the timing constraints in the subsequent timing-driven layout design. As a result, the occurrence of timing errors such as setup time violations is suppressed in static timing analysis performed after timing-driven layout design.

  Furthermore, the logic synthesis device 2 according to the present embodiment can output a net list 27 whose timing, circuit scale, and power consumption are relatively close to the net list after the actual layout design. Note that the logic synthesis device 2 according to the present embodiment maps a high-speed circuit in advance to a location where it is difficult to satisfy timing constraints, for example.

  In this embodiment, the margin setting unit 23 sets a timing margin according to the number of data paths connecting between modules and the frequency of the clock signal corresponding to the data path as an example of the data path. However, the present invention is not limited to this. The margin setting unit 23 is appropriately configured to set a timing margin corresponding to only one of the number of data paths connecting between modules and the frequency of the clock signal corresponding to the data path to the data path. It can be changed.

  Further, the logic synthesis device 2 according to the present embodiment can be realized by, for example, a general-purpose computer system as in the case of the logic synthesis device 1 (see FIG. 4).

<Embodiment 3>
FIG. 9 is a block diagram of a configuration example of the logic synthesis device (semiconductor design device) 3 according to the third embodiment. The logic synthesis device 3 according to the present embodiment sets a timing margin corresponding to the area of the module (third module) and the frequency of the clock signal in the module for the data path in the module, and performs logic synthesis. . As a result, the logic synthesis device 3 according to the present embodiment can more easily perform a design that satisfies the timing constraint in the subsequent timing-driven layout design. This will be specifically described below.

  The logic synthesis device 3 shown in FIG. 9 is a device that logically synthesizes a description (structure description) relating to the structure of a circuit such as an RTL description and outputs it as a net list (logic circuit). Specifically, the logic synthesis device 3 includes a logic synthesis unit 31, a module area extraction unit 32, and a margin setting unit 33, and reads the RTL description 34, the timing constraint information 35, and the library 36 of the semiconductor integrated circuit. To output the net list 37.

  The module area extraction unit 32 extracts the area of the module from the RTL description 24 and the library 36 in which basic logic circuit design information (including area information) is stored. Note that a module is a circuit block that realizes a certain function, but here, in particular, refers to a circuit block of a minimum unit that performs logic synthesis by flattening a lower hierarchy.

  The timing constraint information 35 includes timing margin information according to the area of the module and the frequency of the clock signal in the module, in addition to the timing constraint information used in the conventional logic synthesis.

  FIG. 10 is a diagram showing a timing margin table set for the data path in the module. As shown in FIG. 10, timing margins MA11 to MA11 according to the area A1 to An (n is an integer of 2 or more) of the module and the frequencies F1 to Fm (m is an integer of 2 or more) of the clock signal in the module. MAmn is defined. Note that the timing margins MA11 to MAmn may be coefficients for the basic margin. The timing constraint information 35 includes such timing margin information.

  Returning to FIG. 9, the margin setting unit 33 acquires a timing margin corresponding to the area of the module and the frequency of the clock signal in the module from the timing constraint information 35 and sets it for the data path in the module. .

  Here, the margin setting unit 33 sets a larger timing margin for the data path in the module when the area of the module is large than when it is small. For example, the margin setting unit 33 sets a timing margin larger than the reference margin when the module area is larger than the reference area. The margin setting unit 33 sets a larger timing margin for the data path in the module when the frequency of the clock signal in the module is high than when the frequency is low. Specific setting contents will be described later.

  The logic synthesis unit 31 logically synthesizes the RTL description 34 according to the timing margin set by the margin setting unit 33 and other timing constraints, and outputs it as a netlist 37. The logic synthesis unit 31 reads the library 36 and performs logic synthesis in the same manner as in the past.

  Next, the operation of the logic synthesis device 3 will be described with reference to FIG. FIG. 11 is a flowchart showing the operation of the logic synthesis device 3. First, the logic synthesis device 3 extracts the area of the module from the RTL description 34 and the library 36 (S301). Next, the logic synthesis device 3 acquires a timing margin corresponding to the area of the module and the frequency of the clock signal in the module from the timing constraint information 35, and sets it for the data path in the module (S302). ). Here, the logic synthesis device 3 sets a larger timing margin for the data path in the module when the area of the module is large than when it is small. The logic synthesis device 3 sets a larger timing margin for the data path in the module when the frequency of the clock signal in the module is high than when the frequency is low. Specific setting contents will be described later. Next, the logic synthesizer 3 logically synthesizes the RTL description 34 according to the set timing margin and other timing constraints (S303), and outputs it as a netlist 37 (S304).

  Next, the setting contents of the timing margin for the data path in the module will be described using a specific example.

  FIG. 12 is a circuit diagram showing a part of the netlist 37. The netlist 37 has modules 701 and 702. The module 701 includes flip-flops 703 and 704. The module 702 includes flip-flops 705 and 706. In the example of FIG. 12, the branch point between the clock line of the clock signal input to the flip-flop 703 and the clock line of the clock signal input to the flip-flop 704 is assumed to be outside the module 701. Further, a branch point between the clock line of the clock signal input to the flip-flop 705 and the clock line of the clock signal input to the flip-flop 706 is assumed to be outside the module 702.

  Here, the area of the module 701 is relatively small. Thereby, the clock line becomes relatively short. Therefore, variation in signal propagation delay due to the influence of OCV is relatively small. In other words, the variation in clock skew between the flip-flops 703 and 704 is relatively small.

  On the other hand, the area of the module 702 is relatively large. Thereby, the clock line becomes relatively long. Therefore, variation in signal propagation delay due to the effect of OCV is relatively large. In other words, the variation in clock skew between the flip-flops 705 and 706 is relatively large.

  Therefore, the logic synthesis device 3 according to the present embodiment has a larger (stricter) timing than the data path in the module 701 having a relatively small area for the data path in the module 702 having a relatively large area. A margin is set and logic synthesis is performed.

  In addition, when the frequency of the clock signal is high, the variation in signal propagation delay due to the influence of OCV is relatively greater with respect to the clock period than when the frequency is low.

  Therefore, the logic synthesis device 3 according to the present embodiment has a larger (stricter) timing than a data path in a module with a low clock signal frequency compared to a data path in a module with a high clock signal frequency. Set margin and perform logic synthesis.

  As described above, the logic synthesis device 3 according to the present embodiment performs logic synthesis by setting a timing margin corresponding to the area of the module and the frequency of the clock signal in the module for the data path in the module. As a result, the logic synthesis device 3 according to the present embodiment can more easily perform a design that satisfies the timing constraint in the subsequent timing-driven layout design. As a result, occurrence of timing errors such as setup time is suppressed in static timing analysis performed after timing-driven layout design.

  Furthermore, the logic synthesis device 3 according to the present embodiment can output a net list 37 whose timing, circuit scale, and power consumption are relatively close to the net list after the actual layout design. Note that the logic synthesis device 3 according to the present embodiment maps a high-speed circuit in advance to a location where it is difficult to satisfy timing constraints, for example.

  In the present embodiment, the margin setting unit 33 has been described as an example in which the timing margin corresponding to the area of the module and the frequency of the clock signal in the module is set for the data path in the module. Not limited. The margin setting unit 33 can be appropriately changed to a configuration in which a timing margin corresponding to only one of the module area and the frequency of the clock signal in the module is set in the data path in the module.

  Further, the logic synthesis device 3 according to the present embodiment can be realized by, for example, a general-purpose computer system as in the case of the logic synthesis device 1 (see FIG. 4).

<Embodiment 4>
FIG. 13 is a block diagram of a configuration example of the logic synthesis device (semiconductor design device) 4 according to the fourth embodiment. The logic synthesis device 4 according to the present embodiment has all the functions of the logic synthesis devices 1 to 3.

  The logic synthesis device 4 shown in FIG. 13 includes a logic synthesis unit 41, an FF extraction unit 42a, an inter-module wiring number extraction unit 42b, a module area extraction unit 42c, and a margin setting unit 43, and includes a semiconductor integrated circuit. The RTL description 44, the timing constraint information 45, and the library 46 are read and a netlist 47 is output.

  The logic synthesis unit 41 corresponds to each logic synthesis unit 11, 21, 31. The FF extraction unit 42 a corresponds to the FF extraction unit 12. The inter-module wiring number extraction unit 42 b corresponds to the inter-module wiring number extraction unit 22. The module area extraction unit 42 c corresponds to the module area extraction unit 32. The margin setting unit 43 corresponds to each margin setting unit 13, 23, 33.

  The margin setting unit 43 acquires a timing margin corresponding to the information extracted by the FF extracting unit 42a, the inter-module wiring number extracting unit 42b, and the module area extracting unit 42c from the timing constraint information 45, and each of the plurality of data paths. Set to.

  For example, when a certain data path is a module path, the margin setting unit 43 acquires and sets a timing margin according to the module area and the frequency of the clock signal in the module from the table shown in FIG. . Further, when a certain data path is a data path connecting between modules, the margin setting unit 43 sets a timing margin according to the number of data paths connecting between modules and the frequency of the clock signal corresponding to the data path. Obtain and set from the table shown in FIG. Further, when the data path is a data path between flip-flops operating in synchronization with different clock signals, the margin setting unit 43 sets the obtained timing margin by multiplying it by a coefficient α (α> 1).

  Since the other operations of the logic synthesis device 4 are the same as those of the logic synthesis devices 1 to 3, the description thereof is omitted.

  Thus, the logic synthesis device 4 according to the present embodiment can realize any function of the logic synthesis devices 1 to 3.

  In the present embodiment, the case where the logic synthesis device 4 includes the FF extraction unit 42a, the inter-module wiring number extraction unit 42b, and the module area extraction unit 42c has been described as an example, but the present invention is not limited thereto. The logic synthesis device 4 can be appropriately changed to a configuration having two of the FF extraction unit 42a, the inter-module wiring number extraction unit 42b, and the module area extraction unit 42c.

  Further, the logic synthesis device 4 according to the present embodiment can be realized by, for example, a general-purpose computer system as in the case of the logic synthesis device 1 (see FIG. 4).

  As described above, the logic synthesis apparatuses 1 to 4 according to the above embodiments individually set timing margins for each of a plurality of data paths based on the various types of extraction information described above. As a result, the logic synthesis apparatuses 1 to 4 according to the above-described embodiment can easily perform a design that satisfies the timing constraint in the subsequent timing-driven layout design.

  In the first to fourth embodiments, the case where the logic synthesis apparatus performs logic synthesis on the RTL description and outputs the netlist has been described as an example. However, the present invention is not limited to this. The logic synthesis apparatus can be appropriately changed to a configuration in which a gate-level net list is read instead of the RTL description and the net list is logically synthesized (re-synthesized) again.

  In the first to fourth embodiments, the case where the margin setting unit acquires the timing margin from the timing constraint information has been described as an example. However, the present invention is not limited to this. The margin setting unit can be appropriately changed to a configuration in which the timing margin is generated by itself. Alternatively, the margin setting unit can be appropriately changed to a configuration that generates a part of the timing margin with reference to the timing constraint information.

  Moreover, the logic synthesis apparatuses according to the first to fourth embodiments can also realize arbitrary processing by causing a CPU (Central Processing Unit) to execute a computer program.

  In the above example, the program can be stored and supplied to a computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, DVD (Digital Versatile Disc), BD (Blue-ray (registered trademark) Disc), semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM ( Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

(Difference from conventional technology)
In Patent Document 2, different timing margins are set for a data path between flip-flops operating in synchronization with different clock signals and a data path between flip-flops operating in synchronization with the same clock signal. No point is disclosed or suggested. Further, Patent Document 2 neither discloses nor suggests that a timing margin corresponding to the number of data paths connecting modules is set in the data path.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

1-4 logic synthesis apparatus 11, 21, 31, 41 logic synthesis unit 12 FF extraction unit 13, 23, 33, 42 margin setting unit 14, 24, 34, 44 RTL description 15, 25, 35, 45 timing constraint information 16 , 26, 36, 46 Library 17, 27, 37, 47 Netlist 22 Module wiring number extraction unit 32 Module area extraction unit 42a FF extraction unit 42b Module wiring number extraction unit 42c Module area extraction unit 100 Computer 101 CPU
102 RAM
103 ROM
104 IF
105 HDD
106 Structure description information 107 Logic circuit information 108 Logic synthesis program 501 to 503 Flip flop 504 PLL
505 Frequency divider 601-604 Module 701, 702 Module 703-706 Flip-flop

Claims (16)

Set a larger timing margin for the data path between flip-flops operating in synchronization with different clock signals than for the data path between flip-flops operating in synchronization with the same clock signal,
A method of designing a semiconductor integrated circuit that performs logic synthesis. Extract the description corresponding to the flip-flop from the structure description of the semiconductor integrated circuit,
Set a larger timing margin for the data path between flip-flops operating in synchronization with different clock signals than for the data path between flip-flops operating in synchronization with the same clock signal,
The method for designing a semiconductor integrated circuit according to claim 1, wherein logic synthesis of the structure description is performed. Further extracting from the structure description of the semiconductor integrated circuit the descriptions of the first and second modules that are respectively flattened and subjected to logic synthesis;
A timing margin corresponding to the number of data paths connecting the first and second modules is further set for the data path;
The method of designing a semiconductor integrated circuit according to claim 2, wherein the logic synthesis is performed.   4. The semiconductor integrated circuit according to claim 3, wherein when the number of data paths connecting the first and second modules is smaller than a reference number, a timing margin larger than a reference timing margin is set for the data path. Design method. In addition to the number of data paths between the first and second modules, a timing margin corresponding to the frequency of the clock signal corresponding to the data path is further set for the data path,
The method of designing a semiconductor integrated circuit according to claim 3, wherein the logic synthesis is performed.   When the number of data paths connecting the first and second modules is smaller than the reference number, and when the frequency of the clock signal corresponding to the data path is lower than the reference frequency, the timing is larger than the reference timing margin. 6. The method of designing a semiconductor integrated circuit according to claim 5, wherein a margin is set for the data path. Further extracting a third module that is flattened and subjected to logic synthesis from the structure description of the semiconductor integrated circuit,
A timing margin corresponding to the area of the third module is further set for the data path provided in the third module;
The method of designing a semiconductor integrated circuit according to claim 3, wherein the logic synthesis is performed. A timing margin corresponding to the number of data paths connecting between the first module that is flattened and logically synthesized and the second module that is flattened and logically synthesized is set for the data path. ,
A method of designing a semiconductor integrated circuit that performs logic synthesis. Extracting descriptions of the first and second modules from a structure description of a semiconductor integrated circuit;
A timing margin corresponding to the number of data paths connecting the first and second modules is set for the data path;
The method for designing a semiconductor integrated circuit according to claim 8, wherein logic synthesis of the structure description is performed.   10. The semiconductor integrated circuit according to claim 9, wherein when the number of data paths connecting the first and second modules is smaller than a reference number, a timing margin larger than a reference timing margin is set for the data path. Design method. In addition to the number of data paths between the first and second modules, a timing margin corresponding to the frequency of the clock signal corresponding to the data path is set for the data path,
The method for designing a semiconductor integrated circuit according to claim 9, wherein the logic synthesis is performed.   When the number of data paths connecting the first and second modules is smaller than the reference number, and when the frequency of the clock signal corresponding to the data path is lower than the reference frequency, the timing is larger than the reference timing margin. 12. The method of designing a semiconductor integrated circuit according to claim 11, wherein a margin is set for the data path. First setting process for setting a larger timing margin for a data path between flip-flops operating in synchronization with different clock signals than for a data path between flip-flops operating in synchronization with the same clock signal When,
A semiconductor integrated circuit design program for causing a computer to execute synthesis processing for performing logic synthesis. A first extraction process for extracting a description corresponding to a flip-flop from a structure description of a semiconductor integrated circuit;
First setting process for setting a larger timing margin for a data path between flip-flops operating in synchronization with different clock signals than for a data path between flip-flops operating in synchronization with the same clock signal When,
14. The semiconductor integrated circuit design program according to claim 13, which causes a computer to execute synthesis processing for performing logic synthesis of the structure description. A second extraction process for further extracting descriptions of the first and second modules, which are respectively flattened and subjected to logic synthesis, from the structure description of the semiconductor integrated circuit;
A second setting process for further setting a timing margin according to the number of data paths connecting the first and second modules to the data path;
15. The design program for a semiconductor integrated circuit according to claim 14, wherein a computer executes the synthesis process for performing logic synthesis after the first setting process and the second setting process. A second extraction process for further extracting descriptions of the first and second modules, which are respectively flattened and subjected to logic synthesis, from the structure description of the semiconductor integrated circuit;
A second setting process for further setting a timing margin for the data path according to the number of data paths between the first and second modules and the frequency of the clock signal corresponding to the data path;
15. The design program for a semiconductor integrated circuit according to claim 14, wherein a computer executes the synthesis process for performing logic synthesis after the first setting process and the second setting process.

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