JP2014003200A - Vertical power mosfet and semiconductor device - Google Patents

Abstract

As for junction termination processing of a semiconductor device such as a power MOSFET having a super junction structure, it is common to arrange a super junction structure around an active cell region, thereby increasing the breakdown voltage of the junction termination. . However, as a result of studies by the inventors of the present application, it has been clarified that in such a junction termination structure using a semiconductor substrate portion, a so-called termination length may be relatively long.
An outline of the present invention is to dispose a concentric two-layer floating field plate in a junction termination region in a semiconductor device having a super junction structure in a cell region and junction termination region.
[Selection] Figure 3

Description

  The present application relates to a semiconductor device (or a semiconductor integrated circuit device), and more particularly to a technology effective when applied to a power MOSFET device technology.

  Japanese Unexamined Patent Publication No. 56-169369 (Patent Document 1) or UK Patent Publication No. 2077494 (Patent Document 2) corresponding thereto relates to a junction termination process (junction edge termination) of a power MOSFET. There is a technology that covers a field insulating film thicker than the gate insulating film on the drift region at the end of the main junction in combination with a source potential field plate, a drain potential reverse field plate, and a floating field plate. It is disclosed.

  Japanese Laid-Open Patent Publication No. 2005-209983 (Patent Document 3) and US Patent Publication No. 2005-161761 (Patent Document 4) relate to the junction termination processing of a power MOSFET as described above. There, a field insulating film thicker than the gate insulating film on the drift region at the end of the main junction is covered with a combination of a source potential field plate, a drain potential reverse field plate, and a two-layer floating field plate. Techniques to do this are disclosed.

  Japanese Unexamined Patent Publication No. 2009-21526 (Patent Document 5) relates to a junction termination process of a power MOSFET as described above. There, a junction termination structure in which a metal field plate is connected to a floating field ring is disclosed.

  Japanese Unexamined Patent Publication No. 2011-243859 (Patent Document 6) relates to a junction termination process of a power MOSFET having a super-junction structure. There is disclosed a junction termination structure including a superjunction having a P-type column running substantially parallel to each side of the cell around the cell region.

JP 56-169369 A British Patent Publication No. 2077494 JP 2005-209983 A US Patent Publication No. 2005-161761 JP 2009-21526 A JP 2011-243859 A

  As for junction termination processing of a semiconductor device such as a power MOSFET having a super junction structure, a super junction structure is generally arranged around the active cell region, thereby increasing the breakdown voltage of the junction termination.

  However, as a result of studies by the inventors of the present application, it has been clarified that in such a junction termination structure using a semiconductor substrate portion, a so-called termination length may be relatively long.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the outline of one embodiment of the present application is that a concentric two-layer floating field plate is arranged in a junction termination region in a semiconductor device having a super junction structure in the cell region and the junction termination region.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present application, the junction termination length of the power device can be shortened.

It is a chip upper surface whole figure for demonstrating the device structure etc. of the vertical power MOSFET which is a semiconductor device of one embodiment of this application. FIG. 2 is a plan view of the entire chip for explaining an impurity doping structure and the like in the chip of FIG. 1. FIG. 2 is a plan view of the entire chip schematically showing a junction termination structure of the chip of FIG. 1. FIG. 3 is an enlarged plan view of a chip corner section cutout region R1 of FIG. 2. FIG. 3 is a cross-sectional view of an active cell portion corresponding to a B-B ′ cross section of a cell portion cutout region R <b> 3 in FIG. 1. 1 is a cross-sectional view of a chip from the inside of the cell portion to the end of the chip corresponding to the AA ′ cross section (almost corresponding to the CC ′ cross section of FIG. 4) of the inside of the cell portion of FIG. is there. FIG. 7 is an enlarged chip cross-sectional view of the chip peripheral area R2 in FIG. 6. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (trench formation process) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (trench processing hard mask removing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application; FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (embedded epitaxial growth process) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (planarization process) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (field insulating film etching step) corresponding to the cross section in FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the embodiment of the present application; FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (P body region introducing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 14 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. 13. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (P body region introducing resist film removing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application; FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (first layer polysilicon film forming step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (first layer polysilicon film processing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 18 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (N + source region introduction step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 20 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as in FIG. 19. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (lower interlayer insulating film forming step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (second layer polysilicon film forming step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (second layer polysilicon film processing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (upper interlayer insulating film forming step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (upper interlayer insulating film etching process) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (substrate contact etc. forming step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 27 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (surface metal electrode etc. forming step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 29 is an active cell section sectional view corresponding to FIG. 5 at the same time as FIG. FIG. 7 is a chip cross-sectional view corresponding to FIG. 6 for describing a modification (P-type surface RESURF region) regarding the impurity structure of the substrate surface in the junction termination region in the semiconductor device of the embodiment of the present application. FIG. 31 is an enlarged chip cross-sectional view during the manufacturing process (P-type surface RESURF region introducing step) corresponding to the cross section of FIG. 7 to be inserted between FIG. 11 and FIG. 12 to form the structure of FIG. 30; . Expansion of the chip corner section cutout region R1 of FIG. 2 corresponding to FIG. 4 for explaining Modification Example 1 (round layout) regarding the layout of the feel plate and the like of the chip corner section in the semiconductor device of the one embodiment of the present application. It is a top view. FIG. 2 is an enlarged plan view of the chip corner cutout region R1 in FIG. 2 (only the P column region) showing a modified example (charge balance type separation layout) regarding the superjunction detailed layout of the chip corner portion in the semiconductor device of the embodiment of the present application. Is shown). FIG. 2 is an enlarged plan view (only the P column region is shown) showing a modified example (right angle bend layout) of the super junction detailed layout of the chip corner portion in the semiconductor device of the embodiment of the present application. ). The chip corner section cutout region of FIG. 2 corresponding to FIG. 4 for explaining the second modification (P column ground field plate) regarding the layout of the feel plate and the like of the chip corner section in the semiconductor device of the one embodiment of the present application. It is an enlarged plan view of R1. FIG. 36 is an enlarged chip cross-sectional view corresponding to FIG. 7 in the planar structure of FIG. 35 (substantially corresponding to the C-C ′ cross section of FIG. 35). FIG. 3 is a plan view of the entire chip corresponding to FIG. 2 for explaining a modification (3D structure) related to a super junction structure of a junction termination region in the semiconductor device of the embodiment of the present application. FIG. 38 is an enlarged plan view of a chip corner section cutout region R1 of FIG. 37. 38 is an enlarged chip cross-sectional view corresponding to FIG. 7 in the planar structure of FIG. 38 (corresponding substantially to the C-C ′ cross section of FIG. 38). FIG. 6 is a chip cross-sectional view of a unit cell region corresponding to FIG. 5 for explaining a modification (diode-embedded cell) related to an active cell in the semiconductor device of the embodiment of the present application. FIG. 4 is a plan view of the entire chip structure corresponding to FIG. 3 for explaining the outline of the semiconductor device according to the embodiment (including a modification) of the present application. It is a simulation data figure for demonstrating the merit of the capacitive coupling type | mold junction termination | terminus structure in the semiconductor device of the said one Embodiment of this application.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. Vertical power MOSFET including:
(A) a silicon-based semiconductor substrate having a first main surface and a second main surface;
(B) a cell region provided on the first main surface side;
(C) a drift region of a first conductivity type provided in a substantially entire surface on the first main surface side of the silicon-based semiconductor substrate;
(D) a metal source electrode provided on the first main surface and in the cell region;
(E) a metal drain electrode provided on the second main surface;
(F) a second-conductivity-type main junction region provided on a surface of the drift region on the first main surface side so as to constitute an annular outer edge portion of the cell region;
(G) An annular junction termination region provided on the first main surface side around the cell region so as to surround the cell region;
(H) a super junction structure provided in the drift region in the cell region and the junction termination region;
(I) a plurality of concentric annular lower floating field plates provided on the first principal surface and provided in the junction termination region;
(J) On the first main surface, an annular upper layer provided above the plurality of lower layer floating field plates so as to cover between adjacent lower layer floating field plate pairs. Floating field plate.

  2. In the vertical power MOSFET of item 1, the vertical power MOSFET has a planar structure.

  3. In the vertical power MOSFET of item 1 or 2, each lower floating field plate is formed of a first layer polysilicon film.

  4). In the vertical power MOSFET of item 3, the upper floating field plate is formed of a second layer polysilicon film that is higher than the first layer polysilicon film.

5. The vertical power MOSFET of item 4 further includes:
(K) The second polysilicon film provided on the first main surface and extending from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates. Source potential poly-Si field plate composed of

6). The vertical power MOSFET according to any one of Items 1 to 5 further includes:
(L) Provided on the first main surface from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates, and the same layer as the metal source electrode Source potential metal field plate composed of a metal film.

7). The vertical power MOSFET according to any one of Items 4 to 6 further includes:
(M) provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower-layer floating field plates; A drain potential poly-Si guard ring composed of a silicon film.

8). The vertical power MOSFET according to any one of Items 1 to 7 further includes:
(N) Provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower floating field plates, and the metal source electrode A drain potential metal guard ring composed of the same layer of metal film.

  9. In the vertical power MOSFET according to any one of Items 1 to 8, the super junction structure in the junction termination region is a two-dimensional structure.

  10. In the vertical power MOSFET according to any one of Items 1 to 8, the super junction structure in the junction termination region is a three-dimensional structure.

11. The vertical power MOSFET according to any one of Items 1 to 10, further including:
(P) A surface resurf region of the second conductivity type provided on the surface of the drift region so as to be connected to and surround the outer end of the main junction region.

12 The vertical power MOSFET according to any one of Items 1 to 11 further includes:
(Q) The second conductivity type provided on the first main surface and between the adjacent pair of the plurality of lower floating field plates, and constituting the super junction structure in the junction termination region. An annular metal intermediate field plate, electrically connected to the column region having
Here, the metal intermediate field plate is composed of a metal film in the same layer as the metal source electrode.

13. Semiconductor devices including:
(A) a silicon-based semiconductor substrate having a first main surface and a second main surface;
(B) a cell region provided on the first main surface side;
(C) a drift region of a first conductivity type provided in a substantially entire surface on the first main surface side of the silicon-based semiconductor substrate;
(D) a metal first electrode provided on the first main surface and in the cell region;
(E) a metal second electrode provided on the second main surface;
(F) a second-conductivity-type main junction region provided on a surface of the drift region on the first main surface side so as to constitute an annular outer edge portion of the cell region;
(G) An annular junction termination region provided on the first main surface side around the cell region so as to surround the cell region;
(H) a super junction structure provided in the drift region in the cell region and the junction termination region;
(I) a plurality of concentric annular lower floating field plates provided on the first principal surface and provided in the junction termination region;
(J) On the first main surface, an annular upper layer provided above the plurality of lower layer floating field plates so as to cover between adjacent lower layer floating field plate pairs. Floating field plate.

  14 In the semiconductor device according to Item 13, each lower floating field plate is formed of a first layer polysilicon film.

  15. 14. The semiconductor device according to item 14, wherein the upper floating field plate is composed of a second layer polysilicon film that is higher than the first layer polysilicon film.

16. The semiconductor device of item 14 further includes the following:
(K) The second polysilicon film provided on the first main surface and extending from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates. A first electrode potential poly-Si field plate comprising:

17. The semiconductor device according to any one of Items 13 to 16, further including:
(L) Provided on the first main surface from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates, and the same as the metal first electrode 1st electrode electric potential metal field plate comprised from the metal film of a layer.

18. The semiconductor device according to any one of Items 15 to 17, further including:
(M) provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower-layer floating field plates; A second electrode potential poly-Si guard ring made of a silicon film.

19. The semiconductor device according to any one of Items 13 to 18, further comprising:
(N) The metal first electrode provided on the first main surface and from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower floating field plates. And a second electrode potential metal guard ring composed of the same metal layer.

  20. 20. In the semiconductor device according to any one of Items 13 to 19, the super junction structure in the junction termination region is a two-dimensional structure.

  21. 20. In the semiconductor device according to any one of Items 13 to 19, the super junction structure in the junction termination region is a three-dimensional structure.

22. The semiconductor device according to any one of Items 13 to 21, further including:
(P) A surface resurf region of the second conductivity type provided on the surface of the drift region so as to be connected to and surround the outer end of the main junction region.

23. The semiconductor device according to any one of Items 13 to 22, further comprising:
(Q) The second conductivity type provided on the first main surface and between the adjacent pair of the plurality of lower floating field plates, and constituting the super junction structure in the junction termination region. An annular metal intermediate field plate, electrically connected to the column region having
Here, the metal intermediate field plate is composed of a metal film in the same layer as the metal first electrode.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts and sections for convenience, if necessary. However, unless otherwise specified, they are not independent from each other. Rather, each part of a single example, one of which is a partial detail of the other or a part or all of a modification. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Say. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

  In the present application, “semiconductor active element” refers to a transistor, a diode, or the like.

  In general, a semiconductor element for high power that can handle electric power of several watts or more is called a power semiconductor element or a power semiconductor device. The power MOSFET mainly handled in the present application belongs to a power semiconductor device, and is roughly classified into a vertical power MOSFET and a lateral power MOSFET. In general, a device having a source electrode and a drain electrode on the surface of the chip is a lateral power MOSFET, and a device having a source electrode on the surface of the chip and a drain electrode on the back surface is a vertical power MOSFET.

  This vertical power MOSFET is further classified into a planar power MOSFET, a trench power MOSFET, and the like. In the following embodiments, a specific description will be given mainly using a planar type power MOSFET as an example, but it goes without saying that the junction termination structure described in the present application can be similarly applied to a trench type power MOSFET.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member”, “silicon-based member” and the like are not limited to pure silicon, but include SiGe alloys, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Although SiC has properties similar to SiN, SiON should be classified as a silicon oxide insulating film in many cases, but in the case of an etch stop film, it is close to SiC, SiN, or the like.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to substantially parallel.

  In addition, for a certain region, “whole”, “whole”, “whole area” and the like include cases of “substantially whole”, “substantially general”, “substantially whole area” and the like. Therefore, for example, 90% or more of a certain region can be referred to as “substantially the whole”, “substantially general”, and “substantially the entire region”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is about 10% of the whole, it can be said to be almost rectangular. The same applies to “annular” and the like.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is within about 20%, each element is said to be “almost periodic”. it can. Furthermore, if it is within, for example, about 20% of all elements subject to the periodicity, it can be said that it is “substantially periodic” as a whole.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the “main junction region” is a P-type main junction region in the case of an N-channel type power MOSFET, and is a ring at the outer edge of a cell region directly or electrically connected to the P body region. This is a P-type impurity region. In the following main embodiments (examples of power MOSFETs) of the present application, the main junction region is a part of the cell region and the outer edge thereof. Therefore, the cell region is composed of an active cell region in the inner region, a dummy cell region around it, and a main junction region around it.

  In general, a super junction structure is formed by inserting columnar or plate-like column regions of opposite conductivity type into a semiconductor region of a certain conductivity type at approximately equal intervals so that charge balance is maintained. In this application, when referring to the “super junction structure” by the trench fill method, in principle, a plate region of an opposite conductivity type is formed in a semiconductor region of a certain conductivity type (usually a plate shape, although it is bent or refracted). The “column area” of (good) is inserted at approximately equal intervals so that the charge balance is maintained. In the embodiment, a case where P-type columns are formed in parallel at equal intervals on an N-type semiconductor layer (for example, a drift region) will be described. Further, the thickness Wp (for example, FIG. 11) of the P-type column in each portion may be different depending on the location, but when manufactured by the trench fill method, the same thickness Wp (width) is mutually used. ) Is desirable. This is because if the trench width is different, the embedding characteristics are different in each part.

  In the present application, a drift region that does not have a super junction structure may be referred to as a single conductivity type drift region.

  With respect to the super junction structure, “orientation” means that the P-type column or N-type column constituting the super junction structure is viewed two-dimensionally corresponding to the main surface of the chip (parallel to the main surface of the chip or wafer). The longitudinal direction).

  In addition, the “peripheral super junction structure” refers to a super junction structure provided in a region outside the periphery of the active cell region, that is, a junction termination region (Junction Edge Termination Area). On the other hand, the super junction structure provided in the cell region is referred to as a “cell region super junction structure”.

  Furthermore, in the present application, in the main region of the peripheral super junction region (junction termination region) (excluding a part such as a corner), the degree of freedom in which the depletion layer extends is “3D (three-dimensional) -Resurf”. (Resurf) structure "or simply" 3D structure ". Also, those having the same degree of freedom are called “2D (three-dimensional) -Resurf (resurf) structure” or simply “2D structure”. In the present application, since a pure two-dimensional structure or a three-dimensional structure is not realistic in the chip corner portion, depending on the structure in the main portion (portion excluding the chip corner portion) of the junction termination region, Determine the dimensional structure of the peripheral super junction structure.

  In the present application, the surface resurf region (specifically, “P-type resurf region”) or “junction termination extension” refers to the following regarding the RESURF (Reduced Surface Field) structure. That is, a region of the same conductivity type formed in the surface region of the drift region and connected to the end of the P-type body region (P-type well region) constituting the channel region and having a lower impurity concentration (reverse direction to the main junction) The concentration is such that it is completely depleted when a voltage is applied). Usually, it is formed in a ring shape so as to surround the cell portion.

  In the present application, the “floating field plate” is opposed to “a field plate connected to a fixed potential” (that is, a fixed potential field plate) and “a field plate connected to an impurity region in a semiconductor substrate”. A field plate that is a concept and is not electrically connected to any other region corresponds to this. Therefore, a field plate that is electrically connected to a P column region that is not particularly connected to a fixed potential is not a floating field plate.

  The source potential field plate is a conductor film pattern connected to the source potential or an equivalent potential, and extends above the surface (device surface) of the drift region via the insulating film. The part that surrounds the cell part.

  On the other hand, the guard ring in the chip peripheral region refers to a substantially ring-shaped field plate that is electrically connected to a semiconductor substrate (for example, drain potential) therebelow. In the present application, the term “ring-shaped (annular)” usually means a closed loop (the shape of this loop is almost rectangular, almost circular, or almost as long as certain conditions described later are satisfied). (It may be an elliptical ring), but it does not have to be strictly closed, but only needs to be closed externally. That is, it may be a ring arrangement of conductors separated from each other. Needless to say, the closed loop is preferable from the viewpoint of the withstand voltage characteristic. In addition, with regard to an annular object such as a field plate, “concentric” or “concentric annular” means a line ring (ring composed of lines) formed by a center line along the ring for each of the two annular objects to be compared. When thinking, it means that either of the following holds. That is, both line rings coincide, or one is included in the other.

  In the present application, the term “rectangular” or “rectangular shape” refers to a substantially square or rectangular shape, but may have irregularities having a relatively small area compared to the entire area. Round, chamfering processing, and the like may be performed. Note that “the same orientation” for a rectangle means that at least one of rotational symmetry axes as a corresponding plane figure is substantially the same. In other words, the corresponding sides are almost parallel.

  Furthermore, a floating field ring or a field limiting ring refers to the following cases. In other words, the surface of the drift region (device surface) is provided separately from the P-type body region (P-type well region), and has the same conductivity type and similar concentration (reverse voltage is applied to the main junction). An impurity region or a group of impurity regions having a concentration that does not sometimes completely deplete) and surrounding a cell portion in a single or multiple ring shape.

  Further, in this application, “maintaining local charge balance” means that, for example, when the chip main surface is viewed in plan, charge balance is achieved in a range of distance of about the column thickness (Wp, Wn). Say.

  In the present application, the terms “breakdown voltage” and “breakdown voltage characteristic” are the source-drain breakdown voltage for the power MOSFET and the anode-cathode breakdown voltage for the diode unless otherwise specified.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

  In addition, in the power MOSFET having a super junction, examples of the prior patent application disclosing the floating field plate include the following. Specifically, Japanese Patent Application No. 2010-292118 (Japan application date December 28, 2010), Japanese Patent Application No. 2010-292117 (Japan application date December 28, 2010), Japanese Patent Application No. 2010-292119. (Japan filing date December 28, 2010).

1. Description of device structure and the like of vertical power MOSFET which is a semiconductor device according to an embodiment of the present application (mainly FIGS. 1 to 7)
In the following, a specific description will be given mainly using a device structure (referred to as a “substrate contact groove”) that makes contact with a substrate (such as a P body region) by digging a groove in a semiconductor substrate. Needless to say, the present invention can also be applied to a device that does not use (for example, see FIG. 40).

  Further, in the following, as an example, an example in which MOSFET unit cells are repeatedly arranged in the active cell region (simple active cell) will be specifically described as an example. However, MOSFET cells and diode cells are mixed and arranged. Needless to say, a mixed cell (mixed active cell) may be used. In this application, a cell region or an active cell region includes both simple active cells such as power MOSFETs (including power diodes, IGBTs, etc.) and mixed active cells.

  In this example, a planar power MOSFET manufactured on a silicon-based semiconductor substrate and having a source-drain breakdown voltage of about 600 volts will be described in detail. (The planar power MOSFET is the same in the following sections. However, it is needless to say that it can also be applied to power MOSFETs and other devices having other breakdown voltage values.

  In the following figures, the number of P column regions differs depending on the figure, but this is due to drawing convenience. In other words, in reality, there are about 100 chips in 1 millimeter, which is so fine as to be invisible in the overall chip diagram or a drawing of a level that is one-tenth of the chip size.

  FIG. 1 is an overall view of a chip upper surface for explaining a device structure and the like of a vertical power MOSFET which is a semiconductor device according to an embodiment of the present application. FIG. 2 is an overall plan view of the chip for explaining the impurity doping structure and the like in the chip of FIG. FIG. 3 is a plan view of the entire chip schematically showing the junction termination structure of the chip of FIG. FIG. 4 is an enlarged plan view of the chip corner section cutting region R1 of FIG. FIG. 5 is a cross-sectional view of the active cell portion corresponding to the B-B ′ cross section of the cell portion cutout region R <b> 3 of FIG. 1. FIG. 6 shows a chip extending from the inside of the cell portion to the end portion of the chip corresponding to the inside of the cell portion of FIG. 1 and the AA ′ cross section (substantially corresponding to the CC ′ cross section of FIG. 4). It is sectional drawing. FIG. 7 is an enlarged chip cross-sectional view of the chip peripheral area R2 of FIG. Based on these drawings, a device structure of a vertical power MOSFET which is a semiconductor device according to an embodiment of the present application will be described.

  First, an example of a specific layout of the upper surface of a chip (usually several millimeters square) will be described. As shown in FIG. 1, a power MOSFET element chip 2 in which elements are formed on a square or rectangular (rectangular) plate-like silicon-based semiconductor substrate mainly includes a metal source electrode 5 (for example, an aluminum-based electrode) at the center. Occupies a large area. A cell region 4 is provided below the metal source electrode 5, and an outer end portion thereof is a P-type main junction region 6 (outer edge portion of the P body region). Inside the ring-shaped (annular) P-type main junction region 6 is an active cell region 4 a of the cell region 4.

  Further, an aluminum-based metal guard ring 3 is provided around the ring-shaped (annular) P-type main junction region 6, and a polysilicon gate electrode is provided between the aluminum-based metal guard ring 3 and the metal source electrode 5. A metal gate electrode 7 and a metal gate wiring 7w are provided for taking out the outside. In this example, the outermost portion of the metal source electrode 5 is a metal field plate 62 having a source potential that covers the outer end of the P-type main junction region 6 over the entire circumference.

  Next, the planar diffusion structure and device layout of the chip 2 will be described. As shown in FIG. 2, a cell region 4 (with a cell region superjunction structure 14 underneath) is provided in the central portion of the chip 2, and a large number of linear polysilicons are provided therein. A gate electrode 15 is provided. Furthermore, as described above, the outer edge portion of the cell region 4 is the ring-shaped P-type main junction region 6.

  Next, the superjunction structure around the cell region superjunction structure 14 (junction termination region 80), that is, the peripheral superjunction structure 9 will be described (in this example, both structures are the drift region 11, ie, the N type). It is composed of a P column region 12p provided in the drift region 11n).

  The peripheral side regions 16b and 16d are each provided with a peripheral super junction structure 9 having the same orientation as an extension of the periodicity of the cell region super junction structure 14. On the other hand, the peripheral side regions 16a and 16c are each provided with a peripheral super junction structure 9 that is not connected to the cell region super junction structure 14 and has an orientation orthogonal thereto. In this column layout, each peripheral corner region 17a, 17b, 17c, 17d is connected to the peripheral super junction structure 9 of the left or right peripheral side regions 16a, 16c and has the same orientation. 9 is provided.

  Next, in order to clarify the relationship between various junction termination structures and the cell region 4 in the whole chip, a schematic top view of the whole chip is shown in FIG. In this figure, the details of the junction termination structure are clarified by expressing the cell region 4 smaller than the actual size. Further, for the sake of easy understanding, the number of field plates and the like is displayed smaller than other figures (for example, FIG. 4). As shown in FIG. 3, there is a cell region 4 in the center of the chip 2, and its outer edge is an annular P-type main junction region 6, near the chip end near the periphery of the chip 2. Are provided with a guard ring 3 (63) such as an annular metal guard ring 3 and a poly-Si guard ring 63 (both drain potentials).

  Between the junction termination region 80 between the cell region 4 and the guard ring 3 (63), a plurality of lower floating field plates 30 (30a, 30e) that are separated from each other and have concentric rings are provided. In this example, these lower floating field plates 30 (30a, 30e) are composed of, for example, a first layer polysilicon film. The lower floating field plate 30 (30a, 30e) can be formed of other layers, but using the first layer polysilicon film has an advantage that it can be shared with the gate electrode. In addition, there is an advantage that the thickness of the base insulating film can be controlled relatively easily.

  Between the adjacent lower floating field plates 30 (30a, 30e), an annular upper floating field plate 60 is provided concentrically with them. In this example, the upper floating field plate 60 is composed of, for example, a second layer polysilicon film that is higher than the first layer polysilicon film, and both lower floating field plates 30 (30a, 30e) adjacent to each other. In addition, the entire circumference (inner circumference and outer circumference) overlaps in a plane. The upper floating field plate 60 can be formed of other layers. However, if the upper floating field plate 60 is formed of the second layer polysilicon film, the lower insulating floating film 30 (30a, 30e) has a relatively lower base insulating film thickness. There is an advantage that it can be made thicker than the underlying insulating film thickness. That is, the lower layer floating field plate 30 (30a, 30e) and the upper layer floating field plate 60 can obtain the same electric field relaxation effect as that of the multistage field plate.

  Among these lower layer floating field plates 30 (30a, 30e), between the innermost lower layer floating field plate 30a and the cell region 4 (or P-type main junction region 6), in this example, for example, a source A fixed potential field plate 62 (64) such as a potential metal field plate 62 and a source potential poly-Si field plate 64 is provided. In this example, these fixed potential field plates 62 (64) overlap the entire circumference of the cell region 4, and overlap at least the inner circumference of the inner end lower layer floating field plate 30a and the entire circumference thereof. doing. Here, in this example, the poly-Si field plate 64 at the source potential is composed of, for example, a second-layer polysilicon film in the same layer as the upper floating field plate 60, and the metal field plate 62 is, for example, a metal source It is composed of a metal film in the same layer as the electrode 5. Of course, these fixed potential field plates 62 (64) are not essential, but by arranging them, the electric field concentration in the vicinity of the P-type main junction region 6 can be more effectively reduced. The poly Si field plate 64 may be a metal layer, but by using a polysilicon layer, the second layer polysilicon film in the same layer as the upper floating field plate 60 can be used. Similarly, the metal field plate 62 can be a polysilicon layer or another metal layer, but by using a metal layer, a metal film in the same layer as the metal source electrode 5 can be used.

  On the other hand, in the lower floating field plate 30 (30a, 30e), between the outermost lower end floating field plate 30e and the end of the chip 2, in this example, for example, a metal guard ring 3 having a drain potential, A guard ring 3 (63) such as a poly-Si guard ring 63 having a drain potential is provided. In this example, these fixed potential guard rings 3 (63) overlap at least the outer periphery of the outer end lower layer floating field plate 30e and the entire periphery thereof. Here, in this example, the drain potential poly-Si guard ring 63 is formed of, for example, a second-layer polysilicon film in the same layer as the upper floating field plate 60. The drain potential metal guard ring 3 is, for example, The metal source electrode 5 is composed of the same metal film. Of course, these guard rings 3 (63) are not essential, but by arranging them, the electric field concentration in the vicinity of the chip periphery can be more effectively reduced. Although a poly Si guard ring 63 metal layer can be used, a second layer polysilicon film in the same layer as the upper floating field plate 60 can be used by using a polysilicon layer. Similarly, the metal guard ring 3 can be a polysilicon layer or another metal layer, but by using a metal layer, a metal film in the same layer as the metal source electrode 5 can be used.

  Next, FIG. 4 shows an enlarged plan view of the chip corner portion cutting region R1 of FIGS. As shown in FIG. 4, as described above, the super junction structures 9 and 14 include the P column region 12p (P type drift region 11p) arranged almost periodically and the N type drift region 11n (N column) between them. Region 12n). The peripheral super junction structure 9 in the junction termination region 80 is a two-dimensional structure, and the structure of the field plate and the like in this example has a relatively right-angled layout. A cell region super junction structure 14 is provided in the cell region 4, and a source potential metal field plate 62 and a source potential poly Si field plate 64 are provided from the outer edge of the cell region 4 to the outside. ing. A lower-layer floating field plate 30a is provided outside the source potential metal field plate 62 and the source potential poly-Si field plate 64 so as to partially overlap each other. An upper layer floating field plate 60a is provided outside the lower layer floating field plate 30a so as to partially overlap with the lower layer floating field plate 30a. A lower floating field plate 30b is provided outside the upper floating field plate 60a so as to partially overlap with the upper floating field plate 60a. An upper layer floating field plate 60b is provided outside the lower layer floating field plate 30b so as to partially overlap with the lower layer floating field plate 30b. A lower floating field plate 30c is provided outside the upper floating field plate 60b so as to partially overlap with the upper floating field plate 60b. An upper layer floating field plate 60c is provided outside the lower layer floating field plate 30c so as to partially overlap with the lower layer floating field plate 30c. A lower floating field plate 30d is provided outside the upper floating field plate 60c so as to partially overlap with the upper floating field plate 60c. An upper layer floating field plate 60d is provided outside the lower layer floating field plate 30d so as to partially overlap with the lower layer floating field plate 30d. A lower floating field plate 30e is provided outside the upper floating field plate 60d so as to partially overlap with the upper floating field plate 60d. A drain potential metal guard ring 3 and a drain potential poly-Si guard ring 63 are provided outside the lower floating field plate 30e so as to partially overlap the lower floating field plate 30e. In this example, the metal guard ring 3 includes a poly Si guard ring 63 in a plane.

  Next, FIG. 5 shows a B-B ′ cross section of the cell part cutout region R <b> 3 in FIG. 1. As shown in FIG. 5, a metal back surface drain electrode 24 is provided on the surface of the N + drain region 25 (N-type single crystal silicon substrate) of the back surface 1b of the chip 2, and the upper side of the N + drain region 25 is drifted. This is an area 11. The drift region 11 includes an N column 12n (N type drift region 11n) and a P column 12p (P type drift region 11p). In terms of the manufacturing method, the N column 12n is constituted by, for example, an N type epitaxial region 10n, and the P column 12p is constituted by a P type epitaxial region 10p. A P body region 6 is provided in the surface region of the drift region 11, and an N + source region 26, a P + body contact region 23, and the like are provided in the P body region 6. A polysilicon gate electrode 15 (first layer polysilicon layer) is provided on the semiconductor surface between the pair of N + source regions 26 via a gate insulating film 27, and on the polysilicon gate electrode 15, An interlayer insulating film 29 is provided. An aluminum-based electrode film such as the metal source electrode 5 is formed on the interlayer insulating film 29 and is electrically connected to the N + drain region 25 and the P + body contact region 23 through the substrate contact groove 39. Yes.

  Next, FIG. 6 shows an A-A ′ cross section of the inside of the cell portion and the chip peripheral portion cutting region R <b> 4 in FIG. 1. This section substantially corresponds to the section C-C 'in FIG. As shown in FIG. 6, the surface 1a side of the drift region 11 in the cell region 4 including the active cell region 4a (region where the actual MOSFET is formed), the dummy cell region 4d (region where the dummy MOSFET is formed), and the like. The P body region is formed almost entirely except under the polysilicon gate electrode 15, and the outer edge thereof is a P-type main junction region 6.

  A metal source electrode 5 is provided on the surface 1a of the semiconductor substrate 2 on the active cell region 4a and its periphery, and on the right side thereof, a polysilicon gate wiring 15w (first polysilicon layer) and A metal gate wiring 7w connected through a metal gate wiring-polysilicon gate wiring connecting portion 74 is provided. On the upper interlayer insulating film 69 on the right side of the metal gate wiring 7w, the source field metal field plate 62 connected to the P-type main junction region 6 through the substrate contact trench 39 and the P + body contact region 23 in this portion. Is provided and extends to a part of the junction termination region 80.

  A metal guard ring 3 is formed on the surface 1a of the semiconductor substrate 2 and on the upper interlayer insulating film 69 in the vicinity of the end of the semiconductor chip 2, and an N + channel stop region 31 and a P + chip peripheral contact region 32 are formed. And are electrically connected. Although the following is not essential, in this example, the N + channel stop region 31 is formed at the same time as the N + source region 26, and the P + chip peripheral contact region 32 is the same as the P + body contact region 23. It is made at the same time.

  On the surface 1 a of the semiconductor substrate 2 and on the field insulating film 34 in the junction termination region 80, for example, a lower floating field plate 30 composed of a plurality of first-layer polysilicon layers at regular intervals. Is provided. Between each adjacent pair of the plurality of lower floating field plates 30, an upper floating field plate 60 made of a second polysilicon layer is provided so as to cover them. Between the outer end portion of the P-type main junction region 6 and the cell region 4 closest to the cell region 4 among the plurality of lower layer floating field plates 30, that is, the inner end lower layer floating field plate 30a (30), On the insulating film 29, a source potential poly-Si field plate 64 composed of a second polysilicon layer is provided so as to cover between them.

  Between the P + chip peripheral contact region 32 and a plurality of lower layer floating field plates 30 closest to the cell region 4, that is, the outer end lower layer floating field plate 30e (30) and on the lower interlayer insulating film 29 Is provided with a poly-Si guard ring 63 having a drain potential composed of a second polysilicon layer so as to cover between them.

  Next, FIG. 7 shows an enlarged cross-sectional view of the chip peripheral portion cutting region R2 of FIG. As shown in FIG. 7, on the surface 1a of the semiconductor substrate 2 and on the field insulating film 34 in the junction termination region 80, for example, a plurality of first-layer polysilicon layers are formed at regular intervals. Lower layer floating field plates 30a, 30b, 30c, 30d, and 30e are provided. Between adjacent pairs of the plurality of lower floating field plates 30a, 30b, 30c, 30d, and 30e, an upper floating field plate 60a made of a second polysilicon layer is provided so as to cover between them. , 60b, 60c, 60d. Between the outer end portion of the P-type main junction region 6 and the lowermost floating field plate 30a, 30b, 30c, 30d, 30e closest to the cell region 4, that is, the inner end lower layer floating field plate 30a. A source potential poly-Si field plate 64 composed of a second polysilicon layer is provided on the lower interlayer insulating film 29 so as to cover them. As apparent from the structure, the thickness of the underlying insulating film of the upper floating field plates 60a, 60b, 60c, and 60d is greater than the thickness of the underlying insulating film of the lower floating field plates 30a, 30b, 30c, 30d, and 30e. Is also thicker. As a result, the adjacent upper layer floating field plate and lower layer floating field plate constitute a multi-stage field plate (with different thickness of the base insulating film), which contributes to the relaxation of the electric field strength effectively.

  Further, the one closest to the outer end of the P-type main junction region 6 among the poly Si field plate 64 and the plurality of upper layer floating field plates 60a, 60b, 60c, 60d, that is, between the inner end upper layer floating field plate 60a. Is provided with a metal field plate 62 having a source potential so as to cover at least between them. Similarly, the one closest to the outer end of the P-type main junction region 6 in the drain potential poly-Si guard ring 63 and the plurality of upper-layer floating field plates 60a, 60b, 60c, 60d, that is, the outer-end upper layer A metal guard ring 3 (drain potential) is provided between the floating field plates 60d so as to cover at least the space between them.

2. Description of an example of a manufacturing method for the semiconductor device according to the embodiment of the present application (mainly FIGS. 8 to 29)
In the following, as an example of the manufacturing method for the semiconductor device structure of the above-described embodiment, a trench fill method is shown. Needless to say, however, a multi epitaxy method may be used. Needless to say, the order of introduction of impurities may be appropriately changed as necessary.

  In this section, the process corresponding to the structure of section 1 will be described. However, since these steps are basically common to other structures, as a general rule, the following description is given for other structures. Do not repeat.

  FIG. 8 is an enlarged chip cross-sectional view during the manufacturing process (trench formation process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 8 is an enlarged chip cross-sectional view in the manufacturing process (trench processing hard mask removing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the embodiment; FIG. 10 is an enlarged chip cross-sectional view during the manufacturing process (buried epitaxial growth process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 11 is an enlarged chip cross-sectional view during the manufacturing process (planarization process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 12 is an enlarged chip cross-sectional view in the manufacturing process (field insulating film etching process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 13 is an enlarged chip cross-sectional view in the manufacturing process (P body region introducing step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. 14 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 15 is an enlarged chip cross-sectional view during the manufacturing process (P body region introducing resist film removing step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. is there. 16 is an enlarged chip cross-sectional view during the manufacturing process (first layer polysilicon film forming process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device according to the embodiment of the present application. is there. FIG. 17 is an enlarged chip cross-sectional view during the manufacturing process (first layer polysilicon film processing step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. . 18 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 19 is an enlarged chip cross-sectional view during the manufacturing process (N + source region introduction step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. 20 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 21 is an enlarged chip cross-sectional view during the manufacturing process (lower interlayer insulating film forming step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 22 is an enlarged chip cross-sectional view during the manufacturing process (second layer polysilicon film forming step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. is there. FIG. 23 is an enlarged chip cross-sectional view during the manufacturing process (second layer polysilicon film processing step) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. . FIG. 24 is an enlarged chip cross-sectional view during the manufacturing process (upper interlayer insulating film forming step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 25 is an enlarged chip cross-sectional view during the manufacturing process (upper interlayer insulating film etching process) corresponding to the cross section of FIG. 7 for describing an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. 26 is an enlarged chip cross-sectional view during the manufacturing process (substrate contact etc. forming process) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. 27 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. FIG. 28 is an enlarged chip cross-sectional view in the manufacturing process (surface metal electrode etc. forming step) corresponding to the cross section of FIG. 7 for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. 29 is a cross-sectional view of the active cell portion corresponding to FIG. 5 at the same time as FIG. Based on these, an example of a manufacturing method for the semiconductor device according to the embodiment of the present application will be described.

First, as shown in FIG. 8, for example, an N-type silicon single crystal substrate 25 doped with antimony (for example, on the order of 10 ¹⁸ to 10 ¹⁹ / cm ³ ) (here, for example, a 200φ wafer, the wafer diameter is The semiconductor wafer 1 is prepared. On top of this, for example, a phosphorus-doped N epitaxial layer 10n having a thickness of about 45 micrometers (drift region, the concentration is on the order of, for example, 10 ¹⁵ / cm ^3. This region is an N-type drift region 11n. Part of which is also an N column 12n). On the device surface 1a of the semiconductor wafer 1 (the main surface opposite to the back surface 1b), a P-type column trench forming hard mask film 33 made of, for example, P-TEOS (plasma-tetraethylorthosilicate) or the like is formed. Next, as shown in FIG. 8, by using the P-type column trench forming hard mask film 33 as a mask, the N epitaxial layer 10n and the like are dry-etched, thereby forming the P-type column trench 20. As the dry etching atmosphere, for example, an atmosphere containing Ar, SF ₆ , O ₂ or the like as a main gas component can be exemplified. As the range of the dry etching depth, for example, about 40 to 50 micrometers can be exemplified. It is desirable that the P-type column trench 20 reaches the N-type silicon single crystal substrate 25. However, even if they have not reached, they need only be close.

  Next, as shown in FIG. 9, the hard mask film 33 that has become unnecessary is removed.

Next, as shown in FIG. 10, buried epitaxial growth (intra-trench epitaxial filling method) is performed on the P-type column trench 20, and the P-type buried epitaxial layer 10p (the dopant is boron and the concentration is as shown in FIG. 10). For example, on the order of 10 ¹⁵ / cm ³ ). The P-type epitaxial region 10p is a portion that becomes the P-type drift region 11p, and is also a P column 12p. As conditions for the buried epitaxial growth, for example, processing pressure: for example, about 1.3 × 10 ⁴ Pascal to 1.0 × 10 ⁵ Pascal, and source gas: silicon tetrachloride, trichlorosilane, dichlorosilane, monosilane, etc. can be exemplified.

  Next, as shown in FIG. 11, the P-type buried epitaxial layer 10p outside the P-type column trench 20 is removed by a planarization process such as CMP (Chemical Mechanical Polishing), and the surface 1a of the semiconductor wafer 1 is removed. Flatten. Here, the super junction structure as shown in FIG. 11 may be formed by a multi-epitaxial method in addition to the trench fill method. Thereafter, a silicon oxide film 34 (field insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by thermal oxidation. An example of the thickness of the field insulating film 34 is about 350 nm.

  Next, as shown in FIG. 12, a silicon oxide film etching resist film 36 is formed on the silicon oxide film 34 by lithography. Subsequently, using this as a mask, the field insulating film 34 is patterned by, for example, dry etching using a fluorocarbon-based etching gas or the like. Thereafter, the resist film 36 that is no longer needed is entirely removed.

Next, as shown in FIGS. 13 and 14, a P body region introducing resist film 37 is formed by lithography on the surface 1a of the semiconductor wafer 1 (usually, before this, on the surface 1a of the semiconductor wafer 1). For example, an ion implantation protective film such as a thermal oxide film having a thickness of about 10 nm is formed, but the illustration is complicated, and the description is omitted. Subsequently, using the P body region introducing resist film 37 as a mask, the P type body region 6 is introduced by ion implantation. As this ion implantation condition,
(1) First step: ion species: boron, implantation energy: for example, about 200 keV, dose amount: for example, about 10 ¹³ / cm ² ;
(2) First step: ion species: boron, implantation energy: for example about 75 keV, dose amount: for example on the order of 10 ¹² / cm ² can be exemplified as a suitable range (concentration is, for example, 10 ¹⁷ / about the order of cm ³ ). Thereafter, as shown in FIG. 15, the resist film 37 that is no longer needed is entirely removed.

  Next, as shown in FIG. 16, a gate oxide film 27 (gate insulating film) is formed on the surface 1 a of the semiconductor wafer 1. The thickness of the gate insulating film 27 may be, for example, about 50 nm to 200 nm, although it depends on the breakdown voltage. Examples of the film forming method include CVD (Chemical Vapor Deposition) and thermal oxidation. As wafer cleaning before gate oxidation, for example, the first cleaning liquid, that is, ammonia: hydrogen peroxide: pure water = 1: 1: 5 (volume ratio), and the second cleaning liquid, that is, hydrochloric acid: hydrogen peroxide: Wet cleaning can be applied using pure water = 1: 1: 6 (volume ratio). Next, on the gate oxide film 27, a gate electrode polysilicon film 15, that is, a first layer polysilicon film (having a thickness of about 500 nm, for example) is formed by, for example, low pressure CVD (Chemical Vapor Deposition).

  Next, as shown in FIGS. 17 and 18, the gate electrode 15 and the lower floating field plate 30 are patterned by dry etching (for example, a halogen-based gas atmosphere).

Next, as shown in FIGS. 19 and 20, an N + source region introduction resist film 38 is formed by lithography, and using this as a mask, N + source region 26 and N + channel stopper region 31 at the chip edge portion by ion implantation. Is introduced. Examples of suitable ion implantation conditions include ion species: arsenic, implantation energy: about 40 keV, and dose: about 10 ¹⁵ / cm ² , for example (concentration is, for example, 10 ²⁰ / about the order of cm ³ ). Thereafter, the resist film 38 that is no longer needed is entirely removed.

  Next, as shown in FIG. 21, a PSG (Phospho-Silicate-Glass) film 29 (lower interlayer insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like. As the lower interlayer insulating film 29, in addition to the PSG film, a BPSG film, a TEOS film, an SOG film, an HDP (High Density Plasma) silicon oxide film, a PSG film, and a plurality of these films can be used. A laminated film may be used. As a total thickness of the lower interlayer insulating film 29, for example, about 300 nm can be shown as a suitable example.

  Next, as shown in FIG. 22, a second layer polysilicon film 65 (having a thickness of, for example, about 500 nm) is formed on almost the entire surface of the semiconductor wafer 1 on the surface 1a side by, for example, low pressure CVD.

  Next, as shown in FIG. 23, similarly to the process of FIG. 17, the second-layer polysilicon film 65 is patterned to form an upper floating field plate 60, a poly Si guard ring 63, a source potential poly Si field plate. 64 etc. are formed.

  Next, as shown in FIG. 24, a PSG film 69 (upper interlayer insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like. In addition to the PSG film, the upper interlayer insulating film 69 may be a BPSG film, a TEOS film, an SOG film, an HDP silicon oxide film, a PSG film, or a stacked film of a plurality of these films. As a total thickness of the upper interlayer insulating film 69, for example, about 700 nm can be shown as a preferable example.

  Next, as shown in FIG. 25, the second-layer polysilicon film contact opening 61 is formed by, for example, dry etching using a resist pattern (for example, a fluorocarbon-based gas atmosphere).

Next, as shown in FIGS. 26 and 27, a source contact hole opening resist film is formed on the surface 1a of the semiconductor wafer 1, and it is used as a mask by dry etching (for example, a fluorocarbon-based gas atmosphere). A source contact hole 39 and the like are opened. Subsequently, the resist film that has become unnecessary is entirely removed. Next, after etching the silicon substrate (for example, dry etching in a halogen-based gas atmosphere), the P + body contact region 23 and the P + chip peripheral contact region 32 are introduced by ion implantation. As this ion implantation condition, ion species: BF ₂ , implantation energy: for example, about 30 keV, dose amount: for example, on the order of 10 ¹⁵ / cm ² can be exemplified as suitable ranges (concentration is, for example, 10 ¹⁹ / cm ³ order).

  Next, as shown in FIG. 28 and FIG. 29, an aluminum-based metal layer is formed by sputtering or the like through a barrier metal film such as TiW and patterned, so that the metal source electrode 5 and the source potential are reduced. A metal field plate 62, a guard ring electrode 3 and the like are formed.

  Thereafter, if necessary, for example, a final passivation film such as an inorganic final passivation film or an organic inorganic final passivation film is formed as an upper layer, and a pad opening and a gate opening are opened. As the final passivation film, in addition to a single layer film such as an inorganic final passivation film or an organic inorganic final passivation film, an organic inorganic final passivation film or the like may be laminated on a lower inorganic final passivation film. .

  Next, a back grinding process is performed to reduce the original wafer thickness (for example, about 450 to 750 micrometers) to, for example, about 80 to 280 micrometers (that is, less than 300 micrometers).

  Further, a metal back surface drain electrode 24 (see FIGS. 6 and 7) is formed on the back surface 1b of the wafer 1 by sputtering film formation. The back metal electrode film 24 is formed from the side close to the wafer 1, for example, a back titanium film (gold and nickel diffusion prevention layer), a back nickel film (adhesion layer with a chip bonding material), and a back gold film (nickel oxidation prevention). Layer). Thereafter, when divided into individual chips, the device shown in FIG. 7 is obtained. Furthermore, for example, a packaging process such as transfer molding may be performed with a sealing resin as necessary.

3. Description of Modification (P-type Surface RESURF Region) Related to Impurity Structure of Substrate Surface in Junction Termination Region in Semiconductor Device of One Embodiment of the Present Application (Mainly FIGS. 30 and 31)
In this section, as an example of modification of the device structure in section 1, an example in which a ring-shaped P-type surface RESURF region is provided around the P-type main junction region and will be described.

  In the junction termination structure using the capacitive coupling type floating field plate described above, the breakdown voltage characteristics can be effectively controlled without the P-type surface RESURF region. Providing a mold surface RESURF region has an advantage that tolerance for process variations is improved.

  Further, in terms of the manufacturing process, for example, the following preference of FIG. 31 is only added between the steps of FIGS. 11 and 12, and the other steps are the same as those of FIGS.

  FIG. 30 is a cross-sectional view of a chip corresponding to FIG. 6 for describing a modification (P-type surface RESURF region) relating to the impurity structure of the substrate surface in the junction termination region in the semiconductor device of one embodiment of the present application. 31 is an enlarged chip cross-section during the manufacturing process (P-type surface resurf region introduction process) corresponding to the cross-section of FIG. 7 to be inserted between FIG. 11 and FIG. 12 to form the structure of FIG. FIG. Based on these, a modified example (P-type surface RESURF region) relating to the impurity structure of the substrate surface of the junction termination region in the semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 30, in this example, compared to the example of FIG. 6, a P− type surface resurf region 8 connected to the outer edge portion of the P type main junction region 6 is provided on the surface 1 a side of the drift region 11. It is characterized by that. The P-type surface RESURF region 8 is connected to the outside of the annular P-type main junction region 6 to form a concentric annular region in a plan view. In contrast, the concentration is relatively low so that the depletion layer is fully depleted when it extends. The P-type surface RESURF region 8 is a junction termination extension (junction termination extension region) with respect to the P-type main junction region 6.

As a manufacturing process, after the step of FIG. 11, as shown in FIG. 31, a P-type RESURF region introducing resist film 35 is formed on the silicon oxide film 34 by lithography. Subsequently, the P-type surface resurf region 8 is introduced by ion implantation (for example, boron) using the resist film 35 for introducing the P-type resurf region as a mask. Examples of suitable ion implantation conditions include ion species: boron, implantation energy: about 200 keV, and dose amount: about 1 × 10 ¹¹ / cm ² to 1 × 10 ¹² / cm ^2, for example. Thereafter, the resist film 35 that is no longer needed is entirely removed.

  Thereafter, the process proceeds to the process of FIG. 12, and the following is the same as section 2.

4). Description of Modification Example 1 (Round Layout) Regarding Layout of Feel Plate and the like of Chip Corner Part in Semiconductor Device of One Embodiment of the Present Application (Mainly FIG. 32)
The example described in this section is a modification of the planar shape of the field ring (fixed potential field ring, field ring connected to the floating impurity layer, floating field ring, fixed potential guard ring) in the chip corner portion. Will be explained. That is, this is a modification to FIG.

  FIG. 32 is a cut-out region of the chip corner portion of FIG. 2 corresponding to FIG. 4 for explaining the first modification (round layout) related to the layout of the feel plate and the like of the chip corner portion in the semiconductor device of the embodiment of the present application. It is an enlarged plan view of R1. Based on this, a first modification (round layout) relating to the layout of the feel plate and the like of the chip corner portion in the semiconductor device according to the embodiment of the present application will be described.

  32, as compared with the example of FIG. 4, the field plate of this example (lower floating field plate, upper floating field plate, source potential metal field plate, metal guard ring, poly Si guard ring, source The poly Si field plate (potential) has a relatively arcuate shape at the chip corner. This coincides with the fact that the planar shape of the depletion layer in the corner portion tends to have a relatively round shape, which is advantageous in terms of pressure resistance.

5. Description of various modifications related to the detailed layout of the superjunction of the chip corner portion in the semiconductor device according to the embodiment of the present application (mainly FIGS. 33 and 34)
Regarding the super junction detailed layout of the chip corner, various modifications are possible.
The modification with respect to FIG. 4 is shown. These are only specific examples, and further modifications are possible as necessary.

  FIG. 33 is an enlarged plan view of the chip corner section cutout region R1 of FIG. 2 showing a modified example (charge balance type separation layout) regarding the super junction detailed layout of the chip corner section in the semiconductor device of the embodiment of the present application (P Only the column region is shown). FIG. 34 is an enlarged plan view (P column region) of the chip corner portion cutting region R1 of FIG. 2 showing a modified example (right angle bending layout) regarding the super junction detailed layout of the chip corner portion in the semiconductor device of the embodiment of the present application. Only). Based on these, various modifications relating to the superjunction detailed layout of the chip corner portion in the semiconductor device according to the embodiment of the present application will be described.

(1) Description of charge balance type separation layout (mainly FIG. 33):
The detailed layout of the superjunction shown in FIGS. 2, 4 and 32 is such that the superjunction structure in the chip corner portion (peripheral corner region 17b) is the superjunction of one peripheral side region 16a (main part of the junction termination region) adjacent thereto. It is an extension of the structure. That is, “one simple extension layout”. On the other hand, in this example, as shown in FIG. 33, the super junction structure in the chip corner portion (peripheral corner region 17b) has peripheral side regions 16a and 16b on both sides adjacent to the superjunction structure. ) Is an extension of the super junction structure. Further, the P column regions 12p from both sides are separated from each other in the bent portion, and further, the charge balance is also achieved in the chip corner portion (peripheral corner region 17b) by shifting each other by a half width. Have been to keep.

(2) Description of the right angle bend layout (mainly FIG. 34):
In the example shown in FIG. 34, as in the example of FIG. 33, the super junction structure in the chip corner portion (peripheral corner region 17b) has peripheral side regions 16a and 16b (main portions of the junction termination region) on both sides adjacent thereto. It is constructed by extending the super junction structure. However, unlike the example of FIG. 33, the P column regions 12p from both sides are continuous at the bent portion. This structure has the advantage that the layout is very simple. In addition, since the target property is high, it is advantageous with respect to the withstand voltage characteristics except for the viewpoint of charge balance.

6). Description of Modification 2 (P column connection field plate) regarding the layout of the feel plate and the like of the chip corner portion in the semiconductor device according to the embodiment of the present application (mainly FIGS. 35 and 36)
The lower floating field plate and the upper floating field plate shown in the examples so far are both made of a polysilicon film, but some or all of them may be made of a metal film. In this section, an example in which the middle part of these floating field plate groups is replaced with a metal film (for example, the same layer as the metal source electrode) connected to the P column region will be described.

  35 is a chip corner portion of FIG. 2 corresponding to FIG. 4 for explaining a second modification (P column ground field plate) relating to the layout of the feel plate and the like of the chip corner portion in the semiconductor device of the embodiment of the present application. It is an enlarged plan view of cut-out region R1. 36 is an enlarged chip sectional view corresponding to FIG. 7 in the planar structure of FIG. 35 (substantially corresponding to the C-C ′ section of FIG. 35). Based on these, a second modification (P column ground field plate) relating to the layout of the chip corner part feel plate and the like in the semiconductor device according to the embodiment of the present application will be described.

  In the example shown in FIGS. 35 and 36, as compared with the example of FIGS. 4 and 7, the field plate connected to the P column region directly below instead of the lower floating field plate 30c and the upper floating field plates 60b and 60c. That is, the P column connection field plate 70 is provided. The P column connection field plate 70 is connected to the P column region 12p directly below via a field plate-P column connection portion 73 and a P + metal field plate contact region 75. The P + metal field plate contact region 75 is introduced simultaneously with the P + body contact region 23 and the P + chip peripheral contact region 32, for example. The planar position of the field plate-P column connecting portion 73 is preferably arranged so as to avoid the chip corner portion. This is because in the chip corner portion, the spread of the depletion layer and the objectivity of the super junction structure are greatly different.

  By adopting such a structure, the potential of the P column connection field plate 70 changes as the depletion layer expands, so that efficient electric field relaxation is possible and effective in reducing the junction termination length.

7). Description of Modified Example (3D Structure) of Superjunction Structure of Junction Termination Region in Semiconductor Device of One Embodiment of the Present Application (Mainly FIGS. 37 to 39)
The super junction structure of the junction termination region in the examples so far (this is called the super junction structure of the cell, that is, the peripheral super junction structure as distinguished from the cell super junction structure) is clearly all two-dimensional except for the chip corner. Although it is a structure, it can also be a three-dimensional structure. In the three-dimensional structure, it is considered that the terminal length can be further reduced. Even if the peripheral superjunction structure is changed to three dimensions, the other parts are the same, and the previous examples can be applied to the examples in this section as they are.

FIG. 37 is a plan view of the entire chip corresponding to FIG. 2 for explaining a modification (3D structure) regarding the super junction structure of the junction termination region in the semiconductor device of the embodiment of the present application. FIG. 38 is an enlarged plan view of the chip corner section cutting region R1 of FIG. 39 is an enlarged chip sectional view corresponding to FIG. 7 in the planar structure of FIG. 38 (substantially corresponding to the section CC ′ of FIG. 38). Based on these, a modified example (3D structure) regarding the super junction structure of the junction termination region in the semiconductor device of the embodiment of the present application will be described.

  As shown in FIG. 35, similarly to the case of FIG. 2, the cell region 4 (the cell region super junction structure 14 is provided in the lower part) is provided in the central portion of the chip 2, and the inside thereof is provided. Are provided with a large number of linear polysilicon gate electrodes 15. Furthermore, as described above, the outer edge portion of the cell region 4 is the ring-shaped P-type main junction region 6.

  Next, the superjunction structure around the cell region superjunction structure 14 (junction termination region 80), that is, the peripheral superjunction structure 9 will be described (in this example, both structures are the drift region 11, ie, the N type). It is composed of a P column region 12p provided in the drift region 11n). The peripheral side regions 16a and 16c are each provided with a peripheral super junction structure 9 connected to the cell region super junction structure 14 and having the same orientation. On the other hand, the peripheral side regions 16b and 16d are each provided with a peripheral super junction structure 9 that is not connected to the cell region super junction structure 14 and has an orientation orthogonal thereto. In this column layout, the peripheral corner regions 17a, 17b, 17c, and 17d are periodic extension regions of the peripheral side regions 16b and 16d below or above them.

  As shown in FIG. 37, similarly to FIG. 2, the cell region 4 (the cell region super junction structure 14 is provided in the lower part) is provided in the central portion of the chip 2, and inside thereof, A large number of linear polysilicon gate electrodes 15 are provided. Furthermore, as described above, the outer edge portion of the cell region 4 is the ring-shaped P-type main junction region 6.

  Next, the superjunction structure around the cell region superjunction structure 14 (junction termination region 80), that is, the peripheral superjunction structure 9 will be described (in this example, both structures are the drift region 11, ie, the N type). It is composed of a P column region 12p provided in the drift region 11n). Unlike the case of FIG. 2, the peripheral side regions 16a and 16c are each provided with a peripheral super junction structure 9 connected to the cell region super junction structure 14 and having the same orientation. On the other hand, the peripheral side regions 16b and 16d are each provided with a peripheral super junction structure 9 that is not connected to the cell region super junction structure 14 and has an orientation orthogonal thereto. In this column layout, the peripheral corner regions 17a, 17b, 17c, and 17d are periodic extension regions of the peripheral side regions 16b and 16d below or above them.

  Next, since the layout of the chip corner portion cutout region R1 of FIG. 37 shown in FIG. 38 is exactly the same as that of FIG. 32 except for the peripheral super junction structure 9, description thereof will not be repeated here.

  Next, a chip cross section corresponding to FIG. 7 is shown in FIG. 39 (almost corresponding to the C-C ′ cross section of FIG. 38). As shown in FIG. 39, it is substantially the same as FIG. 7, except that the P column region 12p constituting the peripheral super junction structure 9 (FIG. 38) appears as a cross section in the longitudinal direction. Since there is no difference from the description of FIG. 7 in other points, the description will not be repeated for individual pieces.

  By adopting such a structure, the junction termination length can be further reduced as an effect of the three-dimensional peripheral super junction structure.

8). Description of Modified Example (Diode Embedded Cell) of Active Cell in Semiconductor Device of One Embodiment of the Present Application (Mainly FIG. 40)
In sections 1 and 2, the structure of the active cell has been described specifically with a simple active cell as an example. In this section, as an example of another cell structure, a mixed cell in which a diode cell is added to a MOSFET cell is used. The active cell will be described.

  FIG. 40 is a chip cross-sectional view of the unit cell region corresponding to FIG. 5 for explaining a modification (diode-embedded cell) related to the active cell in the semiconductor device of the embodiment of the present application. Based on this, a modification (diode-embedded cell) related to the active cell in the semiconductor device of the one embodiment of the present application will be described.

  Instead of repeating all or part of the active cell region 4a in FIG. 1 as a simple active cell (unit cell) as shown in FIG. 5, a Schottky diode or the like is provided in a part of the unit cell as shown in FIG. It is also possible to have a built-in mixed active cell repeating structure. As shown in FIG. 40, the mixed unit cell 71 (integrated MOSFET & diode unit cell) is provided with a diode portion 71d and a transistor portion 71t. In this structure, a Schottky junction 72 (a Schottky junction is formed by the metal source electrode 5 and the N column region 12n) is provided in the diode portion 71d. In other respects, the substrate contact groove 39 is provided. 5 is basically the same as FIG.

9. Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIGS. 41 and 42)
FIG. 41 is a plan view of the entire chip corresponding to FIG. 3 for explaining the outline of the semiconductor device according to the embodiment (including the modification) of the present application. FIG. 42 is a simulation data diagram for explaining the merit of the capacitively coupled junction termination structure in the semiconductor device according to the embodiment of the present application. Based on these, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Description of outline of semiconductor device of one embodiment (including modification) of the present application (mainly FIG. 41):
In the vertical power MOSFET which is an example of the semiconductor device according to the embodiment (including the modification) of the present application, as shown in FIG. 41, a plurality of concentric annular shapes are provided between the cell region 4 and the chip end. Lower-layer floating field rings 30a and 30 and upper-layer floating field rings 60 are provided so as to straddle and cover the inner and outer peripheries thereof. As a result, electric field concentration does not occur at any location in the junction termination region 80, and high breakdown voltage characteristics can be exhibited.

  In the semiconductor substrate surface region of the junction termination region 80, there are a plurality of concentric annular lower floating field rings 30 a and 30 that are electrically independent from each other, and an upper floating field that is electrically independent of these is provided between them. This is because, since the ring 60 is covered, no specific curve appears in the distribution of the equipotential surface, and the distribution is relatively uniform.

(2) Description of the merit of the junction termination structure (capacitive coupling type floating field plate) in the power MOSFET which is the semiconductor device of the one embodiment (including the modification) of the present application (mainly FIGS. 41 and 42):
This is shown by simulation in FIG. 42 (simulation result of electric field strength distribution in the blocking mode in the device corresponding to FIG. 6). That is, in a portion (junction termination region 80) of the capacitively coupled floating field plate from the center to the right in the figure, no local high electric field portion is seen at all. In the portion (the portion surrounded by the dotted line), a portion with high electric field strength appears intensively. In this way, it is generally considered that a high electric field strength portion appears intensively inside the cell region 4 in the depth direction is a preferable electric field strength distribution.

  The floating field plate is mainly used in the center of the junction termination region 80. In the junction termination region 80 having a super junction structure, a normal floating field ring or a field plate connected thereto is used. Cannot generally be used because different P column regions can be interconnected (the example in section 6 is an exception). Therefore, there is no fixed potential to be referenced except at the chip end and the cell region end. Therefore, in the above-described embodiment (including the modified example) of the present application, there is an intermediate relationship between the floating field plates (capacitive coupling). It can be seen that the reference potential is automatically created.

10. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the planar type MOS structure has been specifically described as an example. However, the present invention is not limited thereto, and it goes without saying that the present invention can be applied to a trench type gate structure. . In addition, the layout of the gate electrode of the MOSFET is shown as an example in which the gate electrode is arranged in stripes parallel to the pn column. However, it can be arranged in a direction orthogonal to the pn column, arranged in a lattice, or various applications.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited to this, and P + silicon is used. A P channel device may be formed on the upper surface of the N epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and a power device having a super junction structure, that is, a diode, a bipolar transistor (including an IGBT). Needless to say, the present invention can also be applied. Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating these power MOSFETs, diodes, bipolar transistors and the like.

  Furthermore, in the above embodiment, the trench fill method has been specifically described as a method for forming the super junction structure. However, the present invention is not limited thereto, and for example, a multi-epitaxial method can be applied. Needless to say.

  In the above-described embodiments, devices mainly made on a silicon-based semiconductor substrate have been specifically described. However, the present invention is not limited thereto, and a GaAs-based semiconductor substrate, a silicon carbide-based semiconductor substrate, and a silicon nitride. Needless to say, the present invention can be applied almost as it is to a device made on a ride-type semiconductor substrate.

1 Wafer 1a Wafer or semiconductor chip device main surface (first main surface)
1b Back surface of wafer or semiconductor chip (second main surface)
2 Semiconductor chip or chip region 3 Metal guard ring 4 Cell region 4a Active cell region 4d Dummy cell region 5 Metal source electrode 6 P-type main junction region (P base region, P body region or its outer edge)
7 Metal gate electrode 7w Metal gate wiring 8 P-type surface resurf region 9 Peripheral super junction structure 10n N type epitaxial region 10p P type epitaxial region 11 Drift region 11n N type drift region 11p P type drift region 12n N column region 12p P column Region 14 Cell region super junction structure 15 Polysilicon gate electrode (first layer polysilicon film)
15w Polysilicon gate wiring 16a, 16b, 16c, 16d Peripheral side region 17a, 17b, 17c, 17d Peripheral corner region 20 Trench 23 P + body contact region 24 Metal back surface drain electrode 25 N + drain region (N-type single crystal silicon substrate)
26 N + source region 27 Gate insulating film 29 Lower interlayer insulating film 30, 30a, 30b, 30c, 30d, 30e Lower floating field plate 31 N + channel stop region 32 P + chip peripheral contact region 33 Trench processing hard mask film 34 Field insulating film 35 P-type surface resurf region introduction resist film 36 Silicon oxide film etching resist film 37 P body region introduction resist film 38 N + source region introduction resist film 39 Substrate contact groove 60, 60a, 60b, 60c, 60d Upper layer floating Field plate 61 Second layer polysilicon film contact opening 62 Source potential metal field plate 63 Poly Si guard ring 64 Source potential poly Si field plate 65 Second layer layer Resilicon film 69 Upper interlayer insulating film 70 P column connection field plate 71 Integrated MOSFET & diode unit cell 71d Diode part 71t Transistor part 72 Schottky junction 73 Field plate-P column connection part 74 Metal gate wiring-polysilicon gate wiring connection part 75 P + Metal Field plate contact region 80 Junction termination region 83 P column P + contact region R1 Chip corner cutout region R2 Chip peripheral cutout region R3 Cell cutout region R4 Cell portion internal and chip peripheral cutout region Wn N column thickness Wp P column thickness

Claims (20)

Vertical power MOSFET including:
(A) a silicon-based semiconductor substrate having a first main surface and a second main surface;
(B) a cell region provided on the first main surface side;
(C) a drift region of a first conductivity type provided in a substantially entire surface on the first main surface side of the silicon-based semiconductor substrate;
(D) a metal source electrode provided on the first main surface and in the cell region;
(E) a metal drain electrode provided on the second main surface;
(F) a second-conductivity-type main junction region provided on a surface of the drift region on the first main surface side so as to constitute an annular outer edge portion of the cell region;
(G) An annular junction termination region provided on the first main surface side around the cell region so as to surround the cell region;
(H) a super junction structure provided in the drift region in the cell region and the junction termination region;
(I) a plurality of concentric annular lower floating field plates provided on the first principal surface and provided in the junction termination region;
(J) On the first main surface, an annular upper layer provided above the plurality of lower layer floating field plates so as to cover between adjacent lower layer floating field plate pairs. Floating field plate.     2. The vertical power MOSFET according to claim 1, wherein the vertical power MOSFET has a planar structure.     3. The vertical power MOSFET according to claim 2, wherein each lower floating field plate is composed of a first layer polysilicon film.     4. The vertical power MOSFET according to claim 3, wherein the upper floating field plate is composed of a second layer polysilicon film that is higher than the first layer polysilicon film. 5. The vertical power MOSFET of claim 4 further comprising:
(K) The second polysilicon film provided on the first main surface and extending from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates. Source potential poly-Si field plate composed of 6. The vertical power MOSFET of claim 5 further comprising:
(L) Provided on the first main surface from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates, and the same layer as the metal source electrode Source potential metal field plate composed of a metal film. The vertical power MOSFET of claim 6 further comprising:
(M) provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower-layer floating field plates; A drain potential poly-Si guard ring composed of a silicon film. 8. The vertical power MOSFET of claim 7, further comprising:
(N) Provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower floating field plates, and the metal source electrode A drain potential metal guard ring composed of the same layer of metal film.     4. The vertical power MOSFET according to claim 3, wherein the super junction structure in the junction termination region is a two-dimensional structure.     4. The vertical power MOSFET according to claim 3, wherein the super junction structure in the junction termination region is a three-dimensional structure. The vertical power MOSFET of claim 3, further comprising:
(P) A surface resurf region of the second conductivity type provided on the surface of the drift region so as to be connected to and surround the outer end of the main junction region. The vertical power MOSFET of claim 3, further comprising:
(Q) The second conductivity type provided on the first main surface and between the adjacent pair of the plurality of lower floating field plates, and constituting the super junction structure in the junction termination region. An annular metal intermediate field plate, electrically connected to the column region having
Here, the metal intermediate field plate is composed of a metal film in the same layer as the metal source electrode. Semiconductor devices including:
(A) a silicon-based semiconductor substrate having a first main surface and a second main surface;
(B) a cell region provided on the first main surface side;
(C) a drift region of a first conductivity type provided in a substantially entire surface on the first main surface side of the silicon-based semiconductor substrate;
(D) a metal first electrode provided on the first main surface and in the cell region;
(E) a metal second electrode provided on the second main surface;
(F) a second-conductivity-type main junction region provided on a surface of the drift region on the first main surface side so as to constitute an annular outer edge portion of the cell region;
(G) An annular junction termination region provided on the first main surface side around the cell region so as to surround the cell region;
(H) a super junction structure provided in the drift region in the cell region and the junction termination region;
(I) a plurality of concentric annular lower floating field plates provided on the first principal surface and provided in the junction termination region;
(J) On the first main surface, an annular upper layer provided above the plurality of lower layer floating field plates so as to cover between adjacent lower layer floating field plate pairs. Floating field plate.     14. The semiconductor device according to claim 13, wherein each lower floating field plate is composed of a first layer polysilicon film.     15. The semiconductor device according to claim 14, wherein the upper floating field plate is composed of a second layer polysilicon film that is higher than the first layer polysilicon film. 15. The semiconductor device of claim 14, further comprising:
(K) The second polysilicon film provided on the first main surface and extending from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates. A first electrode potential poly-Si field plate comprising: 17. The semiconductor device of claim 16, further comprising:
(L) Provided on the first main surface from the outer edge of the cell region to the innermost one of the plurality of lower floating field plates, and the same as the metal first electrode 1st electrode electric potential metal field plate comprised from the metal film of a layer. 18. The semiconductor device of claim 17, further comprising:
(M) provided on the first main surface from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower-layer floating field plates; A second electrode potential poly-Si guard ring made of a silicon film. 19. The semiconductor device of claim 18, further comprising:
(N) The metal first electrode provided on the first main surface and from the vicinity of the end of the silicon-based semiconductor substrate to the outermost one of the plurality of lower floating field plates. And a second electrode potential metal guard ring composed of the same metal layer.     15. The semiconductor device according to claim 14, wherein the super junction structure in the junction termination region is a two-dimensional structure.

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