JP2014002803A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the efficiency of repairing a word line in a semiconductor device of a type in which a plurality of word lines are selected at one time by one row address.SOLUTION: A semiconductor device 10 includes a bank 20-1, a defective word line address register 36, and an array control circuit 37. The bank 20-1 includes: a plurality of word lines WL which include a first word line WL1 being a defective word line and a second word line WL1 being a normal word line that is not defective; and at least one redundant word line RWL. The bank is configured so as to have the first and second word lines WL1 selected at one time on the basis of a row address XA. The defective word line address register 36stores defective word line information DWAthat identifies the first word line WL1, in association with one of the at least one redundant word line RWL. The array control circuit 37, in response to the supply of the row address XA, selects the redundant word line RWL associated with the defective word line information DWA, instead of the first word line WL1; and selects the second word line WL1.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device of a type in which a plurality of word lines are selected at a time by one row address.

  In a semiconductor device typified by DRAM (Dynamic Random Access Memory), a word line (defective word line) connected to a defective memory cell is replaced with a redundant word line as one of means for relieving a defective memory cell. Processing is performed. For this processing, the semiconductor device is provided with a defective row address storage circuit that stores a row address for each redundant word line. At the time of row access, it is determined whether or not the supplied row address is stored in the defective row address storage circuit. If stored, the word line (defective word line) indicated by the row address is determined. Instead, the corresponding redundant word line is selected.

  By the way, some recent semiconductor devices are configured to use a large number of word lines included in a memory cell array divided into a plurality of blocks. In this type of semiconductor device, the same row address space is allocated to each block, and the word line corresponding to the supplied row address is activated in each block at the time of row access. As a result, the word lines for the number of blocks are activated at a time, so that it is possible to read / write bits for the number of blocks with a single row access. In this case, a predetermined number of redundant word lines are provided in each block, and word line replacement when a defective word line is generated is configured to be completed within the block. That is, the replacement destination of the defective word line is a redundant word line in the same block.

  Patent Documents 1 to 3 disclose a configuration in which replacement is performed in units of blocks.

JP 2004-39680 A JP 2007-172832 A JP 2009-1117016 A

  However, in the semiconductor device having the block configuration described above, when a defective word line is generated in one block and the defective word line is replaced with a redundant word line, the defective word line is also used in other blocks. A word line having the same row address is replaced with a redundant word line. That is, there is a problem that the repair efficiency is not good because redundant word lines corresponding to the number of blocks are used to repair one word line.

  This is because the defective row address storage circuit stores the defective word line by the row address. As described above, in a semiconductor device having a block configuration, the same row address space is assigned to each block. Therefore, when a defective word line is generated in a certain block and its row address is stored in the defective row address storage circuit, even word lines having the same row address in other blocks are treated as defective word lines. turn into.

  This problem commonly occurs in a semiconductor device of a type in which a plurality of word lines are selected at a time by one row address (one row address is assigned to a plurality of word lines) regardless of the presence or absence of the block configuration. It is. Therefore, in this type of semiconductor device, a technique that can improve the relief efficiency of the word line is desired.

  A semiconductor device according to an aspect of the present invention includes a plurality of normal word lines including first and second normal word lines and at least one redundant word line, and the first and second word lines are responsive to address information. A memory cell array configured such that a second normal word line is selected at a time and a defect that identifies the first normal word line in association with one of the at least one redundant word line A defect information storage circuit for storing information, and in response to the supply of the address information, the redundant word line corresponding to the defect information is selected in place of the first normal word line, and the second And a control circuit for selecting the normal word line.

  A semiconductor device according to another aspect of the present invention corresponds to a memory cell array including a plurality of blocks each including a plurality of normal word lines, at least one redundant word line, and each of the at least one redundant word line. At least one defect information storage that stores a row address assigned to a defective word line of the plurality of normal word lines and a block address indicating the block to which the defective word line belongs in association with each other. The redundant word line to be replaced is specified by specifying the circuit and the defect information storage circuit storing the row address in response to the supply of the row address, and the specified defect information The block to be replaced is identified from the block address stored in the storage circuit, and the replacement process is performed. The normal word indicated by the supplied row address is selected for the block other than the block specified as a replacement processing target while selecting the redundant word line specified as a replacement destination for the block specified as the target of replacement And a control circuit for selecting a line.

  According to the present invention, since the word line (normal word line) which is a defective word line is specified by the defect information, when one word line is relieved, the redundant word is extended to other word lines having the same row address. There is no need to replace it with a line. Therefore, the relief efficiency of the word line is improved.

1 is a diagram showing an overall configuration of a semiconductor device 10 according to a first embodiment of the present invention. It is the figure which extracts and shows the characteristic part of this invention among each structure of the semiconductor device 10 shown in FIG. FIG. 3 is a diagram showing an internal circuit of an array control circuit 37 shown in FIGS. 1 and 2. It is a figure which shows the whole structure of the semiconductor device 10 by the 2nd Embodiment of this invention. FIG. 5 is a diagram showing a part characteristic of the present invention extracted from each configuration of the semiconductor device 10 shown in FIG. 4. 6 is a diagram showing an internal circuit of the IO line switch 38 shown in FIGS. 4 and 5. FIG. It is a figure which shows the system configuration example of the computer 70 by the 3rd Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing an overall configuration of a semiconductor device 10 according to a first embodiment of the present invention. As shown in the figure, the semiconductor device 10 has clock terminals 11, 12, a clock enable terminal 13, a command terminal 14, an address terminal 15, and a data input terminal as input / output terminals for transmitting / receiving signals to / from the outside. An output terminal 16 is provided. The semiconductor device 10 includes four banks 20-1 to 20-4 (banks 1 to 4), and each bank includes a row decoder 21, a column decoder 25, and an array control circuit 37 (control circuit). ing. Further, the semiconductor device 10 includes a read / write (RW) amplifier 26, a latch circuit 27, a data input / output buffer 28, a command decoder 30, a chip control circuit 31, a mode register 32, a row address buffer 33, a column address buffer 34, a refresh address. A counter 35, a defective word line address register 36 (defective information storage circuit), and a clock generation circuit 40 are provided.

  Each of the banks 20-1 to 20-4 includes a plurality of bit lines BL extending in one direction, a plurality of word lines WL extending in a direction orthogonal to the bit lines BL, and intersections of the bit lines BL and the word lines WL. This is a memory cell array having memory cells MC provided for each. In FIG. 1, only one bit line BL, word line WL, and memory cell MC are illustrated. Each bit line BL is connected to the first IO line IOL via a sense amplifier and a column switch (not shown). As a specific configuration method of the bit line BL, an open bit line method, a folded method, and the like are known, and the present invention can be applied to any method, but in this embodiment, the folded method is used. This will be explained as a premise.

  Each of the clock terminals 11 and 12 is a terminal to which an external clock signal CK and its inverted signal / CK are supplied, and a clock enable terminal 13 is a terminal to which a clock enable signal CKE is input. In this specification, the symbol “/” added to the head of a signal name indicates that the signal is an inverted signal of the corresponding signal or a low-active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generation circuit 40 is a circuit that generates an internal clock signal LCLK based on the external clock signals CK and / CK, and the generated internal clock signal LCLK is supplied to each part in the semiconductor device 10.

  The command terminal 14 includes a plurality of terminals to which a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are supplied. The external controller supplies various commands such as an act command ACT, a write command WRT, a read command RED, and an auto-refresh command REF to the semiconductor device 10 according to a combination of logical levels of these command signals. The supplied command signal is supplied to the chip control circuit 31 via the command decoder 30 that performs holding, decoding, and counting of the command signal. The chip control circuit 31 generates various internal commands based on the output of the command decoder 30, thereby causing the read / write amplifier 26, the latch circuit 27, the array control circuit 37 for each bank, the row address buffer 33, the column address buffer. 34, the operation of the refresh address counter 35 and the defective word line address register 36 is controlled. Note that the processing of the command decoder 30 and the chip control circuit 31 is performed in synchronization with the internal clock LCLK.

The address terminal 15 is a terminal to which an address signal ADD is supplied. The address signal ADD is input to the semiconductor device 10 in synchronization with the command signal. The address signal ADD is generally composed of 2-bit address signals BA ₀ and BA ₁ and i + 1-bit address signals A _{0 to} A _i . The address signals BA ₀ and BA ₁ are bank addresses indicating the banks to be subjected to operations such as read / write, and are supplied to both the row address buffer 33 and the column address buffer 34. When the address signals A _{0 to} A _i are input in synchronization with the act command ACT, the address signals A _{0 to} A _i indicate a row address XA (X _{0 to} X _i ), which will be described later, and are supplied to the row address buffer 33. On the other hand, when it is input in synchronization with the write command WRT or the read command RED, it indicates a column address YA described later and is supplied to the column address buffer 34. When the semiconductor device 10 has entered the mode register set, the address signal ADD is information indicating the mode of the semiconductor device 10 and is supplied to the mode register 32.

  The address signal buffered in the row address buffer 33 is supplied to the array control circuit 37, and the address signal buffered in the column address buffer 34 is supplied to the column decoder 25. The array control circuit 37 is a circuit that selects (activates) the word line WL in the corresponding bank based on the supplied row address XA (address information). The function of the array control circuit 37 will be described in more detail later. The column decoder 25 controls the connection state of a column switch (not shown) based on the supplied column address YA, thereby converting the bit line BL connected to the memory cell to be accessed to the first IO line shown in FIG. This is a circuit connected to the read / write amplifier 26 through the IOL.

  In addition to the row address XA, the array control circuit 37 is supplied with the refresh address RA from the refresh address counter 35 and with the defective word line information DWA (defective information) from the defective word line address register 36. The refresh address RA is address information indicating a row address to be refreshed. The refresh address counter 35 is configured to generate the refresh address RA under the control of the chip control circuit 31 that has received the input of the auto-refresh command REF. The refresh address counter 35 has an increment circuit (not shown), and generates a refresh address RA so that all row addresses are sequentially subjected to refresh processing. The array control circuit 37 refreshes the memory cells by activating the word line WL indicated by the refresh address RA generated in this way. The defective word line information DWA will be described later.

  The data input / output terminal 16 is a terminal for inputting / outputting read data DQ or write data DQ, and a plurality of data input / output terminals 16 are provided in the semiconductor device 10. The plurality of data input / output terminals 16 are connected to a read / write amplifier 26 via a data input / output buffer 28 and a latch circuit 27, respectively. The data input / output buffer 28 has an input buffer and an output buffer (not shown), and these buffers input / output read data DQ or write data DQ in synchronization with the internal clock signal LCLK. The latch circuit 27 is a circuit that realizes a so-called DDR (Double Data Rate) function, and includes a first-in first-out (FIFO) circuit and a multiplexer circuit. Data input / output of the FIFO circuit is performed in synchronization with the internal clock signal LCLK. The read / write amplifier 26 includes a data amplifier circuit and a multiplexer circuit. With these circuits, parallel read data supplied from the memory cell array is converted from differential format to single-ended format, then converted to serial read data, and output from the data input / output terminal 16 to the outside. On the other hand, serial write data supplied from the data input / output terminal 16 is converted into parallel write data, converted from a single-ended format to a differential format, and then supplied to the memory cell array. The chip control circuit 31 switches between the multiplexer circuit in the latch circuit 27 and the multiplexer circuit in the read / write amplifier 26.

  FIG. 2 is a diagram showing a part characteristic of the present invention extracted from each configuration of the semiconductor device 10 shown in FIG. Although the configuration related to the bank 20-1 is shown in the figure, the same applies to other banks. Hereinafter, the configuration of the semiconductor device 10 will be described in more detail with reference to FIG.

  As shown in FIG. 2, the inside of the bank 20-1 is divided into a plurality of blocks 20-1A to 20-1D that do not share the word line WL. Each of the blocks 20-1A to 20-1D includes two mats M0 and M1, and sense amplifier regions 22 are arranged on both sides of the mats M0 and M1 in the bit line direction (the horizontal direction in the drawing). A large number of sense amplifiers SA are arranged in the sense amplifier region 22, and each sense amplifier SA has both complementary bit lines BL and / BL extending in the same direction as illustrated in FIG. (Folded method). The sense amplifier SA belonging to the block 20-1A is connected to a first IO line IO_A that is a part of the first IO line IOL shown in FIG. 1 via a column switch (not shown). Similarly, the sense amplifiers SA belonging to the blocks 20-1B to 20-1D are connected to the first IO lines IO_B to IO_D through the column switches, respectively. As described above, the connection state of the column switch is controlled by the column decoder 25 that has received the column address YA.

  A row decoder (XDEC) 21 is disposed at one end of each mat M0, M1 in the word line direction. Each row decoder 21 controls the potential of each of the plurality of word lines WL in the corresponding mat in accordance with the mat control signal MAC supplied from the array control circuit 37. Specifically, the potential of the word line indicated by the mat control signal MAC is set higher than the threshold voltage of the cell transistor. As a result, each of the corresponding cell transistors is turned on. On the other hand, the potential of the word line that is not indicated as the selection target by the mat control signal MAC is set lower than the threshold voltage of the cell transistor. As a result, each of the corresponding cell transistors is turned off. Details of the mat control signal MAC will be described later.

  Each of the blocks 20-1A to 20-1D has a first predetermined number of word lines WL and a second predetermined number of redundant word lines RWL. A common row address space is allocated to each of the blocks 20-1A to 20-1D. As a result, each of the blocks 20-1A to 20-1D always has one word line WL having the same row address. For example, the four word lines WL1 shown in FIG. 2 have a common row address, and one word line WL1 is arranged in each of the blocks 20-1A to 20-1D. The plurality of word lines WL in the bank 20-1 to which the same row address is assigned are selected at a time during row access because the row addresses are the same.

The defective word line address register 36 includes defective word line address registers 36 _{1 to} 36 _N which are partial circuits for each redundant word line RWL. N is the total number of redundant word lines RWL provided in the bank 20-1 (= 4 times the second predetermined number). Each of the defective word line address registers 36 _{1 to} 36 _N is configured to store one defective word line information DWA. Hereinafter, the defective word line information DWA stored in the defective word line address registers 36 _{1 to} 36 _N may be referred to as defective word line information DWA _{1 to} DWA _N , respectively. As a specific storage means, a fuse circuit or an antifuse circuit is preferably used.

  The defective word line information DWA is information including a row address XA and a block address. The block address is a total of 4 bits of data corresponding to 1 block, and only one of the 4 bits is 1 and the other 3 bits are 0. Therefore, one of the blocks 20-1A to 20-1D is specified by the block address. The defective word line information DWA identifies one word line WL (of the four word lines to which the row address XA is assigned belongs to the block indicated by the block address).

The word line WL specified by the defective word line information DWA is a defective word line detected by a test during manufacturing. The writing of the defective word line information DWA to the defective word line address register 36 is performed by an external test apparatus or the like. When writing the defective word line information DWA, one corresponding to the redundant word line RWL belonging to the same block as the detected defective word line WL is selected from the defective word line address registers 36 _{1 to} 36 _N. Therefore, it is necessary to write the defective word line information DWA. As shown in FIG. 2, when one block is divided into two mats and the sense amplifier SA is shared between adjacent different blocks, redundant word lines RWL belonging to the same block and belonging to the same mat are used. It is necessary to select the one corresponding to. This is to avoid competition of the sense amplifier SA. That is, in the semiconductor device 10, since one word line WL is selected at a time from each block, if the word line WL in one block is replaced with the redundant word line RWL in another block, At the same time, two word lines WL are selected, and contention for the sense amplifier SA occurs. In order to avoid this, the write destination of the defective word line information DWA is set so that the defective word line WL and the replacement redundant word line RWL are present in the same block (in the same mat in the example of FIG. 2). Must be selected.

  As described above, the array control circuit 37 selects the word line WL in the corresponding bank based on the row address XA (including the refresh address RA) supplied from the row address buffer 33 or the like as described above. It is configured to (activate). Specifically, this selection is performed by supplying the mat control signal MAC indicating the row address XA of the word line WL to be selected to the row decoder 21 of each block.

  In addition to such a basic function, the array control circuit 37 according to the present embodiment has a function of replacing (relieving) a defective word line WL with a redundant word line RWL. The array control circuit 37 performs this replacement only for the block to which the defective word line WL belongs, and performs the operation according to the basic function described above for the other blocks. Hereinafter, the processing at the time of relief will be described in detail.

  When the array control circuit 37 is supplied with the row address XA (including the refresh address RA), the array control circuit 37 first identifies the defective word line address register 36 storing the defective word line information DWA including the row address XA. Based on the result, the redundant word line RWL to be replaced is specified. Further, a block (a block to which a word line WL that is a defective word line belongs) is specified from the block address included in the defective word line information DWA.

FIG. 3 is a diagram showing a part of the internal circuit of the array control circuit 37 for performing the above specific processing. In the same figure, defective word line address registers 36 _{1 to} 36 _N are also shown. As shown in FIG. 3, the array control circuit 37 includes hit signal generation units 50 ₁ to 50 _N provided in one-to-one correspondence with the defective word line address registers 36 _{1 to} 36 _N , a block hit signal generation unit 51, and the like. have. Addresses FA _{0 to} FA _i shown in the figure represent row addresses XA (X _{0 to} X _i ) included in the defective word line information DWA. The block data BA to BD are data constituting the block address described above, and correspond to the blocks 20-1A to 20-1D, respectively.

The hit signal generation unit 50 _k (k = 1 to N) activates the hit signal HIT _k when the corresponding defective word line address register 36 _k stores the row address XA supplied to the array control circuit 37. If, and only if the hit signal hIT _k is activated, activated in response to the block address corresponding to the defective word line address register 36 _k has stored a plurality of intermediate blocks hit signal _/ HIT_A _k ~ _/ HIT_D k Is a circuit that generates

More specifically, the hit signal generation unit 50 _k firstly has a row address XA (X _{0 to} X _i ) supplied from the row address buffer 33 and the like and a row supplied from the corresponding defective word line address register 36 _k. Addresses FA _{0 to} FA _i are compared bit by bit. When all bits are equal, the logical value of the hit signal HIT _k is set to high (active state), and otherwise, the logical value of the hit signal HIT _k is set to low (inactive state). Therefore, the defective word line address register 36 _k which outputs a hit signal HIT _k at the high is identified as a defective word line address register 36 which stores the defective word line information DWA including a row address XA. Then, the array control circuit 37 specifies the redundant word line RWL corresponding to the defective word line address register 36 thus specified as the replacement redundant word line RWL.

Next, the hit signal generation unit 50 _k compares the hit signal HIT _k thus generated with each of the block data BA to BD supplied from the corresponding defective word line address register 36 _k , and according to the result. Controls logical values of intermediate block hit signals / HIT_A _k to / HIT_D _k . Specifically, for example, regarding the intermediate block hit signal / HIT_A _k , when the hit signal HIT _k is high and the block data BA is 1 (high), the logical value is set to low (active state), and otherwise In this case, the logical value is set to high (inactive state). The same applies to the intermediate block hit signals / HIT_B _k to / HIT_D _k . In this way, the logical value of the intermediate block hit signal / HIT_A _k to / HIT_D _k reflects the block address included in the corresponding defective word line information DWA only when the hit signal HIT _k is activated. . Therefore, the block to be replaced is specified by the logical value of the intermediate block hit signal / HIT_A _k to / HIT_D _k .

Block hit signal generator 51, based on the intermediate block hit signal _/ HIT_A 1 ~ _/ HIT_D _N the hit signal generation unit ₅₀ 1 to 50 _N is generated, a circuit for generating a block hit signal HIT_A～HIT_D. Specifically, for example, with respect to the block hit signal HIT_A, and corresponding low logic value if the intermediate block hit signal _/ HIT_A 1 ~ _/ HIT_A _N are all high (inactive state), the logic otherwise The value is set to high (active state). The same applies to the block hit signals HIT_B to HIT_D.

The specific process performed by the array control circuit 37 will be described in more detail with reference to a specific example with reference to FIG. 2 again. As described above, FIG. 2 shows four word lines WL1 to which a common row address is assigned. Of these, the word line WL1 (first word line) arranged in the block 20-1B is defective. It is a word line. The other word lines WL1 (second word lines) are normal word lines that are not defective. Here, since the defective word line address register 36 ₁ Assuming that stores defective word line information DWA according to the defective word line WL1, consisting defective word line address register 36 ₁ to the row address XA1 is output The hit signal HIT ₁ output from the hit signal generator 50 ₁ becomes high. Since the row address XA1 from other defective word line address register ₃₆ 2 ~ 36 _N is not output, the hit signal _HIT 2 _{~HIT N} respectively output from the hit signal generation unit ₅₀ 2 to 50 _N are all at the low . Since the hit signal HIT ₁ is at high, defective word line address register 36 ₁ is identified as defective word line address register 36 which stores the defective word line information DWA including the row address XA1. Accordingly, the redundant word line RWL corresponding to the defective word line address register 36 ₁ is identified as a replacement destination of the redundancy word line RWL.

For the block data BA~BD output from defective word line address register 36 _1, since only the block data BB is 1, the other is 0, the intermediate block hit signal / HIT_A ₁ output from the hit signal generation unit 50 ₁ Of ~ / HIT_D ₁ , only the intermediate block hit signal / HIT_B ₁ is low and the others are high. The intermediate block hit signal _/ HIT_A 2 ~ _/ HIT_D _N output from the other hit signal generation unit ₅₀ 2 to 50 _N, the first place is the hit signal _HIT 2 _{~HIT N} because it is low, both high. Midblock hit signal _/ HIT_A 1 ~ _/ HIT_D _{result N} has a logic value of more, the block hit signal HIT_B becomes high, block hit signal HIT_A, HIT_C, HIT_D becomes low. That is, the block 20-1B is specified as a block to be replaced.

  The array control circuit 37 generates the above-described mat control signal MAC based on the redundant word line RWL and the block specified as described above and supplies them to the row decoder 21 of each block. Specifically, first, the mat control signal MAC indicating the redundant word line RWL specified as the replacement destination is generated and supplied to the block specified as the target of the replacement process. As a result, in the block specified as the target of replacement processing, replacement from the word line WL indicated by the row address XA supplied from the row address buffer 33 or the like to the redundant word line RWL specified as the replacement destination is executed. The Second, the array control circuit 37 generates a mat control signal MAC indicating the row address XA supplied from the row address buffer 33 or the like, and supplies it to other blocks. Thereby, the selection of the word line WL indicated by the row address XA supplied from the row address buffer 33 or the like is executed in a block other than the block specified as the replacement processing target.

  As described above, according to the semiconductor device 10 according to the present embodiment, in addition to the replacement-destination redundant word line RWL, the block to be replaced (the block to which the word line WL that is a defective word line belongs) is also specified. Is done. As a result, when one word line WL is relieved, it is not necessary to replace the redundant word line RWL with another word line WL having the same row address XA, so that one word line WL is relieved. The relief efficiency is improved as compared with the conventional semiconductor device using the redundant word lines RWL for the number of blocks.

In the above description, the case where only one of the four word lines WL indicated by the row address supplied from the row address buffer 33 to the array control circuit 37 is a defective word line WL is taken up. The semiconductor device 10 according to the present embodiment can cope with the case where a plurality of defective word lines WL. For example, when two word lines out of four word lines WL1 to which a common row address XA is assigned are defective word lines, two defective word line addresses corresponding to the block to which each defective word line belongs. The defective word line information DWA is stored in the register 36. At this time, the row address XA is common and the block data BA to BD are different. In this way, the two hit signals HIT _k corresponding to the block where the defective word line exists become high, and two blocks corresponding to the block where the defective word line exists among the block hit signals HIT_A to HIT_D. The hit signal becomes high, and the two defective word lines are replaced with the corresponding two redundant word lines RWL as described above. As a further alternative, the array control circuit 37, without using the block hit signal HIT_A～HIT_D, directly from the intermediate block hit signal _/ HIT_A 1 ~ _/ HIT_D _N, for each redundant word line RWL identified as the replacement destination, replacement processing You may specify the block used as object of. As a result, the block to be replaced is associated with the redundant word line RWL specified as the replacement destination, so that the array control circuit 37 indicates the redundant word line RWL for each specified redundant word line RWL. A mat control signal MAC is generated and supplied to the corresponding block. Since the replacement to the redundant word line RWL is executed in the plurality of blocks in this way, the array control circuit 37 performs an appropriate replacement process even when a plurality of defective word lines WL exist for one row address. It will be possible.

  FIG. 4 is a diagram showing an overall configuration of the semiconductor device 10 according to the second embodiment of the present invention. FIG. 5 is a diagram showing a part characteristic of the present invention extracted from each configuration of the semiconductor device 10 shown in FIG. FIG. 5 shows a configuration related to the bank 20-1, but the same applies to other banks.

  As shown in FIG. 5, the semiconductor device 10 according to the present embodiment is different from the semiconductor device 10 according to the first embodiment in that a redundant block 20-1R is provided in the bank 20-1. ing. The redundant block 20-1R is a block including at least one redundant word line RWL and not including a normal word line WL. In the present embodiment, redundant word lines RWL are aggregated into redundant blocks 20-1R, and each of blocks 20-1A to 20-1D does not include redundant word lines RWL. As shown in FIGS. 4 and 5, the semiconductor device 10 according to the present embodiment includes an IO line switch 38 for switching blocks between the banks 20-1 to 20-4 and the read / write amplifier 26. It is also different from the semiconductor device 10 according to the first embodiment in having it. Hereinafter, these differences will be mainly described in detail.

  On both sides of the redundant block 20-1R in the bit line direction (horizontal direction in the drawing), sense amplifier regions 22 are arranged in the same manner as the mats M0 and M1 of each block. A large number of sense amplifiers SA are arranged in the sense amplifier region 22, and each sense amplifier SA is connected to both complementary bit lines BL and / BL configured in a folded manner. Here, the sense amplifier SA arranged in the adjacent portion of the redundant block 20-1R and the block 20-1A is not shared between the adjacent blocks. This is to avoid competition of the sense amplifier SA. The sense amplifiers SA belonging to the block 20-1R are connected to a redundant IO line IO_R (redundant input / output line) via a column switch (not shown).

  A row decoder (XDEC) 21 is disposed at one end of the redundant block 20-1R in the word line direction. The row decoder 21 is configured to select the redundant word line RWL in the redundant block 20-1R according to the mat control signal MAC supplied from the array control circuit 37.

  One end of the IO line switch 38 is connected to the blocks 20-1A to 20-1D by the first IO lines IO_A to IO_D (first input / output lines) described in the first embodiment, respectively. The redundant block 20-1R is connected by the redundant IO line IO_R (redundant input / output line). On the other hand, the other end of the IO line switch 38 has second IO lines io_A to io_D (second input / output lines corresponding to the blocks 20-1A to 20-1D, respectively, and the second IO line ioL shown in FIG. 4). ) Is connected to the read / write amplifier 26. The IO line switch 38 sets each of the second IO lines io_A to io_D to one of the first IO lines IO_A to IO_D and the redundant IO line IO_R based on the IO switching signal IOCS supplied from the array control circuit 37. Has a function to connect. In a normal state (a state where the IO switching signal IOCS is not activated), the IO line switch 38 connects the second IO lines io_A to io_D to the first IO lines IO_A to IO_D, respectively. The detailed configuration of the IO line switch 38 will be described later.

  The array control circuit 37 according to the present embodiment is the same as the array control circuit 37 according to the first embodiment in that the redundant word line RWL to be replaced and the block to be replaced are specified, and FIG. The internal circuit shown in FIG. However, since the redundant word lines RWL are aggregated in the redundant block 20-1R in the present embodiment, the supply destination of the mat control signal MAC indicating the redundant word line RWL specified as the replacement destination is specified as the target of the replacement process. The row decoder 21 belongs to the redundant block 20-1R instead of the block. For blocks other than the block specified as the target of the replacement process, the mat control signal MAC indicating the row address XA supplied from the row address buffer 33 or the like is supplied as usual. Through these processes, replacement with the redundant word line RWL in the redundant block 20-1R is executed only for the block specified as the target of the replacement process.

  The array control circuit 37 further has a function of generating the above-described IO switching signal IOCS. The IO switching signal IOCS is a signal indicating a block specified as a target of replacement processing, and is activated only when replacement to the redundant word line RWL is executed. When the replacement to redundant word line RWL is not executed, it is inactivated. As the specific IO switching signal IOCS, the block hit signals HIT_A to HIT_D described above are preferably used as they are, but other methods may be used.

  FIG. 6 is a diagram showing an internal configuration of the IO line switch 38. This figure shows an example in which the IO switching signal IOCS is configured by block hit signals HIT_A to HIT_D.

  As shown in the figure, the IO line switch 38 includes a transfer gate 38a connected between the first IO line IO_A and the second IO line io_A, the first IO line IO_B, and the second IO line. transfer gate 38b connected between io_B, transfer gate 38c connected between first IO line IO_C and second IO line io_C, first IO line IO_D and second IO line Transfer gate 38d connected between io_D and transfer gates 38ar-38dr connected between redundant IO line IO_R and second IO lines io_A-io_D, respectively.

  The transfer gates 38a to 38d are configured to be conductive when a corresponding one of the block hit signals HIT_A to HIT_D is low, and to be disconnected otherwise. Therefore, the first IO line and the second IO line are connected to a block that is not subject to replacement with the redundant word line RWL.

  On the other hand, the transfer gates 38ar to 38dr are configured to be conductive when the corresponding one of the block hit signals HIT_A to HIT_D is high, and to be disconnected otherwise. Therefore, the second IO line and the redundant IO line IO_R are connected to the block that is to be replaced with the redundant word line RWL.

  As described above, the IO line switch 38 operates the eight transfer gates 38a to 38d and 38ar to 38dr to change the second IO line of the block to be replaced with the redundant word line RWL to the redundant IO line IO_R. Processing to change the connection. Accordingly, column access can be performed on the memory cells connected to the redundant word line WL.

  As described above, according to the semiconductor device 10 according to the present embodiment, the redundant word lines RWL can be concentrated in the redundant block 20-1R. And of course, even with the semiconductor device 10 according to the present embodiment, when one word line WL is relieved, it is not necessary to replace the redundant word line RWL with another word line WL having the same row address XA. Compared to a conventional semiconductor device that uses redundant word lines RWL as many as the number of blocks to repair one word line WL, the repair efficiency is improved.

  In the present embodiment, unlike the first embodiment, the number of word lines WL that can be replaced with the redundant word line RWL for one row access is limited to only one. This is because the redundant word lines RWL are aggregated into one redundant block 20-1R, and therefore, when replacing a plurality of word lines WL, the sense amplifiers SA compete in the redundant block 20-1R. Because.

  FIG. 7 is a diagram showing a system configuration example of a computer 70 according to the third embodiment of the present invention. As shown in the figure, the computer 70 includes a semiconductor device 10 and a multi-core processor 71. The semiconductor device 10 is the semiconductor device 10 described in the first or second embodiment, and is incorporated in the computer 70 as a so-called main memory in this embodiment.

  The multi-core processor 71 includes four cores 72-1 to 72-4, an input / output device (I / O) 73, an external storage device control block 74, an on-chip memory 75, and an internal bus 76. Configured. The four cores 72-1 to 72-4 are respectively associated with the banks 20-1 to 20-4 of the semiconductor device 10 and are independent of each other via the external storage device control block 74. Read or write.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the semiconductor device 10 having a four-block configuration is taken up, but the present invention can be applied regardless of the number of blocks. The same applies to the number of banks, and the present invention can be applied regardless of the number of banks.

  The present invention can also be applied to a semiconductor device that does not employ a block configuration. That is, by applying the present invention to a semiconductor device of a type in which a plurality of word lines are selected at one time by one row address (one row address is assigned to a plurality of word lines), The relief efficiency can be improved.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11, 12 Clock terminal 13 Clock enable terminal 14 Command terminal 15 Address terminal 16 Data input / output terminal 20-1-20-20 Bank 20-1A-20-1D Block 20-1R Redundant block 21 Row decoder 22 Sense amplifier region 25 column decoder 26 read-write amplifier 27 latch circuit 28 data input-output buffer 30 a command decoder 31 chip control circuit 32 a mode register 33 the row address buffer 34 column address buffer 35 the refresh address counter 36, 36 ₁ -36 _N defective word line address register 37 array control circuit 38 IO line switch 38a-38d, 38ar-38dr transfer gate 40 the clock generating circuit 50 ₁ -50 _N hit signal generator 51 block hit signal Generation unit 70 Computer 71 Multi-core processor 72-1 to 72-4 Core 73 Input / output device 74 External storage device control block 75 On-chip memory 76 Internal bus BL, / BL Bit line IOL, IO_A to IO_D First IO line IO_R Redundancy IO line ioL, io_A to io_D Second IO line WL Word line RWL Redundant word line

Claims (18)

A plurality of normal word lines including the first and second normal word lines and a redundant word line are selected so that the first and second normal word lines are selected at a time in response to address information. A configured memory cell array; and
A defect information storage circuit for storing defect information specifying the first normal word line in association with the redundant word line;
A control circuit for selecting the redundant word line corresponding to the defect information instead of the first normal word line and selecting the second normal word line in response to the supply of the address information; A semiconductor device comprising: A plurality of redundant word lines;
2. The semiconductor device according to claim 1, wherein the defect information storage circuit stores defect information for specifying one of the plurality of normal word lines for each redundant word line. The control circuit specifies one that specifies the first normal word line among the defect information for each redundant word line stored in the defect information storage circuit in response to the supply of the address information. The semiconductor device according to claim 2, wherein the redundant word line corresponding to the specified defect information is selected instead of the first normal word line. The memory cell array has a plurality of blocks each including a plurality of the normal word lines,
4. The semiconductor device according to claim 1, wherein the first and second normal word lines are included in the different blocks. 5. The semiconductor device according to claim 4, wherein each of the plurality of blocks includes a predetermined number of the redundant word lines. The semiconductor device according to claim 5, wherein the redundant word line corresponding to the defect information that specifies the first normal word line is included in the same block as the first normal word line. The semiconductor device according to claim 4, wherein the memory cell array further includes a redundant block including the redundant word line, and the plurality of blocks does not include the redundant word line. A memory cell array including a plurality of blocks each including a plurality of normal word lines and at least one redundant word line;
A row address provided corresponding to each of the at least one redundant word line, each assigned to a defective word line of the plurality of normal word lines, and a block address indicating the block to which the defective word line belongs. At least one defect information storage circuit for storing in association with each other;
In response to the supply of a row address, the defective information storage circuit storing the row address is specified to specify the redundant word line to be replaced, and the specified failure information storage circuit Identify the block to be replaced from the stored block address, select the redundant word line identified as the replacement destination for the block identified as the replacement target, and as the replacement target And a control circuit that selects the normal word line indicated by the supplied row address with respect to the blocks other than the identified block. The control circuit is provided corresponding to each of the at least one defect information storage circuit, and corresponds based on the supplied row address and the row address stored in the corresponding defect information storage circuit. Having at least one hit signal generation unit that generates a hit signal that is activated when the defect information storage circuit stores the supplied row address;
9. The control circuit specifies the defect information storage circuit storing the supplied row address based on the hit signal generated by each of the at least one hit signal generation unit. A semiconductor device according to 1. Each of the at least one hit signal generation unit is activated in response to the block address stored in the corresponding defect information storage circuit only when the generated hit signal is activated. Generate a signal,
10. The control circuit according to claim 8, wherein the control circuit specifies the block to be subjected to replacement processing based on the plurality of intermediate block hit signals respectively generated by the at least one hit signal generation unit. Semiconductor device. The control circuit further includes a block hit signal generation unit configured to generate a plurality of block hit signals corresponding to the plurality of blocks based on the plurality of intermediate block hit signals respectively generated by the at least one hit signal generation unit. Have
The semiconductor device according to claim 10, wherein the control circuit specifies the block to be subjected to replacement processing based on the plurality of block hit signals. The semiconductor device according to claim 10, wherein the control circuit specifies the block to be subjected to replacement processing for each redundant word line specified as a replacement destination. The semiconductor device according to claim 8, wherein each of the plurality of blocks includes a predetermined number of the redundant word lines. The semiconductor device according to claim 13, wherein the block address indicates the block to which the redundant word line corresponding to the defect information storage circuit storing the block address belongs. The control circuit selects the redundant word line by supplying a control signal indicating the redundant word line specified as a replacement destination to the block specified as a target of replacement processing. The semiconductor device according to 13 or 14. The memory cell array further includes a redundant block including the at least one redundant word line, and the plurality of blocks do not include the redundant word line. The semiconductor device described. The semiconductor device according to claim 16, wherein the control circuit selects the redundant word line by supplying a control signal indicating the redundant word line specified as a replacement destination to the redundant block. . Read / write amplifier,
A plurality of first input / output lines provided corresponding to each of the plurality of blocks and connected to the corresponding block;
A redundant input / output line connected to the redundant block;
A plurality of second input / output lines provided corresponding to each of the plurality of blocks and connected to the read / write amplifier;
An input / output line switch having one end connected to the plurality of first input / output lines and the redundant input / output line and the other end connected to the plurality of second input / output lines;
The input / output line switch connects the second input / output line corresponding to the block specified by the control circuit as a target of replacement processing to the redundant input / output line, and the other second input / output line. The semiconductor device according to claim 16, wherein the semiconductor device is connected to the corresponding first input / output line.

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