JP2014089315A - Display control unit and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit configuration for pre-drive in a display control unit that performs pre-drive before driving a display element according to display data.SOLUTION: Before display data is converted into a gradation voltage in a voltage output circuit and a drive terminal is driven, pre-drive data according to the degree of difference between current display data and previous display data is converted into a predetermined value of the gradation voltage in the voltage output circuit and the drive terminal is pre-driven. Since pre-drive data is converted into the predetermined value of the gradation voltage in the voltage output circuit and the drive terminal is pre-driven, no pre-drive voltage output circuit is required for generating and outputting a pre-drive voltage in addition to the voltage output circuit.

Description

  The present invention relates to a display control apparatus and a data processing apparatus using the display control apparatus, and relates to a technique effective when applied to, for example, a communication portable terminal equipped with a liquid crystal controller driver.

  The liquid crystal controller driver outputs a gradation voltage corresponding to display data to a signal line, for example, a source line, which is arranged to intersect the scanning line of the liquid crystal panel. As a technique for precharging the source line, there is a technique described in Patent Document 1. According to this, a precharge driver that precharges the source line from the other end side is employed separately from the source line driver that drives the source line from one end side according to the display data. The precharge driver compares the drive data of the source line, selects one precharge voltage from among four or more types of selection precharge voltages according to the comparison result, and precharges the source line. ing. Here, an attempt is made to cope with an increase in load on the source line accompanying an increase in resolution or display screen.

JP 2010-102146 A

  The present inventor has studied the influence of noise generated at the time of rising of the driving voltage accompanying the source line driving. For example, when a capacitive touch panel is placed over a liquid crystal panel, the detection accuracy may be lowered due to the influence of noise generated with the source line drive. Therefore, by pre-driving the source line before driving with display data, the noise peak value at the rise of each driving voltage can be suppressed and the influence of noise on peripheral circuits such as a touch panel can be reduced. The technique of Patent Document 1 can be applied in terms of pre-driving the source line.

  However, the technology of Patent Document 1 must provide a precharge driver that precharges the source line from the other end side, in addition to the source line driver, and also has a circuit for generating a precharge voltage different from the gradation voltage. Therefore, the overall circuit scale or chip occupation area of the liquid crystal controller driver becomes too large.

  An object of the present invention is to reduce a circuit configuration for pre-driving in a display control apparatus that performs pre-driving before driving a display element according to display data.

  The above and other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, before the display data is converted into gradation voltages by the voltage output circuit and the drive terminal is driven, pre-drive data corresponding to the degree of difference between the current display data and the previous display data is converted by the voltage output circuit. The drive terminal is pre-driven by converting to a predetermined value of the regulated voltage.

  According to this, the predrive data is converted into a predetermined value of the gradation voltage by the voltage output circuit and the drive terminal is predriven, so that the predrive voltage is generated and output separately from the voltage output circuit. No voltage output circuit is required.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the circuit configuration for predrive can be reduced in the display control apparatus that performs predrive before driving the display element according to the display data.

FIG. 1 is a block diagram illustrating the overall configuration of a communication portable terminal. FIG. 2 is a block diagram illustrating the configuration of the liquid crystal controller driver. FIG. 3 is a block diagram showing a first example of a signal electrode driving circuit. FIG. 4 is a characteristic diagram showing the relationship between the N-bit display data and the corresponding gradation voltage subjected to gamma correction. FIG. 5 is a waveform diagram showing the voltage waveform and current waveform of the signal electrode by pre-drive by the voltage output circuit. FIG. 6 is an explanatory diagram illustrating the relationship between predrive data selectable by the predrive selector and predrive selection data. FIG. 7 is a timing chart illustrating the signal electrode driving timing when pre-driving is performed. FIG. 8 is an explanatory diagram illustrating the voltage waveform of the signal electrode according to the pre-drive selection / non-selection state corresponding to the change between the MSB of the previous display data (previous data) and the MSB of the current display data (current data). . FIG. 9 is a block diagram showing a second example of the signal electrode drive circuit. FIG. 10 is an explanatory diagram exemplifying pre-drive data that can be selected when the value of display data is divided into 8 sections (DA1 to DA8) by the MSB side 3 bit value. FIG. 11 is a waveform diagram illustrating a pre-drive waveform according to the second example of the signal electrode drive circuit. FIG. 12 is a block diagram showing a third example of the signal electrode drive circuit. FIG. 13 is a waveform diagram when the driving voltage of the pre-drive is output in a plurality of stages.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Generation of drive voltage using pre-drive data smaller than full scale value before display data>
The display control device (4) according to the present invention outputs a plurality of drive terminals (Ps1 to Psm) connected to the signal electrodes of the display panel (2) and gradation voltages corresponding to display data to the drive terminals. And a signal electrode driver circuit (23). The signal electrode drive circuit includes necessary data (64, 64_1, 64_2) determined based on display data and a data output circuit (40, 40A, 40B) for outputting the display data (50), A voltage output circuit that outputs a gradation voltage using the data output from the data output circuit. The data output circuit determines whether to output predrive data to the voltage output circuit according to the difference between the current display data and the previous display data, and outputs predrive data according to the determination result. Outputs pre-drive data to the voltage output circuit before display data. The pre-drive data is a value smaller than the full scale value of the display data.

  According to this, the predrive data is converted into a predetermined value of the gradation voltage by the voltage output circuit and the drive terminal is predriven, so that the predrive voltage is generated and output separately from the voltage output circuit. No voltage output circuit is required. Therefore, the circuit configuration for pre-driving can be reduced in the display control device that performs pre-driving before driving the signal electrodes according to the display data.

[2] <Pre-drive when MSB value of current display data and previous display data do not match>
In item 1, the data output circuit (40) determines the difference between the current display data and the previous display data based on the value of each MSB. The data output circuit outputs predrive data having a value corresponding to the intermediate voltage of the full-scale voltage in the gradation voltage to the voltage output circuit when the MSB value does not match between the current display data and the previous display data ( FIG. 3).

  According to this, since the data output circuit has only to select whether or not to output the predrive data to the voltage output circuit according to the MSB match / mismatch determination result, the scale of the data output circuit itself is extremely small. can do.

[3] <Selector that designates the predrive data value as selectable>
In item 2, the data output circuit includes a selector (63) in which a value of the pre-drive data is designated to be selectable.

  According to this, since the full-scale intermediate voltage of the gradation voltage may not match the intermediate value of the full-scale value of the display data according to the gamma characteristics of the gradation, the pre-drive data value can be changed by register setting. Therefore, it becomes easy to set the pre-drive data for the intermediate voltage of the full scale of the gradation voltage.

[4] <Predrive data generation according to the MSB and its lower side single or plural bits according to the value>
In item 1, the data output circuit (40A) determines the difference between the current display data and the previous display data based on the value of each MSB and its lower or single or multiple bits. At this time, when the MSB and the value of the single or plural bits on the lower side of the MSB do not match between the current display data and the previous display data, the data output circuit pre-values the value according to the magnitude and direction of the difference. Drive data is output to the voltage output circuit (FIG. 9).

  According to this, since the number of bits used for determination of coincidence / non-coincidence is increased as compared with the case of the item 2 using only the MSB, the predrive data is generated in small increments based on the difference between the current display data and the previous display data. As a result, reduction of the noise can be promoted.

[5] <Pre-drive with multiple stages>
In any one of Items 1 to 4, when the data output circuit (40B) outputs predrive data according to the determination result, the voltage output circuit divides the predrive data into a plurality of times before the display data. Output to. The pre-drive data that is output in a plurality of times has a larger difference value than the previous display data as the data that is output in a plurality of times is output (FIG. 12).

  Thereby, since the drive voltage of the pre-drive is output in a plurality of stages, the noise reduction effect can be promoted although the circuit scale is slightly increased as compared with item 2.

[6] <Generation of drive voltage using pre-drive data smaller than full scale value before display data>
A data processing system (1) according to the present invention includes a microcomputer (7) that executes a program, a display control device (4) that performs display control of display data supplied from the microcomputer, and the display control device. A display device (2) that displays display data based on the output drive voltage, and a touch panel that includes a plurality of intersections formed by a plurality of drive electrodes and a plurality of detection electrodes, and is superimposed on the display control device (3) and a touch panel controller (5) that drives the drive electrode of the touch panel to detect a detection signal from the detection electrode. The display control device includes a plurality of drive terminals (Ps1 to Psm) connected to the signal electrodes of the display panel, and a signal electrode drive circuit (23) for outputting a gradation voltage corresponding to display data to the drive terminals. Prepare. The signal electrode driving circuit includes necessary data (64, 64_1, 64_2) determined based on display data and a data output circuit (430, 40A, 40B) for outputting the display data (50), And a voltage output circuit (41) for outputting a gradation voltage using the data output from the data output circuit. The data output circuit determines whether to output predrive data to the voltage output circuit according to the difference between the current display data and the previous display data, and outputs the predrive data according to the determination result First, pre-drive data is output to the voltage output circuit before display data. The pre-drive data is a value smaller than the full scale value of the display data.

  According to this, the predrive data is converted into a predetermined value of the gradation voltage by the voltage output circuit and the drive terminal is predriven, so that the predrive voltage is generated and output separately from the voltage output circuit. No voltage output circuit is required. Therefore, the circuit configuration for pre-driving can be reduced in the display control device that performs pre-driving before driving the signal electrodes according to the display data. This also contributes to miniaturization of the data processing system. Furthermore, noise generated when driving the signal electrode is mitigated by the pre-drive method of the signal electrode, so that touch detection by the touch panel can be performed with high accuracy.

[7] <Pre-drive when MSB value of current display data and previous display data do not match>
In item 6, the data output circuit (40) determines the difference between the current display data and the previous display data based on the value of each MSB. The data output circuit outputs predrive data having a value corresponding to the intermediate voltage of the full-scale voltage in the gradation voltage to the voltage output circuit when the MSB value does not match between the current display data and the previous display data ( FIG. 3).

  According to this, there exists an effect similar to item 2.

[8] <Selector that specifies pre-drive data value selectable>
In item 7, the data output circuit includes a selector for designating a value of the predrive data.

  According to this, there exists an effect similar to claim | item 3.

[9] <Generation of predrive data according to MSB and its lower-side single or plural bits according to the value>
In item 6, the data output circuit (40A) determines the difference between the current display data and the previous display data based on the value of each MSB and its single or plural bits. The data output circuit outputs pre-drive data having a value corresponding to the magnitude and direction of the difference between the current display data and the previous display data when the MSB and the value of one or more bits on the lower side do not match. The voltage is output to the voltage output circuit (FIG. 9).

  According to this, there exists an effect similar to item 4.

[10] <Pre-drive with multiple stages>
The data output circuit (40B) according to any one of claims 6 to 9, wherein the data output circuit (40B) divides the predrive data into a plurality of times before the display data when outputting the predrive data according to the determination result. Output to the circuit. The predrive data that is output in a plurality of times has a larger difference value from the previous display data as the data that is output in the plurality of times is output (FIG. 12).

  According to this, there exists an effect similar to item 5.

[11] <Mobile communication terminal>
11. The data processing system according to claim 6, further comprising a high-frequency interface that performs high-frequency wireless communication under the control of the microcomputer, and is configured as a portable communication terminal (1).

2. Details of Embodiments Embodiments will be further described in detail.

≪Data processing system≫
FIG. 1 illustrates the overall configuration of a communication portable terminal. The communication portable terminal shown in the figure is a mobile phone or a smartphone, and is an example of a data processing system.

  The communication portable terminal 1 includes a liquid crystal panel (DP) 2 as a display device, a touch panel (TP) 3 as an input device, a liquid crystal controller driver (DPC) 4, and a touch panel controller (TPC) 5. The touch panel 3 is, for example, a mutual capacitive touch panel that enables multi-touch detection, and includes a plurality of intersections formed by a plurality of drive electrodes and a plurality of detection electrodes. The touch panel controller 5 sequentially supplies drive pulses to the drive electrodes, and thereby obtains detection data corresponding to changes in the capacitive coupling state at each intersection based on signals sequentially obtained from the detection electrodes.

  A sub processor (SMPU) 6 that is a microprocessor for the sub system controls the driving of the touch panel 3. In addition, the sub processor 6 performs a digital filter operation on the detection data acquired by the touch panel controller 5, and calculates the position coordinates of the intersection where the capacity variation has occurred based on the data from which the noise has been removed. In short, in order to indicate at which position of the intersection the stray capacitance has changed, that is, at which position of the intersection the finger has approached, the position coordinates when the contact event occurs are calculated.

  The touch panel 3 is configured using a transmissive (translucent) electrode or a dielectric film, and is disposed, for example, on the display surface of the liquid crystal panel 2.

  The host processor (HMPU) 7 generates display data, and the liquid crystal controller driver 4 performs display control for displaying the display data received from the host processor 7 on the liquid crystal panel 2. The host processor 7 obtains the position coordinate data when the contact event occurs from the sub-processor 6, and operates the touch panel 3 based on the relationship between the position coordinate data and the display image displayed on the liquid crystal controller driver 4. Or analyze the input.

  The host processor 7 is connected to a high-frequency communication interface 8, an image processing unit 9, an audio interface 10 connected to a microphone or a speaker, a memory 11, and the like. The host processor 7 realizes a control function as a communication portable terminal by performing application processing such as display control and input control along with baseband processing of high-frequency communication.

  Although not particularly limited, the liquid crystal panel 2 is a dot matrix type panel in which a large number of display pixels are arranged in a matrix. In the liquid crystal panel 2, scanning electrodes (gate lines) and signal electrodes (source lines) are arranged in a matrix, and a TFT (Thin Film Transistor) switch is formed at the intersection. A scanning electrode is connected to the gate of the TFT switch, and a signal electrode is connected to the drain. A liquid crystal pixel electrode of a liquid crystal capacitor serving as a subpixel is connected to the source side of the TFT switch, and an electrode on the opposite side of the liquid crystal capacitor is a common electrode. A signal voltage output from the liquid crystal controller driver 4 is supplied to the signal electrode. The gate electrode is driven by applying a scanning pulse from the liquid crystal controller driver 4 in the arrangement order, for example. For supplying the signal voltage to the signal electrode, a pre-drive method corresponding to the display data is adopted for each horizontal scanning period.

  The liquid crystal controller driver 4 is an example of a display control device, and is a host that has no correlation with the video display mode for displaying the display data supplied together with the display timing on the liquid crystal panel 2, such as a one-segment TV or videophone image, and the display timing. A command display mode for displaying data written from the processor 7 or the like on the liquid crystal panel 2 is provided as a display mode.

  The audio interface 10, the host processor 7, the image processing unit 9, the memory 11, the high-frequency communication interface 8, and the sub-processor can be configured as a system-on-chip single-chip semiconductor device or as a multi-chip semiconductor device. is there.

  Hereinafter, a signal electrode pre-drive method by the liquid crystal controller driver 4 will be described in detail.

≪LCD controller driver≫
FIG. 2 illustrates the configuration of the liquid crystal controller driver 4. Here, the liquid crystal controller driver 4 drives the dot matrix type liquid crystal display panel 2. The liquid crystal controller driver 4 has a frame buffer memory 21 for storing display data to be displayed on a dot matrix type liquid crystal display panel by a bitmap method. The frame buffer memory 21 is constituted by a RAM, for example, a synchronous DRAM.

  The liquid crystal controller driver 4 includes a command register 24 and a sequencer 25 as a control unit for controlling the inside based on a command from the external host processor 7. Also, a pulse generator (CPG) 27 that generates a reference clock pulse based on an external oscillation signal or an oscillation signal from a vibrator connected to an external terminal, and various circuit operations inside the chip based on this clock pulse. A timing generation circuit 28 that generates a timing signal for providing timing is provided. The host processor 7 is connected to the system interface 20 via the system bus SBUS. The system interface 20 receives instruction data (command data) and other control data from the host processor 7. Further, the system interface 20 can receive data such as display data (asynchronous display data) without a display timing signal, and can cope with the command display mode. Although not shown, an external display interface for receiving synchronous display data accompanied by a display timing signal, for example, broadcast data accompanied by a horizontal synchronizing signal and a vertical synchronizing signal, etc. can be provided to cope with a video display mode.

  Asynchronous display data is input to the system interface 20 in units such as words or long words, and written to the frame buffer memory 21. An address counter 26 generates a write address to the frame buffer memory 21 in accordance with an instruction from the sequencer 25. Although not shown in particular, the synchronous display data supplied to the external display interface can also be written into the frame buffer memory 21.

  The display data written in the frame memory 21 is read to the latch circuit 22 in units of display lines, and the display data latched in the latch circuit 22 is given to the signal electrode drive circuit 23 in synchronization with the display timing. The signal electrode drive circuit 23 selects the gradation voltage generated by the gradation voltage generation circuit 31 according to the value of the input display data, and applies to the signal electrode terminals Ps1 to Psm connected to the signal electrodes of the liquid crystal panel 2. Signal voltages S1 to Sm are output. The selection of the gradation voltage and the output operation of the signal voltage employ a pre-drive method that will be described in detail later. The selected gradation voltage is corrected by a γ adjustment circuit (not shown) for correcting the γ characteristic of the liquid crystal panel.

  The scan electrode drive circuit 30 scans and drives the scan electrode terminals Pg1 to Pgi connected to the scan electrodes of the liquid crystal panel 2 by sequentially applying the scan voltages G1 to Gi generated by the liquid crystal drive level generation circuit 29. The liquid crystal drive level generation circuit 29 generates a drive level based on the plurality of power supply voltages PWR.

  Although not particularly limited, the sequencer 25 is configured by a storage circuit that stores a large number of control information for controlling the operation of the liquid crystal controller driver 4. The command register 24 is a register in which index information for referring to control information from the sequencer 25 is written, and the control information is read from the sequencer 25 based on the index information set in the command register 24 by the host processor 7. Index information is positioned as mode data or command data. The control information referred to by the index information is an initial value set in the address counter 26, a selection signal to the signal electrode drive circuit 23, a start enable signal to the timing generation circuit 35, and the like. The timing generation circuit 28 supplies internal control signals necessary for display control and the like to each part of the liquid crystal controller driver 4 in accordance with a given start enable signal.

  Accordingly, the liquid crystal controller driver 4 performs a drawing process of sequentially writing display data to the frame buffer memory 21 based on a command and data from the host processor 7 or the like via the system interface 20, and the frame buffer memory 21. The display data can be read out periodically to output a signal voltage to the signal electrodes of the liquid crystal panel 2 and sequentially output the scanning voltages to the scanning electrodes. Further, the liquid crystal controller driver 4 can output a signal voltage and a scanning voltage for displaying the display data supplied together with the display synchronization signal via the external display interface (not shown) on the liquid crystal panel 2 in real time. . In these operations, the signal electrode drive circuit 23 can drive the signal electrodes of the liquid crystal panel 2 by a pre-drive method. Hereinafter, the signal electrode drive circuit 23 will be described in detail.

≪First example of signal electrode driving circuit≫
FIG. 3 shows a first example of the signal electrode drive circuit 23. In the figure, a configuration of connection to one signal electrode terminal Psi corresponding to one signal electrode is representatively shown. The configuration typically shown in the figure is provided for each signal electrode, that is, for each signal drive terminal. The signal electrode drive circuit 23 outputs the necessary predrive data 64 determined based on the display data 50 for each signal electrode terminal, the data output circuit 40 that outputs the display data 50, and the data output circuit 40. And a voltage output circuit 41 that outputs a gradation voltage using the obtained data. In addition to FIG. 3, the display data 50 is N-bit pixel data corresponding to the signal electrode, and the pre-drive data is also N-bit pre-drive pixel data corresponding thereto.

  The data output circuit 40 is a low voltage operation area (LVA) circuit that is operated with a relatively low power supply voltage (for example, 1.5 V) of a logic circuit. The voltage output circuit 41 is composed of a circuit in a high voltage operation area that is operated at a relatively high power supply voltage (for example, 5 V) for driving the outside.

  The voltage output circuit 41 includes a level shifter 42, a decoder 43, and a plurality of output buffers 44. The level shifter 42 shifts the N-bit display data 50 and the necessary N-bit pre-drive data 64 output from the data output circuit 40 in the low voltage operation area to a voltage level suitable for the operation in the high voltage operation area. The decoder 43 decodes N-bit input data from the level shifter 42, and selects and outputs one gradation voltage from among M kinds of gradation voltages according to the decoding result. The output buffer 44 is constituted by a voltage follower amplifier using an operational amplifier, and outputs the gradation voltage selected by the decoder 43.

  The data output circuit 40 determines whether or not to output the predrive data 64 to the voltage output circuit 41 according to the difference between the current display data and the previous display data, and outputs the predrive data 64 according to the determination result. In this case, the predrive data 64 is output to the voltage output circuit 41 before the display data 50, and the predrive data 64 is set to a value smaller than the full scale value of the display data 50.

  Here, as a specific example, the data output circuit 40 includes an MSB latch circuit 60, an MSB comparison circuit 61, an AND gate 62, a predrive selector 63, and a data selector 65.

  The MSAB latch circuit 60 functions as a delay circuit that delays by one cycle by latching the MSB (most significant bit) value of display data until the next horizontal scanning cycle.

  The MSB comparison circuit 61 compares the MSB (most significant bit) value of the current (current) display data with the MSB value of the previous display data one scan cycle before. A low level is output when there is a match, and a high level is output when there is a mismatch.

  The AND gate 62 takes a logical product of the predrive enable signal 52 and the output of the MSB comparison circuit 61. The predrive enable signal 52 is a signal that is set to the high level in the first half (predrive cycle) of each horizontal scanning cycle. Therefore, if the comparison result of the MSB comparison circuit 61 does not match in the pre-drive cycle, the output (select signal) 66 of the AND gate 62 is high level (pre-drive instruction), and if the comparison result of the MSB comparison circuit 61 matches, the AND The output (selection signal 66) of the gate 62 is set to the low level (pre-drive non-instruction). Here, as is apparent from FIG. 4 showing the relationship between the N-bit display data and the corresponding gradation voltage subjected to gamma correction, if the MSB value of the N-bit display data is a logical value 0, it corresponds to that. The gradation voltage that can be taken by the display data to be displayed is in the range of voltage VA to voltage VB. If the MSB value of the N-bit display data is a logical value 1, the gradation voltage that can be taken by the corresponding display data is in the range of voltage VC to voltage VD. Therefore, if the MSB values of the previous display data and the current display data coincide with each other, the charging voltage difference up to the expected voltage level with respect to the signal electrode is at most the range of voltage VA to VB or the range of voltage VC to VD. If the MSB values of the previous display data and the current display data do not match, the charging voltage difference up to the expected value voltage level with respect to the signal electrode is in the range of voltages VA to VD at the maximum. Paying attention to this difference, pre-drive is not performed if the MSBs of the display data match, and pre-drive is performed if they do not match.

  The data selector 65 selects the display data 50 when the selection signal 66 is at a low level, and selects the pre-drive data 64 when the selection signal 66 is at a high level. Accordingly, when the selection signal 66 is set to a high level in the pre-drive cycle during the current horizontal scanning period, pre-drive data is output first, and then display data is output. As a result, as illustrated in FIG. 5, the voltage output circuit 41 pre-drives and precharges the corresponding signal electrode, and then is driven to a gradation voltage corresponding to display data, that is, an expected value voltage level. When the selection signal 66 is at a low level in the pre-drive cycle, pre-drive is not performed, and display data is used for driving the signal electrode over the horizontal scanning period. This is because the MSB value is the same as the previous value, and the charging voltage until reaching the expected value voltage level is less than about half of the full case voltage.

  The predrive data 64 is output from the predrive data selector 63. As can be seen from FIG. 4, the pre-drive data 63 may be, for example, the full-scale median value of the display data 50, but the median value is not necessarily the full-scale median voltage value of the gradation voltage depending on the gamma value of the image. May not match. Therefore, the predrive selector 63 can select one data from the predrive data PDD1, PDD2, PDD3, and PDD4 by the 2-bit selection data 51 as exemplified in FIG. The selection data 51 is set so that the host processor 7 can rewrite a control register (not shown). Therefore, the data output circuit 40 determines the difference between the current display data and the previous display data regardless of the gamma characteristic based on the value of each MSB, and the data output circuit 40 determines the difference between the current display data and the previous display data. When the MSB values do not match, the pre-drive data 64 having a value corresponding to the intermediate voltage of the full-scale voltage in the gradation voltage can be output to the voltage output circuit 41.

  FIG. 7 illustrates signal electrode drive timings when performing pre-drive. The display data 50 input to the data output circuit 40 is changed from m “0xxxxxxxx” to “1xxxxxxxx” at time t0. Since the MSBs of the signals before and after this time are changed from “0” to “1”, the predrive voltage selection signal “00” is selected during the period t1 to t2 when the predrive enable signal 52 is set to the high level. The pre-drive data “PDD1” is output from the data output circuit 40. Therefore, the output waveform of the signal drive electrode Psi is a voltage corresponding to “0xxxxxxxx” before time t1, and is precharged to a predrive voltage corresponding to the predrive data “PDD1” during the period from time t1 to t2. Thereafter, after time t2, the battery is charged up to an expected value voltage corresponding to the current display data “1xxx”.

  FIG. 8 shows the voltage waveform of the signal electrode (signal driving terminal) according to the pre-drive selection / non-selection state corresponding to the change between the MSB of the previous display data (previous data) and the MSB of the current display data (current data). Illustrated. In A, since the previous data MSB and the current data MSB are inconsistent, pre-drive is performed, the signal electrode is first precharged, and then the signal electrode is driven by the current data. In B, since the current data MSB does not coincide with the previous data MSB, pre-drive is performed and the signal electrode is discharged first, and then the signal electrode is driven by the current data. In C, since the current data MSB is the same as the previous data MSB, the pre-drive is not performed, and the signal electrode is driven by the current data from the beginning. In D, since the current data MSB does not match the previous data MSB, the signal electrode is precharged first by pre-drive, and then the signal electrode is driven by the current data. In E, since the current data MSB is the same as the previous data MSB, the pre-drive is not performed, and the signal electrode is driven and discharged by the current data from the beginning.

  According to the first example of the signal electrode drive circuit, the following effects are obtained.

  (1) Since the pre-drive data is converted into a predetermined value of the gradation voltage by the voltage output circuit 41 and the drive terminal Psi is pre-driven, a pre-drive voltage is generated and output separately from the voltage output circuit 41. No drive voltage output circuit is required. Therefore, the circuit configuration for predrive can be reduced in the liquid crystal controller driver 2 that performs predrive before driving the signal electrodes in accordance with the display data. This also contributes to the miniaturization of the communication portable terminal 1.

  (2) Furthermore, noise generated when the signal electrode Si is driven is mitigated by the signal electrode pre-drive method, so that touch detection by the touch panel can be performed with high accuracy.

  (3) Since the data output circuit has only to select whether or not to output the pre-drive data to the voltage output circuit 41 according to the MSB match / mismatch determination result, the scale of the data output circuit 40 itself is extremely small. can do.

  (4) Since the full scale intermediate voltage of the gradation voltage may not match the intermediate value of the full scale value of the display data according to the gamma characteristics of the gradation, the predrive data value is set by the predrive data selector 63. Since it can be specified variably, it becomes easy to set pre-drive data for the intermediate voltage of the full-scale gradation voltage.

≪Second example of signal electrode drive circuit≫
FIG. 9 shows a second example of the signal electrode drive circuit 23. The difference from FIG. 3 is the configuration of the data output circuit. The data output circuit 40A in FIG. 9 determines the difference between the current display data and the previous display data based on the value of each MSB and its lower or single or multiple bits. At this time, when the MSB and the value of the single or plural bits on the lower side of the MSB do not match between the current display data and the previous display data, the data output circuit pre-values the value according to the magnitude and direction of the difference. Drive data is output to the voltage output circuit 41.

  Here, for example, the necessity of pre-drive is determined using the upper 3 bits of the display data 50. Instead of the MSB latch circuit 60, an upper 3-bit latch circuit 70 is employed. The bit operation circuit 71 calculates the difference between the MSB side 3 bits value of the previous display data one scan cycle before the MSB side 3 bits value of the present (current) display data and sets the sign of the difference. get. If there is no difference, the input data 50 is selected by the data selector 65 through the AND gate 62 as in FIG. 3 even during the predrive enable period by the predrive enable signal.

  If there is a difference, the bit operation circuit 71 selects the predrive data 64A from the predrive data selector 73 based on the calculated difference, the sign of the difference, and the current display data, and supplies the predrive data 64A to the data selector 65. Thus, predrive data 64A is supplied to the voltage output circuit 41 during the predrive enable period.

  The generation logic of the predrive data selection signal by the bit arithmetic circuit 71 will be described. As illustrated in FIG. 10, the value of display data can be divided into 8 sections (DA1 to DA8) by the MSB side 3 bit value. At this time, as selectable predrive data, for example, PDD1 to PDD6 illustrated in FIG. 10 are considered. In this case, the basic logic is selection logic for selecting one pre-drive data located in the middle of the difference between the previous MSB side 3 bit value and the previous MSB side 3 bit value in consideration of the magnitude and direction of the difference. To do.

  For example, when the previous value and the current value of the display data are adjacent sections, for example, in the case of DA0 and DA1, the predrive data PDD0 intermediate between them is selected. When the number of sections interposed between the previous value and the current value of the display data is an odd number, for example, in the case of DA1 and DA3, when the sign of the difference is negative, the boundary of the lower section Pre-drive data PDD1 is selected, and when the sign of the difference is positive, pre-drive data PDD2 at the boundary with the upper section is selected. When the number of divisions interposed between the previous value and the current value of the display data is an even number, for example, in the case of DA1 and DA4, intermediate predrive data regardless of whether the sign of the difference is negative or positive Select PDD2.

  Since other configurations are the same as those in FIG. 3, a detailed description thereof will be omitted.

  According to the second example of the signal electrode driving circuit, as illustrated in FIG. 11, the predrive can be performed more finely than in the first example of FIG. In short, predrive data can be generated in small increments based on the difference between the current and previous display data, and as a result, noise reduction can be promoted. Others are the same as the first example.

≪Third example of signal electrode drive circuit≫
FIG. 12 shows a third example of the signal electrode drive circuit 23. The difference from FIG. 3 is the configuration of the data output circuit. When outputting pre-drive data, the data output circuit 40B of FIG. 12 outputs the pre-drive data to the voltage output circuit 41 in a plurality of times before the display data. The pre-drive data that is output in a plurality of times has a larger difference value than the previous display data as the data that is output in a plurality of times is output. Specifically, two predrive enable signals 52_1 and 52_2 that do not overlap in the enable period are supplied, and AND gates 62_1 and 62_2 for receiving each are separately provided, and predrive selection signals 66_1 and 66_2 are respectively generated. The The data selector 65A selects and outputs predrive data supplied to the input terminal Y according to the selection level of the predrive selection signal 66_1, and selects predrive data supplied to the input terminal X according to the selection level of the predrive selection signal 66_2. And output. When both the predrive selection signals 66_1 and 66_2 are not selected, the data selector 65A selects and outputs the display data 50. Although not particularly limited, the MSB comparison circuit 61A determines whether the pre-drive based on the current display data is precharged or discharged with respect to the previous display data based on the sign 68 of the difference between the two. In response to negative, the selector 69 selects the output of the pre-drive data selectors 63_1 and 63_2 supplied to the input terminals Y and X. For example, when the sign 68 is positive (when predrive becomes precharge), the selector 69 supplies the output of the predrive selector 63_1 to the input terminal Y and the output of the predrive data selector 63_2 to the input terminal X. Conversely, when the sign 68 is negative (when predrive is discharged), the selector 69 supplies the output of the predrive selector 63_1 to the input terminal X and the output of the predrive selector 63_2 to the input terminal Y. The value of the predrive data output from the predrive data selector 63_1 needs to be smaller than the value of the predrive data output from the predrive data selector 63_2. If this relationship is maintained, the value of the predrive data output from the predrive data selectors 63_1 and 63_2 can be variably selected as in the case of FIG.

  As illustrated in the waveform diagram of FIG. 13, the drive voltage of the predrive can be output in a plurality of stages.

  This third example is applicable to the second example. Also, the number of pre-drives can be three or more.

  According to the third example, the pre-drive driving voltage is output in a plurality of stages, so that the noise reduction effect can be promoted although the circuit scale is slightly increased as compared with the first example. Others are the same as the first example.

  It goes without saying that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, the external display interface that inputs display data together with the synchronization signal is not limited to the RGB interface, and may be a YUV interface, other serial graphic interfaces, or the like. The present invention is not limited to the case where the present invention is applied to a communication portable terminal such as a mobile phone or a smart phone, and can be widely applied to data processing systems such as relatively large data processing pads and personal computers. Further, the display control device of the present invention can be applied to a system other than a data processing system provided with a touch panel. This is because the influence of noise on other circuits around the display control device can be mitigated and can contribute to the miniaturization of other systems.

1 Communication portable terminal 2 Liquid crystal panel (DP)
3 Touch panel (TP)
4 LCD controller driver (DPC)
5 Touch panel controller (TPC)
6 Subprocessor (SMPU)
7 Host processor (HMPU)
8 High Frequency Communication Interface 20 System Interface 21 Frame Buffer Memory 24 Command Register 25 Sequencer 27 Pulse Generator (CPG)
28 Timing generation circuit 26 Address counter 23 Signal electrode drive circuit 31 Grayscale voltage generation circuit Ps1-Psm Signal electrode terminal S1-Sm Signal voltage Pg1-Pgi Scan electrode terminal G1-Gi Scan voltage Psi Signal electrode terminal 40 Data output circuit 40A Data Output circuit 40B Data output circuit 41 Voltage output circuit 42 Level shifter 43 Decoder 44 Output buffer 50 Display data 52 Predrive enable signal 52_1, 52_2 Predrive enable signal 60 MSB latch circuit 61 MSB comparison circuit 62 And gate 62_1, 62_2 And gate 63 Pre Drive selector 64 Pre-drive data 64A Pre-drive data 65 Data selector 65A Data selector 66 Selection signal PDD1, PDD2, PDD3 PDD4 Predrive data 66_1, 66_2 Predrive selection signal 68 Symbol 69 Selector 71 Bit operation circuit

Claims (11)

A display control device comprising a plurality of drive terminals connected to signal electrodes of a display panel, and a signal electrode drive circuit for outputting gradation voltages corresponding to display data to the drive terminals,
The signal electrode driving circuit outputs necessary gradation voltage based on display data, a data output circuit for outputting the display data, and a gradation voltage using the data output from the data output circuit. A voltage output circuit,
The data output circuit determines whether to output predrive data to the voltage output circuit according to the difference between the current display data and the previous display data, and outputs predrive data according to the determination result. Outputs pre-drive data to the voltage output circuit before the display data,
The display control device, wherein the predrive data is a value smaller than a full scale value of display data.   2. The data output circuit according to claim 1, wherein the data output circuit determines a difference between the current display data and the previous display data based on the value of each MSB, and the MSB value does not match between the current display data and the previous display data. In this case, the display control device outputs predrive data having a value corresponding to an intermediate voltage of the full-scale voltage in the gradation voltage to the voltage output circuit.   3. The display control device according to claim 2, wherein the data output circuit includes a selector that is designated so that a value of the pre-drive data can be selected.   2. The data output circuit according to claim 1, wherein the data output circuit determines a difference between the current display data and the previous display data based on each MSB and a value of one or more bits on the lower side thereof, and the current and previous display data. A display control device that outputs predrive data having a value corresponding to the magnitude and direction of the difference to the voltage output circuit when the MSB and the value of one or more bits on the lower side do not match. 5. The data output circuit according to claim 1, wherein the data output circuit outputs the predrive data to the voltage output circuit in a plurality of times before the display data when outputting the predrive data based on the determination result. And
The pre-drive data that is output in a plurality of times is a display control device that has a larger difference value than the previous display data as the data that is output in a plurality of times is output. A microcomputer that executes a program; a display control device that performs display control of display data supplied from the microcomputer; a display device that displays display data based on a drive voltage output from the display control device; Touch panel provided with a plurality of intersections formed by a plurality of drive electrodes and a plurality of detection electrodes, and arranged to overlap the display control device, and a touch panel for driving the drive electrodes of the touch panel and detecting detection signals from the detection electrodes A data processing system having a controller,
The display control device includes a plurality of drive terminals connected to signal electrodes of a display panel, and a signal electrode drive circuit that outputs gradation voltages corresponding to display data to the drive terminals,
The signal electrode driving circuit outputs necessary gradation voltage based on display data, a data output circuit for outputting the display data, and a gradation voltage using the data output from the data output circuit. A voltage output circuit,
The data output circuit determines whether to output predrive data to the voltage output circuit according to the difference between the current display data and the previous display data, and outputs the predrive data according to the determination result The pre-drive data is output to the voltage output circuit before the display data,
The data processing system, wherein the predrive data is a value smaller than a full scale value of display data.   7. The data output circuit according to claim 6, wherein the data output circuit determines the difference between the current display data and the previous display data based on the value of each MSB, and the MSB value does not match between the current display data and the previous display data. In this case, the data processing system outputs predrive data having a value corresponding to an intermediate voltage of the full-scale voltage in the gradation voltage to the voltage output circuit.   8. The data processing system according to claim 7, wherein the data output circuit includes a selector that specifies the value of the pre-drive data to be selectable.   7. The data output circuit according to claim 6, wherein the data output circuit determines a difference between the present display data and the previous display data based on a value of each MSB and a single or plural bits on the lower side thereof, and A data processing system that outputs predrive data having a value corresponding to the magnitude and direction of the difference to the voltage output circuit when the MSB and the value of one or more bits on the lower side do not match between data . 10. The data output circuit according to claim 6, wherein the data output circuit outputs the predrive data to the voltage output circuit in a plurality of times before the display data when outputting the predrive data based on the determination result. And
In the data processing system, the pre-drive data that is output in a plurality of times has a larger difference value than the previous display data as the data that is output in the plurality of times is output.   11. The data processing system according to claim 6, further comprising a high-frequency interface that performs high-frequency wireless communication under the control of the microcomputer, and is configured as a mobile communication terminal.

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