JP2014086686A - Semiconductor element mounting substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor element having a terminal portion having good bonding characteristics and low cost and high mass productivity.
A terminal portion for performing wire bonding with a bonding wire containing Cu as a main component is provided, and an NiP alloy plating layer, a Ni plating layer, and a Pd plating are sequentially provided at an end portion of the terminal portion from the terminal portion side. A plating layer having a layer or a Pd alloy plating layer and a noble metal plating layer including at least one Au plating layer, an Ag plating layer, an Au alloy plating layer, an Ag alloy plating layer, or an AuAg alloy plating layer is formed.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor element mounting substrate provided with terminals for wire bonding using a bonding wire containing Cu as a main component.

  2. Description of the Related Art Conventionally, a method as shown in FIG. 2 is known as a method for manufacturing a semiconductor device. Specifically, first, a plating layer 3 having etching resistance is formed in a desired pattern on both surfaces of a metal plate 1 made of a Cu alloy material or the like, and a resist mask 2 having etching resistance is formed on one surface. Then, a part (upper half) of the terminal portion 1a is formed by performing half etching processing, and the metal plate 1 is used as a semiconductor element mounting substrate (see FIGS. 2A and 2B). Next, the semiconductor element 4 is mounted at a predetermined position on the surface subjected to the half etching process, and the electrode of the semiconductor element 4 and the terminal portion 1a are wire-bonded using the bonding wire 5 (FIG. 2 ( C)). Next, the half-etched surface is sealed with a sealing resin 6 (see FIG. 2D). Finally, after removing the resist mask 2 from the surface opposite to the half-etched surface, the remaining portion (lower half) of the terminal portion 1a is removed by etching the surface. The method of forming and making it independent (refer FIG.2 (E)) is known (refer patent document 1, 2).

  Further, in the semiconductor element mounting substrate, an Ni plating layer for preventing Cu in the Cu alloy material from diffusing into the wire bonding portion in order from the terminal portion side to the end portion of the terminal portion; It is known to form a plating layer having a three-layer structure including a Pd plating layer and an Au plating layer, which are noble metal layers for preventing oxidation of the Ni plating layer (see Patent Document 3). This is because the plating layer thus configured has good wire bonding properties with Au wires and solderability with Pb—Sn solder or Pb free solder.

JP 2001-24135 A JP 2007-48978 A JP 2000-77593 A

  By the way, in recent years, consumption of Au wires has increased due to higher density and higher functionality of semiconductor devices, and since the price of Au has also increased in the market, the cost of Au wires in the cost of semiconductor devices has increased. The proportion has increased. Therefore, it has been considered to replace an expensive Au wire with an inexpensive Cu wire.

  However, since the noble metal layer of the plating layer formed on the terminal portion of the semiconductor element mounting substrate as described in Patent Documents 1 and 2 is mainly intended to prevent oxidation of the Ni layer, its thickness is 0. It is formed to be as thin as about 0.003 to 0.4 μm. Moreover, the plating layer as described in Patent Document 3 is formed assuming bonding with an Au wire, and is not formed assuming bonding with a Cu wire. Therefore, when trying to wire-bond Cu wires with different characteristics, for example, hardness, from conventional Au wires to conventional plating layers, it is difficult to perform good bonding and mass productivity cannot be improved. was there.

  Specifically, when Cu wire is used, the connection strength between the Cu wire and the wire bonding portion is likely to be reduced, and productivity is reduced as compared with the case where Au wire is used. There was a problem that the merit due to the price difference disappeared.

  The present invention has been made in view of such problems of the prior art, and an object of the present invention is to mount a semiconductor element having a terminal portion having good bonding characteristics and low cost and high mass productivity. It is to provide a substrate.

  In order to achieve the above object, a substrate for mounting a semiconductor element of the present invention includes a terminal portion that performs wire bonding with a bonding wire containing Cu as a main component, and the end of the terminal portion is connected to the terminal portion side. In order, NiP alloy plating layer, Ni plating layer, Pd plating layer or Pd alloy plating layer, Au plating layer, Ag plating layer, Au alloy plating layer, Ag alloy plating layer or AuAg alloy plating layer A plating layer having a noble metal plating layer is formed.

  In the semiconductor element mounting substrate of the present invention, it is preferable that a NiP alloy plating layer is formed between the Ni plating layer and the Pd plating layer or the Pd alloy plating layer.

  In the semiconductor element mounting substrate of the present invention, the noble metal plating layer includes, in order from the terminal portion side, the Au plating layer or the Au alloy plating layer, and the Ag plating layer or the Ag alloy plating layer. It is preferable to become.

  In the semiconductor element mounting substrate of the present invention, the noble metal plating layer includes, in order from the terminal portion side, the Ag plating layer or the Ag alloy plating layer, the Au plating layer, or the Au alloy plating layer. It is preferable to become.

  In the semiconductor element mounting substrate of the present invention, a plating layer having the same configuration as the plating layer may be formed at an end portion of the terminal portion opposite to the end portion on the wire bonding side. preferable.

  ADVANTAGE OF THE INVENTION According to this invention, the board | substrate for semiconductor element mounting provided with the terminal part which has a favorable bonding characteristic, and low cost and high mass production can be provided.

It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device using the semiconductor element mounting substrate which concerns on an Example. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device using the semiconductor element mounting substrate which concerns on a prior art example.

  Embodiments of a semiconductor element mounting substrate according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device using a semiconductor element mounting substrate according to an embodiment.

  In the figure, 11 is a metal plate, 11a is a terminal portion, 21 is a dry film resist, 22 is a resist mask having plating resistance, 23 is a resist mask having etching resistance, 31 is a plating layer, and 41 is a semiconductor element. , 51 are bonding wires, and 61 is a sealing resin.

  First, as shown in FIG. 1A, a dry film resist 21 is laminated on both surfaces of a metal plate 11 made of a Cu material having a plate thickness of 0.125 mm.

  Next, as shown in FIG. 1B, exposure processing and development processing are performed using a glass mask on which a desired pattern is formed, and the regions other than the region where the terminal portions 11a on both surfaces of the metal plate 11 are formed. A resist mask 22 having plating resistance is formed in the region.

  Next, as shown in FIG. 1C, a NiP alloy plating layer (thickness: about 0.25 μm) is sequentially formed in the region where the terminal portions 11a on both surfaces of the metal plate 11 are formed, from the metal plate 11 side. A plating layer 31 (thickness: a Ni plating layer (thickness: about 0.7 μm), a Pd plating layer (thickness: about 0.015 μm), and an Au plating layer (thickness: about 0.006 μm) : About 1 μm).

  Next, as shown in FIG. 1D, the resist mask 22 having plating resistance is peeled off from both surfaces of the metal plate 11.

  Next, as illustrated in FIG. 1E, a resist mask 23 having etching resistance is formed so as to cover the entire lower surface of the two surfaces of the metal plate 11. The reason why the resist mask 23 having etching resistance is formed only on the lower surface side is that the plating layer 31 having etching resistance serves as a resist mask on the upper surface side. Therefore, if the plating layer 31 formed on the upper surface side does not have etching resistance, a resist mask having etching resistance is also formed at a desired position on the upper surface side at this stage.

  Next, as shown in FIG. 1F, half etching processing is performed on the upper surface side of the metal plate 11 to form a half on the upper surface side of the terminal portion 11a, and the metal plate 11 is used as a semiconductor element mounting substrate. .

  Next, as shown in FIG. 1G, a semiconductor element 41 having a plurality of electrodes is placed at a predetermined position on the upper surface side of the semiconductor element mounting substrate 12. Then, each electrode of the semiconductor element 41 is wire-bonded to the plating layer 31 formed at the end portion on the upper surface side of the corresponding terminal portion 11a by using a bonding wire 51 containing Cu as a main component.

  Next, as shown in FIG. 1H, the upper half of the terminal portion 11 a, the semiconductor element 41, and the bonding wire 51 are resin-sealed using a sealing resin 61.

  Next, as shown in FIG. 1I, the resist mask 23 having etching resistance is peeled off from the lower surface side of the metal plate 11.

  Finally, as shown in FIG. 1 (J), etching is performed on the lower surface side of the metal plate 11 to form a half on the lower surface side of the terminal portion 11a, and each terminal portion 12a is made independent.

  Since the semiconductor device manufactured in this way is usually one that produces a plurality of semiconductor devices at a time, the individual semiconductor devices are completed by cutting or the like thereafter.

  Here, the plating layer 31 formed on the end portion of the terminal portion 11a of the manufactured semiconductor device will be described in detail.

  As for this plating layer 31, the NiP alloy plating layer is formed in the metal plate 11 side most. Since this NiP alloy plating layer has high heat resistance and is difficult to oxidize compared to the Ni layer, oxidation of the Ni plating layer formed on this NiP alloy layer can be prevented. Moreover, since this NiP alloy plating layer has good solder coverage, it can ensure good solderability.

  In addition, the plating layer 31 has a Ni plating layer formed on the NiP alloy plating layer formed closest to the metal plate 11 side. This Ni plating layer is formed in order to prevent Cu in the metal plate 11 made of a Cu material from diffusing into a wire bonding portion, for example, the outermost layer of the plating layer.

  A Pd plating layer is formed on the Ni plating layer. This Pd plating layer has a good gas barrier property and can prevent oxidation of the Ni plating layer as a base. The Pd plating layer has a thickness of about 0.4 μinch (0.010 μm) to about 3 μinch (0.076 μm).

  Furthermore, an Au plating layer is formed on the Pd plating layer. This Au plating layer is formed in order to prevent oxidation of the Pd plating layer as a base. The thickness of the Au plating layer is about 0.12 μinch (0.003 μm) to about 3 μinch (0.076 μm).

  Note that the plating layer of the semiconductor device of the present invention is not limited to the above-described four-layer plating layer. For example, a four-layered plating layer including a NiP alloy plating layer, a Ni plating layer, a Pd plating layer, and an Ag plating layer may be used in this order from the metal plate side. Further, in order from the metal plate side, a plating layer having a five-layer structure including a NiP alloy plating layer, a Ni plating layer, a NiP alloy plating layer, a Pd plating layer, and an Au plating layer may be used. Alternatively, a five-layer plating layer including a NiP alloy plating layer, a Ni plating layer, a NiP alloy plating layer, a Pd plating layer, and an Ag plating layer may be used in this order from the metal plate side. Further, in order from the metal plate side, a five-layered plating layer including a NiP alloy plating layer, a Ni plating layer, a Pd plating layer, an Au plating layer, and an Ag plating layer may be used. Further, in order from the metal plate side, a five-layered plating layer including a NiP alloy plating layer, a Ni plating layer, a Pd plating layer, an Ag plating layer, and an Au plating layer may be used. Further, in order from the metal plate side, a six-layer plating layer including a NiP alloy plating layer, a Ni plating layer, a NiP alloy plating layer, a Pd plating layer, an Ag plating layer, and an Au plating layer may be used. Furthermore, in order from the metal plate side, a plating layer having a six-layer structure including a NiP alloy plating layer, a Ni plating layer, a NiP alloy plating layer, a Pd plating layer, an Au plating layer, and an Ag plating layer may be used.

  A plating layer made of an alloy containing Pd may be used instead of the Pd plating layer. Further, as the noble metal layer, a plating layer made of an alloy containing Au instead of the Au plating layer may be used, or a plating layer made of an alloy containing Ag instead of the Ag plating layer may be used. Instead of the layer and the Au plating layer, a plating layer made of an alloy containing Au and Ag may be used.

  In addition, from the sample which formed the plating layer which consists of a NiP alloy plating layer, Ni plating layer, Pd plating layer, and Ag plating layer like this invention, and the Ni plating layer, Pd plating layer, and Au plating layer like before When the Φ30 μm Cu wire was bonded to each plating layer of the sample on which the plating layer was formed, the hooks were put under the wire, and the strength when the wire was pulled up and fractured was compared. The average value was 6.5 gf for the conventional product.

  The substrate for mounting a semiconductor element of the present invention is extremely useful in practice because a bonding wire containing Cu as a main component can be suitably bonded.

DESCRIPTION OF SYMBOLS 1,11 Metal plate 1a, 11a Terminal part 1b Mounting part 2 Resist having etching resistance 21 Dry film resist 22 Resist mask having plating resistance 3, 31 Plating layer 4, 41 Semiconductor element 5, 51 Bonding wire 6, 61 Sealing resin

Claims (5)

Provided with a terminal portion for wire bonding with a bonding wire mainly composed of Cu,
In order from the terminal portion side to the end portion of the terminal portion, a NiP alloy plating layer, a Ni plating layer, a Pd plating layer or a Pd alloy plating layer, an Au plating layer, an Ag plating layer, an Au alloy plating layer, Ag A substrate for mounting a semiconductor element, wherein a plating layer having an alloy plating layer or a noble metal plating layer including at least one AuAg alloy plating layer is formed.   The substrate for mounting a semiconductor element according to claim 1, wherein a NiP alloy plating layer is formed between the Ni plating layer and the Pd plating layer or the Pd alloy plating layer.   The noble metal plating layer is composed of the Au plating layer or the Au alloy plating layer and the Ag plating layer or the Ag alloy plating layer in this order from the terminal portion side. The semiconductor element mounting substrate as described.   The noble metal plating layer is composed of the Ag plating layer or the Ag alloy plating layer and the Au plating layer or the Au alloy plating layer in this order from the terminal side. The semiconductor element mounting substrate as described.   5. The plating layer having the same configuration as the plating layer is formed at an end portion of the terminal portion opposite to the end portion on the wire bonding side. The substrate for mounting a semiconductor element according to the item.

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