JP2014085385A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high definition display device.SOLUTION: A display device comprises: a plurality of semiconductor layers (SC); a first insulating film; a first conductive layer; a second insulating film; and a display element. The first conductive layer is provided on the first insulating film and is formed of a metal. The display element has a second conductive layer that is provided on the second insulating film. The first conductive layer and second conductive layer are opposed to each other, forming a capacitance part.

Description

  Embodiments described herein relate generally to a display device.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. Among them, an active matrix display device in which each pixel is provided with a pixel switch having a function of electrically separating an on-pixel and an off-pixel and holding a video signal to the on-pixel includes various types of information including portable information devices. It is used for the display.

  As such a flat-type active matrix display device, an organic EL display device using a self-luminous element has attracted attention, and research and development have been actively conducted. The organic EL display device has characteristics that it does not require a backlight, is suitable for moving image reproduction because of high-speed responsiveness, and is suitable for use in a cold region because the luminance does not decrease at low temperatures.

  In general, an organic EL display device includes a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element.

  As a pixel circuit driving method, a method using a voltage signal is known. In addition, by switching the voltage power supply, switching between low and high, and outputting both the video signal and the initialization signal from the video signal wiring, the number of pixel constituent elements and the number of wirings can be reduced, and the pixel layout area There has been proposed a display device that achieves higher definition by reducing the size of the screen.

US Pat. No. 6,229,506 JP 2007-310311 A JP 2011-145622 A

Incidentally, in recent years, there has been a further demand for higher definition of pixels. As the size of a pixel is reduced, it has become difficult to arrange a plurality of elements of each pixel within a predetermined region.
The present invention has been made in view of the above points, and an object thereof is to provide a high-definition display device.

A display device according to an embodiment includes:
A plurality of semiconductor layers;
A first insulating film provided above the plurality of semiconductor layers;
A first conductive layer provided on the first insulating film and made of metal;
A second insulating film provided on the first insulating film and the first conductive layer;
A display element having a second conductive layer provided on the second insulating film,
The first conductive layer and the second conductive layer are opposed to each other to form a capacitor portion.

FIG. 1 is a plan view schematically showing the display device according to the first embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 4 is a partial cross-sectional view showing the display device according to the first embodiment, and shows a drive transistor, a power supply line, a connection electrode, a conductive layer, and a pixel electrode. FIG. 5 is a plan view showing the display device according to the first embodiment, and is a diagram showing an overall schematic structure of the conductive layer shown in FIGS. 3 and 4. FIG. 6 is an enlarged plan view showing the connection electrode and the conductive layer. FIG. 7 is a schematic diagram illustrating an example of an arrangement configuration of pixels according to the first embodiment. FIG. 8 is a timing chart showing the control signal of the scanning line driving circuit when the pixel arrangement according to the first embodiment is adopted and the offset cancel operation is performed once. FIG. 9 is a timing chart showing control signals of the scanning line driving circuit when the pixel arrangement according to the first embodiment is adopted and the offset cancel operation is performed twice. FIG. 10 is a partial cross-sectional view showing a modification of the display device according to the first embodiment, and shows a drive transistor, a power supply line, a connection electrode, a conductive layer, and a pixel electrode. FIG. 11 is a partial cross-sectional view showing another modification of the display device according to the first embodiment, and is a view showing a drive transistor, a power supply line, a conductive layer, and a pixel electrode. FIG. 12 is an equivalent circuit diagram of a pixel of the display device according to the second embodiment. FIG. 13 is a partial cross-sectional view illustrating the display device according to the second embodiment, and is a diagram illustrating a drive transistor, a power supply line, a connection electrode, a conductive layer, and a pixel electrode. FIG. 14 is a partial cross-sectional view illustrating a modification of the display device according to the second embodiment, and is a diagram illustrating a drive transistor, a power supply line, a connection electrode, a conductive layer, and a pixel electrode. FIG. 15 is a partial cross-sectional view illustrating another modification of the display device according to the second embodiment, and is a diagram illustrating a drive transistor, a power supply line, a conductive layer, and a pixel electrode.

  Hereinafter, the display device and the driving method of the display device according to the first embodiment will be described in detail with reference to the drawings. In this embodiment, the display device is an active matrix display device, more specifically, an active matrix organic EL (electroluminescence) display device.

  FIG. 1 is a plan view schematically showing the display device according to the present embodiment. FIG. 2 is an equivalent circuit diagram of a pixel of the display device of FIG. FIG. 3 is a partial cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. In FIG. 3, the display device is drawn such that the display surface, that is, the front surface or the light emitting surface faces upward, and the back surface faces downward. This display device is a top emission type organic EL display device adopting an active matrix driving method.

  As shown in FIG. 1, the display device according to the present embodiment is configured as, for example, an active matrix type display device of type 2 or more, and includes a display panel DP and a controller 12 that controls the operation of the display panel DP. It is out. In this embodiment, the display panel DP is an organic EL panel.

  The display panel DP includes an insulating substrate SUB having light transmissivity such as a glass plate, m × n pixels PX arranged in a matrix on the display region R1 of the insulating substrate SUB, and a plurality (m / 2) of pixels. The first scanning line Sga (1 to m / 2), the plurality (m) of second scanning lines Sgb (1 to m), and the plurality of (m / 2) third scanning lines Sgc (1 to 1). m / 2), a plurality (m / 2) of reset wirings Sgr (1 to m / 2), and a plurality (n) of video signal lines VL (1 to n).

  The pixels PX are arranged m in the column direction Y and n in the row direction X. The first scanning line Sga, the second scanning line Sgb, and the reset wiring Sgr are provided to extend in the row direction X. The reset wiring Sgr is formed of a plurality of electrodes that are electrically connected to each other. The video signal line VL extends in the column direction Y.

  As shown in FIGS. 1 and 2, the display panel DP includes a high-potential power line SLa that is fixed to a high potential Pvdd and a low-potential power electrode SLb that is fixed to a low potential Pvss. The high potential power supply line SLa is connected to a high potential power supply, and the low potential power supply electrode SLb is connected to a low potential power supply (reference potential power supply).

  The display panel DP has scanning line driving circuits YDR1 and YDR2 that sequentially drive the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc for each row of the pixels PX, and a signal line drive that drives the video signal line VL. A circuit XDR is provided. The scanning line drive circuits YDR1 and YDR2 and the signal line drive circuit XDR are integrally formed on the non-display area R2 outside the display area R1 of the insulating substrate SUB, and constitute the drive unit 10 together with the controller 12.

  Each pixel PX includes a display element and a pixel circuit that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, an organic EL diode OLED (hereinafter simply referred to as a diode OLED) including at least an organic light emitting layer as a photoactive layer is used.

  As shown in FIG. 2, the pixel circuit of each pixel PX is a voltage signal type pixel circuit that controls light emission of the diode OLED in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, a storage capacitor Cs and auxiliary capacitance Cad are included. The holding capacitor Cs and the auxiliary capacitor Cad are capacitors. The auxiliary capacitor Cad is an element provided for adjusting the light emission current amount. The capacitance part Cel is the capacitance of the diode OLED itself (parasitic capacitance of the diode OLED). The diode OLED also functions as a capacitor.

  Each pixel PX includes an output switch BCT. A plurality of pixels PX adjacent in the column direction Y share the output switch BCT. In this embodiment, the four pixels PX adjacent in the row direction X and the column direction Y share one output switch BCT. The scanning line driving circuit YDR2 (or the scanning line driving circuit YDR1) is provided with a plurality of reset switches RST. The reset switch RST and the reset wiring Sgr are connected one to one.

  Here, the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST are composed of TFTs (thin film transistors) of the same conductivity type, for example, N-channel type.

  In the display device according to the present embodiment, the TFTs constituting each driving transistor and each switch are all formed in the same process and the same layer structure, and are top-gate thin film transistors using polysilicon as the semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, the output switch BCT, and the reset switch RST has a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal is a source electrode, the second terminal is a drain electrode, and the control terminal is a gate electrode.

  In the pixel circuit of the pixel PX, the drive transistor DRT and the output switch BCT are connected in series with the diode OLED between the high potential power line SLa and the low potential power electrode SLb. The high potential power supply line SLa (high potential Pvdd) is set to a potential of 10 V, for example, and the low potential power supply electrode SLb (low potential Pvss) is set to a potential of 1.5 V, for example.

  In the output switch BCT, the drain electrode is connected to the high potential power supply line SLa, the source electrode is connected to the drain electrode of the drive transistor DRT, and the gate electrode is connected to the first scanning line Sga. Thus, the output switch BCT is controlled to be on (conductive state) and off (non-conductive state) by the control signal BG (1 to m / 2) from the first scanning line Sga. The output switch BCT controls the light emission time of the diode OLED in response to the control signal BG.

  In the drive transistor DRT, the drain electrode is connected to the source electrode of the output switch BCT and the reset wiring Sgr, and the source electrode is connected to one electrode (here, the anode) of the diode OLED. The other electrode (here, the cathode) of the diode OLED is connected to the low potential power supply electrode SLb. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal Vsig to the diode OLED.

  In the pixel switch SST, the source electrode is connected to the video signal line VL (1 to n), the drain electrode is connected to the gate electrode of the driving transistor DRT, and the gate electrode functions as a signal writing control gate wiring. It is connected to Sgb (1 to m). The pixel switch SST is on / off controlled by a control signal SG (1 to m) supplied from the second scanning line Sgb. The pixel switch SST controls connection / disconnection between the pixel circuit and the video signal line VL (1-n) in response to the control signal SG (1-m), and the corresponding video signal line VL (1 To n) capture the video signal Vsig into the pixel circuit.

  The reset switch RST is provided in the scanning line driving circuit YDR2 every two rows. The reset switch RST is connected between the drain electrode of the drive transistor DRT and the reset power supply. In the reset switch RST, the source electrode is connected to the reset power supply line SLc connected to the reset power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode is connected to the third scanning line Sgc functioning as a reset control gate wiring. Has been. As described above, the reset power supply line SLc is connected to the reset power supply and is fixed to the reset potential Vrst that is a constant potential.

  The reset switch RST switches between the reset power supply line SLc and the reset wiring Sgr in a conductive state (ON) or a non-conductive state (OFF) in accordance with a control signal RG (1 to m / 2) given through the third scanning line Sgc. Switch. By switching the reset switch RST to the on state, the potential of the source electrode of the drive transistor DRT is initialized.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board (not shown) arranged outside the display panel DP, and controls the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal.

  The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits YDR1 and YDR2 and the signal line driving circuit XDR, respectively, and the digital video signal and the initial stage are synchronized with the horizontal and vertical scanning timings. The signal is supplied to the signal line drive circuit XDR.

  The signal line drive circuit XDR converts the video signal sequentially obtained in each horizontal scanning period to the analog format under the control of the horizontal scanning control signal, and converts the video signal Vsig corresponding to the gradation to the plurality of video signal lines VL (1 to n). In parallel. The signal line drive circuit XDR supplies the initialization signal Vini to the video signal line VL.

The scanning line driving circuits YDR1 and YDR2 include a shift register, an output buffer, and the like (not shown), transfer a horizontal scanning start pulse supplied from the outside sequentially to the next stage, and three types of pixels PX in each row via the output buffer Control signals, that is, control signals BG (1 to m / 2), SG (1 to m), and RG (1 to m / 2) are supplied (FIG. 2). Note that the control signal RG is not directly supplied to the pixel PX, but a predetermined voltage is supplied from the reset power supply line SLc fixed to the reset potential Vrst at a predetermined timing according to the control signal RG.
Accordingly, the first scanning line Sga, the second scanning line Sgb, and the third scanning line Sgc are driven by the control signals BG, SG, and RG, respectively.

Next, the configuration of the drive transistor DRT and the diode OLED will be described in detail with reference to FIG.
The N-channel TFT in which the driving transistor DRT is formed includes a semiconductor layer SC. The semiconductor layer SC is formed on the undercoat layer UC formed on the insulating substrate SUB. The semiconductor layer SC is, for example, a polysilicon layer including a p-type region and an n-type region.

  The semiconductor layer SC is covered with a gate insulating film GI. On the gate insulating film GI, the gate electrode G of the drive transistor DRT is formed. The gate electrode G is opposed to the semiconductor layer SC. An interlayer insulating film II is formed on the gate insulating film GI and the gate electrode G.

  A source electrode SE and a drain electrode DE are further formed on the interlayer insulating film II. The source electrode SE and the drain electrode DE are connected to the source region and the drain region of the semiconductor layer SC through contact holes formed in the interlayer insulating film II and the gate insulating film GI, respectively.

  An insulating planarizing film PL is formed on the interlayer insulating film II, the source electrode SE, and the drain electrode DE. The gate insulating film GI, the interlayer insulating film II, and the planarizing film PL function as a first insulating film.

  On the planarizing film PL, a connection electrode AE and a conductive layer OE as a first conductive layer are formed. In this embodiment, the conductive layer OE and the connection electrode AE are formed of metal (for example, Al: aluminum). The connection electrode AE is connected to the source electrode SE of the drive transistor DRT through a contact hole provided in the planarizing film PL. A passivation film PS is formed on the planarizing film PL, the conductive layer OE, and the connection electrode AE. The passivation film PS functions as a second insulating film.

  The diode OLED includes a pixel electrode PE, an organic layer ORG, and a counter electrode CE. In this embodiment, the pixel electrode PE is an anode, and the counter electrode CE is a cathode.

  A pixel electrode PE is formed on the passivation film PS. The pixel electrode PE is connected to the connection electrode AE through a contact hole provided in the passivation film PS. The pixel electrode PE functions as a second conductive layer. The pixel electrode PE is a back electrode having light reflectivity. The pixel electrode PE is formed by laminating a transparent electrode layer (for example, ITO: indium tin oxide) and a light reflective electrode layer (for example, Al).

  When forming the pixel electrode PE, a transparent conductive material (for example, ITO) is deposited on the passivation film PS, and then a light-reflective conductive material (for example, Al) is deposited, and then a photolithography method is used. Then, the pixel electrode PE is formed by patterning.

  A partition insulating layer PI is further formed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the pixel electrode PE, or a slit is provided at a position corresponding to a column or row formed by the pixel electrode PE. Here, as an example, the partition insulating layer PI has a through hole at a position corresponding to the pixel electrode PE.

  On the pixel electrode PE, an organic layer ORG including a light emitting layer is formed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, blue, or achromatic. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with the counter electrode CE. In this example, the counter electrode CE is an electrode connected to each other between the pixels PX, that is, a common electrode. In this example, the counter electrode CE is a cathode and a light-transmitting front electrode. The counter electrode CE is, for example, an electrode wiring formed in the same layer as the source electrode SE and the drain electrode DE through a contact hole provided in the planarization film PL, the passivation film PS, and the partition insulating layer PI (see FIG. (Not shown).

  In the diode OLED having such a structure, when the holes injected from the pixel electrode PE and the electrons injected from the counter electrode CE are recombined inside the organic layer ORG, the organic molecules constituting the organic layer ORG are changed. Excitons are generated by excitation. The excitons emit light in the process of radiation deactivation, and the light is emitted from the organic layer ORG to the outside through the transparent counter electrode CE.

  Next, the configuration of the conductive layer OE and the auxiliary capacitor Cad will be described in detail with reference to FIGS. FIG. 4 is a partial cross-sectional view showing the display device according to this embodiment, and is a view showing the drive transistor DRT, the power supply line PSH, the connection electrode AE, the conductive layer OE, and the pixel electrode PE. FIG. 5 is a plan view showing the display device according to the present embodiment, and is a diagram showing an overall schematic structure of the conductive layer OE shown in FIGS. 3 and 4. FIG. 6 is an enlarged plan view showing the connection electrode AE and the conductive layer OE.

  As shown in FIGS. 3 to 6, the conductive layer OE is provided to face the entire display region R1. The conductive layer OE has one opening in each pixel PX, and is formed with a gap around the periphery of the connection electrode AE.

  The conductive layer OE is connected to the power supply line PSH through the contact hole CH formed in the planarizing film PL outside the display region R1. The power supply line PSH is connected to a constant potential power supply. In this embodiment, the power supply line PSH is connected to a high potential power supply and is fixed at a high potential Pvdd.

  The conductive layer OE and the pixel electrode PE are opposed to each other and form an auxiliary capacitor Cad (capacitor portion). The auxiliary capacitor Cad can be formed without using the semiconductor layer. The auxiliary capacitor Cad can be formed in a region facing the element using the semiconductor layer, that is, the auxiliary capacitor Cad can be efficiently arranged, so that the use efficiency of the space can be improved.

  In this embodiment, since the display device is a top emission display device, the conductive layer OE can be formed of metal (for example, Al). Note that when the display device is a bottom emission type display device or a light transmission type display device such as a liquid crystal display device, the conductive layer OE cannot be formed of metal.

Next, the arrangement configuration of the plurality of pixels PX will be described. FIG. 7 is a schematic diagram illustrating an arrangement configuration of the pixels PX according to the present embodiment.
As shown in FIG. 7, the pixel PX is a so-called vertical stripe pixel. In the row direction X, a pixel PX configured to display a red image, a pixel PX configured to display a green image, a pixel PX configured to display a blue image, and no pixel Pixels PX configured to display a chromatic image are alternately arranged. In the column direction Y, pixels PX configured to display the same color image are arranged.

  The red (R) pixel PX, the green (G) pixel PX, the blue (B) pixel PX, and the achromatic (W) pixel PX form a picture element P. In the first embodiment, the picture element P has four (four colors) pixels PX, but is not limited to this and can be variously modified. For example, when the achromatic pixel PX is not provided, the picture element P may include three (three colors) pixels PX of red, green, and blue.

  The output switch BCT is shared by four adjacent pixels (two adjacent in the column direction Y and two adjacent in the row direction X). From the above, the number of first scanning lines Sga and third scanning lines Sgc is m / 2.

Note that the arrangement configuration of the pixels PX is not limited to the present embodiment (FIG. 7) and can be variously modified. For example, the pixel PX may be a so-called RGBW square pixel. In this case, for example, any two of red, green, blue and achromatic pixels PX are arranged in even rows, and the remaining two are arranged in odd rows.
Here, in the present embodiment, the terminology of the pixel PX and the picture element P has been described, but the pixel can be rephrased as a sub-pixel. In this case, the picture element is a pixel.

  Next, the operation of the display device (organic EL display device) configured as described above will be described. 8 and 9 are timing charts showing control signals of the scanning line drive circuits YDR1 and YDR2 during operation display, respectively.

  FIG. 8 shows a case in which the offset cancellation period is once for vertical stripe pixels, and FIG. 9 shows a case in which the offset cancellation period is multiple times (here, twice as a representative example) for vertical stripe pixels. Therefore, in this embodiment, the display device can be driven using the control signal of FIG. 8 or the control signal of FIG.

  For example, the scanning line drive circuits YDR1 and YDR2 generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1 to STV3) and a clock (CKV1 to CKV3). The pulses are output as control signals BG (1 to m / 2), SG (1 to m), and RG (1 to m / 2). Here, one horizontal scanning period is set to 1H.

  The operation of the pixel circuit includes a source initialization operation performed during the source initialization period Pis, a gate initialization operation performed during the gate initialization period Pig, and an offset cancellation (OC) operation performed during the offset cancellation period Po. It is divided into a video signal writing operation performed during the video signal writing period Pw and a display operation (light emitting operation) performed during the display period Pd (light emission period).

  As shown in FIGS. 8, 9, 1, and 2, the driving unit 10 first performs a source initialization operation. In the source initialization operation, the control signal SG turns off the pixel switch SST from the scanning line drive circuits YDR1 and YDR2, and the control signal BG turns off the output switch BCT. The level (off potential: low level here) and the control signal RG are set to a level (on potential: high level here) that turns on the reset switch RST.

  The output switch BCT and the pixel switch SST are turned off (non-conductive state), the reset switch RST is turned on (conductive state), and the source initialization operation is started. When the reset switch RST is turned on, the source electrode and drain electrode of the drive transistor DRT are reset to the same potential as the potential of the reset power supply (reset potential Vrst), and the source initialization operation is completed. Here, the reset power supply (reset potential Vrst) is set to −2 V, for example.

  Next, the driving unit 10 performs a gate initialization operation. In the gate initialization operation, the control signal SG turns on the pixel switch SST from the scanning line drive circuits YDR1 and YDR2 (on potential: high level here), and the control signal BG turns off the output switch BCT. The level and control signal RG is set to a level that turns on the reset switch RST. The output switch BCT is turned off, the pixel switch SST and the reset switch RST are turned on, and the gate initialization operation is started.

  In the gate initialization period Pig, the initialization signal Vini (initialization voltage) output from the video signal line VL is applied to the gate electrode of the driving transistor DRT through the pixel switch SST. As a result, the potential of the gate electrode of the drive transistor DRT is reset to a potential corresponding to the initialization signal Vini, and information of the previous frame is initialized. The voltage level of the initialization signal Vini is set to 2V, for example.

  Subsequently, the drive unit 10 performs an offset cancel operation. The control signal SG is turned on, the control signal BG is turned on (high level), and the control signal RG is turned off (low level). As a result, the reset switch RST is turned off, the pixel switch SST and the output switch BCT are turned on, and the threshold value offset cancel operation is started.

  In the offset cancel period Po, the initialization signal Vini is applied to the gate electrode of the drive transistor DRT through the video signal line VL and the pixel switch SST, and the potential of the gate electrode of the drive transistor DRT is fixed.

  Further, the output switch BCT is in an ON state, and a current flows from the high potential power supply line SLa to the drive transistor DRT. The potential of the source electrode of the drive transistor DRT is initially set to the potential (reset potential Vrst) written in the source initialization period Pis, and the current flowing through between the drain electrode and the source electrode of the drive transistor DRT is gradually reduced. In the meantime, the TFT shifts to the high potential side while absorbing and compensating for the TFT characteristic variation of the drive transistor DRT. In the present embodiment, the offset cancellation period Po is set to a time of about 1 μsec, for example.

  At the end of the offset cancellation period Po, the potential of the source electrode of the drive transistor DRT becomes Vini−Vth. Vini is the voltage value of the initialization signal Vini, and Vth is the threshold voltage of the drive transistor DRT. As a result, the voltage between the gate electrode and the source electrode of the drive transistor DRT reaches the cancel point (Vgs = Vth), and the potential difference corresponding to the cancel point is stored (held) in the storage capacitor Cs. As in the example shown in FIG. 9, the offset cancellation period Po can be provided a plurality of times as necessary.

  Subsequently, in the video signal writing period Pw, the control signal SG sets the pixel switch SST to an on state, the control signal BG sets the output switch BCT to an on state, and the control signal RG sets the reset switch RST to an off state. Set to level. Then, the pixel switch SST and the output switch BCT are turned on, the reset switch RST is turned off, and the video signal writing operation is started.

In the video signal writing period Pw, the video signal Vsig is written from the video signal line VL through the pixel switch SST to the gate electrode of the drive transistor DRT. In addition, a current flows from the high potential power supply line SLa to the low potential power supply electrode SLb through the output switch BCT and the driving transistor DRT, and via the capacitance portion (parasitic capacitance) Cel of the diode OLED. Immediately after the pixel switch SST is turned on, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B), and the potential of the source electrode of the drive transistor DRT is Vini−Vth + Cs (Vsig−Vini) / (Cs + Cel + Cad). It becomes.
Vsig is the voltage value of the video signal Vsig, Cs is the capacity of the storage capacitor Cs, Cel is the capacity of the capacitor part Cel, and Cad is the capacity of the auxiliary capacitor Cad.

  Thereafter, a current flows to the low-potential power supply electrode SLb via the capacitance part Cel of the diode OLED, and at the end of the video signal writing period Pw, the potential of the gate electrode of the drive transistor DRT is Vsig (R, G, B), drive The potential of the source electrode of the transistor DRT is Vini−Vth + ΔV1 + Cs (Vsig−Vini) / (Cs + Cel + Cad).

The relationship between the current Idrt flowing through the driving transistor DRT and the capacitance Cs + Cel + Cad is expressed by the following equation, and ΔV1 corresponds to the voltage value of the video signal Vsig determined from the following equation, the video writing period Pw, and the transistor mobility. This is the displacement of the potential of the source electrode.

here,
Idrt = β × (Vgs−Vth) ²
= {(Vsig−Vini) × (Cel + Cad) / (Cs + Cel + Cad)} ²
It is.

  β is defined by the following equation.

β = μ × Cox × W / 2L
W is the channel width of the drive transistor DRT, L is the channel length of the drive transistor DRT, μ is the carrier mobility, and Cox is the gate capacitance per unit area.

Thereby, the variation in mobility of the drive transistor DRT is corrected.

  Finally, in the display period Pd, the control signal SG is at a level at which the pixel switch SST is turned off, the control signal BG is at a level at which the output switch BCT is turned on, and the control signal RG is at a level at which the reset switch RST is turned off. Is set. The output switch BCT is turned on, the pixel switch SST and the reset switch RST are turned off, and the display operation is started.

  The drive transistor DRT outputs a drive current Ie having a current amount corresponding to the gate control voltage written in the storage capacitor Cs. This drive current Ie is supplied to the diode OLED. As a result, the diode OLED emits light with a luminance corresponding to the drive current Ie, and performs a display operation. The diode OLED maintains the light emitting state after one frame period until the control signal BG becomes the off potential again.

  The above-described source initialization operation, gate initialization operation, offset cancellation operation, video signal writing operation, and display operation are sequentially performed on each pixel PX, thereby displaying a desired image.

  According to the display device and the display device driving method according to the first embodiment configured as described above, the display device includes a plurality of semiconductor layers (SC) and a first insulating film (gate insulating film GI, interlayer). Insulating film II and planarization film PL), conductive layer OE (first conductive layer), second insulating film (passivation film PS), and diode OLED are provided.

  The gate insulating film GI, the interlayer insulating film II, and the planarizing film PL are provided above the plurality of semiconductor layers. The conductive layer OE is provided on the planarizing film PL and is made of metal. The passivation film PS is provided on the planarization film PL and the conductive layer OE. The diode OLED has a pixel electrode PE (second conductive layer) provided on the passivation film PS.

  The conductive layer OE and the pixel electrode PE are opposed to each other and can form an auxiliary capacitor Cad (capacitor portion). Since the auxiliary capacitor Cad can be formed without using the semiconductor layer, the auxiliary capacitor Cad can be formed in a region facing the element using the semiconductor layer. Compared to the case where the auxiliary capacitor Cad is formed using a semiconductor layer, the auxiliary capacitor Cad can be arranged efficiently, so that the space utilization efficiency can be improved. And it can contribute to high definition of the pixel PX.

  In the display period Pd, the output current Iel in the saturation region of the drive transistor DRT is applied to the diode OLED to emit light. Here, when the gain coefficient of the driving transistor DRT is β, the output current Iel is expressed by the following equation.

Iel = β × {(Vsig−Vini−ΔV1) × (Cel + Cad) / (Cs + Cel + Cad)} ²
β is defined by the following equation.

β = μ × Cox × W / 2L
W is the channel width of the drive transistor DRT, L is the channel length of the drive transistor DRT, μ is the carrier mobility, and Cox is the gate capacitance per unit area.

  Therefore, the output current Iel becomes a value that does not depend on the threshold voltage Vth of the drive transistor DRT, and the influence of the variation of the threshold voltage of the drive transistor DRT on the output current Iel can be eliminated.

In addition, since the absolute value of ΔV1 increases as the mobility μ of the driving transistor DRT increases, the influence of the mobility μ can be compensated. Therefore, it is possible to suppress the occurrence of display defects, unevenness, and rough feeling due to these variations, and to perform high-quality image display.
From the above, a high-definition display device and a driving method of the display device can be obtained.

  Here, a modification of the display device according to the first embodiment will be described. FIG. 10 is a partial cross-sectional view showing a modification of the display device according to the first embodiment, and shows a drive transistor DRT, a power supply line PSH, a connection electrode AE, a connection electrode RE, a conductive layer OE, and a pixel electrode PE. It is. FIG. 11 is a partial cross-sectional view showing another modification of the display device according to the first embodiment, and is a view showing a drive transistor DRT, a power supply line PSH, a conductive layer OE, and a pixel electrode PE.

  As shown in FIG. 10, the conductive layer OE is made of metal (for example, Al). The connection electrode AE and the connection electrode RE are formed of a transparent conductive material (for example, ITO). The connection electrode RE is connected to the power supply line PSH through the contact hole CH formed in the planarizing film PL. After forming the connection electrode AE and the connection electrode RE with ITO or the like, the conductive layer OE is formed with Al or the like.

  Although not shown, when the connection electrode AE, the connection electrode RE, and the like are formed of a transparent conductive material, the electrode is formed of the same material on the wiring such as the power supply line PSH and the video signal line VL outside the display region R1. A layer may be formed. The electrode layer has moisture resistance and is exposed to the atmosphere. That is, since the wiring exposed to the atmosphere can be covered with the electrode layer, the deterioration of the wiring (product) can be reduced.

  As shown in FIG. 11, the pixel electrode PE may be directly connected to the source electrode SE of the drive transistor DRT through a contact hole provided in the planarization film PL and the passivation film PS.

  Next, a display device and a driving method of the display device according to the second embodiment will be described. In this embodiment, the same functional parts as those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 12 is an equivalent circuit diagram of a pixel of the display device according to the present embodiment.

FIG. 13 is a partial cross-sectional view showing the display device according to the present embodiment, and is a view showing the drive transistor DRT, the power supply line PSL, the connection electrode AE, the conductive layer OE, and the pixel electrode PE.

  As shown in FIGS. 12 and 13, the conductive layer OE is connected to the power supply line PSL through the contact hole CH formed in the planarizing film PL outside the display region R1. The power supply line PSL is connected to a constant potential power supply. In this embodiment, the power supply line PSL is connected to a low potential power supply and is fixed to the low potential Pvss.

  The conductive layer OE and the pixel electrode PE are opposed to each other and form an auxiliary capacitor Cad (capacitor portion). The auxiliary capacitor Cad can be formed without using the semiconductor layer. Since the auxiliary capacitor Cad can be arranged efficiently, the space utilization efficiency can be improved.

  According to the display device and the driving method of the display device according to the second embodiment configured as described above, the display device includes a plurality of semiconductor layers (SC) and a first insulating film (gate insulating film GI, interlayer). Insulating film II and planarization film PL), conductive layer OE (first conductive layer), second insulating film (passivation film PS), and diode OLED are provided. The conductive layer OE is connected to a power supply line PSL (low potential power supply).

  The conductive layer OE and the pixel electrode PE are opposed to each other and can form an auxiliary capacitor Cad (capacitor portion). Since the auxiliary capacitor Cad can be formed without using the semiconductor layer, the auxiliary capacitor Cad can be formed in a region facing the element using the semiconductor layer. Since the use efficiency of the space can be improved, it is possible to contribute to high definition of the pixel PX.

In addition, the same effects as those of the first embodiment described above can be obtained.
From the above, a high-definition display device and a driving method of the display device can be obtained.

  Here, a modification of the display device according to the second embodiment will be described. FIG. 14 is a partial cross-sectional view showing a modification of the display device according to the second embodiment, and shows a drive transistor DRT, a power supply line PSL, a connection electrode AE, a connection electrode RE, a conductive layer OE, and a pixel electrode PE. It is. FIG. 15 is a partial cross-sectional view illustrating another modification of the display device according to the second embodiment, and is a diagram illustrating a drive transistor DRT, a power supply line PSL, a conductive layer OE, and a pixel electrode PE.

  As shown in FIG. 14, the conductive layer OE is made of metal (for example, Al). The connection electrode AE and the connection electrode RE are formed of a transparent conductive material (for example, ITO). The connection electrode RE is connected to the power supply line PSL through the contact hole CH formed in the planarizing film PL. After forming the connection electrode AE and the connection electrode RE with ITO or the like, the conductive layer OE is formed with Al or the like.

  Although not shown, when the connection electrode AE, the connection electrode RE, and the like are formed of a transparent conductive material, the electrode is formed of the same material on the wiring such as the power supply line PSL and the video signal line VL outside the display region R1. A layer may be formed. The electrode layer has moisture resistance and is exposed to the atmosphere. That is, since the wiring exposed to the atmosphere can be covered with the electrode layer, the deterioration of the wiring (product) can be reduced.

  As shown in FIG. 15, the pixel electrode PE may be directly connected to the source electrode SE of the drive transistor DRT through a contact hole provided in the planarization film PL and the passivation film PS.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the semiconductor layer of the TFT is not limited to polysilicon, but can be composed of amorphous silicon. The TFT and the drive transistor DRT constituting each switch are not limited to N-channel TFTs but may be formed of P-channel TFTs. Similarly, the reset switch RST may be formed of a P-channel or N-channel TFT. The shapes and dimensions of the drive transistor DRT and the switch are not limited to the above-described embodiments, and can be changed as necessary.

  Further, the output switch BCT is provided so as to be shared by four pixels PX. However, the present invention is not limited to this, and the number of output switches BCT can be increased or decreased as necessary. For example, one output switch BCT may be provided for each pixel PX. Further, two pixels PX provided in 2 rows and 1 column share one output switch BCT, and 8 pixels PX provided in 2 rows and 4 columns share one output switch BCT. It may be.

Furthermore, all the pixels PX in one row may share one output switch BCT. In this case, the output switch BCT and the first scanning line Sga may be provided in the scanning line driving circuit YDR2 (YDR1). That is, in the output switch BCT, the source electrode is connected to the high potential power supply, the drain electrode is connected to the reset wiring Sgr, and the gate electrode is connected to the first scanning line Sga.
Furthermore, the self-light-emitting element constituting the pixel PX is not limited to the diode (organic EL diode) OLED and can be formed by applying various display elements capable of self-light emission.

The auxiliary capacitor Cad only needs to be connected between the source electrode of the driving transistor DRT and the constant potential wiring. Examples of the constant potential wiring include a high potential power supply line SLa, a low potential power supply line SLb, and a reset wiring Sgr.
Embodiments of the present invention are not limited to display devices and display device driving methods, and can be applied to various display devices and display device driving methods.

  DP ... display panel, 10 ... drive unit, 12 ... controller, YDR1, YDR2 ... scan line drive circuit, XDR ... signal line drive circuit, Sga ... first scan line, Sgb ... second scan line, Sgc ... third scan line , Sgr ... reset wiring, VL ... video signal line, P ... picture element, PX ... pixel, OLED ... diode, SST ... pixel switch, DRT ... drive transistor, BCT ... output switch, RST ... reset switch, Cs ... holding capacitor, Cad: auxiliary capacitance, SC: semiconductor layer, GI: gate insulating film, II: interlayer insulating film, PL: planarizing film, AE, RE ... connection electrode, OE ... conductive layer, PS ... passivation film, PE ... pixel electrode, PSH, PSL ... power supply line, CH ... contact hole, Y ... column direction, X ... row direction.

Claims (10)

A plurality of semiconductor layers;
A first insulating film provided above the plurality of semiconductor layers;
A first conductive layer provided on the first insulating film and made of metal;
A second insulating film provided on the first insulating film and the first conductive layer;
A display element having a second conductive layer provided on the second insulating film,
The display device in which the first conductive layer and the second conductive layer face each other to form a capacitor portion.   The display device according to claim 1, wherein the second conductive layer is formed by laminating a transparent electrode layer and a light-reflecting electrode layer. A plurality of pixels provided in a matrix along the row direction and the column direction;
Each of the plurality of pixels is
The display element connected between a high potential power source and a low potential power source;
A drive transistor having a source electrode connected to the display element, a drain electrode connected to a reset wiring, and a gate electrode;
An output switch connected between the high-potential power supply and the drain electrode of the drive transistor, and switching between the high-potential power supply and the drain electrode of the drive transistor to a conductive state or a non-conductive state;
A pixel switch connected between the video signal line and the gate electrode of the driving transistor, and for switching whether to take in a signal applied through the video signal line to the gate electrode side of the driving transistor;
A storage capacitor connected between a source electrode and a gate electrode of the driving transistor,
The display device according to claim 1, wherein the driving transistor, the output switch, the pixel switch, and the storage capacitor are formed using the plurality of semiconductor layers. A first scan line connected to the output switch;
A second scan line connected to the pixel switch;
A scanning line driving circuit connected to the first scanning line and the second scanning line;
The display device according to claim 3, further comprising: a signal line driving circuit connected to the video signal line.   The display device according to claim 3, wherein the output switch is shared by the plurality of pixels. A plurality of pixels provided in a matrix along the row direction and the column direction;
Each of the plurality of pixels is
The display element connected between a high potential power source and a low potential power source;
A drive transistor having a source electrode connected to the display element, a drain electrode connected to a reset wiring, and a gate electrode;
A pixel switch connected between the video signal line and the gate electrode of the driving transistor, and for switching whether to take in a signal applied through the video signal line to the gate electrode side of the driving transistor;
A storage capacitor connected between a source electrode and a gate electrode of the driving transistor,
The display device according to claim 1, wherein the driving transistor, the pixel switch, and the storage capacitor are formed using the semiconductor layer. A scan having an output switch connected between the high-potential power supply and the reset wiring and switching between the high-potential power supply and the reset wiring to a conductive state or a non-conductive state, and a first scanning line connected to the output switch. A line drive circuit;
A second scanning line connected to the scanning line driving circuit and the pixel switch;
The display device according to claim 6, further comprising: a signal line driving circuit connected to the video signal line. Each of the plurality of pixels further includes an auxiliary capacitor that is the capacitor.
The first conductive layer is connected to a constant potential power source;
The display device according to claim 3, wherein the second conductive layer is connected to a source electrode of the driving transistor. The constant potential power source is the high potential power source or the low potential power source,
The display device according to claim 8, wherein the first conductive layer is connected to a power supply line connected to the power source having the constant potential outside the display region. Further comprising a moisture-proof electrode layer formed on the power line outside the display area;
The display device according to claim 9, wherein the electrode layer is exposed to the atmosphere.

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