JP2014078586A - Zinc oxide semiconductor transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a zinc oxide semiconductor transistor which increases controllability of a threshold value.SOLUTION: A zinc oxide semiconductor transistor comprises: a substrate having a flat surface; an insulation film formed on the substrate; an island-like channel formation layer which is formed on the insulation film and composed of a zinc oxide semiconductor; and a source electrode and a drain electrode which are formed on the channel formation layer, in which a residual stress of an intrinsic channel region between the source electrode and the drain electrode is made larger than a residual stress in a peripheral part outside the intrinsic channel region.

Description

  The present invention relates to a zinc oxide based semiconductor transistor.

  Since zinc oxide-based semiconductors exhibit high carrier mobility even if they are polycrystalline, research and development of optical and electronic devices using them are being conducted. For example, a zinc oxide-based semiconductor has a property of transmitting visible light, and thus has attracted attention as a driving transistor for a flat panel display (see, for example, Patent Document 1 or Patent Document 2).

  In addition, a zinc oxide based semiconductor has an energy gap between a valence band and a conduction band of about 3 eV, and is expected to exhibit excellent dielectric breakdown voltage characteristics.

  Here, an example of a conventional ZnO transistor will be described with reference to FIG. 10A and 10B are explanatory views of the structure of a conventional ZnO transistor. FIG. 10A is a plan view of the main part, and FIG. 10B is along the alternate long and short dash line connecting AA 'in FIG. FIG.

  In this ZnO transistor, a gate insulating film 32 is formed on a substrate to be a gate electrode 31, a ZnO polycrystalline film is formed thereon, and then patterned to be electrically isolated as a ZnO channel region 33. . Next, a source electrode 34 and a drain electrode 35 are formed so as to cover both ends of the ZnO channel region 33, thereby manufacturing a transistor.

JP 2012-019682 A JP 2008-537631 A

  The switching power supply transistor and the display driving transistor are required to have a characteristic that current is not passed when the threshold voltage is controlled and the gate voltage is set to 0V. The threshold value of the ZnO-based transistor is controlled by changing the carrier concentration.

  However, this carrier concentration is caused by oxygen vacancies in the ZnO-based semiconductor, and it is difficult to control the oxygen vacancies, and therefore there is a problem that threshold control is difficult.

  Therefore, it aims at improving the controllability of the threshold value of a zinc oxide semiconductor transistor.

  From one disclosed aspect, a substrate having a flat surface, an insulating film formed on the substrate, an island-shaped channel forming layer made of a zinc oxide-based semiconductor formed on the insulating film, and the channel forming layer A source electrode and a drain electrode formed thereon, and a residual stress in an intrinsic channel region between the source electrode and the drain electrode is greater than a residual stress in a peripheral portion outside the intrinsic channel region A zinc oxide based semiconductor transistor is provided.

  According to the disclosed zinc oxide based semiconductor transistor, the controllability of the threshold value of the zinc oxide based semiconductor transistor can be improved.

1 is a configuration explanatory diagram of a zinc oxide based semiconductor transistor according to an embodiment of the present invention. It is explanatory drawing of the definition of the distance in a measurement. It is a transfer characteristic figure of the zinc oxide system semiconductor transistor of an embodiment of the invention. It is explanatory drawing of the distance dependence of the ON voltage of the zinc oxide type semiconductor transistor of embodiment of this invention. It is a structure explanatory drawing of the ZnO transistor of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the ZnO transistor of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 6 of the manufacturing process of the ZnO transistor of Example 1 of this invention. It is explanatory drawing after FIG. 7 of the manufacturing process of the ZnO transistor of Example 1 of this invention. It is a structure explanatory drawing of the ZnO transistor of Example 2 of this invention. It is structure explanatory drawing of the conventional ZnO transistor.

  Here, with reference to FIG. 1 thru | or FIG. 4, the zinc oxide type semiconductor transistor of embodiment of this invention is demonstrated. FIG. 1 is a diagram illustrating the configuration of a zinc oxide based semiconductor transistor according to an embodiment of the present invention, in which a channel forming layer 3 made of a zinc oxide based semiconductor is provided on a substrate 1 with an insulating film 2 interposed therebetween. A source electrode 4 and a drain electrode 5 are formed. Here, a region connecting the outer frames of the source electrode 4 and the drain electrode 5 surrounded by a broken line is defined as an intrinsic channel region 6.

  When the substrate 1 has an inverted staggered configuration, a conductive semiconductor substrate such as a conductive silicon substrate or a metal substrate such as an aluminum substrate is used and the substrate 1 is used as a gate electrode. On the other hand, in the case of a forward staggered configuration, the substrate may be a conductive substrate or an insulating substrate. For example, a polyimide film may be used.

  As the zinc oxide-based semiconductor, an oxide semiconductor containing ZnO as a maximum component is used, which is typically ZnO or ZnMgO, but an In—Sn—Ga—Zn—O-based oxide semiconductor, In—Ga— Zn-O-based oxide semiconductor, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn- O-based oxide semiconductor, Sn-Al-Zn-O-based oxide semiconductor, In-Hf-Zn-O-based oxide semiconductor, In-La-Zn-O-based oxide semiconductor, In-Ce-Zn-O Oxide semiconductor, In—Pr—Zn—O oxide semiconductor, In—Nd—Zn—O oxide semiconductor, In—Pm—Zn—O oxide semiconductor, In—Sm—Zn—O oxide Semiconductor, In-Eu-Zn-O-based oxide semiconductor In-Gd-Zn-O-based oxide semiconductor, In-Tb-Zn-O-based oxide semiconductor, In-Dy-Zn-O-based oxide semiconductor, In-Ho-Zn-O-based oxide semiconductor, In- Er-Zn-O-based oxide semiconductors, In-Tm-Zn-O-based oxide semiconductors, In-Yb-Zn-O-based oxide semiconductors, In-Lu-Zn-O-based oxide semiconductors, binary systems An In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, or an Al—Zn—O-based oxide semiconductor that is a metal oxide may be used.

  Such a zinc oxide based semiconductor has orientation and exhibits a large piezoelectric effect. As a method for forming the zinc oxide-based semiconductor film, for example, a high-frequency sputtering method, an atomic layer deposition method, or a pulse laser deposition method can be used. The c-axis alignment film is oriented in the direction.

When the insulating film 2 is used as a gate insulating film, silicon oxide (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), polyimide, hafnium oxide ( HfO ₂ ) may be used.

  As the source electrode 4 and the drain electrode 5, titanium (Ti), gold (Au), aluminum (Al), molybdenum (Mo), ZnO, InZnO, or InGaZnO may be used. A similar material may be used for the gate electrode in the case of a forward staggered configuration. In addition, as a formation method of the source electrode 4 and the drain electrode 5, various vapor deposition methods can be used, for example, an electron beam vapor deposition method and a thermal resistance heating vapor deposition method can be used.

  A zinc oxide-based semiconductor is a substance having a large piezoelectric effect, and an electric charge is induced on a surface or an interface by applying a stress. Stress is applied to the zinc oxide-based semiconductor due to the difference in thermal expansion coefficient from the substrate, but when the zinc oxide-based semiconductor is made into an island shape, the stress is relieved by deformation at the end, and the stress is applied to the central portion. It will be in the state where it took. Therefore, in the case of a narrow island-shaped region in which the entire conventional island-shaped region becomes a channel region, the stress is relaxed and hardly applied.

On the other hand, as shown in FIG. 1, by performing device isolation wider than the intrinsic channel region 6 of the transistor, residual stress can be generated in the intrinsic channel region 6, thereby causing negative charges in the intrinsic channel region 6. Can be induced to shift the threshold value V _th (V _on ) in the positive direction.

  FIG. 2 is an explanatory diagram of the definition of the distance (d) when measuring the transfer characteristic of the zinc oxide based semiconductor transistor, and the distance from the center line in the channel length direction of the intrinsic channel region 6 is defined as d [μm]. To do. 2A is a plan view of the main part, and FIG. 2B is a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG.

FIG. 3 is a transfer characteristic diagram of a zinc oxide based semiconductor transistor. Here, the measurement was performed with the substrate being a silicon substrate and the zinc oxide based semiconductor being ZnO having a thickness of 20 nm. As shown in the figure, the threshold value _Vth shifts in the positive direction as the distance d increases, and is almost saturated at d = 53.6 μm. The characteristic of d = 64.5 μm was also measured, but the illustration is omitted because it is indistinguishable from d = 101.6 μm.

FIG. 4 is an explanatory diagram of the distance dependence of the on-voltage V _on of the zinc oxide based semiconductor transistor according to the embodiment of the present invention, and represents FIG. 3 from another viewpoint. As shown in the figure, there is a tendency to saturate from d≈50 μm. Therefore, a stable improvement effect can be obtained by setting the distance d [μm] from the center line of the intrinsic channel region 6 in the channel length direction to the end of the channel formation layer 3 to 50 μm or more.

Note that the stress applied to the zinc oxide based semiconductor film depends on the film thickness and is inversely proportional to the film thickness. Therefore, when the thickness of the channel formation layer is t [nm],
d ≧ 50 × (20 / t)
You can do it. Also, the distance d ′ [μm] in the channel width direction is
d ′ ≧ 50 × (20 / t)
This makes it possible to obtain uniform characteristics along the channel width direction.

  This relationship is the same except for the combination of the silicon substrate and the ZnO film. However, since the relationship of the thermal expansion coefficient is different, the distance d dependence of the transfer characteristic is measured and empirically determined. A distance that can be regarded as saturation in is sufficient.

  Since such a zinc oxide based semiconductor transistor is transparent to visible light and has a high breakdown voltage, it is suitable as a driving transistor for a large flat panel display having one pixel.

  Next, a ZnO transistor according to Example 1 of the present invention will be described with reference to FIGS. FIG. 5 is a configuration explanatory view of a ZnO transistor according to the first embodiment of the present invention, FIG. 5 (a) is a plan view of a main part, and FIG. 5 (b) is an AA ′ in FIG. 5 (a). It is sectional drawing along the dashed-dotted line which connects.

As shown in FIG. 5, an island-like region 14 made of ZnO having a thickness of 20 nm is provided on a silicon substrate 11 serving as a gate electrode through a SiO ₂ gate insulating film 12 having a thickness of 100 nm to form a channel formation layer. . The size of this island-shaped region is 200 μm × 143 μm. Next, a source electrode 16 and a drain electrode 17 made of Ti and Au having a thickness of 10 nm and 100 nm and a size of 100 μm × 20 μm are formed. A rectangular region indicated by a broken line connecting the outer frame of the source electrode 16 and the drain region 17 is an intrinsic channel region 15. Here, the distance between the end of the intrinsic channel region 15 in the channel length direction and the end of the island region 14 is 50 μm, and the distance between the end of the intrinsic channel region 15 and the end of the island region 14 in the channel width direction is 50 μm.

Next, with reference to FIGS. 6 to 8, a manufacturing process of the ZnO transistor according to the first embodiment of the present invention will be described. In addition, in each figure, figure (a) is a principal part top view, and figure (b) is sectional drawing along the dashed-dotted line which connects AA 'in figure (a). First, as shown in FIG. 6, the silicon substrate 11 is thermally oxidized on the silicon substrate 11 to form a SiO ₂ gate insulating film 12 having a thickness of 100 nm. Next, a ZnO polycrystalline film 13 having a thickness of 20 nm is formed using an atomic layer deposition method (ALD method). The ZnO polycrystalline film 13 is a film naturally c-axis oriented.

  Next, as shown in FIG. 7, the ZnO polycrystalline film 13 is patterned into a rectangular shape with a size of 200 μm × 143 μm by using a photolithography technique and an etching technique to form an island-like region 14 that becomes a channel formation layer.

  Next, as shown in FIG. 8, the source electrode 16 and the drain electrode 17 made of Ti and Au having a thickness of 10 μm and 100 nm and a size of 100 μm × 20 μm are formed by using a photolithography technique and a lift-off technique. The basic structure of one ZnO transistor is completed. Note that an electron beam evaporation method is used as a method for forming the Ti and Au films.

  As described above, in the first embodiment of the present invention, the island-shaped region 14 is larger than the intrinsic channel region 15, that is, wider than the intrinsic channel region 15, so that the charge is reproduced in the intrinsic channel region 15. It remains significantly in good character and the threshold value shifts positively.

  Next, a ZnO transistor according to Example 2 of the present invention will be described with reference to FIG. 9. This Example 2 has a forward stagger type structure. FIG. 9 is a configuration explanatory view of the ZnO transistor according to the first embodiment of the present invention, FIG. 9A is a plan view of a main part, and FIG. 9B is an AA ′ in FIG. 9A. It is sectional drawing along the dashed-dotted line which connects.

As shown in FIG. 9, a SiO ₂ film 22 is formed on the surface of a silicon substrate 21 by thermal oxidation, and a ZnO polycrystalline film having a thickness of 20 nm is deposited thereon by high frequency sputtering. Next, the ZnO polycrystalline film is patterned into a rectangular shape having a size of 200 μm × 143 μm by using a photolithography technique and an etching technique to form island-like regions 23 that become channel forming layers.

Next, a source electrode 26 and a drain electrode 27 made of Ti and Au having a thickness of 10 nm and 100 nm and a size of 100 μm × 20 μm are formed by using a photolithography technique and a lift-off technique. Next, a SiN (Si ₃ N ₄ ) gate insulating film 24 having a thickness of 30 nm is formed by plasma CVD. Here, the SiN film covering the source electrode 26 and the drain electrode 27 is not shown.

  Next, the gate electrode 25 in which Ti (thickness is 50 nm) and Au (thickness is 100 nm) having a size of 100 μm × 1 μm is formed again by using the photolithography technique and the lift-off technique, thereby implementing the present invention. The basic configuration of the ZnO transistor of Example 2 is completed.

  In Example 2 of the present invention, the structure is a forward stagger type structure. However, since the device isolation is larger than that in the intrinsic channel region 28, the charge remains in the intrinsic channel region 28 with good reproducibility. The threshold shifts positive.

Here, the following supplementary notes are attached to the embodiments of the present invention including Example 1 and Example 2.
(Appendix 1) A substrate having a flat surface, an insulating film formed on the substrate, an island-shaped channel forming layer made of a zinc oxide-based semiconductor formed on the insulating film, and formed on the channel forming layer A residual stress in an intrinsic channel region between the source electrode and the drain electrode is greater than a residual stress in a peripheral portion outside the intrinsic channel region. Zinc oxide based semiconductor transistor.
(Supplementary note 2) The zinc oxide based semiconductor transistor according to supplementary note 1, wherein the substrate is a gate electrode and the insulating film is a gate insulating film.
(Appendix 3) The substrate is either a conductive semiconductor substrate or a metal substrate, and the insulating film is any one of SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ , AlN, HfO ₂ or polyimide. The zinc oxide-based semiconductor transistor according to appendix 2, characterized by:
(Supplementary note 4) The oxidation according to supplementary note 1, wherein a gate insulating film is provided on the channel formation layer between the source electrode and the drain electrode, and a gate electrode is provided on the gate insulating film. Zinc-based semiconductor transistor.
(Supplementary Note 5) The substrate is a silicon substrate, and the distance d [μm] from the center line in the channel length direction of the intrinsic channel region to the end of the channel formation layer indicates the thickness of the channel formation layer t [ nm]
d ≧ 50 × (20 / t)
The zinc oxide-based semiconductor transistor according to any one of appendix 1 to appendix 3, wherein
(Supplementary Note 6) The distance d ′ [μm] from the end of the intrinsic channel region in the channel width direction to the end of the channel forming layer is d ′ ≧ 50 × (20 / t)
The zinc oxide-based semiconductor transistor according to appendix 5, wherein
(Supplementary note 7) The zinc oxide-based semiconductor transistor according to any one of supplementary notes 1 to 6, wherein the zinc oxide-based semiconductor is an oxide semiconductor containing ZnO as a maximum component.
(Supplementary note 8) A flat panel display using the zinc oxide semiconductor transistor according to any one of supplementary notes 1 to 3 as a pixel switching transistor.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating film 3 Channel formation layer 4 Source electrode 5 Drain electrode 6 Intrinsic channel region 11 Silicon substrate 12 SiO ₂ Gate insulating film 13 ZnO polycrystalline film 14 Island-like region 15 Intrinsic channel region 16 Source electrode 17 Drain electrode 21 Silicon substrate 22 SiO ₂ film 23 Island-like region 24 SiN gate insulating film 25 Gate electrode 26 Source electrode 27 Drain electrode 28 Intrinsic channel region 31 Gate electrode 32 Gate insulating film 33 ZnO channel region 34 Source electrode 35 Drain electrode

Claims (7)

A substrate with a flat surface;
An insulating film formed on the substrate; and an island-shaped channel forming layer made of a zinc oxide-based semiconductor formed on the insulating film;
A source electrode and a drain electrode formed on the channel formation layer;
A zinc oxide based semiconductor transistor, wherein a residual stress in an intrinsic channel region between the source electrode and the drain electrode is larger than a residual stress in a peripheral portion outside the intrinsic channel region. The substrate is a gate electrode, and
The zinc oxide based semiconductor transistor according to claim 1, wherein the insulating film is a gate insulating film.   The zinc oxide semiconductor transistor according to claim 1, wherein the substrate is any one of a conductive semiconductor substrate, a metal substrate, and a polyimide film. Providing a gate insulating film on the channel formation layer between the source electrode and the drain electrode;
2. The zinc oxide based semiconductor transistor according to claim 1, wherein a gate electrode is provided on the gate insulating film. The substrate is a silicon substrate;
When the distance d [μm] from the center line in the channel length direction of the intrinsic channel region to the end of the channel formation layer is the thickness of the channel formation layer t [nm],
d ≧ 50 × (20 / t)
The zinc oxide based semiconductor transistor according to any one of claims 1 to 3, wherein 6. The zinc oxide according to claim 1, wherein the insulating film is one of SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ , AlN, HfO _2, or polyimide. Semiconductor transistor.   The zinc oxide based semiconductor transistor according to any one of claims 1 to 6, wherein the zinc oxide based semiconductor is a polycrystalline film having c-axis orientation.

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