JP2014075694A - Gate driver and switching method - Google Patents

Abstract

A gate driver that eliminates the need for a gate resistor and reduces power consumption is provided.
A gate driver includes a drive control unit and a gate drive unit. Upon receiving the control signal for switching the power transistor to the conductive state, the drive control unit 10 switches the drive signal from the first level to the second level, and switches the drive signal to the first level after the first period has elapsed. Further, control is performed so as to switch to the second level after the second period has elapsed. When the control signal for switching the power transistor to the cut-off state is received, the drive signal is switched from the second level to the first level, the drive signal is switched to the second level after the third period has elapsed, and the fourth period Control to switch to the first level after elapse. The gate driver 40 amplifies and outputs the drive signal.
[Selection] Figure 1

Description

  The present invention relates to an apparatus for driving a power transistor such as an inverter / converter.

In recent years, it has been desired to reduce the power consumption of the power control circuit and the circuit area. For example, Patent Document 1 discloses a simple and stable power source without preparing a dedicated power source as a power source for an upper arm driving circuit for supplying a gate signal to the main IGBT 21 of the inverter upper arm in a MOS gate driving power IC. There is disclosed a gate drive circuit having: Patent Document 2 discloses a technique for switching the drive circuit before the surge voltage is generated and shortening the turn-off time without being affected by variations in the threshold voltage of the power MOS.
In a conventional power control circuit such as an inverter or converter, a gate resistor is provided between the gate terminal of a power transistor such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOS and the output terminal of a gate driver. The role of the gate resistance is, for example, the following two points.
(A) To suppress overshoot / undershoot and ringing of the gate voltage due to the influence of the parasitic inductance.
(B) The slew rate of the voltage or current applied between the emitter and collector (or between the drain and source) of the power transistor is suppressed to an appropriate value.
A power control circuit having such a gate resistor has the following problems, for example.
First, a switching loss occurs in a power transistor such as an IGBT or a power MOS (first problem).
Second, Joule loss due to gate resistance occurs (second problem).
Third, the gate resistance must be prepared as an external component (third problem).

On the other hand, when trying to realize a power control circuit that reduces power consumption and circuit area by a configuration that does not include a gate resistor, another problem occurs as described below, and it is necessary to solve these problems. Become.
-Gate voltage overshoot, undershoot, and ringing occur due to the parasitic inductance (L _{G in} FIG. 1) (first problem).
-Since the slew rate of the current flowing through the power transistor is not limited, a large surge voltage is generated (second problem), and the radiation noise generated by the inverter increases when the power transistor is destroyed (third problem) It is a problem.

JP 2004-304527 A JP 2001-45742 A

  However, an effective means for the problem caused by removing the gate resistance from the power control circuit has not been found. For example, Patent Documents 1 and 2 are not techniques focused on removing gate resistance.

The inventors have found a gate driver that does not have a gate resistance and can reduce power consumption.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  When the gate driver of one embodiment receives a control signal for switching the power transistor to the conductive state or the cut-off state, the gate driver switches a signal level after a lapse of a predetermined period to generate a drive signal that forms a pulse having a reverse polarity with a predetermined width. Output to the power transistor.

  According to one embodiment, it is possible to provide a gate driver that includes a gate resistor and can reduce power consumption.

It is a block diagram which shows the structural example of the gate driver of one Embodiment. It is a figure which shows the structural example of the power control circuit which has gate resistance. It is a timing chart which shows the fluctuation of voltage and current, and power loss when IGBT changes between an ON state and an OFF state. It is a figure which shows the structural example of the power control circuit which is not provided with a gate resistance. It is a timing chart which shows the example of a fluctuation | variation of the gate voltage of the power transistor of the power control circuit which is not provided with a gate resistance. It is a figure which shows an example of the voltage in the electric power control circuit which is not provided with gate resistance, and an electric current. FIG. 3 is a diagram illustrating a configuration example of a power control circuit including the gate driver according to the first embodiment. 4 is a timing chart showing voltage and current fluctuations of the power control circuit according to the first embodiment. It is a figure which shows the other structural example of a power control circuit provided with the gate driver of the other structural example of Embodiment 1. FIG. It is a figure which shows the example of a waveform of a voltage and an electric current when a power transistor is changed to an ON state. It is a figure which shows the example of a waveform of a voltage and an electric current when a power transistor is changed to an OFF state. It is a figure explaining the characteristic of the switching system which the power control circuit using a gate resistance implements. It is a figure explaining the characteristic of the switching system which the power control circuit of Embodiment 1 implements. It is a figure explaining the switching time of one Embodiment. It is a figure which compares and demonstrates the fluctuation | variation of the voltage and electric current of the power control circuit of one Embodiment, and another power control circuit. It is a figure explaining the structure in which the power control circuit of one Embodiment reduces power consumption, without generating Joule loss. It is a figure which shows the structural example of the gate driver which has an active mirror clamp and uses the gate resistance _RG . It is a figure explaining the function of the active mirror clamp in the gate driver of one Embodiment. It is a figure explaining the method of determining the pulse width of a drive signal. It is a figure explaining an example of the procedure which adjusts the pulse width of a drive signal. It is another figure explaining an example of the procedure which adjusts the pulse width of a drive signal. It is a figure which shows the structural example of a power control circuit provided with the function to adjust a pulse width. It is a figure explaining the relationship between the drive signal of the gate driver of one Embodiment, and the slew rate of the gate voltage of a power transistor. It is a figure explaining the relationship between a slew rate and an overshoot. It is a diagram illustrating a method to reduce the gate voltage V _GE, the convergence of the gate current I _G in a simpler way. FIG. 10 is a diagram illustrating a configuration example of a gate driver that uses a gate resistor and has a slew rate adjustment function. FIG. 5 is a diagram illustrating a configuration example of a gate driver according to an embodiment and including a slew rate adjustment function. It is a figure which shows an example of the power control circuit comprised from the gate driver which has a function which adjusts a pulse width. It is a figure which shows the other example of the power control circuit comprised from the gate driver which has the function to adjust a pulse width. It is a figure which shows the further another example of the power control circuit comprised from the gate driver which has the function to adjust a pulse width.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  When the gate driver of one embodiment receives a control signal for switching the power transistor to an ON state (conduction state) or an OFF state (blocking state, non-conduction state), the gate driver switches the signal level after a predetermined period of time A drive signal (gate drive signal) in which a pulse having a width is formed is output to the power transistor. FIG. 1 is a schematic diagram illustrating a configuration example of a gate driver. The gate driver 1 includes a drive control unit 10 and a gate drive unit 40. The drive signal is a signal for controlling the gate voltage so that the power transistor is switched to the ON state or the OFF state.

  The drive control unit 10 receives a control signal from the input terminal 2 and generates a drive signal in which a reverse polarity pulse is generated by switching the signal level for a predetermined period with respect to the signal level for controlling the ON state or the OFF state. To control. Specifically, when receiving a control signal for switching the power transistor to the ON state, the drive control unit 10 switches the drive signal from the first level to the second level, and the drive signal is changed to the first signal after the first period. Control is performed so as to switch to the first level and to switch to the second level after the second period. On the other hand, when receiving a control signal for switching the power transistor to the OFF state, the drive control unit 10 switches the drive signal from the second level to the first level, and the drive signal is switched to the second level after the third period has elapsed. And after the fourth period, the first level is switched. For example, the first level is a high level and the second level is a low level.

For example, the drive control unit 10 is realized by the timing control unit 20 and the logic unit 30.
The timing control unit 20 detects the timing at which the first to fourth periods have elapsed, and instructs the logic unit 30 to switch the signal level of the drive signal at the detected timing.
The logic unit 30 switches the drive signal between the first level and the second level according to the signal output from the timing control unit 20.
The first to fourth periods are predetermined periods. The first to fourth periods are used as parameters for determining the pulse width because the signal level of the drive signal is switched after the period has elapsed.

The gate drive unit 40 amplifies the drive signal output from the drive control unit 10 and outputs the amplified drive signal from the output terminal 3 to the power transistor.
For example, the gate driving unit 40 is realized by the first switch unit 41 and the second switch unit 42. The gate driving unit 40 turns on one of the first and second switch units 41 and 42 to amplify and output the driving signal.
In FIG. 1, the left waveform of the gate driver 1 shows an example of a control signal, and the right waveform shows an example of a drive signal.

The drive control unit 10 and the gate drive unit 40 will be described with reference to specific configurations in each embodiment.
In describing an embodiment, first, the problems of the conventional technology will be described with reference to the drawings, and then the embodiment will be described with a specific configuration.

First, a power control circuit including a gate resistor will be described with reference to FIG. The power control circuit 93 shows a configuration example including a gate driver 91, a power transistor 90, and a gate resistor _RG . As shown in FIG. 2, in the power control circuit 93 such as an inverter or a converter, a gate resistor _RG is provided between the gate terminal of a power transistor 90 such as an IGBT or a power MOS and the output terminal of the gate driver 91. The role of the gate resistor R _G, as described above, the parasitic inductance L _G effect to suppress the overshoot, undershoot and ringing of the gate voltage V _GE by the, and the emitter of the power transistor 90 - collector (or drain - The slew rate of the voltage or current applied between the sources is suppressed to an appropriate value.

In the power control circuit 93 shown in FIG. 2, it has been explained that there are mainly three problems. Hereinafter, these problems will be described in detail.
First, the first problem, that switching loss of a power transistor such as an IGBT or a power MOS occurs, will be described. The power transistor 90 is normally used in an ON state or an OFF state. In the ON state, the collector-emitter or drain-source resistance is several mΩ to several tens mΩ. A current flows in the ON state, the collector - emitter or drain - becomes the voltage V _CE is approximately zero between the source. Therefore, the power loss P _LOSS = V _CE × I _CE of the power transistor is not so large. Further, in the OFF state collector - emitter or drain - power loss does not occur because the current I _CE between the source is zero. On the other hand, when the power transistor 90 makes a transition from the OFF state to the ON state, or when the power transistor 90 makes a transition from the ON state to the OFF state, the half ON state is entered. The half ON state is a state between the ON state and the OFF state. In this half-ON state, both the collector-emitter or drain-source voltage V _CE and the current I _CE are applied. For this reason, the power transistor power loss P _LOSS = V _CE × I _CE increases momentarily.

FIG. 3 is a timing chart showing voltage / current fluctuations and power loss when an IGBT as an example of the power transistor 90 transitions between an ON state and an OFF state. The gate voltage V _GE of the power transistor 90 varies according to the gate driver output voltage _VOUT . Power loss occurs in the half ON state period TR in which the power transistor 90 transitions to the ON state and the half ON state period TF in which the power transistor 90 transitions to the OFF state. Therefore, the power loss of the power transistor 90 is proportional to the length of the half-ON period and the switching frequency. The frequency of switching is determined by the modulation frequency of the inverter and cannot be changed. The length of the half-ON period is determined by the time for charging and discharging the gate voltage V _GE of the power transistor 90. For this reason, it depends on the magnitude of the gate resistance _RG . That is, if the gate resistance _RG is large, the power loss (switching loss) generated when the power transistor 90 is switched increases. In other words, the rise of the gate voltage V _GE is slow period TR or TF half ON state becomes longer, the power loss increases. Thus, the problem is that the power loss of the power transistor 90 during switching is large.

Next, the second problem, generation of Joule loss (gate drive loss) due to the gate resistance _RG will be described. Each time the charge and discharge the gate of the power transistor 90, for example, the gate current _{I G} flows of 2A～4A, Joule loss occurs due to the gate resistor _{R G.} As an example, in a gate driver that drives an IGBT having a gate voltage V _GE = 15 [V] and a gate charge Q _G = 6000 [nQ], Joule loss in which gate resistance is generated by one charge / discharge is C _{GE. ^{V G 2/2 = Q G}} V G / 2 = 45 [uJ], a 90 [uJ] in the charge-discharge cycle. In an inverter with a PWM modulation frequency of 20 kHz, the loss due to the gate resistance _RG is 90 [uJ] × 20 kHz = 1.8 W, resulting in a power loss that cannot be ignored. Therefore, since it is necessary to prepare a heat dissipation measure and a power supply circuit, it is desirable to suppress the Joule loss of the gate resistance _RG from the viewpoint of cost.

Finally, the third problem, that the gate resistance _RG must be prepared as an external component, will be described. As described above, the gate resistance _RG loses about 0.5 W to 2 W of power. For this reason, the gate resistance is usually not built in an IC (Integrated Circuit) (the loss is too large for the resistance element built in the IC) and is mounted as an independent external component. In addition, since an appropriate value of the gate resistance _RG needs to be adjusted according to the IGBT to be connected, the length of the gate wiring, and the like, the gate resistance _RG is not usually built in the IC. For this reason, the component cost of the gate resistance _RG , the mounting area of the board, and the design cost of the inverter manufacturer are required.

On the other hand, when the gate resistance _RG is removed from the power control circuit 93, the first to third problems described above seem to improve, but another problem occurs as described above. . A new problem will be described below. FIG. 4 shows a configuration example of a power control circuit without a gate resistor.
First, the power control circuit 95, the parasitic inductance L _G of the gate wiring, the overshoot of the gate voltage, undershoot, ringing occurs (first problem). If the overshoot in the ON state of the power transistor 90 exceeds the rated voltage, the gate is destroyed. On the other hand, ringing in the OFF state causes an unintended ON state. In the power control circuit 93 of FIG. 2, the gate resistance _RG functions as a damping element, and suppresses overshoot and undershoot. FIG. 5 shows a timing chart showing an example of fluctuations in the gate voltage of the power transistor 90 of the power control circuit 95 having no gate resistance. When the gate driver output voltage _VOUT rises, the gate voltage V _GE of the power transistor 90 causes overshoot, and an unrated voltage is applied to the gate voltage V _GE, which may cause destruction. Further, when the gate driver output voltage _VOUT drops, the gate voltage V _GE of the power transistor 90 drops, causing undershoot and ringing. In such a case, when the voltage fluctuates in the vicinity of the threshold value VTH, the power transistor 90 is unintentionally switched between ON and OFF. As shown in FIG. 5, the rise and fall of the power transistor is accelerated and the periods TR and TF shown in FIG. 3 are shortened, but there is a problem that breakdown due to an unrated voltage or unintended ON / OFF switching occurs. There is.

Next, in the power control circuit 95, a second problem that occurs because the current slew rate (dI _CE / dt) flowing through the power transistor 90 is not limited will be described.
2 and 4, when the load _RL is an inductive load (V = LdI / dt) such as a motor or a coil, the collector-emitter of the power transistor 90 is caused by a large current slew rate dI _CE / dt. A large surge voltage appears in the inter-or drain-source voltage V _CE . As a result, the current slew rate (dI _CE / dt) increases. This, in the power control circuit 93 and 95, change in the gate voltage _{V GE} and no gate resistance _{R G} is small or the gate resistance _{R G} is because steeper. The voltage change at this time is shown in FIG. In FIG. 6, the power transistor gate voltage V _GE (one-dot broken line), collector-emitter or drain-source current I _CE (broken line) and voltage V _CE (solid line), and current slew rate (dI _CE / dt). (Dotted line) is shown. Collector - emitter or drain - voltage V _CE between the source is a case where the surge voltage shown by the arrow has occurred, it shows an ideal voltage V _CE with a dotted line.
If this surge voltage exceeds the rated voltage, the power transistor 90 may be destroyed.
The overshoot of the collector-emitter voltage or the drain-source voltage _VCE increases due to the inductive load of the load _RL . At this time, if the collector-emitter or drain-source voltage _VCE exceeds the rated voltage, the power transistor 90 does not operate normally.

In addition, if the current slew rate (dI _CE / dt) flowing through the power transistor 90 is not limited, radiation noise (EMI) generated by a power control circuit such as an inverter increases (third problem).
Since the above-described problem occurs, there is a limit in reducing the resistance value of the gate resistance _RG . The appropriate gate resistance _RG depends on the electrical characteristics and load of the IGBT.

In response to the above-described problems and new problems, in one embodiment, the power control circuit does not include the gate resistance _RG , and the problem that occurs when the gate resistance _RG is not included is solved. Provided is a power transistor for reducing power consumption. A schematic configuration example of the power transistor is as shown in FIG. The power control circuit using the gate driver 1 of FIG. 1 reduces the switching loss and Joule loss by eliminating the gate resistance _RG . In addition, the cost caused by providing the gate resistance _RG can be reduced. In addition, by having a configuration in which a pulse of reverse polarity is inserted into the drive signal, the occurrence of overshoot, undershoot and ringing of the gate voltage is suppressed, and the slew rate of the current flowing through the power transistor is controlled. Realize. Details will be described below with reference to a specific configuration.

Embodiment 1. FIG.
FIG. 7 is a diagram illustrating a configuration example of a power control circuit including the gate driver according to the first embodiment.
The power control circuit 101 includes a power transistor 90 and a gate driver (switching circuit) 100. No gate resistance is provided between the power transistor 90 and the gate driver 100. A control signal is input from the outside to the gate driver 100 from the input terminal IN, and a drive signal is output from the output terminal OUT.
The power transistor 90 is configured by, for example, an IGBT or a power MOS. In the present embodiment, the description will be made on the assumption that the power transistor 90 is composed of an IGBT. In the drawings referred to in the following description, for ease of explanation, components related to the gate driver 100 for the power transistor 90 are shown, and components such as the load _RL may be omitted as appropriate.
The gate driver 100 includes a drive control unit 110 having a timing circuit (timing control unit) 121 and logic circuits (logic units) 131 and 132, a first transistor (first switch unit) 141, and a second transistor (second switch unit). ) 142 having a gate driver 140.
The drive control unit 110 and the gate drive unit 140 are a configuration example for realizing the drive control unit 10 and the gate drive unit 40 of FIG.

When the timing circuit 121 receives a control signal for switching the power transistor 90 to the ON state, the timing circuit 121 notifies the logic circuits 131 and 132 when the first period elapses from when the control signal is received, and then the second period. Is passed to the logic circuits 131 and 132 again. In addition, when receiving a control signal for switching the power transistor 90 to the OFF state, the timing circuit 121 notifies the logic circuits 131 and 132 when the third period elapses from when the control signal is received, and then the fourth circuit. When this period elapses, the logic circuits 131 and 132 are notified again.
The output of the logic circuit 131 is connected to the gate of the first transistor 141. The output of the logic circuit 132 is connected to the gate of the second transistor 142. The logic circuits 131 and 132 output the input control signal to the gate of the first transistor 141. In addition, the logic circuits 131 and 132 switch the level of the control signal according to the passage of the first to fourth periods notified from the timing circuit 121.

The first and second transistors 141 and 142 are configured to switch between an ON state and an OFF state in accordance with a control signal output from the logic circuits 131 and 132. The first transistor 141 includes a PMOS transistor having a source terminal connected to the power supply VCC, a drain terminal connected to the second transistor 142, and a gate terminal connected to the logic circuit 131. The second transistor 142 includes an NMOS transistor having a source terminal connected to the ground GND, a drain terminal connected to the first transistor, and a gate terminal connected to the logic circuit 132. The voltage of the gate driver output voltage VOUT is determined according to the ON state of the first and second transistors.
The power control circuit 101 shows a configuration example in which a gate resistor is not used, but is not limited thereto. The gate driver of one embodiment (including this embodiment and each of the embodiments described below) is also used in a power control circuit that uses a gate resistor whose gate resistance is much smaller than that of a conventional power control circuit. Applicable. The very small resistance value is, for example, a value that causes the first to third problems when there is no gate resistance described above.

FIG. 8 is a timing chart showing voltage and current fluctuations of the power control circuit of the first embodiment. In FIG. 8, the first to fourth periods are indicated as periods Ta, Tb, Tc, and Td, respectively.
When the power transistor 90 is changed to the ON state (turned on), the gate driver 100 changes the drive signal from the first level to the second level, and then temporarily changes to the first level when the period Ta elapses. return. Furthermore, when the period Tb elapses, the second level is restored. Further, when the power transistor is shifted to the OFF state (turned off), the gate driver 100 changes the drive signal from the second level to the first level, and then temporarily changes to the second level when the period Tc elapses. Return to. Further, when the period Td elapses, the first level is restored.

For example, the gate driver output voltage _{V OUT} gate current (gate drive current) _{I G} increases it's high level period Ta. The influence of the parasitic inductances L _G, the gate current I _G was increased once does not decrease unless the voltage level of the gate driver output voltage V _OUT to be lower than the gate voltage V _GE. Therefore, when the left gate voltage V _GE gate current I _G is greater it has reached the desired voltage, the charge on the gate is continuously supplied, then the gate voltage V _GE causes an overshoot. In order to avoid this, the voltage level of the gate driver output voltage _VOUT is set to the low level during the period Tb so that the gate current _IG becomes zero in accordance with the timing when the gate voltage V _GE reaches the desired voltage level. This reduces the gate current I _G gradually, the gate current I _G is zero by the time period Tb is completed, the gate voltage V _GE has reached the desired voltage level. Period to attenuate the gate current I _G Tb, the case without the Td, the gate voltage V _GE is as shown in FIG. 5, the overshoot waveform repeating undershoot. As shown in FIG. 8, the time (length) of each of the periods Ta to Td is a parameter that determines the pulse width.

In addition, FIG. 8 shows ON / OFF states of the first and second switch units, specifically, the first and second transistors 141 and 142 constituting the gate driving unit 140. FIG. 8 shows the ON state as a high level and the OFF state as a low level. As shown in FIG. 8, the first and second switch units are configured such that one of them is in an ON state and the other is in an OFF state in response to a signal from the drive control unit 110. By configuring so that one of the first and second switch sections is in the ON state, the gate driver 100 and the power transistor 90 can be connected to each other when the drive signal is at the first or second level. This ensures current flow. In other words, the drive signal is in each case the first and second level, it is possible to secure the flow of current in the parasitic inductance L _G. As a result, the gate current once increased can be actively reduced. As a result, the peak value of the gate current can be increased, so that the switching time can be shortened.

FIG. 9 shows a configuration example of a power control circuit including a gate driver having another circuit configuration according to the first embodiment.
The power control circuit 201 includes a power transistor 90 and a gate driver 200. The configuration other than the gate driver 200 is the same as that in FIG.
The gate driver 200 includes a drive control unit 210 having timing circuits 221 to 224 and logic circuits 231 to 233, and a gate drive unit 240 having first transistors 241, second transistors 242, and NOT circuits 243 and 244.
The drive control unit 110 and the gate drive unit 140 are a configuration example for realizing the drive control unit 10 and the gate drive unit 40 of FIG.
The timing circuit 221 includes a delay element that receives a control signal input from the input terminal IN and outputs a first delay signal obtained by delaying the control signal by a time period Ta. The timing circuit 223 is the same as the timing circuit 221 except that the third delay signal obtained by delaying the control signal by the time period Tc is output.
The timing circuit 222 includes a delay element that receives the first delay signal and outputs a second delay signal obtained by delaying the first delay signal by a time period Tb. The timing circuit 224 includes a delay element that receives the third delay signal and outputs a fourth delay signal obtained by delaying the third delay signal by a time period Td.

The logic circuit 231 includes an XOR circuit that receives a control signal, a first delay signal, and a second delay signal and outputs a first operation result obtained by performing an exclusive OR (XOR) operation.
The logic circuit 232 includes an XOR circuit that receives the control signal, the third delay signal, and the fourth delay signal and outputs a second operation result obtained by performing an exclusive OR operation.
The logic circuit 233 includes a selector circuit that outputs one of the first calculation result and the second calculation result as PREOUT in accordance with the control signal.

The NOT circuits 243 and 244 output the logical negation of PREOUT output from the logic circuit 233 to the gate terminals of the first and second transistors 241 and 242.
The first and second transistors 241 and 242 are configured to switch between an ON state and an OFF state in accordance with a control signal output from the logic circuit 233.
The first transistor 241 includes a PMOS transistor having a source terminal connected to the power supply VCC, a drain terminal connected to the second transistor 242, and a gate terminal connected to the NOT circuit 243. The second transistor 142 includes an NMOS transistor having a source terminal connected to the ground GND, a drain terminal connected to the first transistor, and a gate terminal connected to the NOT circuit 244. The voltage of the gate driver output voltage _VOUT is determined according to the ON state of the first and second transistors.

  FIG. 9 shows an example of a specific circuit for realizing the operations of the gate drivers 10 and 100 shown in FIGS. 1 and 7, and the present invention is not limited to this. 9, timing circuits 221 to 224 are circuit examples for realizing the timing control unit in FIG. 1, and logic circuits 231 to 233 are circuit examples for realizing the logic unit 30 in FIG. The first transistor 241 and the NOT circuit 243 are circuit examples for realizing the first switch unit 41 in FIG. 1 and the second transistor 242 and the NOT circuit 244 are the second switch unit 42 in FIG.

An operation example of the power control circuit 201 in FIG. 9 will be described. The power control circuit 201 operates in the same manner as the waveform shown in FIG. 8 to change the ON / OFF state of the power transistor 90.
When the control signal input from the input terminal IN changes from the low level (L) to the high level (H), the logic circuit 233 selects the output of the logic circuit 231 (first operation result). The timing circuit 221 maintains the output at the low level until the period Ta elapses immediately after the control signal changes from the low level to the high level. Until the period Ta elapses, the input of the logic circuit 231 becomes LLH from the top of FIG. Therefore, the output of the logic circuit 231 and the output PREOUT of the logic circuit 233 output a high level. When the period Ta elapses, the input of the logic circuit 231 becomes HLH, so that the output PREOUT becomes low level. When the period Tb further elapses, the output of the timing circuit 222 also becomes high level. Accordingly, since the input of the logic circuit 231 becomes HHH, the output PREOUT becomes high level. As shown in FIG. 8, the period Ta changes to a high level, the period Tb changes to a low level, and then changes to a high level.

On the other hand, when the control signal input from the input terminal IN changes from the high level to the low level, the logic circuit 233 selects the output (second operation result) of the logic circuit 232. The timing circuit 223 maintains the output at the high level until the period Tc elapses immediately after the control signal changes from the high level to the low level. Until the period Tc elapses, the input of the logic circuit 232 becomes LHH from the top of FIG. Therefore, the output of the logic circuit 232 and the output PREOUT of the logic circuit 233 output a low level. When the period Tc elapses, the input of the logic circuit 232 becomes LHL, so that the output PREOUT becomes high level. When the period Td further elapses, the output of the timing circuit 224 also goes to a low level. Accordingly, since the input of the logic circuit 232 becomes LLL, the output PREOUT becomes low level. As shown in FIG. 8, a transition is made to the low level during the period Tc, the high level during the period Td, and then to the low level.
Since the operation is performed as described above, the duration of the period Ta to Td determines the pulse width formed in the drive signal.

Next, voltage and current fluctuations of the power control circuit 201 will be described with reference to FIGS.
FIGS. 10 and 11 show examples of Spice (Simulation Program with Integrated Circuit Emphasis) simulation waveforms when the power transistor 90 is changed to the ON state or the OFF state using the gate drive method of the gate driver 200 shown in FIG. It is. 10 and 11 show the waveform of the power control circuit having the gate resistance (for example, the power control circuit 93 in FIG. 2) and the power control without the gate resistance in addition to the waveform of the power control circuit 201 of the first embodiment. The waveform of a circuit (for example, the power control circuit 95 of FIG. 4) is shown.
FIG. 10 is a waveform example when the power transistor 90 is changed to the ON state, and FIG. 11 is a waveform example when the power transistor 90 is changed to the OFF state.
10 and 11 show waveforms of the gate driver output voltage V _OUT [V], the IGBT gate voltage V _GE [V], and the gate current I _G [A]. In the figure, the solid line is a waveform example of the power control circuit 201 in FIG. 9, the one-dot broken line is a waveform example of the power control circuit 93 with a gate resistance in FIG. 2, and the dotted line is a power control without a gate resistance in FIG. 10 is a waveform example of a circuit 95. In addition, since each line overlaps, the entire dotted line is shifted slightly upward and the entire dashed line is shifted downward relative to the solid line, and is shown at a position slightly shifted from the actual value. As an actual value, for example, from the time −0.5 to 0 μsec, the three lines are overlapped.
In FIG. 10, the period Ta is set to 400 ns, the period Tb is set to 75 ns, and FIG. 11 illustrates the case where the period Ta is set to 215 ns and the period Tb is set to 170 ns.

The time required for charging the gate voltage V _GE of the power transistor 90 in the turn-on waveform of FIG. 10 requires 1100 ns or more in the gate drive method using the power control circuit 93 with a gate resistance. This is because the charge is charged while damping with the gate resistance.
In the power control circuit 95 gate drive system of the gate resistance free is can be reduced to approximately 330ns by omitting the gate resistance, the overshoot of the gate voltage V _GE occurs. As a result, a voltage of about 20 V (out of rating) is applied, and the element can be destroyed.
In the gate drive system of the power control circuit 201 of the present embodiment, the overshoot of the gate voltage V _GE is eliminated while realizing a rise time equivalent to that without the gate resistance (1/3 compared to the conventional system). . In this embodiment, the time required for turn-on is reduced from 1100 ns to 330 ns when the power control circuit 93 is used, and a time reduction of 30% is realized. In addition, unlike the power control circuit 95, no linking occurs.

The time required for discharging the gate voltage V _GE of the power transistor 90 in the turn-off waveform of FIG. 11 requires 800 ns or more in the gate drive system of the power control circuit 93 with gate resistance.
In the power control circuit 95 gate drive system of the gate-free, which can be reduced to approximately 300ns by omitting the gate resistance, undershoot of the gate voltage V _GE occurs. As a result, a voltage of about −30 V (out of rating) is applied, so that the element can be destroyed. In addition, unintended turn-on can occur due to ringing.
In the driving method of this embodiment, while realizing the case where the gate resistance is not equal to fall time (350 ns 1/2 as compared with the conventional method), eliminating the undershoot of the gate voltage V _GE. In this embodiment, the time required for turn-on is reduced from 800 ns to 350 ns when the power control circuit 93 is used, and a time reduction of 44% is realized. In addition, unlike the power control circuit 95, no linking occurs.

Thus, faster charging and discharging of the gate by eliminating the gate resistance, while minimizing the switching losses of the power transistors 90, an overshoot of the waveform caused by the parasitic inductances L _G, in order to solve the problems undershoot occurs The signal is equalized by the output voltage of the gate driver. The output of the gate driver performing equalization may if high and low levels 2 levels or more, by adjusting the width of the pulse to be inserted for equalizing the gate voltage of the power transistor at the tip passing through the parasitic inductances L _G V _GE is controlled to a desired voltage.

  The characteristics of the switching method of the first embodiment described above will be described in comparison with a power control circuit having a gate resistance, for example, the power control circuit 93 in FIG. FIG. 12A is a diagram for explaining the characteristics of the switching method implemented by the power control circuit using a gate resistor. FIG. 12B is a diagram illustrating the characteristics of the switching method performed by the power control circuit according to the embodiment. FIG. 12B shows a case where the gate driver 100 included in the power control circuit 101 is used as a gate driver as an example.

First, as shown in FIG. 12A, a power control circuit using a gate resistor has the following characteristics.
(1-a) Since the rise and fall of the gate voltage of the power transistor 90 is slow and the half ON state period TR and the half ON state period TF to transition to the OFF state become long, the power transistor 90 has a large power loss. .
(2-a) The resistance value of the gate resistance is adjusted so that overshoot of the collector-emitter or drain-source voltage _VCE does not occur.
(3-a) Since heat loss of the gate resistance occurs, the power consumption of the gate driver increases.
(4-a) The cost, area, and design man-hour of the external gate resistor are generated for the user who uses the power control circuit.
(5-a) Each driver circuit is required for a plurality of gate drive methods (normal ON / OFF, soft turn-off, clamp).

On the other hand, as shown in FIG. 12B, the power control circuit of one embodiment has the following characteristics.
(1-b) Since the rise and fall of the gate voltage of the power transistor 90 are fast and the half-ON period TR and the half-ON period TF for transitioning to the OFF state are shortened, the power loss of the power transistor 90 is small. .
(2-b) While charging the gate at a high speed, the gate charge speed is partially limited so that the collector-emitter or drain-source voltage _VCE does not overshoot. Charge rate limit, as well as adjust the pulse width to be inserted into the drive signal to compensate for the effects of the parasitic inductance L _G in the output waveform of the drive signal. In addition, the configuration is realized without using a gate resistor.
(3-b) The power consumption of the gate driver is small. In addition, the gate charge of the power transistor 90 can be regenerated. This will be described with reference to FIG.
(4-b) The cost, area, and design man-hour of the external gate resistor are not generated for the user who uses the power control circuit.
(5-b) A plurality of gate drive methods can be realized with one driver circuit.

FIG. 13 is a diagram illustrating the switching time according to an embodiment. FIG. 13 shows the gate voltage V _GE , the collector-emitter or drain-source voltage V _CE and current I _CE , and the power loss P _LOSS = V _CE × I _CE for the power transistor 90. The power loss is represented by an area region indicated by hatching, and the switching time is represented by an arrow.
By using the gate driver of one embodiment, the charge time of the gate voltage of the power transistor 90 is shortened. As a result, the rise time and fall time of the current I _CE and the fall time and rise time of the gate voltage shown in FIG. 13 are shortened compared to FIG. In other words, the switching times TR and TF are shortened, and the power loss of the power transistor 90 can be reduced. Thus, according to the gate driver of one embodiment, it is possible to suppress the power loss that is the first problem that occurs when the gate resistance is used.

FIG. 14 is a diagram illustrating comparison of voltage / current fluctuations between the power control circuit of one embodiment and another power control circuit. Voltage and current of a power control circuit with a gate resistance (for example, the power control circuit 93 of FIG. 2), a power control circuit without a gate resistance (for example, the power control circuit 95 of FIG. 4), and the power control circuit of one embodiment. Shows fluctuations. Although the power control circuit without a gate resistance is a system that is difficult to actually use, a waveform example is shown for the sake of explanation. Figure 14 shows the gate driver output voltage _{V OUT,} the waveform of the gate current _{I G} and the gate voltage _{V GE.}
As shown in FIG. 14, in one embodiment, as described with reference to FIG. 13, in addition to being able to suppress power loss, the problem that occurs in the power control circuit when no gate resistance is provided is also solved. It is possible. Specifically, overshoot, undershoot, and ringing of the gate voltage V _GE shown in the waveforms of the gate current _IG and the gate voltage V _GE of the power control circuit without a gate resistance can be avoided.

FIG. 15 is a diagram illustrating a mechanism in which the power control circuit of one embodiment reduces power consumption without causing Joule loss.
Since the power control circuit of one embodiment does not use a gate resistor, no Joule loss occurs. As a result, the power required for the gate drive is reduced. In addition, the electric charge charged at the gate of the power transistor is regenerated to the power source as electric power, not Joule heat. As a result, power consumption can be reduced. With reference to FIG. 15, it will be described that the gate driver is configured to regenerate power wo.
15 shows, the upper shows the gate driver output voltage _{V OUT,} the waveform of the gate current _{I G} and the gate voltage _{V GE} of the power transistor. In addition, a diagram illustrating a charge source and a discharge destination of charges to the gate of the power transistor 90 in the power control circuit for the periods Ta to Td is shown in the lower stage. In FIG. 15, the configuration of the power control circuit is shown in a simplified manner centering on elements related to the description. Specifically, a power transistor 90 and a gate driver are shown, and regarding the gate driver, a PMOS transistor SW1 serving as a first switch unit and an NMOS transistor SW2 serving as a second switch unit are illustrated. One of the PMOS transistor SW1 and the NMOS transistor SW2 is turned on and the other is turned off, as in the state transition of the first and second switch sections shown in FIG. A thick solid arrow indicates a current flow, and a dotted arrow indicates a return current flow.

In the period Ta, in the gate driver, the PMOS transistor SW1 is in the ON state, and a current flows from the power supply VCC to the power transistor 90 via the PMOS transistor SW1. Therefore, the gate of the power transistor 90 is charged from the power supply VCC. At this time, the return current flows from the power transistor 90 to the gate driver via the ground GND.
In the period Tb, the gate driver, a NMOS transistor SW2 is turned ON, the energy of the parasitic inductance _{L G,} a current flows through the power transistor 90 from the ground GND through the NMOS transistor SW2. For this reason, the gate of the power transistor 90 is charged from the ground GND. At this time, the return current flows from the power transistor 90 to the ground GND.

In the period Tc, the NMOS transistor SW2 is in the ON state in the gate driver, and a current flows from the power transistor 90 to the ground GND through the NMOS transistor SW2. Therefore, the gate of the power transistor 90 is discharged to the ground GND. At this time, the return current flows from the ground GND to the power transistor 90.
In the period Td, the gate driver, a PMOS transistor SW1 is turned ON, the energy of the parasitic inductance _{L G,} current flows (regenerative current) from the power transistor 90 to the power supply VCC via the PMOS transistor SW1. Therefore, the gate of the power transistor 90 is discharged to the power supply VCC. The discharged charge becomes regenerative power used by the power supply VCC. At this time, the return current flows from the ground GND to the power transistor 90.

The gate driver of the present embodiment is configured to realize the charge and discharge of the gate charge as described in FIG. Thereby, in addition to avoiding the generation of Joule loss by not arranging the gate resistor _RG , an advantageous effect of reducing power consumption can be achieved. Specifically, by utilizing the parasitic inductance L _G, it is possible to reduce the power supplied from the power source VCC to the power transistor 90. Further, the regenerative current, the charges charged in the gate capacitor C _G of the power transistor 90 can be reused in the gate driver power supply VCC.

Next, in one embodiment, it will be described that the circuit area and the like can be reduced.
First, the elimination of the gate resistance _RG eliminates the need for an external resistor. Thereby, a part cost, a mounting area, and a design man-hour can be reduced.
In addition, in one embodiment, the circuit area of the gate driver can be reduced. This will be described with reference to FIGS. 16A and 16B. FIG. 16A is a diagram illustrating a configuration example of a gate driver having an active mirror clamp and using a gate resistor _RG . In a gate driver using the gate resistor _RG , self-turn-on due to parasitic coupling occurs unless the gate of the power transistor 90 is clamped to the ground GND with a low resistance. In order to prevent the self-turn-on when the power transistor 90 is turned off, the gate driver includes an active mirror clamp. In the active mirror clamp, when the command from the control logic 96 causes the power transistor 90 to transition to the OFF state and the gate voltage is 1.5 V or less, the gate is clamped to the ground GND with a low resistance.

The configuration example of FIG. 16A includes an NMOS transistor SW3 functioning as an active mirror clamp in addition to the PMOS transistor SW1 and NMOS transistor SW2 functioning as first and second switch sections. As described above, the gate driver 97 of FIG. 16A includes two systems of circuits. For example, when a 10Ω or 0.5Ω transistor is used for the gate driver, the area of the transistor of the gate driver is increased unlike a transistor such as a logic device. In other words, the area penalty increases.
FIG. 16B is a diagram illustrating the function of the active mirror clamp of the gate driver according to the embodiment. Since the gate driver of one embodiment has a configuration without the gate resistance _RG , it can be sufficiently clamped to the ground GND by the low-side transistor of the gate driver body. In other words, the gate drive system can handle all gate resistances with a single system circuit. This eliminates the need for a transistor dedicated for active mirror clamping. Therefore, the area of the NMOS transistor SW3 functioning as an active mirror clamp can be reduced.

In general, a drive transistor of a gate driver has a large current capacity, usually about 2A to 4A, and also has a low resistance when turned on, about 1Ω. Therefore, the occupied area in the chip increases. Since the transistor can be omitted, the chip size can be reduced.
In the description of this embodiment, for example, in the description of FIGS. 12B and 13 to 16B, the gate driver of one embodiment includes the gate drivers 1, 100, and 200 in FIGS. The gate driver described in the embodiment, or a configuration appropriately changed based on these gate drivers is included. Similarly, in addition to the power control circuits 101 and 201 of FIGS. 7 and 9, the power control circuit of one embodiment appropriately includes power control circuits described in the following embodiments, or based on these power control circuits. Includes changed configurations.

Embodiment 2. FIG.
In the second embodiment, adjustment of the pulse width of the drive signal will be described.
In the switching method control performed by the gate drivers 100 and 200 shown in FIGS. 7 and 9, the pulse width formed in the drive signal is determined according to the period of the period Ta to Td. In the present embodiment, a method for determining periods Ta, Tb, Tc, and Td for determining the pulse width will be described.
FIG. 17 shows an example of a method for determining the pulse width of the drive signal. A switching system of the present embodiment, in the period Ta, the time after the Tb is completed t2, the gate voltage V _GE of the power transistor is converged to a desired voltage, it is desirable that the gate current I _G is converged to zero. Therefore, the period Ta, at time t2 after Tb is completed, the gate voltage V _GE and the gate current I _G is measured, comparing the measured value with a desired value. Based on the comparison result, it is determined whether the pulse width is too wide or narrow, in other words, whether the periods Ta and Tb are long or short. Based on the determined result, the lengths of the periods Ta and Tb are determined. FIG. 18 shows an example of a procedure for adjusting the pulse width of the drive signal. FIG. 18 shows an example in which the desired voltage of the gate voltage V _GE of the power transistor is 15V. For example, when the gate voltage V _GE is smaller than 15 V (V _GE <15 V) and the gate current _IG is smaller than zero (I _G <0), the period Ta is widened and the period Tb is narrowed. In other words, the period Ta is lengthened and the period Tb is shortened. Gate voltage take other values V _GE and the gate current I period by the procedure shown in FIG. 18 with the case of _G Ta, adjusts the Tb. Period Ta, by adjusting the Tb, the gate voltage _{V GE} is the 15V, the gate current _{I G} is adjusted so as to converge to zero.

For example, a method is employed in which the voltage and current at the output terminals of the gate drivers 100 and 200 are measured and the pulse width is automatically calibrated. For the periods Tc and Td, the pulse width can be determined by the same method as the periods Ta and Tb. In addition, not only the gate voltage V _GE and the gate current I _G at the time t2, information on whether the (measured) transiently overshoots-undershoot occurs during t0~t2 also the use, calibration Speeds up and increases the accuracy of convergence.

FIG. 19 is another diagram for explaining an example of a procedure for adjusting the pulse width of the drive signal. In FIG. 19, nine types of cases are classified as in FIG. 18, and the waveforms of the gate driver output voltage V _OUT , the gate current I _G , and the gate voltage V _GE are shown in each case. From the left, the vertical column indicates the case where the gate current I _G is smaller than zero (I _G <0), the case where it coincides with zero (I _G = 0), and the case where it is larger than zero (I _G > 0). The horizontal rows show that when the gate voltage V _GE is less than 15V (V _GE <15V), when the gate voltage V _GE matches 15V (V _GE = 15V), when the gate voltage V _GE is greater than 15V (V _GE > 15V). Then, by adjusting the period Ta, Tb, central gate voltage _{V GE} is 15V and the gate current _{I G} is zero _{(V GE = 15V, I G} = 0) to converge to. The periods Tc and Td can be adjusted similarly to the periods Ta and Tb.
The signal level of the drive signal is changed by adjusting the periods Ta to Td by the method described with reference to FIGS. Thereby, the pulse width formed in the drive signal can be adjusted to an appropriate length.

FIG. 20 illustrates an example of a power control circuit 301 having a function of adjusting the periods Ta to Td described with reference to FIGS. A power control circuit 301 in FIG. 20 shows a configuration example including a gate driver 300 in which a calibration function is added to the gate driver 200 in FIG. Calibration function of FIG. 20, by adjusting the period Ta to Td, the pulse width for forming the drive signal to zero gate current I _G, and functions to converge the gate voltage V _GE to a desired voltage. As a configuration (calibration unit) that realizes the calibration function, a gate voltage sensor 351, a gate current sensor 352, and a calibration block 353 are provided.
The gate voltage sensor 351 is a sensor that measures the gate voltage _VGE .
Gate current sensor 352 is a sensor for measuring the gate current _{I G.}
Calibration block 353, based on the gate voltage _{V GE} of the sensor is measured and the gate current _{I G,} a block for adjusting the period Ta to Td. The calibration block 353 adjusts the periods Ta to Td according to the method shown in FIGS.
The timing circuits 221 to 224 are configured by delay elements having variable delays, and the delay of the delay elements is adjusted by the calibration block 353.

The gate voltage V _GE is preferably measured from the vicinity of the gate of the power transistor 90 by Kelvin measurement. The gate current _IG is the polarity of the IR drop voltage of the transistor 241 or the transistor 242 in the vicinity of the output of the gate driver 300 (the voltage drop or rise represented by the product of the on-resistance R of the transistor and the current I flowing through the transistor). by measuring, it is possible to know the direction of the current I _G. For example, in the direction in which the transistor 241 is on and _IG is positive (the direction in which the gate of the IGBT is charged), the voltage of the output _VOUT of the gate driver 300 becomes lower than 15V due to the IR drop of the transistor 241. Conversely, in the direction in which the transistor 241 is on and _IG is negative (the direction in which the gate of the IGBT is discharged), the voltage of the output _VOUT of the gate driver 300 is higher than 15V. As another method for measuring the direction of the gate current _IG, the direction of the current can be known by measuring the polarity of the voltage immediately after the transistor of the gate driver 300 is turned off near the output of the gate driver 300. it can. Immediately after the transistor of the gate driver 300 is turned off, an electromotive force is generated because current tends to flow due to parasitic inductance. Therefore, if _{I G} is a positive direction, the voltage is -VF of the output _{V OUT} (forward voltage drop of the parasitic diode of the VF transistor 242), when _{I G} is a negative direction, the voltage of the output _{V OUT} is VCC + VF (VF is a forward voltage drop of the parasitic diode of the transistor 241).
By having a calibration function, the gate driver 300, based on the measured and the gate voltage V _GE and the gate current I _G, the period Ta to Td, it is possible to adjust the pulse width to the appropriate values in other words .

Embodiment 3. FIG.
In order to solve the second and third problems related to the control of the current slew rate that occur in the case of a power control circuit without a gate resistance, it is necessary to adjust the slew rate of the gate voltage of the power transistor.
For example, in the power control circuit 93 shown in FIG. 2, the slew rate is adjusted by changing the value of the gate resistance. On the other hand, in the power control circuit of one embodiment, it is assumed that a gate resistance is not used or a gate resistance having a very small resistance value is used. For this reason, the power control circuit of one embodiment requires means other than the gate resistance in order to adjust the slew rate.
FIG. 21 is a diagram for explaining the relationship between the drive signal of the gate driver and the slew rate of the gate voltage of the power transistor according to one embodiment. FIG. 21 shows an output waveform of the gate driver for adjusting the slew rate of the gate voltage. In one embodiment, in the process of transitioning the gate voltage V _GE from the first level to the second level, Insert a first level pulse. Thereby, the slew rate of the gate voltage can be adjusted. After the gate voltage V _GE reaches the desired second level, the gate driver output voltage _VOUT is fixed at the second level.
As shown in FIG. 21, the slew rate of the gate voltage is adjusted according to the pulse width and the number of pulses inserted into the drive signal. By increasing the number of pulses to be inserted into the drive signal, the rise of the gate voltage is delayed and the slew rate is reduced, in other words, the slew rate is laid down. In addition, the rise of the gate voltage can be delayed by increasing the pulse width of the first level (reverse polarity).
Figure 21 shows the power transistor from the OFF state when switching to the ON state, the gate voltage _{V GE} of the gate driver output voltage _{V OUT} and the power transistor. When the power transistor is switched from the ON state to the OFF state, the adjustment can be performed in the same manner as in FIG.

Next, the relationship between shortening the slew rate and preventing overshoot will be described with reference to FIG.
By slewing the slew rate, the surge voltage as shown in FIG. 6 can be suppressed. On the other hand, since switching time becomes long, the switching loss of a power transistor will increase. Therefore, as shown in FIG. 22, the gate voltage is charged and discharged at a high speed up to the area before the surge voltage appears (the slew rate of the gate voltage is increased to a large current), and in the area where the surge voltage appears, the gate voltage is increased. slowly charging and discharging the voltage (lay the slew rate, inhibiting the gate current I _G) performs control. In other words, the collector - emitter or drain - region not related to the overshoot of the voltage V _CE between the source quickly charge and discharge the gate charge to increase the slew rate of the gate voltage V _GE. On the other hand, the collector - emitter or drain - part related to the overshoot of the voltage V _CE between the source lowers the slew rate of the gate voltage V _GE. Thus, by controlling the current slew rate of the gate current I _G (dV _GE / dt) according to the region, the following two advantageous effects can be achieved at the same time.
(1) shortening the switching time to reduce the switching loss, and
(2) Suppress the surge voltage to reduce overshoot and avoid the influence on the power transistor.

For comparison, FIG. 22 shows a driving method when the gate resistance is low and a driving method when the gate resistance is high, in addition to the driving method of the embodiment. The driving method according to an embodiment works to adjust the slew rate of the gate voltage according to the region, and the driving method and the gate resistance when the gate resistance is low and the gate resistance is high in contrast to a large current immediately after the start of the switching period In the case of the driving method, the slew rate of the gate voltage is substantially proportional to the quotient (V _GE / R _G ) of the gate voltage and the gate resistance. As a result, in the driving method when the gate resistance is low, the switching time is shortened and the switching loss is reduced. On the other hand, the overshoot becomes large and there is a concern about the influence on the power transistor. Further, in the driving method in the case where the gate resistance is high, the switching time becomes long and the switching loss becomes large. On the other hand, since the overshoot is small, the influence on the power transistor is eliminated.
As described above, in the gate driver in which the slew rate cannot be adjusted according to the region without using the gate resistance as in the embodiment, the value of the gate resistance cannot be changed during the operation. Therefore, as one embodiment, it is impossible to realize the function of controlling the actively gate current I _G by the region. Although variable current control may be realized, it is not preferable because of a thermal problem because the voltage division ratio to the gate driver becomes large.

  The configuration example of the power control circuit or the gate driver according to the embodiment described in the third embodiment includes the configuration of each of the above-described embodiments, for example, the power control circuit including the gate driver illustrated in FIGS. . The function described in this embodiment can be realized by any one of these gate drivers.

Embodiment 4 FIG.
In the fourth embodiment, a mode for facilitating the adjustment of the pulse width described in the second embodiment will be described.
In Embodiment 2, as shown in FIG. 17, by the opposite polarity of the pulses (reverse pulses) one inserted into the drive signals, both of the gate voltage V _GE and the gate current I _G at the time t2 to a desired value at the same time It is assumed that In this approach, the combined included both the gate voltage V _GE and the gate current I _G at the time t2 is set to a desired value at the same time, it is necessary to strictly adjust the parameters for determining the pulse width.
Therefore, in this embodiment, the gate voltage V _GE and the gate current I _G By the time pulse for first polarity opposite ends, is squirreled combined rough to approximate the desired value, small gate in the remaining period it is intended to improve the convergence of the gate voltage by a current I _G.

Figure 23 is a diagram for explaining a method of achieving gate voltage V _GE, the convergence of the gate current I _G in a simpler way. In FIG. 23, the time axis indicating the elapsed time from time t0 is shown in the center, the pulse width adjustment method of the second embodiment is shown on the upper stage of the time axis, and the pulse width adjustment technique of the present embodiment is shown on the lower stage. .
In the adjustment of the pulse width of the second embodiment shown in the upper stage, from time t0 to time t1 (first period) and time t1 so that the current becomes zero and the gate voltage matches a desired value (for example, 15 V) at time t2. To t2 (second period). If the adjustment of the pulse width is not properly performed, an increase in switching time and an overshoot of the gate voltage occur, resulting in an increase in switching loss and an increase in stress on the power transistor 90.
In the present embodiment shown in the lower part, the first reverse polarity pulse is inserted to adjust to the vicinity of the desired value, and then one or more reverse polarity pulses are inserted to match the desired value. In FIG. 23, the pulse widths from time t0 to t11 (first period) and from time t11 to t12 (second period) are adjusted so that the current is near zero and the gate voltage is near 15 V at time t12. Thereafter, from time t12 to t16, a pulse having a large duty ratio is inserted finely, and the current is converged to zero and the gate voltage is converged to 15V.

Even when the power transistor 90 transitions from the ON state to the OFF state, a plurality of pulses are inserted into the drive signal in the same manner as the transition to the ON state to converge the current and voltage to desired values. However, in the case of transition to the OFF state, even if some undershoot occurs, the influence on the power transistor is small. For this reason, accuracy is not required compared to the case of transition to the ON state.
In this embodiment, for example, in FIGS. 9 and 20, the number of timing circuits 221 to 224 included in the drive control unit 210 is increased, and the delay amount of the delay element configuring each timing circuit is adjusted to adjust the pulse with an appropriate pulse width. Can be realized by a configuration in which the driving circuit is formed.
By adjusting the number of pulses to be inserted into the drive signal as in this embodiment, the accuracy required for the calibration of the parameter that determines the pulse width can be relaxed.

Embodiment 5. FIG.
In the fifth embodiment, a configuration example of a gate driver when adjusting the slew rate of the gate voltage will be described in comparison with a gate driver using a gate resistance _RG .
FIG. 24 is a diagram illustrating a configuration example of a gate driver using a gate resistance _RG and having a slew rate adjustment function. The gate driver 98 includes a PMOS transistor SW1 and NMOS transistors SW2 to SW4 as a configuration corresponding to the gate driving unit 40 of one embodiment.
FIG. 25 is a diagram illustrating a configuration example of the gate driver according to the embodiment and including a slew rate adjustment function. The gate driver 400 includes a drive control unit 410 and a gate drive unit 440. The drive control unit 410 includes at least first to third slew rate control units 411 to 412 as a function of controlling the slew rate of the gate voltage. For example, the first to third slew rate control units 411 to 412 include delay elements according to the number of pulses formed in the drive signal. The gate driver 440 includes a PMOS transistor SW1 and an NMOS transistor SW2.
24 and 25, the control signal (gate control signal) is a signal for controlling normal turn-on and turn-off of the power transistor 90. The abnormality detection signal is a signal for notifying that an abnormality has been detected. The control signal and the abnormality detection signal are input to the gate drivers 98 and 400 from the input terminals.

The gate driver using the gate resistance R _G, using a plurality of gate resistor R _G to change the slew rate and the like. In the gate driver 98 of FIG. 24, circuits (transistors) of 2 to 4 systems having different gate resistances _RG are mounted. Specifically, in addition to the main system of 5Ω, two systems of a gate resistance smaller than 1Ω (<1Ω) and a gate resistance of 47Ω are provided, and a total of three types of circuits are required. The main system circuit includes a PMOS transistor SW1 and an NMOS transistor SW2. The other two systems are active mirror clamp and soft turn-off. The active mirror clamp is a circuit that works to prevent self-turn-on by clamping the gate to the ground GND with an impedance close to 0Ω when the power transistor 90 is turned off, and is configured by the NMOS transistor SW3. The soft turn-off works to suppress dI _CE / dt with a high resistance and to prevent breakdown due to the generation of a surge voltage. The soft turn-off is composed of an NMOS transistor SW4. The comparator 99 detects that the power transistor 90 has transitioned to the OFF state.

  On the other hand, the gate driver 400 of one embodiment is configured to control the slew rate of the gate voltage by the first to third slew rate control units 411 to 412. The first to third slew rate controllers 411 to 412 are configured to generate drive signals having different pulse widths and different numbers of pulses to be inserted in order to control different slew rates. For example, the first to third slew rate control units 411 to 412 have different numbers of delay elements and different delay lengths. The first to third slew rate control units 411 to 412 have the number of delay elements so that the gate voltage becomes a desired voltage according to the ratio (duty ratio) of the pulse widths of the first and second levels of the drive signal. The delay amount of each delay element is adjusted. If the gate voltage can be controlled to a desired voltage, the slew rate of the gate voltage can also be adjusted. Thus, a desired pulse is inserted into the drive signal. For the control of the slew rate of the gate voltage, the method described in the third and fourth embodiments can be used.

In the drive control unit 410, the first slew rate control unit 411 controls normal turn-on of the power transistor 90. Therefore, the first slew rate control unit 411 is configured to generate a drive signal when receiving a control signal for switching the power transistor 90 to the ON state.
The second slew rate control unit 412 controls normal turn-off of the power transistor 90. Therefore, the second slew rate control unit 412 is configured to generate a drive signal when receiving a control signal for switching the power transistor 90 to the OFF state.
The third slew rate control unit 413 controls soft turn-off when an abnormality is detected. Therefore, the third slew rate control unit 413 is configured to generate a drive signal when receiving the abnormality detection signal.
The comparator 414 detects that the power transistor 90 has transitioned to the OFF state.
As described with reference to FIGS. 24 and 25, in one embodiment, the number of transistors compared to the configuration using the gate resistance is also achieved even when the gate voltage / gate current slew rate is controlled. Can be reduced. Therefore, the circuit scale can be suppressed.

Embodiment 6. FIG.
In the second embodiment, an example of the gate driver including the calibration block for adjusting the pulse width has been described. In the sixth embodiment, another configuration example of the gate driver having a function of adjusting the pulse width will be described. 26A to 26C are diagrams illustrating an example of a power control circuit including a gate driver having a function of adjusting a pulse width. 26A to 26C show examples in which the configuration of the drive control unit 110 of the power control circuit 101 in FIG. 7 is changed. Therefore, the configuration with the same reference numerals as those in FIG. In addition, the configuration example of the drive control unit shown in FIGS. 26A to 26C can be incorporated not only in the power control circuit 101 in FIG. 7 but also in other power control circuits as shown in FIGS. Needless to say.

In FIG. 26A, the drive control unit 510A of the gate driver 500A includes a logic circuit 511 (logic unit) and a register file 512 (timing control unit). The logic circuit 511 implements a function of receiving a control signal and inserting a pulse having a reverse polarity into the drive signal based on information stored in the register file 512. For example, the logic circuit 511 includes a delay element that can change the length of each of the periods Ta to Td according to information held in the register file 512. In the register file, information for determining the pulse width by an external program signal, in other words, information for determining the time of the periods Ta to Td (for example, information for specifying the times and times of the periods Ta to Td) is written. FIG. 26A shows a configuration example having the register file 512 in the logic circuit 511. However, the location of the register file is not limited to this, and any location where the logic circuit 511 can refer to information held in the register is shown. That's fine.
The drive control unit 510A can adjust the pulse width by rewriting the information held in the register file 512. Therefore, the pulse width can be adjusted to an appropriate length from an external device that uses the gate driver 500A.

Figure 26B, the drive control unit 510B of the gate driver 500B, in addition to the logic circuit 511 and the register file 512 of Figure 26A includes, a sensor function of measuring the gate voltage _{V GE} and the gate current _{I G,} and a calibration circuit 513 A configuration example is shown.
Sensor function detects nearby gate voltage V _GE and the gate current I _G of the gate of the power transistor 90, and outputs a gate voltage sense signal and the gate current sense signal to the calibration circuit 513. Even when the voltage sensor function is added, the influence of the parasitic resistance 514 and the parasitic inductance 515 is small because the value of the current I flowing through the voltage sensor or the time differential dI / dt thereof is small.
The calibration circuit 513 adjusts the pulse width based on the gate voltage sense signal and the gate current sense signal. For example, the method shown in FIGS. 18 and 19 may be used to adjust the pulse width. The calibration circuit 513 writes the adjusted result to the register file 512.
The operation of the logic circuit 511 is the same as that in FIG. 26A.
The drive control unit 510B can adjust the pulse width by rewriting information held in the register file 512 by the calibration circuit 513 and the sensor function. Therefore, the pulse width can be adjusted according to the operating status of the power transistor 90. In this case, the device using the gate driver 500B does not need to adjust the pulse width.

FIG. 26C shows a configuration example in which the drive control unit 510C of the gate driver 500C includes an isolator 516 and command data 517 in addition to the logic circuit 511 and the register file 512 of FIG. 26A. The drive control unit 510C is a configuration example that adjusts the pulse width in accordance with a command signal input from the outside. The drive control unit 510C receives the command signal via the isolator 516 and holds it in the command data 517. The command signal includes a register setting signal for setting information for determining the pulse width in the register file and a control signal for controlling the gate. As for the command signal, a register setting signal is superimposed on the control signal by a command, time division multiplexing, or the like.
The command data 517 is configured to set register setting signal information in a register file and output a control signal to the logic circuit 511.
The operation of the logic circuit 511 is the same as that in FIG. 26A.
The drive control unit 510 </ b> C can set information for adjusting the pulse width in the register file 512 by receiving the command signal and holding it in the command data 517. Therefore, the pulse width can be adjusted to an appropriate length by a command signal input from an external device (such as a microcomputer) that operates in a power domain different from that of the gate driver 500C.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Not too long.

1, 12, 91, 97, 98, 100, 200, 300, 400, 500A, 500B, 500C Gate driver 2 Input terminal 3 Output terminals 10, 110, 210, 410 Drive control unit 20, timing control unit 30 Logic unit 40 140, 240, 440 Gate driver 90 Power transistors 93, 95, 101, 201, 301, 401, 501
96, 11 Control block 99, 414 Comparator 121, 221-224 Timing circuit 131, 132, 231-233, 511 Logic circuit 141, 241 First transistor 142, 242 Second transistor 243, 244 NOT circuit 351 Gate voltage sensor 352 Gate current sensor 353 calibration block 411 first slew rate control unit 412 the second slew rate control section 413 third slew rate control unit 512 register file 513 the calibration circuit 514 parasitic resistance 515 parasitic inductance 516 isolator 517 command data _{L G} parasitic inductance R _G gate resistance _RL load SW1 PMOS transistors SW2, SW3, SW4 NMOS transistors

Claims (18)

When receiving the control signal for switching the power transistor to the conductive state, the drive signal for controlling the gate voltage of the power transistor is switched from the first level to the second level, and the drive signal is When the control signal for switching to the first level and further switching to the second level after the elapse of a second period and receiving the control signal for switching the power transistor to the cutoff state, the drive signal is changed from the second level. A drive control unit that controls to switch to the first level, switch the drive signal to the second level after a lapse of a third period, and further switch to the first level after a lapse of a fourth period;
A gate driver for amplifying and outputting the drive signal;
With gate driver. In the first period and the second period, the current is supplied from the power source in the first period, and the supply of the current from the power source is stopped in the second period. The gate voltage of the power transistor is adjusted to reach a desired voltage level after the lapse of time,
In the third period and the fourth period, the current is discharged to the ground in the third period, and the current is regenerated to the power source in the fourth period. The gate driver according to claim 1, wherein the gate driver is adjusted so that the gate voltage reaches a ground level. The gate driver is
A first switch that is controlled to be in an OFF state when the drive signal is at the first level, and to be in an ON state when the drive signal is at the second level;
The gate driver according to claim 1, further comprising: a second switch unit that is controlled to be in an ON state when the drive signal is at the first level and to be in an OFF state when the drive signal is at the second level. One end of the first switch unit is connected to a power source,
The second switch unit has one end connected to the other end of the first switch unit and the other end connected to the ground.
The first switch unit supplies charges from the power supply to the gate of the power transistor in the first period, and regenerates charges from the gate of the power transistor to the power supply in the fourth period. ,
4. The second switch unit supplies electric charges from the ground to the gate of the power transistor in the second period, and discharges electric charges from the gate of the power transistor in the third period. The listed gate driver. The drive control unit
A timing control unit for instructing switching of the drive signal when detecting timing at which the first to fourth periods have elapsed;
The gate driver according to claim 1, further comprising: a logic unit that controls switching of the drive signal between the first level and the second level in accordance with an instruction from the timing control unit.   When the first and second periods have elapsed, the gate voltage and gate current of the power transistor are detected, and the detected values are compared with desired values to adjust the first and second periods. When the third and fourth periods have elapsed, a gate voltage and a gate current of the power transistor are detected, and the detected values are compared with desired values to compare the third and fourth periods. The gate driver according to claim 1, further comprising: a calibration unit that determines whether or not adjustment of the four periods is necessary and adjusts the first to fourth periods according to a determination result.   The calibration unit widens the first period when the gate voltage is smaller than a desired value when the first and second periods have elapsed, and the gate current is smaller than the desired value. In this case, the second period is shortened. When the gate voltage is larger than a desired value, the first period is shortened. When the gate current is larger than a desired value, the second period is shortened. The gate driver according to claim 6, wherein the gate driver is controlled to extend the period.   The drive control unit further controls the drive signal to switch between the first level and the second level after the first and second periods or the third and fourth periods. The gate driver according to claim 1.   The drive control unit repeatedly switches the drive signal between the first level and the second level, and switches the length between the first level and the second level between the first half and the second half. The gate driver according to claim 8, wherein the gate driver is changed. In the first period and the second period, the power is supplied from the power source in the first period, and the supply of the current is stopped in the second period, whereby the power is supplied after the second period. The gate voltage of the transistor is adjusted to reach any range below the desired voltage level,
In the third period and the fourth period, the current is discharged to the ground in the third period and the current to the power source is regenerated in the fourth period. Adjusted so that the gate voltage reaches any range above ground level,
The drive control unit repeats the insertion of the first level pulse a plurality of times after the second period has elapsed, and repeats the insertion of the second level pulse a plurality of times after the fourth period has elapsed. Item 1. The gate driver according to Item 1. The drive control unit
When the control signal for switching the power transistor to the conductive state is received, the drive signal is switched from the first level to the second level, and then the signal level of the drive signal is switched to the drive signal. A first slew rate controller that controls to form at least one pulse of opposite polarity;
Upon receiving a control signal for switching the power transistor to the cutoff state, the drive signal is switched from the second level to the first level, and then the signal level of the drive signal is switched to reverse polarity to the drive signal. A second slew rate control unit that controls to form at least one pulse of
A third slew rate control unit that controls the slew rate of the gate voltage of the power transistor to be lower than the drive signal controlled by the second slew rate control unit when it is notified that an abnormality has been detected. And a gate driver according to claim 1. The drive control unit includes a register file for setting the first to fourth periods,
The gate driver according to claim 1, wherein the register file is configured to be rewritable from outside.   The gate driver according to claim 1, wherein the second period has a length different from that of the first period, and the fourth period has a length different from that of the third period. In response to a control signal that controls the power transistor,
When the control signal instructs to switch to the conductive state, the drive signal for controlling the gate of the power transistor is switched from the first level to the second level and then output, and then the drive signal is Switching to the first level after elapse of the period, and switching to the second level after elapse of the second period,
When the control signal instructs to switch to the cut-off state, the drive signal is switched from the second level to the first level and output, and then the drive signal is output after the third period has elapsed. Switching method, and further switching to the first level after the fourth period has elapsed. When receiving the control signal for switching the power transistor to the conductive state, the drive signal for controlling the gate voltage of the power transistor is switched from the first level to the second level, and the drive signal is A drive control unit that controls to switch to the first level and then switch to the second level after a second period has elapsed;
A gate driver for amplifying and outputting the drive signal;
With gate driver.   When the drive control unit receives the control signal for switching the power transistor to the cutoff state, the drive control unit switches the drive signal from the second level to the first level, and the drive signal is changed to the first after the third period has elapsed. The gate driver according to claim 15, wherein the gate driver is controlled to switch to the second level and to switch to the first level after the fourth period has elapsed.   The gate driver according to claim 15, wherein the second period has a length different from that of the first period.   The gate driver according to claim 16, wherein the fourth period has a length different from that of the third period.

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