JP2014072682A - Optical phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical phase-locked loop circuit that implements an optical phase lock capable of suppressing a frequency detuning fluctuation by means of a third order phase-locked loop circuit having a simple configuration.SOLUTION: The optical phase-locked loop circuit comprises: a phase comparison section for generating a phase error signal indicating a phase error between an optical phase modulation signal and local oscillation light; a loop filter function section for generating a local oscillation control signal from the phase error signal; and a local oscillation light generation section for setting the phase or frequency of the local oscillation light on the basis of the local oscillation control signal. The loop filter function section includes: a splitter for splitting the phase error signal into three, first to third signals; oscillation control signal generation means for generating an oscillation control signal on the basis of the first signal; a first additive processing section for adding the second signal and the oscillation control signal together to generate an addition signal; a loop filter for generating a filter output signal from the addition signal; and a second additive processing section for adding the third signal and the filter output signal together to generate the local oscillation control signal.

Description

  The present invention particularly relates to an optical phase-locked loop circuit suitable for use in receiving a phase modulation signal by homodyne detection.

  Along with the recent increase in capacity of optical communication, coherent communication using phase modulation and the like, which can easily improve bandwidth utilization efficiency by multi-leveling as compared to conventional intensity modulation, has attracted attention. In communication using phase modulation, information is superimposed on the phase and transmitted.

  As a reception method in coherent communication, there are a reception method using homodyne detection and a reception method using heterodyne detection. In homodyne detection, local oscillation light having the same frequency and phase as the carrier wave of the phase-modulated reception signal is generated at the receiving end, and demodulation is performed by causing interference between the carrier wave of the reception signal and the local oscillation light. In heterodyne detection, a carrier wave of a phase-modulated received signal and a local oscillation light slightly different in frequency are generated at the receiving end, and the carrier wave of the reception signal and the local oscillation light are interfered to perform down-conversion and demodulation. . Both homodyne detection and heterodyne detection can be realized by using a phase synchronization circuit of the received signal and the local oscillation light.

  In communication by homodyne detection, an optical phase-locked loop technique disclosed in Non-Patent Document 1 is known. In the technique disclosed in this Non-Patent Document 1, by setting the modulation degree of a received binary phase shift keying (BPSK) signal to less than 100%, a carrier is left in the BPSK signal, Homodyne detection is performed by performing phase synchronization on the remaining carrier. In this case, since the carrier remains, that is, the modulation degree is not 100%, the signal / noise ratio (SNR: Signal to Noise Ratio) of the demodulated signal is theoretically deteriorated. This is because the baseband of the BPSK signal is mixed when the carrier wave of the received signal and the local oscillation light are caused to interfere with each other.

  On the other hand, in order to demodulate a phase-shift keying (PSK) signal with a modulation factor of 100%, the PSK signal does not include the spectrum component of the carrier wave. A means for extracting the error is required. As a means for extracting this phase error, a multiplication method and a Costas loop are known.

  For example, a BPSK signal is phase-modulated with a binary value whose phase is shifted by π with respect to the carrier wave. When a multiplication method that simply multiplies the carrier wave is used, for example, in the case of double multiplication, the phase 0 or π of the carrier wave is doubled to appear as 0 or 2π. Due to the periodicity of the trigonometric function, the waveform in each time slot has the same shape, and as a result, it is possible to extract a signal having a frequency twice the carrier wave. However, in optical communication in which the frequency of the carrier wave reaches several hundred THz, it is difficult to use the multiplication method due to the characteristics of the electrical device.

  In the case of the Costas loop disclosed in Non-Patent Document 2, it is possible to extract twice the phase error between the carrier wave and the local oscillation light. In this Costas loop, the I-axis signal is sin (θ + d) and the Q-axis signal is −cos (θ + d). Here, θ represents a phase error between the carrier wave of the received signal and the local oscillation light. Further, d represents a data string and takes π / 2 or −π / 2 for each time slot. When these are multiplied, the change in the data string d is canceled and sin2θ is output. Therefore, this multiplication signal can be used as a control signal for the phase locked loop.

  In the Costas loop, it is known that demodulation is difficult when the frequency difference between the carrier wave and the local oscillation light fluctuates with time. For example, when a semiconductor laser is used as a light source for signal light or local oscillation light, the fluctuation of both is generally several hundred Hz to several tens MHz (see, for example, Patent Document 1). In order to realize the frequency pull-in range required for stable operation of the optical phase-locked loop circuit, the operating band of each element constituting the circuit is required up to about several tens GHz. However, it is not easy to configure a circuit with each element satisfying these operating band requirements.

  In order to solve this problem, there is a technique of connecting a frequency discriminator in parallel with a phase-locked loop circuit (for example, see Non-Patent Document 3). By providing the frequency discriminator, the phase-locked loop circuit also functions as a frequency-locked loop, so that phase synchronization is realized after canceling frequency fluctuations.

  In addition, a column configuration in which a frequency locked loop on the front side and a phase locked loop on the rear side are provided in series has been proposed. In this case, frequency synchronization is realized, and phase synchronization is realized after frequency fluctuation is suppressed. For this reason, stability increases compared with a parallel structure.

  Further, in the field of electrical phase synchronization technology, a third-order loop phase synchronization circuit has been proposed as a technology for ensuring sufficient stability without using a frequency synchronization loop (see, for example, Non-Patent Document 4). In this third-order loop phase synchronization circuit, a frequency synchronization function is inherent in the phase synchronization circuit. For this reason, stability can be obtained only by the phase synchronization circuit.

JP-A-11-133472

Stefano Camadel et al. "10 GBIT / S 2-PSK TRANSMISSION AND HOMODYNE COHERENT DETECTION USING COMMERCIAL OPTIONAL COMPONENTS" ECOC 2003, Vol. 3, We. P. 122, pp. 800-801 Y. Chiou and L. Wang, “Effect of Optical Amplifier Noise on Laser Linewidth Requirements in Long Haul Optical Fiber Community Stimulus Coastal Resources PLL”. 14, no. 10, pp. 2126-2134 (1996) Takahide Sakamoto et al. , “Real-Time Homedyne Reception of 40-Gb / s BPSK signal by Digital Optical-Locked Loop” ECOC2010, 19-23 September, 2010, Tori Minoru Kamada et al. “A third-order phase-locked loop whose stability has been improved by inserting an active filter into the second loop of the double loop” IEICE Transactions A Vol. J82-A No. 2, pp. 273-282 February 1999

  However, in the technique of connecting a frequency discriminator in parallel with the phase-locked loop circuit disclosed in Non-Patent Document 3, since the effects of the phase-locked loop and the frequency-locked loop interfere with each other, improvement in stability cannot be expected.

  In addition, a tandem configuration in which a frequency locked loop and a phase locked loop are provided in series is difficult to realize in an optical phase locked loop circuit. For example, two optical hybrid couplers and two balance detectors are required, and a frequency shift applied to the optical voltage controlled oscillator (optical VCO) is required twice. Thus, the apparatus configuration becomes large.

  In the third-order loop phase locked loop circuit disclosed in Non-Patent Document 4, a steady error occurs according to the difference in gain between the two VCOs. For stable operation, it is necessary to reduce the gains of these two VCOs, so that they are not applied as an optical phase-locked loop circuit.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to realize optical phase synchronization capable of suppressing frequency detuning fluctuations using a simple third-order loop phase synchronization. An object is to provide an optical phase-locked loop circuit.

  In order to achieve the above-described object, the optical phase-locked loop circuit of the present invention includes a phase comparison unit, a loop filter function unit, and a local oscillation light generation unit.

The phase comparison unit generates a phase error signal indicating a phase error between the optical phase modulation signal and the local oscillation light. The loop filter function unit generates a local oscillation control signal from the phase error signal. The local oscillation light generation unit is a unit that generates local oscillation light, and sets the phase or frequency of the local oscillation light based on the local oscillation control signal. In this optical phase loop synchronization circuit, the closed loop transmission coefficient H ₁ (s) satisfies the expression (1) for the coefficients τ ₁ , τ ₂ and K _VCO ′.

Here, K _PC is a gain coefficient of the phase comparison unit, and K _VCO is a gain coefficient of the local oscillation light generation unit.

  Assuming that the phase θin (t) of the optical phase modulation signal has a fluctuation component proportional to the square of time or less, it is given by the following equation (2).

  Here, R is the rate of change proportional to the square of time, that is, the rate of time change of the frequency transition, Δω is the frequency transition, and Δθ is the time displacement of the phase. The phase θin (t) of the optical phase modulation signal expressed by the equation (2) assumes a phase fluctuation including a ramp response that causes a fluctuation more sudden than a linear phase fluctuation.

  At this time, the stationary phase error is given by the following equation (3).

  That is, the steady phase error in this optical phase locked loop circuit is 0, and the component of the signal change rate R does not remain in the steady phase error. That is, according to the configuration of the present invention, it is possible to completely cancel the influence of the rate of change R proportional to the square of time, and the transient stability is improved.

It is a schematic diagram for demonstrating schematically the optical phase locked loop circuit of this invention. It is a schematic diagram for demonstrating the structural example of an optical phase locked loop circuit. It is a schematic diagram for demonstrating the sample hold circuit with which an optical phase locked loop circuit is provided. It is a schematic diagram for demonstrating the loop filter function part with which an optical phase locked loop circuit is provided. It is a schematic diagram for demonstrating the loop filter with which a loop filter function part is provided. It is a schematic diagram for demonstrating the digital calculating part with which a phase comparison part is provided. It is an example of a block diagram of the optical phase locked loop circuit of this invention. It is a block diagram of the conventional optical phase-locked loop circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the drawings are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described, but it is merely a preferred example. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention. In each figure, the optical signal is indicated by a thick line, and the electric signal is indicated by a thin line.

(Outline of optical phase-locked loop circuit)
The outline of the optical phase-locked loop circuit according to the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram for schematically explaining an optical phase-locked loop circuit.

  The optical phase-locked loop circuit 10 includes a phase comparison unit 100, a loop filter function unit 200, and a local oscillation light generation unit 300.

  The optical phase-locked loop circuit 10 includes, for example, a binary phase modulation (BPSK) signal or a quaternary phase modulation (QPSK) signal as an optical phase modulation signal (indicated by an arrow S10 in the figure). A Shift Keying signal is input.

  The optical phase modulation signal S10 input to the optical phase locked loop circuit 10 is sent to the phase comparison unit 100. Further, the local oscillation light (indicated by an arrow S300 in the figure) generated by the local oscillation light generation unit 300 is input to the phase comparison unit 100. The phase comparison unit 100 generates a phase error signal S100 indicating a phase error between the input optical phase modulation signal S10 and the local oscillation light S300. The intensity of the phase error signal S100 corresponds to the phase error. The phase comparison unit 100 sends the generated phase error signal S100 to the loop filter function unit 200.

  The loop filter function unit 200 generates a local oscillation control signal (indicated by an arrow S200 in the figure) from the phase error information included in the phase error signal S100. The loop filter function unit 200 realizes a function as a so-called loop filter and a function as a frequency discriminator.

  The local oscillation light generation unit 300 is a unit that generates the local oscillation light S300 based on the local oscillation control signal S200, and functions as an optical voltage controlled oscillator (optical VCO). In the local oscillation light generation unit 300, the phase or frequency of the local oscillation light S300 is set based on the local oscillation control signal S200.

Here, the transfer coefficient of the loop filter function unit 200 is such that the closed loop transfer coefficient H ₁ (s) of the loop circuit becomes the above-described expression (1) with respect to the coefficients τ ₁ , τ ₂ and K _VCO ′. Is set. K _PC is a gain coefficient of the phase comparison unit 100, and K _VCO is a gain coefficient of the local oscillation light generation unit 300. A specific configuration example of the loop filter function unit 200 will be described later.

(Configuration example of optical phase-locked loop circuit)
A configuration example of the optical phase-locked loop circuit of the present invention will be described with reference to FIGS. FIG. 2 is a schematic diagram for explaining a configuration example of an optical phase-locked loop circuit. FIG. 3 is a schematic diagram for explaining a sample hold circuit included in the optical phase locked loop circuit. FIG. 4 is a schematic diagram for explaining a loop filter function unit included in the optical phase-locked loop circuit. FIG. 5 is a schematic diagram for explaining a loop filter provided in the loop filter function unit. FIG. 6 is a schematic diagram for explaining a calculation unit included in the phase comparison unit.

  The optical phase-locked loop circuit 11 of this configuration example includes a clock signal generation unit 400 and first and second delay units 450 in addition to the phase comparison unit 100, the loop filter function unit 200, and the local oscillation light generation unit 300. -1 and 450-2.

  The phase comparison unit 100 includes a 90 ° hybrid coupler 120, first and second balance detectors 122-1 and 122-2, first and second sample and hold circuits 130-1 and 130-2, and a digital operation unit. 150.

  The 90 ° hybrid coupler 120 that is an interference signal generation unit can be configured in the same manner as in Non-Patent Document 2, and includes first and second beam combiners and a 90 ° phase shifter. The first and second beam combiners and the 90 ° phase shifter are not shown.

  The optical phase modulation signal S10 input as the reception signal is branched into two, one is sent to the 90 ° hybrid coupler 120 (indicated by an arrow S12 in the figure), and the other is sent to the clock signal generating means 400 (in the figure). , Indicated by arrow S14). The optical phase modulation signal S12 and the local oscillation light S300 generated by the local oscillation light generation unit 300 are input to the 90 ° hybrid coupler 120 in a state where the polarization planes coincide. The 90 ° hybrid coupler 120 causes the optical phase modulation signal S12 and the local oscillation light S300 to interfere with each other to generate a first interference signal S120-1 and a second interference signal S120-2 that reflect the phase error of both signals. To do. In order to make the polarization planes of the optical phase modulation signal S12 and the local oscillation light S300 input to the 90 ° hybrid coupler 120 coincide with each other, a conventionally known polarization plane controller can be used. Omitted.

  The first beam combiner combines the optical phase modulation signal S12 and the local oscillation light S300 to obtain these sum and difference components as the first interference signal S120-1. The second beam combiner combines the optical phase modulation signal S12 and the optical signal obtained by phase shifting the local oscillation light S300 by π / 2 (90 °) to thereby generate the second interference signal S120-2. To obtain these sum and difference components.

  The first interference signal S120-1 and the second interference signal S120-2 generated by the 90 ° hybrid coupler 120 are sent to the first and second balance detectors 122-1 and 122-2, respectively.

  The first balance detector 122-1 as the first modulated electric signal generating means generates the first modulated electric signal S122-1 from the first interference signal S120-1. The first balance detector 122-1 includes two photodetectors inside. The first balance detector 122-1 photoelectrically converts the sum component and the difference component included in the first interference signal S120-1, respectively, and then subtracts the difference component photoelectric conversion signal from the sum component photoelectric conversion signal. The signal is generated as a first modulated electrical signal S122-1.

  The second balance detector 122-2 as the second modulated electric signal generating means generates the second modulated electric signal S122-2 from the second interference signal S120-2. The second balance detector 122-2 includes two photodetectors inside. The second balance detector 122-2 photoelectrically converts the sum component and difference component included in the second interference signal S120-2, and then subtracts the difference component photoelectric conversion signal from the sum component photoelectric conversion signal. The signal is generated as a second modulated electrical signal S122-2.

  In the following description, the first modulated electrical signal S122-1 may be referred to as an I-axis signal, and the second modulated electrical signal S122-2 may be referred to as a Q-axis signal.

  The I-axis signal S122-1 is branched into two, one of which is output from the optical phase-locked loop circuit 11 as the demodulated signal S124-1, and the other is sent to the first sample and hold circuit 130-1 (in the figure, (Indicated by arrow S126-1). The Q-axis signal S122-2 is branched into two, one of which is output as the demodulated signal S124-2 from the optical phase-locked loop circuit 11, and the other is sent to the second sample and hold circuit 130-2 ( In the figure, it is indicated by an arrow S126-2). If the optical phase modulation signal S10 is a BPSK signal, the Q-axis signal may not be output from the optical phase locked loop circuit 11.

  The first sample and hold circuit 130-1 as the first intensity holding means holds the intensity of the I-axis signal S126-1 for a predetermined period. The period held by the first sample-and-hold circuit 130-1 is determined corresponding to the cycle T of the clock signal S400 generated by the clock signal generation means 400.

  Here, the first sample hold circuit 130-1 will be described with reference to FIG. FIG. 3 is a schematic diagram illustrating a configuration example of the sample hold circuit 130-1. The sample hold circuit 130-1 in this configuration example includes a first buffer 132, a second buffer 136, a capacitor 138, and a switch 134. The switch 134 opens and closes in accordance with the period T of the clock signal, whereby the voltage corresponding to the signal strength is held in the capacitor 138 for a period determined by the period T. Note that the sample hold circuit 130-1 only needs to have a function of holding the intensity for a predetermined period, and is not limited to this configuration example. The second sample and hold circuit 130-2 as the second intensity holding unit can be configured in the same manner as the first sample and hold circuit 130-1, and thus the description thereof is omitted.

  The first and second sample hold circuits 130-1 and 130-2 respectively hold the intensities of the I-axis signal and the Q-axis signal for a predetermined period, that is, the first intensity hold signal S130-1 that has been sample-held. And a second intensity holding signal S130-2. The first and second intensity holding signals S130-1 and S130-2 are sent to the calculation means.

  In this configuration example, the calculation means is configured as a digital calculation unit 150 that processes a digital signal. For this reason, the phase modulation unit 100 converts the first and second intensity holding signals S130-1 and S130-2, which are analog signals, into digital signals before the digital operation unit 150, respectively. Analog-digital converters (A / D) 140-1 and 140-2 are provided. Further, a digital-analog converter (D / A) 190 that converts an arithmetic processing signal, which is a digital signal, into an analog signal is provided at the subsequent stage of the digital arithmetic unit 150. Note that when the arithmetic means is configured as an analog arithmetic means for processing an analog signal, A / D and D / A are not necessary. In the following description, the signals before and after the A / D conversion are referred to as first and second intensity holding signals S130-1 and S130-2, and the signals before and after the D / A conversion are both This is referred to as a phase error signal S100. A configuration example of the digital arithmetic unit 150 will be described later.

  The clock signal generation unit 400 includes a 1-bit delay interferometer 410, a photoelectric converter 420, a clock extractor 430, and a frequency divider 440.

  The 1-bit delay interferometer 410 divides the optical phase modulation signal S14 into two branches, delays one of them after being delayed by 1 bit, and causes the interference to generate a 1-bit delayed interference signal S410. At the time of interference, if the phase error between the two is 0, they are strengthened, and if π, they are weakened. As a result, the 1-bit delayed interference signal S410 is generated as a signal similar to the light intensity modulation signal.

  The photoelectric converter 420 photoelectrically converts the 1-bit delayed interference signal S410 to generate a delayed interference electrical signal S420.

  The clock extractor 430 extracts a clock S430 having a period Ts from the delayed interference electric signal S420.

  The frequency divider 440 divides the clock S430 having the period Ts extracted by the clock extractor 430 to generate the clock signal S400 having the period T. The period T of the clock signal S400 defines the holding period in the sample and hold circuit 130. Therefore, by dividing the frequency, a frequency that can be processed by the digital arithmetic unit 150 is obtained. Since the fluctuation component of the phase error may be about several MHz, the frequency of the clock extraction signal should be sufficiently higher than this.

  It should be noted that each component of the clock signal generating unit 400 can be any suitable conventionally known component.

  The clock signal S400 is branched into two, and one (indicated by an arrow S400-1 in the figure) is sent to the first delay unit 450-1, and the other (indicated by an arrow S400-2 in the figure) is the first. 2 to the delay unit 450-2. The clock signals S450-1 and S450-2, the timings of which are adjusted by the first and second delay units 450-1 and 450-2, respectively, are the first and second sample and hold circuits 130-1 and 130-2. Sent to.

  A configuration example of the loop filter function unit 200 will be described with reference to FIG.

  The loop filter function unit 200 includes a loop filter 240, an oscillation control signal generation unit 220, a branching device 210, a first adder 230, and a second adder 250.

  The branching device 210 branches the phase error signal S100 into the first to third signals S211 to S213. The first to third signals S211 to S213 obtained by the three branches are sent to the oscillation signal generation unit 220, the first adder 230, and the second adder 250, respectively.

The oscillation control signal generation unit 220 includes a voltage controlled oscillator (VCO) 222, a reference frequency oscillator 224, and a multiplier 226. The gain coefficient of the _VCO 222 included in the oscillation control signal generation unit 220 can be K _VCO ′.

  The VCO 222 generates an oscillation signal S222 based on the first signal S211. The reference frequency oscillator 224 generates a reference signal S224 having the same oscillation frequency as the center frequency of the VCO 222. The multiplier 226 generates the oscillation control signal S220 by multiplying the oscillation signal S222 and the reference signal S224.

  As described above, the oscillation control signal generation unit 220 generates the oscillation control signal S220 based on the first signal S211. The oscillation control signal S220 generated by the oscillation control signal generation unit 220 is sent to the first adder 230.

  Here, in the oscillation control signal S220 generated by the multiplier 226, the sum frequency component and the difference frequency component of the oscillation signal S222 and the reference signal S224 are mixed. By using the reference frequency oscillator 224 having a sufficiently large reference oscillation frequency and the VCO 222 having a sufficiently large center frequency as compared with the cut-off frequency band of the loop filter 240, this sum frequency component can be removed by the loop filter 240. is there.

  The first adder 230 adds the second signal S212 received from the branching device 210 and the oscillation control signal S220 received from the oscillation control signal generation unit 220, thereby generating an addition signal S230. The addition signal S230 generated by the first adder 230 is sent to the loop filter 240.

  As the loop filter 240, for example, a complete integration type first-order filter can be used. A configuration example of the loop filter 240 is shown in FIG. The transfer function F (s) of the complete integration type first-order filter shown in FIG. 5 is given by the following equation (4).

  The loop filter 240 generates a filter output signal S240 from the addition signal S230. The filter output signal S240 generated by the loop filter 240 is sent to the second adder 250.

  The second adder 250 adds the third signal S213 and the filter output signal S240 to generate a local oscillation control signal S200. The local oscillation control signal S200 generated by the second adder 250 is sent to the local oscillation light generation unit 300.

Next, the local oscillation light generation unit 300 will be described. The local oscillation light generation unit 300 as a local oscillation light generation unit includes a voltage controlled oscillator (VCO) 310, a light source 320, and a modulator 330. The VCO 310 changes its own transmission frequency f _VCO according to the phase error signal S100. Light source 320 generates continuous light S320 of the carrier frequency _{f 0} of the optical phase modulation signal S10, a so-called continuous light (CW light). The modulator 330 modulates the continuous light S320 according to the oscillation signal S310 generated by the VCO 310 to obtain a local oscillation light S300. The local oscillation light S300 generated by the local oscillation light generation unit 300 is sent to the 90 ° hybrid coupler 120.

  Here, as the modulator 330, for example, a single side band (SSB) modulator can be used. The SSB modulator is a modulator that outputs only a single sideband. For this reason, the use of the SSB modulator eliminates the need for a bandpass filter that removes excess sidebands.

  The digital arithmetic unit 150 will be described with reference to FIG. FIG. 6A is a schematic diagram illustrating a configuration example of the digital arithmetic unit 150 when the optical phase modulation signal S10 is a BPSK signal. FIG. 6B is a schematic diagram illustrating a configuration example of the digital arithmetic unit 150 when the optical phase modulation signal S10 is a QPSK signal.

  When the optical phase modulation signal S10 is a BPSK signal, the digital calculation unit 150 includes a multiplication processing unit 152. In this case, the digital calculation unit 150 generates a signal obtained by multiplying the first intensity holding signal S130-1 and the second intensity holding signal S130-2 as the phase error signal S100. The first intensity holding signal S130-1 is obtained by sampling and holding the I-axis signal (sin (θ + d)), and the second intensity holding signal S130-2 is obtained by applying the Q-axis signal (−cos (θ + d)). Sample hold. At this time, the phase error signal S100 as a multiplication signal is −cos (θ + d) · sin (θ + d) = − 2 sin (2θ + 2d).

  In the case of a BPSK signal, the data string d is d = π / 2 and −π / 2. Therefore, the phase error signal S100 becomes sin 2θ, and twice the phase error is extracted. By using this phase error signal S100 as a feedback control signal, a phase locked loop for BPSK can be configured. The phase error signal S100 generated by the digital arithmetic unit 150 is sent to the loop filter function unit 200.

  When the optical phase modulation signal S10 is a QPSK signal, the digital calculation unit 150 includes an addition processing unit 162, a subtraction processing unit 164, and first to third multiplication processing units 166, 168, and 170. The first intensity holding signal input to the digital arithmetic unit 150 is branched into three (indicated by arrows S131, S132, and S133 in the figure), and an addition processing unit 162, a subtraction processing unit 164, and a first multiplication processing unit. 166. Similarly, the second intensity holding signal input to the digital calculation unit 150 is branched into three (indicated by arrows S134, S135, and S136 in the figure), and the addition processing unit 162, the subtraction processing unit 164, and the first The data is sent to the multiplication processing unit 166.

  The addition processing unit 162 adds the first intensity holding signal S131 and the second intensity holding signal S134 to generate an addition signal S162. The first intensity holding signal S131 is obtained by sampling and holding the I-axis signal (sin (θ + d)), and the second intensity holding signal S134 is obtained by sampling and holding the Q-axis signal (−cos (θ + d)). It is. Therefore, the addition signal S162 is sin (θ + d) −cos (θ + d).

  The subtraction processing unit 164 performs subtraction between the first intensity holding signal S132 and the second intensity holding signal S135 to generate a subtraction signal S164. At this time, the subtraction signal S164 is sin (θ + d) + cos (θ + d).

  The first multiplication processing unit 166 multiplies the first intensity holding signal S133 and the second intensity holding signal S136 to generate a multiplication signal S166. At this time, the multiplication signal S166 is −cos (θ + d) · sin (θ + d) = − 2 sin (2θ + 2d).

  The second multiplication processing unit 168 multiplies the addition signal S162 generated by the addition processing unit 162 and the subtraction signal S164 generated by the subtraction processing unit 164. At this time, the multiplication signal S168 in the second multiplication processing unit 168 is {sin (θ + d) −cos (θ + d)} · {sin (θ + d) + cos (θ + d)} = sin2 (θ + d) −cos2 (θ + d) = −cos (2θ + 2d).

  The third multiplication processing unit 170 multiplies the multiplication signal S166 generated by the first multiplication processing unit 166 and the multiplication signal S168 generated by the second multiplication processing unit 168 to obtain the phase error signal S100. Generate. At this time, the phase error signal S100 is {−2 sin (2θ + 2d)} · {−cos (2θ + 2d)} = − sin (4θ + 4d).

  In the case of a QPSK signal, the data string d is d = kπ / 2 (k = 0, 1, 2, 3). Therefore, the phase error signal S100 becomes sin 4θ, and four times the phase error is extracted. By using this phase error signal as a feedback control signal, a phase locked loop for QPSK can be configured.

(Loop circuit transfer function)
The transfer function of the optical phase locked loop circuit will be described with reference to FIG. FIG. 7 is a block diagram of the optical phase-locked loop circuit mainly described with reference to FIGS. 1 and 4.

A phase modulation signal and local oscillation light are input to the phase comparison unit 100. This phase modulation signal is expressed as θ _in using the phase, and the local oscillation light (S5) is expressed as θ _out using the phase. When the gain coefficient of the phase comparator 100 is _{K PC,} the phase error signal outputted from the phase comparator 100 _is a _{K PC} theta. Here, θ is θ _in −θ _out .

The phase error signal is branched into three by the branching device to the first to third signals. These first to third signals are all K _PC θ. That is, in FIG. 7, the signals indicated by S1 and S4 are represented as K _PC θ.

The oscillation control signal generation means 220 generates an oscillation control signal (S2) based on the first signal. When the gain coefficient of the voltage controlled oscillator is K _VCO ′, the oscillation control signal (S2) is expressed by the following equation (5).

  The oscillation control signal (S2) and the first signal (S1) are added by the first adder 230 and then sent to the loop filter 240 to generate a filter output signal (S3). The filter output signal (S3) is expressed by the following equation (6) using the transfer function F (s) of the loop filter.

  The local oscillation control signal is generated by adding the third signal (S4) and the filter output signal (S3).

Furthermore, when the gain coefficient of the local oscillation light generation unit 300 is K _VCO , the local oscillation light (S5) is expressed by the following equation (7).

At this time, the closed-loop transfer coefficient H ₁ (s) of the optical phase-locked loop circuit is expressed by the following formula (8). When this is modified, formula (9) is obtained.

  From the equations (4), (7) and (9), the above equation (1) is obtained.

  Now, it is assumed that the phase of the optical phase modulation signal is given by the above equation (2). The Laplace transform of this equation (2) is given by the following equation (10).

  At this time, the stationary phase error can be obtained by using the equations (1) and (10), and the above equation (3) is obtained. That is, the steady phase error in this optical phase locked loop circuit is zero.

  For comparison, the steady-state error of the conventional optical phase-locked loop circuit will be described.

  FIG. 8 is a block diagram of a conventional optical phase-locked loop circuit. In the conventional optical phase-locked loop circuit, the phase comparison unit 100 and the local oscillation light generation unit 300 have the same configuration as that of the above-described embodiment, but the loop filter function unit is configured by only the loop filter 240. Different.

In this conventional synchronous loop, 1-H ₂ (s) is given by the following equation (11).

  As a result, the component of the signal change rate R remains in the steady phase error, as the steady phase error is given by the following equation (12).

  On the other hand, according to the configuration of the present invention, it is possible to completely cancel the influence of the change rate, and it is understood that the transient stability is improved.

10, 11 Optical phase-locked loop circuit 100 Phase comparison unit 120 90 ° hybrid coupler 122 Balance detector 124 Loop filter 130 Sample hold circuit 132, 136 Buffer 134 Switch 138 Capacitor 140 Analog-digital converter (A / D)
150 Digital operation unit 190 Digital-analog converter (D / A)
200 Loop Filter Function Unit 210 Branching Unit 220 Oscillation Control Signal Generation Unit 222, 310 Voltage Controlled Oscillator (VCO)
224 Reference frequency oscillator 226 Multiplier 230 First adder 240 Loop filter 250 Second adder
300 Local oscillation light generator
320 Light source 330 Modulator 400 Clock signal generation means
410 1-bit delay interferometer 420 Photoelectric converter 430 Clock extractor 440 Frequency divider 450 Delay device

Claims (12)

A phase comparator that generates a phase error signal indicating a phase error between the optical phase modulation signal and the local oscillation light;
A loop filter function unit for generating a local oscillation control signal from the phase error signal;
A means for generating the local oscillation light, and a loop circuit comprising a local oscillation light generation unit for setting a phase or a frequency of the local oscillation light based on the local oscillation control signal,
When the gain coefficient of the phase comparison unit is K _PC and the gain factor of the local oscillation light generation unit is K _VCO , the closed loop transmission coefficient H _{1 of the} loop circuit is used for the coefficients τ ₁ , τ _2, and K _VCO ′. (S) satisfies Formula (1), The optical phase-locked loop circuit characterized by the above-mentioned.

The loop filter function unit
A loop filter in which the transfer coefficient F (s) is given by (τ ₂ s + 1) / τ ₁ s;
The optical phase-locked loop circuit according to claim 1, further comprising: an oscillation control signal generating unit including a voltage controlled oscillator having a gain coefficient of K _VCO ′. The loop filter function unit includes a branching unit, first and second adders,
The branching device branches the phase error signal into three first to third signals,
The oscillation control signal generating means generates an oscillation control signal based on the first signal,
The first adder generates an addition signal by adding the second signal and the oscillation control signal,
The loop filter generates a filter output signal from the sum signal,
3. The optical phase-locked loop circuit according to claim 2, wherein the second adder generates the local oscillation control signal by adding the third signal and the filter output signal. 4. Generating a phase error signal indicating a phase error of the optical phase modulation signal and the local oscillation light, the gain factor and the phase comparator of the K _PC,
A loop filter function unit for generating a local oscillation control signal from the phase error signal;
A means for generating the local oscillation light, comprising: a local oscillation light generation unit having a gain coefficient of K _VCO that sets a phase or a frequency of the local oscillation light based on the local oscillation control signal; Function part
A branching device for branching the phase error signal into first to third signals;
An oscillation control signal generating means including a voltage controlled oscillator having a gain coefficient of K _VCO ′ and generating an oscillation control signal based on the first signal;
A first adder that generates an addition signal by adding the second signal and the oscillation control signal;
A loop filter having a transfer coefficient F (s) given by (τ ₂ s + 1) / τ ₁ s and generating a filter output signal from the sum signal;
A second adder for generating the local oscillation control signal by adding the third signal and the filter output signal;
An optical phase-locked loop circuit comprising: The oscillation control signal generating means includes a reference frequency oscillator and a multiplier,
The voltage controlled oscillator generates an oscillation signal based on the first signal;
The reference frequency oscillator generates a reference signal having the same oscillation frequency as the center frequency of the voltage controlled oscillator,
The optical phase-locked loop circuit according to claim 3, wherein the multiplier generates the oscillation control signal by multiplying the oscillation signal and the reference signal. The phase comparison unit includes:
Interference signal generating means for causing the phase-modulated signal and the local oscillation light to interfere with each other and generating first and second interference signals reflecting the phase error of both signals;
First modulated electrical signal generating means for generating a first modulated electrical signal from the first interference signal;
Second modulated electrical signal generating means for generating a second modulated electrical signal from the second interference signal;
First intensity holding means for holding the intensity of the first modulated electric signal for a predetermined period to generate a first intensity holding signal;
Second intensity holding means for holding the intensity of the second modulated electric signal for a predetermined period to generate a second intensity holding signal;
6. The optical phase-locked loop circuit according to claim 1, further comprising a calculation unit that generates a phase error signal from the first and second intensity holding signals. A clock signal generating means;
The input phase modulation signal is branched into two, one is sent to the interference signal generation means, the other is sent to the clock signal generation means,
The clock signal generation means extracts a clock from the phase modulation signal to generate a clock signal,
The said 1st and 2nd intensity | strength holding means hold | maintains the intensity | strength of the said 1st and 2nd intensity | strength holding means for the period corresponding to the period of the said clock signal, respectively. Optical phase-locked loop circuit. The clock signal generation means includes
A 1-bit delay interferor that bifurcates the phase-modulated signal, delays one of the signals after being delayed by 1 bit, and generates a 1-bit delayed interference signal;
A photoelectric converter that photoelectrically converts the 1-bit delayed interference signal to generate a delayed interference electrical signal;
A clock extractor for extracting a clock from the delayed interference electrical signal;
The optical phase-locked loop circuit according to claim 7, further comprising a frequency divider that divides the clock to generate a clock signal. The optical phase-locked loop circuit according to any one of claims 6 to 8, wherein the arithmetic means includes a multiplication processing unit that multiplies the first intensity holding signal and the second intensity holding signal. The computing means includes an addition processing unit, a subtraction processing unit, and first to third multiplication processing units,
The first and second intensity holding signals input to the calculation means are each branched into three and sent to the addition processing unit, the subtraction processing unit, and the first multiplication processing unit,
The addition processing unit adds the first intensity holding signal and the second intensity holding signal,
The subtraction processing unit subtracts the first intensity holding signal and the second intensity holding signal,
The first multiplication processing unit multiplies the first intensity holding signal and the second intensity holding signal,
The second multiplication processing unit multiplies the addition signal generated by the addition processing unit and the subtraction signal generated by the subtraction processing unit,
The third multiplication processing unit multiplies the multiplication signal generated by the first multiplication processing unit and the multiplication signal generated by the second multiplication processing unit to generate a phase error signal. The optical phase-locked loop circuit according to any one of claims 6 to 8. The computing means is a digital computing means,
An analog-digital converter is provided at the input unit of the arithmetic means,
The optical phase-locked loop circuit according to any one of claims 6 to 10, wherein a digital-analog converter is provided at an output section of the arithmetic means. The local oscillation light generator is
A voltage-controlled oscillator that generates the local oscillation signal based on the local oscillation control signal;
A light source that generates continuous light;
12. The apparatus according to claim 1, further comprising a single sideband (SSB) modulator that modulates the continuous light by the local oscillation signal to generate the local oscillation light. Optical phase-locked loop circuit.

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