JP2014067912A - Current mirror circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current mirror circuit excellent in stability of mirror-ratio accuracy.SOLUTION: In a current mirror circuit composed of first and second MOS transistors provided on a silicon substrate and having a gate connected to each other, first and second well regions are formed on the silicon substrate, and the first and second well regions have the same polarity and different impurity concentrations from each other. Further, the first and second MOS transistors are both formed in the first well region.

Description

  The present invention relates to a current mirror circuit composed of a pair of MOS transistors. In particular, the present invention relates to a current mirror circuit with excellent mirror ratio accuracy.

  As electronic devices become more sophisticated, analog ICs such as voltage regulators and Li protection ICs are required to have higher output voltage accuracy. These ICs are mainly composed of elements such as a reference voltage circuit, a comparator, a bleeder resistor, and a current mirror circuit. Increasing the accuracy of each of these elements leads to higher accuracy of the entire IC.

  A current mirror circuit which is one of element circuits is a circuit used when a constant current is required inside an IC. For example, it is used in a load stage of a comparator as a constant current source, or a predetermined time constant is determined in combination with a capacitor to constitute a delay circuit.

  The simplest configuration of this current mirror circuit is a circuit in which the gates of two transistors A and B are connected as shown in FIG. In this circuit, when the input current I1 is input from the source side of the transistor A, the output current I2 is increased or decreased by a predetermined current ratio from the drain side of the transistor B and output. At this time, I1 / I2, which is the current ratio between the input current and the output current, is called a mirror ratio and is an index representing the characteristics of the current mirror circuit. This mirror ratio becomes 1, for example, when the characteristics of the transistors A and B are completely equal. If the channel length L is L1 and L2, respectively, and other parameters are equal, the mirror ratio is determined by the L length ratio L1 / L2.

  However, when L and W deviate from the target values due to fluctuations in manufacturing process conditions, the mirror ratio accuracy decreases. Furthermore, the mirror ratio accuracy similarly decreases when a characteristic variation that causes a threshold voltage change such as a short channel effect, an inverse short channel effect, or a narrow channel effect occurs.

  Therefore, as one method for solving these problems, by connecting transistors of the same size in parallel, the deviation of the effective gate width caused by the spread of the edge of the element isolation oxide film is suppressed, and the mirror as designed. A current mirror circuit capable of obtaining a ratio is provided (see, for example, Patent Document 1).

  As another method, there is provided a current mirror circuit in which transistors of different sizes are connected in parallel through a fuse in advance and are adjusted to an ideal mirror ratio by fuse trimming (see, for example, Patent Document 2).

  Furthermore, a method of predicting the occurrence mechanism of the inverse short channel effect, which is one of the causes of lowering the mirror ratio accuracy, by simulation and reflecting it in the circuit design in advance is disclosed (for example, see Patent Document 3). .

JP-A-5-95233 JP 2009-147881 A Japanese Patent Laid-Open No. 10-50995

  Certainly, according to the methods disclosed in Patent Documents 1 and 2, variations due to the manufacturing process can be absorbed and a highly accurate current mirror circuit can be configured. However, since the occupied area is increased by increasing the number of transistors to be configured or separately providing trimming fuses, there is a problem that it is difficult to reduce the chip size.

  Also, with the method according to Patent Document 3, even if the reverse short channel effect occurs, the accuracy of the current mirror circuit can be maintained by predicting the threshold voltage change in advance and incorporating it into the circuit design. it can. However, at present, the reverse short channel effect may or may not occur depending on the process conditions. Under such circumstances, it is impossible to design a circuit so as to correspond to any of them.

  Therefore, in the present invention, in the current mirror circuit composed of the first and second MOS transistors whose gates are connected to each other, the first and second well regions are formed on the silicon substrate. The first and second well regions are well regions having the same polarity and different impurity concentrations, and the first and second MOS transistors are both current mirror circuits formed in the first well region. By providing the above, the above-described problem can be solved.

  That is, according to the present invention, by independently changing only the well concentration of the pair transistor used in the current mirror, the occurrence of the reverse short channel effect is effectively suppressed without affecting other elements, and the stability is improved. An excellent high-precision current mirror circuit can be provided.

  In carrying out the present invention, the polarities of the first and second well regions are N-type, and the impurity concentration of the first well region is lower than the impurity concentration of the second well region. It is preferable. This is because the well concentration of the transistor that determines the accuracy of the current mirror can be set to a low concentration condition that can easily suppress the reverse short channel.

  In carrying out the present invention, when the impurity concentration of the first well region is N1, and the impurity concentration of the second well region is N2, the ratio N1 / N2 between N1 and N2 is a value of 0.5 or less. It is preferable that This is because a value within such a range can effectively suppress the occurrence of the reverse short channel effect without affecting other elements.

  In implementing the present invention, the mirror ratio of the current mirror circuit is preferably determined by adjusting the L length of the first MOS transistor and the L length of the second MOS transistor. With this configuration, the mirror ratio can be easily adjusted, and a desired mirror ratio accuracy can be arbitrarily set.

  As described above, in the present invention, by independently changing the well concentration of the pair transistor constituting the current mirror, the low concentration condition in which the reverse short channel effect is unlikely to occur can be achieved, and the mirror ratio accuracy is stabilized. A current mirror circuit excellent in performance can be provided.

Circuit diagram of delay time circuit using current mirror circuit of the present invention Cross-sectional structure diagram explaining reverse short channel effect (1) Cross-sectional structure diagram explaining reverse short channel effect (2) Cross-sectional structure diagram explaining reverse short channel effect (Part 3) Concentration profile explaining reverse short channel effect Characteristic diagram showing the relationship between the occurrence of reverse short channel and well concentration Arrangement of transistors according to the present invention Conventional current mirror circuit

Hereinafter, embodiments of the current mirror circuit of the present invention will be described with reference to FIGS.
1. Description of Circuit FIG. 1 is a delay time circuit using a current mirror circuit of the present invention. This circuit is composed of five transistors (Tr1 to Tr5). Tr1 and Tr2 constitute a current mirror circuit C1, and Tr3 to Tr5 constitute a current mirror circuit C2. At this time, the basic parameters of Tr1 to Tr5 are set as follows.

Tr1: PchTr Vth = -0.6V L = 30um W = 30um
Tr2: PchTr Vth = −0.6V L = 120 um W = 30 um
Tr3-5: NchTr Vth = 0.6V L = 12um W = 100um
Here, PcnTr represents a P-channel transistor, NchTr represents an N-channel transistor, Vth represents a threshold voltage, L represents a channel length, and W represents a channel width.

  First, the input current I1 flows between the source and drain of Tr1. This I1 is mirrored to I2 by the current mirror circuit C1. The mirror ratio at this time is 0.25, which is the L length ratio of Tr1 and Tr2.

  I2 then enters the source of Tr3. This Tr3 constitutes a current mirror circuit C2 together with Tr4 and Tr5. Since Tr3, 4 and 5 have the same structure and their gates are connected to each other, I2 is mirrored to I3 and I4, and I2 = I3 = I4.

  Finally, the output current I6 is obtained as I3 + I4. By connecting a capacitor to the Iout terminal, a predetermined time constant is determined, and a delay time circuit can be configured.

2. Inverse short channel effect The circuit operation as described above is an ideal situation, and actually, a characteristic variation caused by a manufacturing process occurs. As an example, there is a phenomenon peculiar to a MOS transistor called reverse short channel effect in which the threshold voltage increases as the channel length becomes shorter.

In general, a MOS transistor has a so-called short channel effect in which the threshold voltage decreases as the channel length decreases. On the other hand, on the other hand, when the channel length is shortened, the reverse short channel effect in which the threshold voltage increases may occur.
There are several factors that cause this reverse short channel effect, but the following three are mainly considered.

  First, the gate oxide film thickness as shown in FIG. FIG. 2 is a cross-sectional view of the P-type MOS transistor 11. The PMOS transistor 11 includes an Si substrate 1 (N-type substrate), an N well 2 (Phos), a gate oxide film 3 (800 mm), a polysilicon gate 4 (Phos), and a source / drain region 5 (Boron). And a channel region 6 (Boron). At this time, the gate oxide film 3 is ideally formed with a uniform thickness, but depending on the process conditions, a locally thickened region 7 may be formed at the channel end. . For example, when a polysilicon gate is thermally oxidized, the gate end is excessively oxidized and eroded inward (gate bird's beak). In the case of such a shape, when the L length is sufficiently long (B >> A), there is almost no influence of the end A, but when the L length is short (B≈A), the end A The influence increases and the threshold voltage rises. That is, a so-called reverse short channel effect in which the threshold voltage increases as the L length becomes shorter appears.

  Next, as shown in FIG. 3, even when the channel end portion is not thickened, when nitriding is performed after forming the oxide film, the SiN region 8 is formed at the channel end portion, and the dielectric is formed. In some cases, the same effect as when the gate oxide film is effectively thickened may occur in relation to the rate.

  Finally, as shown in FIG. 4, a region having a high impurity concentration may be formed in the vicinity of the boundary between the source / drain and the channel region (region 9 in FIG. 4). Although there are various theories, impurity redistribution occurs in the vicinity of the channel edge due to crystal defects generated during source / drain ion implantation. As a result, it is considered that the high concentration region 9 is formed just under the gate.

  FIG. 5 is a diagram depicting an impurity concentration profile at the XX section in FIG. In FIG. 5, a line A indicates a boron concentration profile, and a line B indicates a phosphorus concentration profile. Here, the line B shows the concentration profile when the reverse short channel is not generated, and the line B ′ shows the concentration profile when the reverse short channel is generated. As can be seen from this figure, the concentration profile when the reverse short channel occurs has a peak C in the vicinity of the end of the gate electrode. This is caused by the impurity redistribution described above.

3. Well Concentration Dependence Among the above-described reverse short channel effects, particularly in the case of the cause shown in FIG. 4, the dependence varies depending on the well concentration.

  FIG. 6 is a characteristic diagram showing the relationship between the occurrence of a reverse short channel and the well concentration. In this figure, the horizontal axis represents the channel length L, and the vertical axis represents the PMOS threshold voltage. Of the two curves, the dotted line is the characteristic of the conventional high concentration N well (Phos dose = 5.75E12 / cm2), and the solid line is the characteristic of the low concentration N well of the present invention (Phos dose = 2.5E12 / cm2). It is a curve. As can be seen from this figure, it can be seen that the occurrence of the reverse short channel is suppressed as the well concentration is lower. This is because the height of the peak C in FIG. 5 decreases as the well concentration decreases.

4). Therefore, in the present invention, in order to suppress the occurrence of the reverse short channel, the N well concentration of the paired transistors constituting the current mirror is reduced. However, simply reducing the well concentration of the entire IC simply changes the threshold voltages of all PMOSs and greatly affects the junction breakdown voltage and punch-through breakdown voltage. In addition, there is a difference in the concentration between the N well and the P well, and the balance between the PMOS and NMOS is also deteriorated. Therefore, in the present invention, only the well concentration of the transistor in which the reverse short channel is a problem is partially changed. In this way, partial optimization can be performed without affecting the entire IC.

  A specific layout is shown in FIG. This figure shows a layout of a current mirror circuit composed of a PMOS 21 as a first transistor and a PMOS 22 as a second transistor 2. The source 21 a of the PMOS 1 and the source 22 a of the PMOS 2 are connected to the power supply voltage via the metal wiring 25. The drain 21b of the PMOS 1 is connected to the gate 21c of the PMOS 1 through the metal wiring 26, and an input current I1 flows there. Further, the drain 22b of the PMOS 2 is connected to the metal wiring 27, through which the output current I2 flows.

  In such a layout, the feature of the present invention is that only PMOS 1 and PMOS 2 are arranged in the N well 23 which is the first well region, and the other PMOS is arranged in the N well 24 which is the second well region. It is. That is, only PMOS1 and PMOS2 are formed in wells independent of other PMOS. With this configuration, even if reverse short channels are generated in PMOS1 and PMOS2, the well concentration can be changed independently, so that the mirror ratio accuracy can be stabilized without affecting other elements. A current mirror circuit excellent in performance can be configured.

  Furthermore, it is preferable that the concentration of the N well 23 as the first well region is lower than the concentration of the N well 24 as the second well region. This is because by arranging the transistor in which the reverse short channel is a problem in the thinner well, the occurrence of the reverse short channel can be effectively suppressed.

  Specifically, the ion implantation amount of the N well 23 as the first well region is set to a value within the range of Phos2.50E12 to 3.00E12 / cm2, and the N well 24 as the second well region The ion implantation amount is preferably set to a value within the range of Phos5.00E12 to 6.00E12 / cm2. Further, when the impurity concentration of the first well region is N1, and the impurity concentration of the second well region is N2, it is preferable that the ratio N1 / N2 of N1 and N2 is 0.5 or less. This is because by setting the value within such a range, it is possible to set a well concentration that can suppress the reverse short channel most.

5. Adjustment of mirror ratio In the current mirror circuit employing the transistor having the above-described structure, the mirror ratio is to adjust the L length of the first MOS transistor and the L length of the second MOS transistor in FIG. Is preferably determined by:

  When the reverse short channel occurs, it is difficult to adjust the mirror ratio with the L length, but with the current mirror circuit of the present invention in which the reverse short channel does not easily occur, the mirror ratio can be adjusted with the L length. Can be used. From the viewpoint of accuracy, it is more preferable to adjust by the number of transistors, but it is more preferable to adjust by L length in consideration of the influence of the increase in occupied area.

6). Applicable range Further, the L length of the first MOS transistor is a value in the range of 10 to 30 μm, the L length of the second MOS transistor is a value in the range of 40 to 300 μm, and the mirror The ratio is preferably a value within the range of 0.1 to 0.25.

  In the present invention, since the occurrence of the reverse short channel is suppressed, the present invention can be applied to a wide range of L lengths. However, since the short channel effect occurs, the L length may be 10 μm or more. preferable.

1 Si substrate 2 Well 3 Gate oxide film 4 Polysilicon gate 5 Source / drain 6 Channel region 7 Gate bird's beak region 8 SiN region 9 High concentration region 11 MOS transistor 21 First MOS transistor (PMOS 1)
21a Source terminal 21b of the first MOS transistor Drain terminal 21c of the first MOS transistor Gate terminal 22 of the first MOS transistor Second MOS transistor (PMOS2)
22a Source terminal 22b of the second MOS transistor Drain terminal 23 of the second MOS transistor First well region 24 Second well regions 25-27 Metal wiring

Claims (2)

A current mirror circuit formed of a first and a second MOS transistor formed on a silicon substrate and having gates connected to each other,
First and second well regions are formed on the silicon substrate, and the first and second well regions are well regions having the same polarity and different impurity concentrations, and the first well region The impurity concentration of is made thinner than the impurity concentration of the second well region,
The first and second MOS transistors are both formed in the first well region,
The mirror ratio is determined by adjusting the L length of the first MOS transistor and the L length of the second MOS transistor,
The other MOS transistor having the same polarity as the first and second MOS transistors is formed in the second well region.   When the impurity concentration of the first well region is N1, and the impurity concentration of the second well region is N2, the ratio N1 / N2 between N1 and N2 is 0.5 or less. The current mirror circuit according to claim 1.

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