JP2014067886A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress thinning of an electrode film formed on a capacitance insulating film.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of forming a first electrode film, forming an amorphous film on the first electrode film, forming a second electrode film on the amorphous film, and crystallizing the amorphous film after a second crystal film is formed.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a capacitor.

In order to realize both the demand for miniaturization and the securing of capacity, the related DRAM (Dynamic Random Access Memory) adopts a three-dimensional structure for the capacitor. In order to cope with further miniaturization, an insulating film having a high relative dielectric constant, which is advantageous for increasing the capacity, is employed as the capacitor insulating film. For example, zirconium oxide (ZrO ₂ ) is known as a capacitive insulating film material having a high relative dielectric constant (see, for example, Patent Documents 1 to 3).

JP 2002-314072 A JP 2012-142487 A JP 2012-146915 A

  When zirconium oxide is used as the capacitor insulating film material, there is a problem of thinning the film thickness of the upper electrode (for example, TiN film) formed on the capacitor insulating film smaller than the design value. The thinning of the upper electrode leads to insufficient capacity of the capacitor and deteriorates the characteristics.

  In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a first electrode film is formed, an insulating film is formed in an amorphous state on the first electrode film, and the insulating film is formed on the insulating film. A second electrode film is formed, and the insulating film is crystallized after forming the second crystal film.

  According to one embodiment of the present invention, the second electrode film is formed on the insulating film formed in an amorphous state, and then the insulating film is crystallized. An insulating film having a desired relative dielectric constant can be obtained while preventing the thinning of the film.

1 is a partial cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention. It is a flowchart for demonstrating the manufacturing process of the capacitor in the manufacturing method of a related semiconductor device. 5 is a flowchart for explaining a capacitor manufacturing process in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. (A) is a figure for demonstrating the state of the capacitive insulating film formed according to the flow of FIG. 2, (b) is a figure for demonstrating the state of the upper electrode similarly formed according to the flow of FIG. is there. (A) is a figure for demonstrating the state of the capacity | capacitance insulating film formed according to the flow of FIG. 3, (b) is a figure for demonstrating the state of the upper electrode similarly formed according to the flow of FIG. is there. It is a fragmentary sectional view showing one process for explaining a manufacturing method of a semiconductor device concerning a 1st embodiment of the present invention. FIG. 7 is a partial cross-sectional view for explaining a process following the process of FIG. 6. It is a fragmentary sectional view for demonstrating the process following the process of FIG. FIG. 9 is a partial cross-sectional view for explaining a process following the process of FIG. 8. It is a graph which shows the correlation with the density | concentration of the aluminum oxide in the zirconium oxide after the annealing process by different temperature, and the dielectric constant of a zirconium oxide.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a DRAM is shown as an example of a semiconductor device, but the present invention is not limited to a DRAM and can be applied to other semiconductor devices including a capacitor.

  FIG. 1 is a partial cross-sectional view showing a configuration example of DRAM 100 according to the first embodiment of the present invention.

  The illustrated DRAM 100 includes a silicon substrate 1. A plurality of MOS (Metal Oxide Semiconductor) transistors (not shown) are formed on the silicon substrate 1.

  More specifically, the silicon substrate 1 has a plurality of active regions defined by element isolation regions. A pair of impurity diffusion regions is formed in each active region. A gate insulating film and a gate electrode are stacked on the upper surface of the silicon substrate 1 between the pair of impurity diffusion regions. The pair of impurity diffusion regions, the gate insulating film, and the gate electrode constitute a MOS transistor.

  A first interlayer insulating film 2 covering the MOS transistor is formed on the silicon substrate 1. A plurality of bit lines (not shown) are formed on the first interlayer insulating film 2. A plurality of first contact plugs (not shown) penetrating the first interlayer insulating film 2 are formed. Each of the first contact plugs electrically connects one of the impurity diffusion layers of the corresponding MOS transistor and the corresponding bit line.

  A second interlayer insulating film 3 is formed on the first interlayer insulating film 2 so as to cover the plurality of bit lines. A plurality of second contact plugs 4 are formed through the second interlayer insulating film 3. Each of the second contact plugs 4 is connected to the other of the impurity diffusion layers of the corresponding MOS transistor.

  A stopper film 5 is formed on the second interlayer insulating film 3. A plurality of lower electrodes 7 are formed through the stopper film 5. Each bottom surface portion of the lower electrode 7 is connected to the upper surface of the corresponding second contact plug 4. A support film (insulating film) 18 is connected to part of the side surface of each lower electrode 7. The support film 18 prevents mutual contact between the adjacent lower electrodes 7 and realizes mutual support.

  The lower electrode 7 is formed in a crown shape with a high aspect ratio, and has an inner wall and an outer wall. The surfaces of these inner and outer walls are covered with a capacitive insulating film 8 along with the upper surface of the stopper film 5. The surface of the capacitive insulating film 8 is covered with the upper electrode 9. The lower electrode 7, the capacitive insulating film 8 and the upper electrode 9 constitute a capacitor 10.

  The upper electrode 9 is embedded with an embedded film 11 that is a conductor. The space remaining inside the lower electrode 7 is also filled with the buried film 11. A plate electrode 12 is formed on the upper surface of the buried film 11. The plate electrode 12 is electrically connected to the upper electrode 9 through the buried film 11.

  A fourth interlayer insulating film 13 is provided so as to cover the plate electrode 12. A third contact plug 14 is formed so as to penetrate the fourth interlayer insulating film 13 and connected to the plate electrode 12.

  A plurality of wirings 16 are disposed on the upper surface of the fourth interlayer insulating film 13. A part of the plurality of wirings 16 is connected to the plate electrode 12 via the third contact plug 14.

  The wiring 16 and the fourth interlayer insulating film 13 are covered with a fifth interlayer insulating film 17.

  A method of manufacturing DRAM 100 configured as described above will be described below. Here, a manufacturing process of the capacitor 10 which is a characteristic part of the present invention will be described. About other processes, since a publicly known process can be adopted, the explanation is omitted.

  As shown in FIG. 2, the related capacitor manufacturing process generally includes three steps: lower electrode formation (step S201), capacitive insulating film formation (step S202), and upper electrode formation (step S203).

  On the other hand, as shown in FIG. 3, the manufacturing process of the capacitor 10 according to the present embodiment is roughly the lower electrode formation (step S301), the capacitive insulating film formation (step S302), and the upper electrode formation (step S303). In addition to the above three steps, it comprises a total of four steps of annealing (step S304).

  Note that the manufacturing process of the capacitor 10 according to the present embodiment does not simply add an annealing process to the manufacturing process of the related capacitor. As will be described below, the capacitor insulating film forming steps S202 and S302 are different, which requires annealing.

  Hereinafter, with reference to FIGS. 4 and 5, a related capacitor manufacturing process and a capacitor manufacturing process according to the present embodiment will be described.

In the related capacitor manufacturing method, as shown in FIG. 4A, the capacitor insulating film 8B is formed so as to cover the surface of the lower electrode 7 formed in step S201 (step S202). Zirconium oxide (ZrO ₂ ) is used as the material of the capacitive insulating film 8B. In order to achieve a desired dielectric constant, zirconium oxide is formed in a crystalline state. Cracks 20A generated between crystals are present on the surface of the capacitive insulating film 8B.

  Subsequently, as shown in FIG. 4B, the upper electrode 9A is formed so as to cover the surface of the capacitive insulating film 8B (step S203). Since the crack 20A exists on the surface of the capacitive insulating film 8B serving as the base, the material of the upper electrode 9A is also used to bury the crack 20A. As a result, the film thickness (X2, Z2) of the upper electrode 9A becomes smaller (thinner film thickness) than the design value. The thinning of the upper electrode 9 </ b> A causes a decrease in the charge retention amount and degrades the characteristics of the DRAM 100.

Also in the manufacturing process of the capacitor 10 according to the present embodiment, the capacitive insulating film 8A is formed so as to cover the surface of the lower electrode 7 formed in step S301. However, as shown in FIG. 5A, the capacitor insulating film 8A is formed so as not to cause cracks (to be in a smooth state) on its surface. This is realized by using zirconium oxide doped with aluminum (Al-doped ZrO ₂ ) as a raw material of the capacitive insulating film 8A and setting the film formation temperature so as to be in an amorphous state.

  Next, the upper electrode 9 is formed so as to cover the surface of the capacitive insulating film 8A (step S203). At this time, the process temperature is set so that the capacitive insulating film 8A maintains an amorphous state. As a result, the surface of the capacitive insulating film 8A as a base is maintained in a smooth state, and the upper electrode 9 is formed with a film thickness as designed.

  Next, annealing is performed (step S203) to change the film quality of the amorphous capacitive insulating film 8A into a crystallized capacitive insulating film 8, thereby improving the relative dielectric constant. At this time, the capacitor insulating film 8 becomes columnar crystals, and cracks 20 are generated between the crystals as shown in FIG. The upper electrode 9 is not affected by the crack 20. That is, a part of the upper electrode 9 does not enter the crack. Therefore, the generation of the crack 20 does not affect the film thickness of the upper electrode 9, and the upper electrode 9 maintains the film thickness (X1, Z1) at the time of formation.

  As described above, in the present embodiment, by controlling the film quality variation of the capacitive insulating film, a desired relative dielectric constant is realized, and the film thickness variation of the upper electrode is suppressed.

  Next, with reference to FIGS. 6 to 10, the manufacturing process of the capacitor 10 according to the present embodiment will be described in more detail.

  First, in order to obtain the state shown in FIG. 6, the MOS transistor, the first interlayer insulating film 2, the first contact plug, the bit line, the second interlayer insulating film 3 and the like are formed on one side of the silicon substrate 1 by a known method. A second contact plug 4 is formed.

  Next, a stopper film 5 that is a 30 nm thick silicon nitride film (SIN) is formed by CVD (Chemical Vapor Deposition) so as to cover the second interlayer insulating film 3 and the second contact plug 4. Subsequently, a third interlayer insulating film 6 which is a silicon oxide film having a thickness of 1 μm is formed by a CVD method so as to cover the upper surface of the stopper film 5. Further, a support film 18 which is a silicon nitride film having a thickness of 100 nm is formed by CVD so as to cover the upper surface of the third interlayer insulating film 6.

  Next, the cylinder hole 21 penetrating the support film 18, the third interlayer insulating film 6, and the stopper film 5 is formed by photolithography and dry etching. The cylinder hole 21 is arranged corresponding to each second contact plug 4, and at least a part of the upper surface of the corresponding second contact plug 4 is exposed on the bottom surface thereof.

  Next, in order to obtain the state shown in FIG. 7, titanium nitride (TiN) serving as a lower electrode is formed by SFD (Sequential Flow Deposition) so as to cover the inner wall of the cylinder hole 21. At this time, the cylinder hole 21 remains without being completely filled with titanium nitride.

  Next, by using a photolithography method and a dry etching method, a part of the support film 18 is removed together with the titanium nitride formed on the upper surface thereof, and a part of the upper surface of the third interlayer insulating film 6 is exposed. At this time, by appropriately adjusting the thickness of the photoresist, the removal of the support film 18 is completed, and at the same time, the remaining titanium nitride formed on the upper surface of the support film 18 can be removed. it can. Thereby, the lower electrode 7 is formed simultaneously with the partial removal of the support film 18.

Next, the third interlayer insulating film 6, which is a silicon oxide film, is completely removed by wet etching using hydrofluoric acid (HF + H ₂ O). Thereby, the side part of the lower electrode 7 is exposed. At this time, the silicon nitride film constituting the stopper film 5 and the support film 18 and the titanium nitride constituting the lower electrode 7 remain without being etched by hydrofluoric acid. The second interlayer insulating film 3 covered with the stopper film 5 and the lower electrode 7 also remains without being etched. Since the adjacent lower electrodes 7 are connected to each other by the remaining support film 18, they support each other and stand without collapsing.

Next, as shown in FIG. 8, an aluminum oxide (Al ₂ O ₃ ) film and a zirconium oxide (ZrO ₂ ) film are alternately laminated by an ALD (Atomic Layer Deposition) method so as to cover the surface of the lower electrode 7. A capacitive insulating film 8A, which is a thin film, is formed. In addition, the inside of the broken-line circle in a figure corresponds to the part shown to Fig.5 (a).

  In the ALD method, the silicon substrate 1 maintained at a predetermined temperature is subjected to (1) supply and adsorption of source gas, (2) vacuum purge, (3) supply of oxidizing gas, and (4) vacuum purge. The one cycle process is repeated a plurality of times to perform film formation. When two kinds of thin films are formed, a cycle structure for each insulating film is alternately repeated to form a laminated structure.

For film formation of aluminum oxide, TMA (Trimethyl aluminum: Al (CH ₃ ) ₃ ) can be used as a source gas, and ozone (O ₃ ) can be used as an oxidizing gas. The processing temperature can be 270 ° C. On the other hand, for film formation of zirconium oxide, TEMAZ (Tetrakis ethyl methyl amino zirconium: Zr [N (CH ₃ ) CH ₂ CH ₃ ] ₄ ) can be used as a source gas and ozone (O ₃ ) as an oxidizing gas. The processing temperature can be 215 ° C. In any film formation, the processing temperature is set to a temperature that maintains the amorphous state without promoting the crystallization of the capacitive insulating film 8A.

  In the ALD method, when two types of thin films are alternately formed, it is not always necessary to change the type of the thin film every cycle. That is, after performing one thin film for one to several cycles, the process of performing the other thin film for one to several cycles may be repeated. For example, after forming zirconium oxide corresponding to 10 cycles continuously, aluminum oxide corresponding to 1 cycle may be formed and laminated. As described above, by adjusting the number of cycles when forming each thin film, a film that can be regarded as one film component doped with the other film component can be formed. That is, the capacitive insulating film 8A that can be regarded as being doped with aluminum in the zirconium oxide film can be formed. In addition, the concentration of aluminum (aluminum oxide) contained in the zirconium oxide film (capacitive insulating film 8A) can be controlled.

  The concentration of aluminum in the capacitive insulating film 8A can be set to 3.0 to 6.0 at%, but is preferably 3.0 to 4.5 at%. In order to reduce the aluminum concentration to less than 3.0 at%, the number of zirconium oxide film formation cycles must be increased. Therefore, the capacity insulating film 8A is thickened, and the capacity of the capacitor 10 is hindered. Further, if the aluminum concentration is higher than 6.0 at%, the heating temperature in the subsequent annealing process must be increased, and the operation of the DRAM 100 becomes unstable due to an excessive heat load. The lower the aluminum concentration, the higher the dielectric constant, but the processing temperature for forming the upper electrode 9 must be lowered, leading to a reduction in throughput.

  Next, as shown in FIG. 9, titanium nitride (TiN) to be the upper electrode 9 is formed by SFD so as to cover the surface of the capacitive insulating film 8A. The processing temperature at this time is set to 250 ° C. to 270 ° C. If it is the temperature of this range, the capacity | capacitance insulating film 8A will crystallize, and an unevenness | corrugation will not arise in the surface. Therefore, the surface of the capacitor insulating film 8A is in a smooth state, and the upper electrode 9 does not enter the crack of the capacitor insulating film 8A. Therefore, the upper electrode 9 is formed with a designed film thickness without being thinned.

  In addition, the inside of the broken-line circle in a figure corresponds to the part shown in FIG.5 (b).

  Thereafter, the capacitive insulating film 8A is crystallized by annealing to form the capacitive insulating film 8.

10, zirconium oxide after annealing (ZrO ₂₎ Concentration (hereinafter, described as AlO concentration) of the aluminum oxide during the correlation of the relative dielectric constant of ZrO ₂ ZrO ₂ annealing temperature by (300 ° C., 450 ° C. 550 ° C.).

As understood from FIG. 10, the dielectric constant of ZrO ₂ is by crystallization of ZrO ₂ by annealing, thereby improving than amorphous. The annealing temperature necessary for crystallization of ZrO ₂ needs to be higher as the AlO concentration is higher. However, it is desirable that the annealing temperature be as low as possible. Therefore, there is an optimum annealing temperature according to the AlO concentration. In the present embodiment, the temperature is set to 450 ° C. (AL concentration: 3.0 to 4.5 at%) or 550 ° C. (AL concentration: 4.5 to 6.0 at%) depending on the AlO concentration.

The relative permittivity of ZrO ₂ after annealing is higher when the AlO concentration is 3.0 to 4.5 at% than when the AlO concentration is 4.5 to 6.0 at%. It is desirable to be 0.0 to 4.5 at%.

  After the annealing process, the buried film 11 and the plate electrode 12 are sequentially formed by a known method to cover the capacitor 10. Further, the fourth interlayer insulating film 13, the third contact plug 14, the wiring 16, and the fifth interlayer insulating film 17 are formed, and the DRAM 100 shown in FIG. 1 is completed.

  As described above, in this embodiment, the capacitor insulating film 8A is first formed in an amorphous state, and then the upper electrode 9 is formed at a temperature lower than the temperature at which the crystallization of the capacitor insulating film 8A starts, and then annealing is performed. Then, the capacitor insulating film 8A is crystallized. According to such a method, the capacitor insulating film 8A can be crystallized while preventing the upper electrode 9 from being thinned, so that the capacity of the capacitor 10 can be improved, and the shortage of the storage capacity can be prevented and the DRAM 100 can be operated stably. Can be made.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made. For example, the film formation method and film formation conditions for each film are not limited to the above-described examples, and can be appropriately selected and changed according to the purpose.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 1st interlayer insulation film 3 2nd interlayer insulation film 4 2nd contact plug 5 Stopper film 6 3rd interlayer insulation film 7 Lower electrode 8, 8A, 8B Capacitance insulation film 9, 9A Upper electrode 10 Capacitor 11 Embedding Film 12 Plate electrode 13 Fourth interlayer insulating film 14 Third contact plug 16 Wiring 17 Fifth interlayer insulating film 18 Support film 20, 20A Crack 21 Cylinder hole 100 DRAM

Claims (8)

Forming a first electrode film;
Forming an insulating film in an amorphous state on the first electrode film;
Forming a second electrode film on the insulating film;
Crystallizing the insulating film after forming the second crystal film;
A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 1, wherein the crystallization of the insulating film is performed by annealing.   The method of manufacturing a semiconductor device according to claim 2, wherein the formation of the second electrode film is performed at a temperature lower than the annealing temperature.   The insulating film is an Al-doped ZrO film, and the temperature for forming the second electrode film is set based on the concentration of aluminum contained in the Al-doped ZrO film. The manufacturing method of the semiconductor device of description.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the lower the aluminum concentration, the lower the temperature at which the second electrode film is formed.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the aluminum concentration is 3.0 to 6.0 at%.   7. The method of manufacturing a semiconductor device according to claim 4, wherein the Al-doped ZrO film is formed by alternately stacking AlO films and ZrO films using an ALD method.   The method for manufacturing a semiconductor device according to claim 1, wherein the second electrode film is a TiN film.

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