JP2014063851A - Resistance change memory - Google Patents

Abstract

A peripheral transistor is miniaturized and the reliability of the peripheral transistor is prevented from deteriorating.
A resistance change memory includes a memory cell array and a peripheral circuit that controls the operation of the memory cell array. The memory cell array 11 includes a plurality of memory cells MC, and each memory cell MC includes a variable resistance element 20 and a selection transistor 21. The variable resistance element 20 is provided on a contact plug that is electrically connected to the diffusion layer of the selection transistor 21. The peripheral circuit 12 includes a resistance element 51 and a peripheral transistor 50. The resistance element 51 is provided on a contact plug that is electrically connected to the diffusion layer of the peripheral transistor 50. The resistance element 51 has the same structure as the variable resistance element 20.
[Selection] FIG.

Description

  Embodiments described herein relate generally to a resistance change memory.

  2. Description of the Related Art Magnetic random access memory (MRAM) is known as a resistance change memory that stores data according to a resistance change of a storage element. The MRAM uses, as a storage element, an MTJ (Magnetic Tunnel Junction) element that uses a magnetoresistive effect in which a resistance value changes depending on the magnetization state of a magnetic layer.

  The memory cell of the MRAM includes an MTJ element and a selection transistor connected to one end of the MTJ element. In the selection transistor, in order to increase the on-current, for example, a method of increasing the gate voltage when the transistor is on is used. When a large vertical electric field is applied to the gate insulating film of the select transistor by boosting the gate voltage, the reliability of the gate insulating film is deteriorated. In the MRAM, there is a problem that the write current is reduced due to the influence of the bit line resistance and the MTJ resistance in addition to the parasitic resistance of the select transistor, and a write failure occurs. However, boosting the gate voltage increases the write current. It is an effective means.

  In order to increase the capacity of the MRAM, it is required to reduce the size of the memory cell and reduce the chip size of the MRAM. In order to reduce the chip size of the MRAM, it is important to reduce the size of the peripheral circuit (core circuit) that drives the memory cell array. At this time, the gate length of the MOS transistor included in the peripheral circuit is reduced. Is required. When a boosted voltage Vpp higher than the power supply voltage is applied to the word line during data writing, the boosted voltage Vpp is applied between the source and drain of the MOS transistor in the peripheral circuit that drives the word line. When the boosted voltage Vpp is applied between the source and drain of the MOS transistor having a reduced gate length, it becomes difficult to suppress the short channel effect, and the gate insulating film is deteriorated due to HCI (Hot Carrier Injection) or gate insulation. There is a problem such as time-dependent dielectric breakdown (TDDB) of the film.

JP 2002-359356 A

  The embodiment provides a resistance change memory capable of suppressing deterioration in reliability of a peripheral transistor while miniaturizing the peripheral transistor.

  The resistance change memory according to the embodiment includes a plurality of memory cells, and each of the plurality of memory cells includes a variable resistance element and a selection transistor, and the variable resistance element is electrically connected to a diffusion layer of the selection transistor. A memory cell array provided on the contact plugs connected to each other, and controls the operation of the memory cell array, and includes a resistance element and a peripheral transistor, and the resistance element is electrically connected to a diffusion layer of the peripheral transistor. And a peripheral circuit provided on the contact plug. The resistance element has the same structure as the variable resistance element.

The circuit diagram which extracted a part of MRAM. The figure which shows the target regarding the characteristic of a cell transistor and a peripheral transistor. The figure which shows the simulation result regarding the characteristic of a cell transistor and a peripheral transistor. The figure which shows the simulation result after the parameter adjustment regarding a peripheral transistor. The graph which shows the relationship between the contact resistivity of a peripheral transistor, and a threshold voltage. The graph which shows the relationship between the on-current and off-current of a peripheral transistor, and contact resistivity. The graph which shows the relationship between the horizontal electric field of the channel region of a peripheral transistor, and contact resistivity. The block diagram of MRAM concerning this embodiment. FIG. 3 is a layout diagram of a memory cell array. FIG. 10 is a cross-sectional view of the memory cell array along the line AA ′ shown in FIG. 9. FIG. 10 is a cross-sectional view of the memory cell array along the line BB ′ shown in FIG. 9. The circuit diagram of a memory cell array. Sectional drawing of an MTJ element. FIG. 3 is a layout diagram of a peripheral circuit according to the first embodiment. FIG. 15 is a cross-sectional view of a peripheral circuit along the line AA ′ shown in FIG. 14. FIG. 15 is a cross-sectional view of a peripheral circuit along the line BB ′ shown in FIG. 14. FIG. 6 is a layout diagram of a peripheral circuit according to a second embodiment. FIG. 18 is a cross-sectional view of a peripheral circuit along the line AA ′ shown in FIG. 17. FIG. 18 is a cross-sectional view of a peripheral circuit along the line BB ′ shown in FIG. 17. The figure explaining the arrangement density of the MTJ element of a memory cell array and a peripheral circuit. Sectional drawing of the MTJ element contained in a peripheral circuit.

  Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[1. Simulation and Discussion]
As the resistance change memory, various types of memories such as MRAM, resistance random access memory (ReRAM), and phase-change random access memory (PCRAM) can be used. . In the present embodiment, an MRAM will be described as an example of the resistance change memory. The MRAM includes an MTJ (Magnetic Tunnel Junction) element that uses a magnetoresistive effect as a storage element, and stores information according to the magnetization arrangement of the MTJ element.

  The MRAM includes a memory cell array and a peripheral circuit (core circuit) that drives the memory cell array. FIG. 1 is a circuit diagram in which a part of the MRAM is extracted.

  A memory cell MC included in the memory cell array includes an MTJ element (magnetoresistance effect element) 20 and a selection transistor 21. The selection transistor 21 is composed of, for example, an N channel MOSFET. One end of the MTJ element 20 is electrically connected to the bit line BL, and the other end is electrically connected to the drain of the selection transistor 21. The source of the selection transistor 21 is electrically connected to the bit line / BL.

  In FIG. 1, a plurality of circuits and elements connected to the memory cell MC are included in the peripheral circuit. The bit line BL is electrically connected to one end of the current path of the column selection transistor CT1, and the other end of the current path of the column selection transistor CT1 is electrically connected to the write circuit. The bit line / BL is electrically connected to one end of the current path of the column select transistor CT2, and the other end of the current path of the column select transistor CT2 is electrically connected to the write circuit. A column selection signal CSL is supplied from the column decoder to the gates of the column selection transistors CT1 and CT2.

  A driver DR1 is connected to the word line WL. The driver DR1 is composed of, for example, a P-channel MOSFET T1 and an N-channel MOSFET T2. The word line WL is electrically connected to a connection node N1 between the P-channel MOSFET T1 and the N-channel MOSFET T2. The source of the P-channel MOSFET T1 is electrically connected to the power supply terminal of the boost voltage Vpp. Boosted voltage Vpp is higher than power supply voltage Vcc, and is generated by boosting power supply voltage Vcc. The source of the N-channel MOSFET T2 is electrically connected to the ground terminal Vss. The gates of the P-channel MOSFET T1 and the N-channel MOSFET T2 are connected to the driver DR2 via the connection node N2.

  The driver DR2 is composed of, for example, a P-channel MOSFET T3 and an N-channel MOSFET T4. The drains of the P-channel MOSFET T3 and the N-channel MOSFET T4 are electrically connected to the connection node N2. The source of P-channel MOSFET T3 is electrically connected to the power supply terminal of boosted voltage Vpp. The source of the N-channel MOSFET T4 is electrically connected to the ground terminal Vss. A control signal DS is supplied to the gates of the P-channel MOSFET T3 and the N-channel MOSFET T4.

  When the word line WL is selected, the control signal DS becomes high level. When the control signal DS becomes high level, the connection node N2 becomes low level, and the boosted voltage Vpp is applied to the word line WL. That is, in the present embodiment, a boosted voltage Vpp higher than the power supply voltage Vcc can be applied to the word line WL. Thereby, the driving force of the selection transistor 21 is increased, and the write current flowing through the MTJ element 20 can be increased.

  FIG. 2 is a diagram showing target values (targets) regarding the sizes, bias conditions, and characteristics of the cell transistors and peripheral transistors. The cell transistor refers to a selection transistor included in the memory cell MC. The peripheral transistor refers to an N-channel MOSFET included in the peripheral circuit, and corresponds to, for example, T2 in FIG.

  In FIG. 2, gate length Lg (nm), fin-type semiconductor width Wfin (nm), gate oxide film thickness (nm), drain voltage Vd / gate voltage Vg (V), threshold voltage Vtsat (V) in the saturation region, The on-current Ion (μA / μm) and the off-current Ioff (nA / μm). FIG. 2 shows a simulation result when a fin-type MOSFET is used as the cell transistor and the peripheral transistor. As the cell transistor and the peripheral transistor, various transistors such as a planar FET, a fin FET, an RCAT (Recess Channel Array Transistor), and a saddle fin FET can be used.

  FIG. 3 is a diagram illustrating simulation results regarding the characteristics of the cell transistor and the peripheral transistor. The peripheral transistors in FIG. 3 have the same parameters (including the impurity concentration of the diffusion layer, ion implantation conditions, etc.) as the cell transistors except for the size (for example, the gate length and the size of the source / drain regions) and the bias conditions. When the peripheral transistor is formed with the same parameters as the cell transistor, the threshold voltage Vtsat of the peripheral transistor is slightly higher than the target.

  FIG. 4 is a diagram illustrating a simulation result after adjusting parameters for peripheral transistors. In case 1 of FIG. 4, channel ion implantation is performed in order to match the threshold voltage Vtsat of the peripheral transistors with the target. That is, impurity ions for lowering the threshold voltage are implanted into the channel region of the peripheral transistor. In Case 1 of FIG. 4, the threshold voltage Vtsat of the peripheral transistors is adjusted to be the same as that of the target, but the on-current Ion is 1.65 times that of the target. For this reason, there are concerns about deterioration of the gate oxide film due to HCI and TDDB of the gate oxide film.

  In the case 2 of FIG. 4, in addition to the adjustment of the case 1, the on-current Ion is adjusted by adjusting the impurity concentration of the source / drain region (diffusion layer). In Case 2, the on-current Ion can be adjusted to a value close to the target.

FIG. 5 is a graph showing the relationship between the contact resistivity ρco and the threshold voltage Vt between the source / drain regions of the peripheral transistors and the silicide (contact plug). The vertical axis in FIG. 5 represents the threshold voltage Vt (V) of the peripheral transistor, and the horizontal axis in FIG. 5 represents the contact resistivity ρco (Ω · μm ² ) between the source / drain regions and the silicide. Silicide is a layer formed at the contact portion of the contact plug connected to the source / drain region. FIG. 5 shows a graph of threshold voltages in the linear region and the saturation region. FIG. 5 shows that the threshold voltage Vt hardly changes even when the contact resistivity ρco is changed. If the silicide material is determined, it can be considered that the contact resistivity ρco is determined by the impurity concentration at the interface between the source / drain regions and the silicide.

FIG. 6 is a graph showing the relationship between the on-current Ion (and off-current Ioff) of the peripheral transistor and the contact resistivity ρco between the source / drain region and the silicide. The vertical axis in FIG. 6 represents the on-state current Ion (A / μm) and the off-current Ioff (nA / μm) of the peripheral transistor, and the horizontal axis in FIG. 5 represents the contact resistivity ρco (Ω · μm ² ). FIG. 6 shows a graph of the off current Ioff when the drain voltage Vd = 1.8V and Vd = 0.1V. As can be seen from FIG. 6, as the contact resistivity ρco increases (corresponding to the decrease in the impurity concentration at the interface between the source / drain regions and the silicide), the off-current Ioff remains the same and the on-current Ion decreases. . For example, when ρco = 10Ω · μm ² , Ion≈400 μA / μm.

FIG. 7 is a graph showing the relationship between the lateral electric field E in the channel region of the peripheral transistor and the contact resistivity ρco between the source / drain region and the silicide. The vertical axis in FIG. 7 represents the lateral electric field E (MV / cm) of the channel region of the peripheral transistor, and the horizontal axis in FIG. 7 represents the contact resistivity ρco (Ω · μm ² ) between the source / drain region and the silicide. ing. FIG. 7 plots the maximum value of the lateral electric field E (lateral electric field at the drain end) when the peripheral transistor is on. FIG. 7 shows that the lateral electric field at the drain end of the peripheral transistor decreases as the contact resistivity ρco increases. For example, when ρco = 10 Ω · μm ² , E≈0.6 MV / cm, and increasing the contact resistivity ρco is effective in suppressing hot carriers.

  From the above simulation, the peripheral transistor can be adjusted to a desired characteristic by adjusting the contact resistivity of the contact plug electrically connected to the source / drain region of the peripheral transistor. Further, by increasing the contact resistivity, the on-state current and the lateral electric field in the channel region can be reduced with almost no change in the threshold voltage of the peripheral transistors.

  Therefore, in the present embodiment, a MOSFET having the same structure as the cell transistor is used as the peripheral transistor, and the MTJ element is used as a resistance element in order to satisfy a target value (target) related to the characteristics of the peripheral transistor. The resistance value of the element is added as a parasitic resistance to the contact plug of the peripheral transistor. Thus, by adjusting the parasitic resistance of the contact plug electrically connected to the source / drain region of the peripheral transistor, the peripheral transistor having the desired characteristics can be obtained while making the peripheral transistor and the cell transistor have the same structure and size. Realize.

[2. Overall configuration of MRAM]
FIG. 8 is a block diagram of an MRAM (magnetic memory) 10 according to this embodiment. The MRAM 10 includes a memory cell array 11 and a peripheral circuit (core circuit) 12. The memory cell array 11 includes a plurality of memory cells MC. Each memory cell MC includes an MTJ element (magnetoresistance effect element) 20 and a selection transistor 21. In the memory cell array 11, a plurality of word lines WL each extending in the row direction and a plurality of bit line pairs BL, / BL each extending in the column direction are arranged.

  A row decoder 13 is connected to the plurality of word lines WL. The row decoder 13 selects and drives any one of the plurality of word lines WL based on the row address.

  A write circuit 15 and a read circuit (sense amplifier) 16 are connected to the plurality of bit line pairs BL and / BL via a column selection circuit 14. The column selection circuit 14 includes a number of column selection transistors corresponding to the plurality of bit line pairs BL, / BL. The column selection transistor is composed of, for example, an N channel MOSFET. The column selection circuit 14 selects the bit line pair BL, / BL necessary for the operation in accordance with an instruction from the column decoder 17. The column decoder 17 decodes the column address and sends this decode signal (column selection signal CSL) to the column selection circuit 14.

  The write circuit 15 receives write data from the outside. The write circuit 15 writes data to the selected memory cell by supplying a write current to the bit line pair BL, / BL connected to the selected memory cell to be written.

  The sense amplifier 16 applies, for example, a read current to the bit line pair BL, / BL connected to the selected memory cell to be read, and detects data stored in the selected memory cell based on the read current. Data read by the sense amplifier 16 is output to the outside.

[3. Configuration of memory cell array]
FIG. 9 is a layout diagram of the memory cell array 11. 10 is a cross-sectional view of the memory cell array 11 along the line AA ′ shown in FIG. FIG. 11 is a cross-sectional view of the memory cell array 11 along the line BB ′ shown in FIG.

  The P-type semiconductor substrate 30 is an element region (active area) AA in which an element isolation insulating layer 31 is formed in the surface region, and a region where the element isolation insulating layer 31 is not formed is an element region (active area) AA. A plurality of active areas AA are provided on the semiconductor substrate 30. A plurality of active areas AA arranged below one bit line pair BL, / BL have a staggered arrangement (zigzag arrangement). The element isolation insulating layer 31 is configured by, for example, STI (Shallow Trench Isolation).

  Each active area AA is provided with a selection transistor 21 made of an N-channel MOSFET. The selection transistor 21 includes a source region 32, a drain region 33, a gate insulating film 34, a gate electrode GC, a cap layer 35, and a sidewall 36.

The source region 32 and the drain region 33 are provided to be separated from each other in the active region AA, and are constituted by an N ⁺ type diffusion layer formed by introducing a high concentration N-type impurity into the active region AA. . On the active region AA between the source region 32 and the drain region 33, a gate electrode GC extending in the Y direction is provided via a gate insulating film. The gate electrode GC functions as the word line WL. An insulating cap layer 35 is provided on the gate electrode GC. An insulating side wall 36 is provided on the side surface of the gate electrode GC. A contact plug (CB) 37 is provided on the source region 32. A contact plug (CB) 38 is provided on the drain region 33.

  Hereinafter, the structure of the memory cell array connected to the bit line pair BL1, / BL1 will be described. The structure of the memory cell array connected to the other bit line pair BL, / BL is the same as that of the bit line pair BL1, / BL1. It is repetition.

  An MTJ element 20 is provided on the contact plug 38. An upper electrode UE extending in the Y direction is provided on the MTJ element 20. A plurality of MTJ elements 20 are arranged every other word line WL. The plurality of MTJ elements 20 arranged below the bit line pair BL1, / BL1 have a staggered arrangement (zigzag arrangement).

  On the contact plug 37, a via plug V0 is provided. An upper electrode UE extending in the Y direction is provided on the via plug V0. Each upper electrode UE electrically connects the MTJ element 20 adjacent to the Y direction and the via plug V0.

  A via plug V1 is provided on the upper electrode UE and above the via plug V0. The via plug V1 is electrically connected to one of the bit line pair BL1, / BL1 (M1) extending in the X direction. A space between the semiconductor substrate 30 and the bit line is filled with an interlayer insulating layer 39.

  Next, the circuit configuration of the memory cell array 11 will be described. FIG. 12 is a circuit diagram of the memory cell array 11. As described above, the plurality of MTJ elements 20 arranged below the bit line pair BL1, / BL1 has a staggered arrangement (zigzag arrangement). Due to this, the plurality of MTJ elements 20 arranged below the bit line pair BL1, / BL1 are electrically connected alternately to the bit line pair BL1, / BL1.

  Specifically, one end of the first MTJ element 20 is electrically connected to the bit line / BL 1, and the other end is electrically connected to the drain of the selection transistor 21. The source of the selection transistor 21 connected to the first MTJ element 20 is electrically connected to the bit line BL1.

  One end of the second MTJ element 20 adjacent to the first MTJ element 20 is electrically connected to the bit line BL 1, and the other end is electrically connected to the drain of the selection transistor 21. The source of the selection transistor 21 connected to the second MTJ element 20 is electrically connected to the bit line / BL1.

  Next, the configuration of the MTJ element 20 will be described. FIG. 13 is a cross-sectional view of the MTJ element 20.

  The MTJ element 20 is configured by laminating a base layer 40, a storage layer 41, a nonmagnetic layer (tunnel barrier layer) 42, a reference layer 43, and a hard mask layer 44 in order from the bottom. The arrows in the figure represent the state of magnetization. The planar shape of the MTJ element 20 is not particularly limited and is, for example, a circle or an ellipse.

  Each of the storage layer 41 and the reference layer 43 is made of a ferromagnetic material and has a magnetic anisotropy in a direction perpendicular to the film surface, and their easy magnetization direction is perpendicular to the film surface. That is, the MTJ element 20 is a perpendicular magnetization MTJ element in which the magnetization directions of the storage layer 41 and the reference layer 43 are each perpendicular to the film surface. The MTJ element 20 may be an in-plane magnetization MTJ element in which the magnetization directions of the storage layer 41 and the reference layer 43 are in the in-plane direction.

  The storage layer 41 has a variable magnetization direction (inverts). The reference layer 43 has an invariable magnetization direction (fixed). The reference layer 43 is designed to have a perpendicular magnetic anisotropy energy sufficiently larger than that of the storage layer 41. The magnetic anisotropy can be set by adjusting the material configuration and the film thickness. In this way, the magnetization reversal current of the storage layer 41 is reduced, and the magnetization reversal current of the reference layer 43 is made larger than that of the storage layer 41. Thereby, it is possible to realize the MTJ element 20 including the storage layer 41 whose magnetization direction is variable and the reference layer 43 whose magnetization direction is unchanged with respect to a predetermined write current.

  The nonmagnetic layer 42 can be made of a nonmagnetic metal, a nonmagnetic semiconductor, an insulator, or the like. When an insulator is used as the nonmagnetic layer 42, it is called a tunnel barrier layer. As the tunnel barrier layer 42, magnesium oxide (MgO) or the like is used.

  The underlayer 40 is made of a nonmagnetic material and is provided to control the crystal orientation of the memory layer 41. The hard mask layer 44 is made of, for example, metal and is used as a mask when the MTJ element 20 is processed. As the hard mask layer 44, tantalum (Ta) or the like can be used.

  In the present embodiment, a spin injection writing method is adopted in which a write current is directly supplied to the MTJ element 20 and the magnetization state of the MTJ element 20 is controlled by this write current. The MTJ element 20 can take either a low resistance state or a high resistance state depending on whether the relative relationship of magnetization between the storage layer 41 and the reference layer 43 is parallel or antiparallel.

  When a write current from the storage layer 41 to the reference layer 43 is applied to the MTJ element 20, the relative magnetization relationship between the storage layer 41 and the reference layer 43 becomes parallel. In the parallel state, the MTJ element 20 has the lowest resistance value, and the MTJ element 20 is set in the low resistance state. The low resistance state of the MTJ element 20 is defined as data “0”, for example.

  On the other hand, when a write current from the reference layer 43 toward the storage layer 41 is passed through the MTJ element 20, the relative relationship of magnetization between the storage layer 41 and the reference layer 43 becomes antiparallel. In the anti-parallel state, the MTJ element 20 has the highest resistance value, and the MTJ element 20 is set to the high resistance state. The high resistance state of the MTJ element 20 is defined as data “1”, for example.

  Thereby, the MTJ element 20 can be used as a storage element capable of storing 1-bit data (binary data). The assignment of the resistance state and data of the MTJ element 20 can be arbitrarily set.

  When reading data from the MTJ element 20, a read voltage is applied to the MTJ element 20, and the resistance value of the MTJ element 20 is detected based on the read current flowing through the MTJ element 20 at this time. This read voltage is set to a value sufficiently smaller than the threshold value at which magnetization is reversed by spin injection.

[4. Peripheral circuit configuration]
Next, the configuration of the peripheral transistors included in the peripheral circuit 12 will be described. This peripheral transistor corresponds to one of the MOSFETs T1 to T4 in FIG. The peripheral transistors included in the peripheral circuit 12 are formed on, for example, a semiconductor substrate on which the memory cell array 11 is formed.

  In this embodiment, the parasitic resistance of the contact plug is increased by electrically connecting the MTJ element to the contact plug electrically connected to the source / drain region (diffusion layer) of the peripheral transistor. With respect to the position where the MTJ element is arranged, the first embodiment in which one MTJ element is arranged above the source region or drain region of the peripheral transistor and two MTJ elements above the source region and drain region of the peripheral transistor are arranged. And a second embodiment in which elements are arranged. First, the first embodiment will be described.

  In the following description, a case where the peripheral transistor is formed of an N-channel MOSFET will be described as an example. However, the case where the peripheral transistor is a P-channel MOSFET can be similarly realized. When the peripheral transistor is composed of a P-channel MOSFET, the conductivity types of the well and the diffusion layer may be controlled in reverse.

  FIG. 14 is a layout diagram of the peripheral circuit 12 according to the first embodiment. FIG. 15 is a cross-sectional view of the peripheral circuit 12 along the line AA ′ shown in FIG. FIG. 16 is a cross-sectional view of the peripheral circuit 12 along the line BB ′ shown in FIG.

  The peripheral circuit 12 includes a plurality of peripheral transistors 50 and a plurality of MTJ elements 51. The size and structure of the peripheral transistor 50 are the same as the size and structure of the selection transistor 21 included in the memory cell MC. The stacked structure of the MTJ element 51 is the same as the stacked structure of the MTJ element 20 included in the memory cell MC. The arrangement of the MTJ elements 51 is also the same as that of the MTJ elements 20 included in the memory cell array 11. The layout of the peripheral circuit 12 shown in FIGS. 14 to 16 is the same as the layout of the memory cell array 11 shown in FIGS. In FIG. 14, the bit line BL is replaced with the signal line SL, and the word line WL is replaced with the gate electrode GC.

  In the peripheral circuit 12 configured as described above, a part of the plurality of via plugs V1 can be replaced with the MTJ element 51. That is, in the peripheral transistor 50, the resistance value of the MTJ element 51 can be added as a parasitic resistance to the contact plug 38 electrically connected to the drain region 33. The resistance value of the via plug V1 is, for example, less than 100Ω, and the resistance value of the MTJ element 51 is, for example, several kΩ. Therefore, in this embodiment, a resistance of several kΩ can be added to the contact plug 38.

  In the first embodiment, the arrangement density of the MTJ elements in the peripheral circuit 12 is the same as the arrangement density of the MTJ elements in the memory cell array 11. In the first embodiment, since the arrangement density of MTJ elements is the same in the peripheral circuit 12 and the memory cell array 11, it is possible to form the MTJ elements in the same design rule in the peripheral circuit 12 and the memory cell array 11. There is an advantage that the process difficulty does not become high.

  FIG. 17 is a layout diagram of the peripheral circuit 12 according to the second embodiment. 18 is a cross-sectional view of the peripheral circuit 12 taken along the line AA ′ shown in FIG. FIG. 19 is a cross-sectional view of the peripheral circuit 12 along the line BB ′ shown in FIG.

  An MTJ element 51 is provided on the contact plug 37 on the source region 32 of the peripheral transistor 50. An MTJ element 51 is provided on the contact plug 38 on the drain region 33 of the peripheral transistor 50. That is, in the second embodiment, the via plug V0 of the first embodiment is replaced with the MTJ element 51, and a plurality of MTJ elements 51 are arranged in a lattice pattern. Other configurations are the same as those of the first embodiment.

  In the second embodiment, both the contact plug 37 electrically connected to the source region 32 of the peripheral transistor 50 and the contact plug 38 electrically connected to the drain region 33 of the peripheral transistor 50 include the MTJ element. A resistance value of 51 can be added as a parasitic resistance.

  FIG. 20 is a diagram for explaining the arrangement density of MTJ elements in the memory cell array 11 and the peripheral circuit 12. FIG. 20A shows the MTJ element of the memory cell array 11, and FIG. 20B shows the MTJ element of the peripheral circuit 12. F (minimum feature size) in the figure is the minimum processing dimension. The diameter of the MTJ element is F.

  In the memory cell array 11, MTJ elements are arranged at a 4F pitch in each of the X direction and the Y direction. In the oblique direction, MTJ elements are arranged at a pitch of 2√2F.

  In the peripheral circuit 12, the MTJ elements are arranged at a 2F pitch in each of the X direction and the Y direction. In the oblique direction, MTJ elements are arranged at a pitch of 2√2F.

  In the second embodiment, the arrangement density of MTJ elements in the peripheral circuit 12 is higher than the arrangement density of MTJ elements in the memory cell array 11. For this reason, the process difficulty at the time of forming the MTJ element of the peripheral circuit 12 becomes high. In the second embodiment, MTJ elements can be formed with high density by using nanoimprint technology or the like. In the second embodiment, since the MTJ elements are arranged in both the source region and the drain region, the increase in parasitic resistance is larger than that in the first embodiment, and the deterioration of the gate insulating film due to the HCI or the TDDB of the gate insulating film. It is more effective to suppress this.

  It is known that the magnetization reversal current Ic of the MTJ element depends on the size of the MTJ element, and the magnetization reversal current Ic increases as the size of the MTJ element increases. When the via plug is replaced with an MTJ element as in this embodiment, the resistance value of the MTJ element 51 changes when the magnetization of the MTJ element 51 (specifically, the memory layer 41) is reversed while the peripheral transistor 50 is operating. Resulting in. As a result, the operation of the peripheral circuit 12 may be hindered. Therefore, it is desirable to make it difficult for the magnetization of the MTJ element 51 to reverse during the operation of the peripheral transistor 50.

  As a first method for making the magnetization of the MTJ element 51 difficult to reverse, the size (planar size) of the MTJ element 51 of the peripheral circuit 12 is made larger than the size of the MTJ element 20 of the memory cell array 11. In the example of FIG. 20, the size of the MTJ element 51 is set to be greater than F and less than 2F.

  Further, as a second method for making it difficult for the magnetization of the MTJ element 51 to be reversed, the film thickness of the storage layer of the MTJ element 51 is set to the same level as the film thickness of the reference layer. FIG. 21 is a cross-sectional view of the MTJ element 51. The stacked structure of the MTJ element 51 is the same as the stacked structure of the MTJ element 20. The film thickness of the storage layer 41 of the MTJ element 51 is larger than the film thickness of the storage layer 41 of the MTJ element 20. Further, the film thickness of the storage layer 41 of the MTJ element 51 is approximately the same as the film thickness of the reference layer 43. In this case, the size of the MTJ element 51 may be the same as the size of the MTJ element 20. In the example of FIG. 20, the size of the MTJ element 51 is set to the same F as the size of the MTJ element 20.

  By using the first method or the second method, when a current is passed through the MTJ element 51, the magnetization reversal of the storage layer 41 hardly occurs. That is, the first magnetization reversal current at which the resistance change of the MTJ element 51 occurs is larger than the second magnetization reversal current at which the resistance change of the MTJ element 20 occurs. Thereby, it is possible to suppress a change in the resistance value of the MTJ element 51 while the peripheral transistor 50 is operating.

[5. effect]
As described above in detail, in the present embodiment, the MRAM (resistance change memory) 10 includes a memory cell array 11 including a plurality of memory cells MC each having an MTJ element (variable resistance element) 20 and a selection transistor 21, and a memory cell array. 11 and the peripheral circuit 12 including the MTJ element (resistive element) 51 and the peripheral transistor 50. The MTJ element 20 is provided on a contact plug that is electrically connected to the diffusion layer of the selection transistor 21. Similarly, the MTJ element 51 is provided on a contact plug that is electrically connected to the diffusion layer of the peripheral transistor 50. The peripheral transistor 50 has the same layout as that of the selection transistor 21. Further, the MTJ element 51 is used as a parasitic resistance for increasing the resistance value of the contact plug.

  Therefore, according to the present embodiment, it is possible to suppress deterioration of the reliability of the peripheral transistor 50 while miniaturizing the peripheral transistor 50. Thereby, when the size of the memory cell array 11 is reduced, the size of the peripheral circuit 12 can be reduced, and as a result, the chip size of the MRAM 10 can be reduced.

  In addition, since the memory cell array 11 and the peripheral circuit 12 have the same configuration, the memory cell array 11 and the peripheral circuit 12 can be simultaneously formed on the same substrate. Thus, the peripheral transistor 50 having desired characteristics can be formed while suppressing the manufacturing cost.

  Further, the size of the peripheral transistor (including the channel length and the size of the diffusion layer) can be made the same as the size of the selection transistor while the peripheral transistor has desired characteristics. Thereby, the size of the peripheral circuit 12 can be reduced. Furthermore, when the size of the memory cell array 11 is reduced with the miniaturization of the MTJ element 20, the size of the peripheral circuit 12 can be reduced accordingly. As a result, the chip size of the MRAM 10 can be reduced. Further, even when the size (including the gate length) of the peripheral transistor 50 is the same as that of the selection transistor 21, the peripheral transistor having desired characteristics can be obtained by controlling the contact resistance of the source / drain region using the MTJ element 51. 50 can be realized.

  Further, by making the magnetization reversal current of the MTJ element 51 larger than that of the MTJ element 20, the resistance value of the MTJ element 51 is hardly changed while the peripheral circuit 12 is operating. Thereby, it is possible to suppress the operation of the peripheral circuit 12 from becoming unstable.

  In the present embodiment, the MTJ element 51 is used in the peripheral circuit 12 in order to increase the contact resistance of the peripheral transistor 50, but the method of using the MTJ element 51 as a resistance element is limited to the above. It is not a thing. The MTJ element 51 may be used as a resistance element necessary for the peripheral circuit 12 and other circuits.

  In the above embodiment, the MRAM is described as an example of the resistance change memory. However, as another resistance change memory, a resistance random access memory (ReRAM) and a phase change random access memory (PCRAM) are used. It can also be applied to Phase-Change Random Access Memory.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... MRAM, 11 ... Memory cell array, 12 ... Peripheral circuit, 13 ... Row decoder, 14 ... Column selection circuit, 15 ... Write circuit, 16 ... Read circuit, 17 ... Column decoder, 20 ... MTJ element, 21 ... Selection transistor, DESCRIPTION OF SYMBOLS 30 ... Semiconductor substrate, 31 ... Element isolation insulating layer, 32 ... Source region, 33 ... Drain region, 34 ... Gate insulating film, 35 ... Cap layer, 36 ... Side wall, 37, 38 ... Contact plug, 39 ... Interlayer insulating layer, 40 ... Underlayer, 41 ... Memory layer, 42 ... Tunnel barrier layer, 43 ... Reference layer, 44 ... Hard mask layer, 50 ... Peripheral transistor, 51 ... MTJ element.

Claims (6)

Each of the plurality of memory cells includes a variable resistance element and a selection transistor, and the variable resistance element is on a contact plug electrically connected to a diffusion layer of the selection transistor. A memory cell array provided;
A peripheral circuit that controls an operation of the memory cell array and includes a resistance element and a peripheral transistor, and the resistance element is provided on a contact plug electrically connected to a diffusion layer of the peripheral transistor;
Comprising
The resistance element has the same structure as the variable resistance element,
The first current at which the resistance change of the resistance element occurs is larger than the second current at which the resistance change of the variable resistance element occurs,
The size of the resistance element is larger than the size of the variable resistance element,
Each of the variable resistance element and the resistance element comprises a magnetoresistive element,
The magnetoresistive element includes a storage layer whose magnetization direction is variable, a reference layer whose magnetization direction is unchanged, and a nonmagnetic layer sandwiched between the storage layer and the reference layer,
The resistance change memory according to claim 1, wherein a film thickness of the memory layer of the resistance element is larger than a film thickness of the memory layer of the variable resistance element. Each of the plurality of memory cells includes a variable resistance element and a selection transistor, and the variable resistance element is on a contact plug electrically connected to a diffusion layer of the selection transistor. A memory cell array provided;
A peripheral circuit that controls an operation of the memory cell array and includes a resistance element and a peripheral transistor, and the resistance element is provided on a contact plug electrically connected to a diffusion layer of the peripheral transistor;
Comprising
The resistance change memory, wherein the resistance element has the same structure as the variable resistance element.   The resistance change memory according to claim 2, wherein the first current at which the resistance change of the resistance element occurs is greater than the second current at which the resistance change of the variable resistance element occurs.   4. The resistance change memory according to claim 2, wherein the size of the resistance element is larger than the size of the variable resistance element. Each of the variable resistance element and the resistance element comprises a magnetoresistive element,
3. The magnetoresistive element includes a storage layer having a variable magnetization direction, a reference layer having an invariable magnetization direction, and a nonmagnetic layer sandwiched between the storage layer and the reference layer. The resistance change memory according to any one of 1 to 4.   The resistance change memory according to claim 5, wherein a film thickness of the memory layer of the resistance element is larger than a film thickness of the memory layer of the variable resistance element.

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