JP2014053345A - Method of manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to reduce warpage of a semiconductor substrate while preventing peeling of an amorphous silicon film. Further, the amorphous silicon film is prevented from being peeled off by a high temperature annealing process performed after the amorphous silicon film is formed.
A method of manufacturing a semiconductor device according to the present invention includes an amorphous silicon film formed on a surface of a semiconductor substrate by a plasma CVD method using silane gas as a raw material and maintaining the temperature of the semiconductor substrate at a predetermined film formation temperature. And a step (step S2) of applying a heat treatment to the semiconductor substrate at a temperature equal to or lower than the predetermined film-forming temperature after forming the amorphous silicon film.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming an amorphous silicon film.

  One type of thin film constituting a semiconductor device is an amorphous silicon film. An amorphous silicon film is a thin film made of non-crystallized silicon, and in recent years, it is often formed using a plasma CVD (Chemical Vapor Deposition) method.

  The plasma CVD method is a thin film formation method in which a thin film is formed by depositing a plasma source gas on a substrate surface. In the implementation of the plasma CVD method, a single wafer processing apparatus for processing wafers one by one is used. More specifically, first, one wafer is set on a stage provided in a film forming chamber of a single wafer apparatus, and heated to a predetermined film forming temperature. In this state, a silane gas as a source gas is supplied into the film forming chamber and a high frequency electric field is applied. Then, silane gas is turned into plasma, and atoms excited thereby adhere to the wafer, and an amorphous silicon film is formed on the surface of the wafer.

  Patent Document 1 discloses an example in which an amorphous silicon film is formed by a plasma CVD method.

JP 2003-197536 A

  However, a wafer having an amorphous silicon film formed as described above may have a large convex warp. This problem is that the amorphous silicon film formed by the plasma CVD method has a strong compressive stress, and when using a single wafer apparatus, the amorphous silicon film is formed only on one surface of the wafer. It is generated by. For example, in the case of a wafer which is a silicon substrate having a thickness of 750 μm and a thickness of 300 mmΦ, the warpage may reach a maximum of 200 μm (maximum height of the convex portion).

  After the amorphous silicon film is formed, a lithography process is performed. The limit value of the warp amount allowed there is 100 μm at the maximum height of the convex portion. Wafers with warpage exceeding this value must be discarded, causing a decrease in yield.

  Further, the process after the formation of the amorphous silicon film may include an annealing process (hereinafter referred to as “high temperature heat treatment”) at a temperature higher than the film formation temperature of the amorphous silicon film. When this high-temperature heat treatment is performed in a state in which the wafer is warped as described above, the amorphous silicon film may be peeled off.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an amorphous silicon film is formed on a semiconductor substrate by a plasma CVD method using silane gas as a raw material and maintaining the temperature of the semiconductor substrate at a predetermined film formation temperature. And forming the amorphous silicon film, and then subjecting the semiconductor substrate to a heat treatment at a first temperature equal to or lower than the predetermined deposition temperature.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of cell transistors on a surface of a semiconductor substrate; and a plurality of capacitive contacts each connected to one controlled electrode of the plurality of cell transistors. A step of forming a pad, and a step of forming an amorphous silicon film on the plurality of capacitive contact pads by a plasma CVD method using silane gas as a raw material and maintaining the temperature of the semiconductor substrate at a predetermined film formation temperature. And a step of applying a heat treatment to the semiconductor substrate at a first temperature not higher than the predetermined film-forming temperature after forming the amorphous silicon film, and provided for each of the capacitive contact pads. A plurality of cylinder holes penetrating the silicon film and the stopper film and exposing the upper surface of the capacitive contact pad corresponding to the bottom surface. Forming a conductive film at a growth temperature higher than the predetermined film forming temperature, and etching back to form a lower electrode that covers an inner surface of each of the plurality of cylinder holes, and the amorphous material. Removing the porous silicon film, forming a capacitive insulating film covering the surface of the lower electrode, and forming an upper electrode covering the surface of the lower electrode via the capacitive insulating film. Features.

  According to the present invention, since the heat treatment (hereinafter referred to as “low temperature heat treatment”) is performed at a first temperature lower than the film formation temperature after the amorphous silicon film is formed, the removal of the amorphous silicon film is performed. It is possible to reduce the warpage of the semiconductor substrate while preventing it. In addition, since the warpage of the semiconductor substrate is reduced, it is possible to prevent the amorphous silicon film from being peeled off even if a high-temperature heat treatment is performed thereafter.

(A) is the figure which showed typically a part of cross section in the middle of manufacture of the semiconductor device by the 1st Embodiment of this invention. (B) is a diagram showing an example of a state in which peeling of the amorphous silicon film 103 has occurred. It is a flowchart which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. (A) is a figure which shows the measurement result of the heat processing time dependence of the curvature amount of the wafer 101. FIG. (B) is a figure which shows the result of having measured the relative change of the amount of hydrogen desorbing from the amorphous silicon film 103 for every temperature of heat processing using the temperature rising desorption gas analysis method. It is a flowchart which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. It is a top view of the semiconductor device 1 by the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device 1 corresponding to the AA line of FIG. It is a figure which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1A is a diagram schematically showing a part of a cross section of the semiconductor device according to the first embodiment of the present invention during manufacturing. This semiconductor device is, for example, a DRAM (Dynamic Random Access Memory). In the manufacturing process, a plurality of semiconductor devices are formed in a matrix on the surface of the wafer, and then separated into individual semiconductor devices by dicing. To be separated. FIG. 1 shows a state before singulation. As shown in FIG. 1, an insulating film 102 and an amorphous silicon film 103 are laminated in this order on the upper surface of a wafer 101.

  As the wafer 101, it is preferable to use a commercially available product having a diameter of 300 mm and a thickness of 750 μm. Various semiconductor substrates such as an n-type single crystal substrate, a compound semiconductor substrate, a TFT substrate, and an SOI structure substrate can be used as the wafer 101. The insulating film 102 may be a silicon nitride film or a silicon oxide film. In addition, transistors, various wirings, and the like may be provided inside the insulating film 102 and the wafer 101. The amorphous silicon film 103 may be directly formed on the surface of the wafer 101 without providing the insulating film 102.

  The present embodiment is characterized in that the warpage of the wafer 101 can be reduced while preventing the separation of the amorphous silicon film 103 by devising the manufacturing method of the semiconductor device having the above structure. . Hereinafter, this characteristic point will be described with reference to a method for manufacturing a semiconductor device.

FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment. In the figure, only the process after the formation of the insulating film 102 is shown. As shown in the figure, in this manufacturing method, an amorphous silicon film 103 is formed on the upper surface of the insulating film 102 (step S1). Specifically, the wafer 101 on which the insulating film 102 is formed is set in a film formation chamber of a single wafer processing type plasma CVD apparatus having parallel plate electrodes. Then, while maintaining the wafer 101 at a predetermined film formation temperature, hydrogen and monosilane gas (SiH ₄ ) are supplied into the film formation chamber, and the atmospheric pressure in the film formation chamber is controlled to a predetermined value. This predetermined value is preferably set to 22 Torr, for example. Next, when high-frequency power of a predetermined voltage (for example, 400 W) is supplied to the parallel plate electrodes while the atmospheric pressure is stable at the predetermined value, high-frequency plasma is generated in the deposition chamber. As a result, the silicon product dissociated from the monosilane gas as the source gas is deposited on the upper surface of the insulating film 102, and the amorphous silicon film 103 is formed. Hereinafter, description will be made on the assumption that the thickness of the amorphous silicon film 103 formed in this way is 1500 nm.

  Here, the predetermined film forming temperature is preferably 550 ° C. or less, and more preferably 550 ° C. It is not preferable that the deposition temperature exceeds 550 ° C. because the amorphous silicon film 103 contains a polycrystalline component and cannot maintain the non-crystalline state. If the amorphous silicon film 103 contains a polycrystalline component, the surface of the amorphous silicon film 103 becomes uneven, making it difficult to perform lithography and dry etching with high accuracy in a later process. Become. The amorphous silicon film 103 formed while maintaining an amorphous state has an extremely flat surface, which is advantageous for high-precision processing. Further, if the amorphous state is maintained at the time of formation, the flatness of the surface is maintained even when crystallized by a subsequent heat treatment or the like.

In addition to the monosilane gas (SiH ₄ ) described above, a silane gas that does not contain elements other than silicon and hydrogen, such as disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ), is used as the source gas. be able to. Silane gas having an element other than silicon and hydrogen as a composition such as dichlorosilane (SiH ₂ Cl ₂ ) or trimethylsilane (SiH (CH ₃ ) ₃ ) has an element other than silicon and hydrogen in the amorphous silicon film 103. Since it will be contained, it is not preferable. Further, as described above, hydrogen is preferably used as the gas (carrier gas) supplied together with the source gas. Although it is conceivable to supply nitrogen as a carrier gas, it is not preferable because a nitride having a Si—N bond is contained in the amorphous silicon film 103.

  After step S1 is completed, an annealing process (low-temperature heat treatment) is performed in a nitrogen atmosphere at a temperature (first temperature) equal to or lower than the deposition temperature of the amorphous silicon film 103 (step S2). Specifically, after the film formation in step S1 is completed, the wafer 101 is once taken out from the plasma CVD apparatus. Thereafter, the taken wafer 101 is set in a batch processing apparatus having a furnace body capable of batch processing a plurality of wafers 101, and low-temperature heat treatment is performed in the batch processing apparatus. In the process of taking out the wafer 101 from the plasma CVD apparatus, the amorphous silicon film 103 temporarily changes in temperature from the deposition temperature to the deposition temperature or lower. However, since the time accompanied by this temperature change is within 20 seconds at the longest, it does not correspond to the low-temperature heat treatment step of Step S2. As will be described later, low-temperature heat treatment for a long time (at least 20 minutes or more) is required to reduce the amount of warpage of the wafer 101 to a significant degree. Further, after the amorphous silicon film 103 is formed on the wafer 101 by the plasma CVD apparatus, it is continuously performed in the same apparatus (without going through the process of taking out the wafer 101 from the plasma CVD apparatus) for 20 minutes or more. It is also possible to perform the heat treatment. Therefore, the heat treatment (temperature change) in the step of taking out the wafer 101 from the plasma CVD apparatus is not a low-temperature heat treatment step constituting the feature of the present invention. However, in the latter example (example in which the low temperature heat treatment process in step S2 is performed in the plasma CVD apparatus), since the plasma CVD apparatus is a single wafer processing apparatus, it is necessary to process the wafers 101 one by one. become. Since such a process can be considered as an exaggeration of productivity, the latter example is not practical.

  The low-temperature heat treatment in step S2 is performed to eliminate the warp of the wafer 101, and the first temperature is set to a temperature equal to or lower than the film formation temperature in order to prevent the amorphous silicon film 103 from being peeled off. . Hereinafter, detailed explanation will be given while showing results of actual experiments.

  FIG. 3A is a diagram showing a measurement result of the heat treatment time dependency of the warpage amount of the wafer 101. This figure shows an example in which the temperature of the heat treatment is 420 ° C., 450 ° C., 500 ° C., and 545 ° C. with respect to the case where the film formation temperature of the amorphous silicon film 103 is 550 ° C. In the example shown in the figure, the warpage amount of the wafer 101 immediately after the film formation is 170 μm. From the results shown in the figure, even if the temperature of the heat treatment is any of the above four, the warpage amount of the wafer 101 tends to decrease with the passage of time, while the reduction rate per hour decreases with the passage of time. It is understood. Further, it is understood that the lower the heat treatment temperature, the smaller the decrease rate per time, and the decrease in the warpage amount stops at a large value.

  As described above, the maximum value of the warp amount of the wafer 101 that can be exposed by lithography is 100 μm. If the amount of warpage is larger than this value, processing using lithography cannot be performed in a later process. Therefore, in step S2, the amount of warpage of the wafer 101 needs to be suppressed to 100 μm or less. When FIG. 3A is viewed from this viewpoint, when the temperature of the heat treatment is 420 ° C. or 450 ° C., it is difficult to suppress the warpage amount of the wafer 101 to 100 μm or less even if the treatment is performed over a long time. It is understood. On the other hand, when the temperature of the heat treatment is 500 ° C. or 545 ° C., the amount of warpage of the wafer 101 can be suppressed to 100 μm or less by performing the processing for about 50 minutes and about 24 minutes, respectively.

  FIG. 3B is a diagram showing a result of measuring a relative change in the amount of hydrogen desorbed from the amorphous silicon film 103 by using a temperature-programmed desorption gas analysis method for each heat treatment temperature. In the figure, the peak value of the spectrum of hydrogen molecules detected during the heat treatment for 5 minutes is plotted. Also in this figure, as in FIG. 3A, an example in which the deposition temperature of the amorphous silicon film 103 is 550 ° C. is shown.

  From the result of FIG. 3B, it is understood that hydrogen desorption does not occur when the temperature of the heat treatment is 400 ° C. or lower. Further, it is understood that hydrogen desorption occurs when the temperature of the heat treatment exceeds 400 ° C., and the amount of desorbed hydrogen increases as the temperature of the heat treatment increases between 400 ° C. and 620 ° C. Further, it is understood that when the temperature of the heat treatment exceeds 620 ° C., the amount of detached hydrogen decreases rapidly as the temperature increases.

  In the measurement of FIG. 3B, for the temperature higher than 400 ° C., different wafers 101 were prepared for each temperature, and the test was performed. The presence or absence of peeling of the film 103 was also verified. As a result, it was confirmed that the amorphous silicon film 103 was peeled off from the wafer 101 which was heat-treated at a temperature higher than 550 ° C. which is the film forming temperature. FIG. 1B shows an example where the amorphous silicon film 103 is peeled off. On the other hand, peeling of the amorphous silicon film 103 was not confirmed for the wafer 101 that was heat-treated at a temperature of 550 ° C. or lower. In addition, as a result of examination including the results of verifying various film formation temperatures, the amorphous silicon film 103 is peeled off when heat treatment is performed at a temperature higher than the film formation temperature of the amorphous silicon film 103. It was confirmed that it occurred.

  Here, the fact that the amount of warpage of the wafer 101 has decreased means that the stress of the amorphous silicon film 103 has decreased. As a factor for reducing the stress, in addition to the desorption of hydrogen described in FIG. 3B, crystallization of the amorphous silicon film 103 may be considered. However, as shown in FIG. Since the amount of warpage is also reduced by the heat treatment at 550 ° C. or less in which the state is maintained, it is appropriate to consider that the decrease in the amount of warpage due to the heat treatment in step S2 is caused by the desorption of hydrogen.

  From the experimental results described above, it can be said that the heat treatment in step S2 must first be performed at a temperature lower than the film formation temperature. This is for preventing peeling of the amorphous silicon film 103. As described above, since the film forming temperature needs to be 550 ° C. or lower from the viewpoint of maintaining the non-crystalline state, the temperature of the heat treatment in step S2 needs to be 550 ° C. or lower.

  Secondly, from the viewpoint of generating hydrogen desorption and thereby reducing the warpage of the wafer 101, it is necessary to set the temperature of the heat treatment in step S2 to 400 ° C. or more and 700 ° C. or less as shown in FIG. There is. The fact that the temperature of the low-temperature heat treatment is 400 ° C. or higher means that the film forming temperature must also be 400 ° C. or higher.

  In summary, it can be said that it is preferable to perform step S2 at a temperature not higher than the film formation temperature within the range where the film formation temperature and the temperature of the low-temperature heat treatment in step S2 are both 400 ° C. or higher and 550 ° C. or lower. By doing so, it is possible to maintain the amorphous state of the amorphous silicon film 103, prevent the amorphous silicon film 103 from being peeled off, and reduce the warpage of the wafer 101.

  However, as shown in FIG. 3A, at a temperature close to 400 ° C., there is a high possibility that the limit value 100 μm of the warpage amount allowed in the lithography process cannot be achieved. Therefore, from the viewpoint of achieving this limit value, it can be said that it is more preferable to set the temperature of the low-temperature heat treatment in step S2 to 500 ° C. or higher in consideration of the result of FIG. That is, it can be said that it is more preferable that both the film formation temperature and the temperature of the low-temperature heat treatment in step S2 be 500 ° C. or higher and 550 ° C. or lower.

  Furthermore, it can be said that the higher the temperature of the low-temperature heat treatment in step S2, the better, from the viewpoint of reducing the warpage amount as quickly as possible and shortening the manufacturing time. In order to prevent the amorphous silicon film 103 from being peeled off by the low temperature heat treatment, it can be said that the temperature of the low temperature heat treatment in step S2 is preferably set slightly lower than the film formation temperature. Therefore, as the optimum conditions, the film formation temperature is set to 550 ° C. which is the upper limit value capable of maintaining the amorphous state, and the temperature of the low-temperature heat treatment in step S2 is set to 545 ° C. shown in FIG. .

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, after the amorphous silicon film 103 is formed, the annealing process (low temperature heat treatment) is performed at a temperature lower than the film forming temperature. Thus, it is possible to reduce the warpage of the wafer 101 while preventing the amorphous silicon film 103 from being peeled off. Further, the annealing process at a temperature lower than the film forming temperature can be finished as quickly as possible, and the manufacturing time can be shortened.

  In the above embodiment, the warping of the wafer 101 is reduced by the annealing process after the film formation, but the inventor of the present invention says whether the warping of the wafer 101 can be reduced by adjusting the film forming conditions. I also confirmed the point. As a result, the hydrogen content in the amorphous silicon film 103 cannot be changed greatly by adjusting the deposition conditions, at least under the constraint that silane gas is used as the source gas and the plasma CVD method is used. Therefore, it was concluded that it is difficult to reduce the warpage of the wafer 101. After all, as described in the above embodiment, after the amorphous silicon film 103 is formed, annealing treatment (low temperature heat treatment) at a temperature lower than the film forming temperature can reduce the warpage of the wafer 101. It seems to be the best way.

In addition to the plasma CVD method, a thermal CVD method can be used for forming the amorphous silicon film. In the thermal CVD method, monosilane (SiH ₄ ) is supplied as a raw material gas to a furnace apparatus having a temperature of 500 to 550 ° C. in which a plurality of wafers are set, and silicon generated by thermally decomposing this is deposited on the substrate surface. This is a method for forming an amorphous silicon film, and when the thermal CVD method is used, the warpage of the wafer as described above does not occur. On the other hand, however, the thermal CVD method has a problem that productivity is poor as compared with the plasma CVD method because the film formation rate regulated by temperature is slow. One of the features of the present invention is that the warpage of the wafer can be reduced while using a plasma CVD method with high productivity.

  FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the present embodiment is the same as that shown in FIG. Further, steps S1 and S2 in FIG. 4 are the same steps as steps S1 and S2 shown in FIG. The semiconductor device manufacturing method according to the present embodiment differs from the semiconductor device manufacturing method according to the first embodiment in that step S3 is performed after step S2. Hereinafter, the description will be given focusing on the difference.

  In step S3, annealing (high temperature heat treatment) is performed at a temperature (second temperature) higher than the deposition temperature of the amorphous silicon film 103. This high-temperature heat treatment is not intended to process the amorphous silicon film 103, but is performed to process another film (not shown) in a later process. The specific value of the second temperature is also determined by the convenience of processing other films, and the state of the amorphous silicon film 103 is not considered. In a specific example, the second temperature may reach 650 ° C., for example. This value of 650 ° C. is higher than 550 ° C., which is the upper limit value of the deposition temperature of the amorphous silicon film 103 necessary for maintaining the amorphous state. In the third embodiment to be described later, a more specific example of the high temperature heat treatment will be described.

  If step S3 is executed after step S1 without passing through step S2, the amorphous silicon film 103 is peeled off as described in the first embodiment. However, in this embodiment, since the annealing process (step S2) at a temperature equal to or lower than the film formation temperature is performed before step S3, the stress on the amorphous silicon film 103 is reduced at the stage of step S2. To do. Therefore, since the stress of the amorphous silicon film 103 is small in the step S3, the possibility that the amorphous silicon film 103 is peeled off during the high-temperature heat treatment in the step S3 is reduced.

  Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. FIG. 5 is a plan view of the semiconductor device 1 according to the third embodiment of the present invention. FIG. 6 is a cross-sectional view of the semiconductor device 1 corresponding to the line AA in FIG. 7 to 9 show a method of manufacturing the semiconductor device 1 according to the present embodiment, and are cross-sectional views of the semiconductor device 1 being manufactured corresponding to the line AA in FIG.

  In the following, the structure of the semiconductor device 1 as a finished product will be described first, and then the method for manufacturing the semiconductor device according to the present embodiment will be described.

  The semiconductor device 1 is a DRAM and has a semiconductor substrate 2 as shown in FIG. As shown in FIG. 5, a plurality of word lines WL extending in the Y direction and a plurality of bit lines BL extending in the X direction are arranged on the surface of the semiconductor substrate 2. FIG. 5 shows only two word lines WL and three bit lines BL, but actually, a larger number of word lines WL and bit lines BL are arranged.

  An element isolation insulating film I constituting an element isolation region is embedded in the surface of the semiconductor substrate 2, and a plurality of active regions K are partitioned in a matrix on the surface of the semiconductor substrate 2 by the element isolation insulating film I. Yes. Each active region K has a long planar shape in the X ′ direction inclined with respect to the X direction. When viewed in the Y direction, the active regions K and the element isolation insulating films I are alternately spaced at equal intervals and at equal pitches. Is arranged.

  As shown in FIG. 5, two word lines WL and one bit line BL correspond to each active region K, and a cell transistor and a cell capacitor are provided for each word line WL. As shown in FIG. 5, capacitance contact plugs 22a and 22b are arranged in each active region K. These are respectively connected to one of the two word lines WL and one of the cell transistors. A conductor connecting the control electrode and the lower electrode of the cell capacitor.

  As shown in FIG. 6, the word line WL is configured by a buried conductor buried in the surface of the semiconductor substrate 2. More specifically, a trench 3 extending in the Y direction is provided on the surface of the semiconductor substrate 2, and a titanium nitride film 7 and a tungsten film 8 are formed inside the trench 3 through a thin gate insulating film 6. A laminated film is embedded. The word line WL is composed of this laminated film. A cap insulating film 9 is embedded in the upper portion of the trench 3. The upper surface of the cap insulating film 9 is located at the same height as the upper surface of the element isolation insulating film I.

  A region located between two word lines WL in the semiconductor substrate 2 in the active region K constitutes a bit line contact region 4. An impurity diffusion layer 12 is provided above the bit line contact region 4. This impurity diffusion layer 12 constitutes one controlled electrode (one of source / drain) of each of the two corresponding cell transistors. In addition, the regions located on both sides of the two word lines WL in the semiconductor substrate 2 in the active region K respectively constitute the capacitor contact region 5. An impurity diffusion layer 21 is provided above each capacitor contact region 5. These impurity diffusion layers 21 constitute the other controlled electrode (the other of the source / drain) of the corresponding cell transistor.

  An interlayer insulating film 10 is formed on the upper surface of the semiconductor substrate 2. The interlayer insulating film 10 is provided with a bit line contact hole 11 with an impurity diffusion layer 12 exposed on the bottom surface. The bit line BL is formed by laminating a polysilicon film 13 and a tungsten film 14 formed inside and above the bit line BL. Consists of a membrane. An insulating film 15 made of a silicon nitride film is formed on the upper surface of the tungsten film 14 constituting the bit line BL. As shown in FIG. 6, a liner film 16 is formed on the side surface of the laminated film composed of the polysilicon film 13, the tungsten film 14, and the insulating film 15. The liner film 16 is also formed on the upper surface of the interlayer insulating film 10. An SOD (spin on dielectric) film 17 is formed on the upper surface of the liner film 16. The upper surface of the SOD film 17 is located at the same height as the upper surface of the insulating film 15.

  Above each of the two impurity diffusion layers 21, a capacitor contact hole 20 that penetrates the interlayer insulating film 10, the liner film 16, and the SOD film 17 is provided. Each capacitance contact hole 20 is filled with a conductive film such as tungsten, and constitutes the above-described capacitance contact plugs 22a and 22b.

  Capacitor contact pads 30 are provided on the upper surfaces of the capacitor contact plugs 22a and 22b, respectively. In addition, a stopper film 31 having a film thickness covering the entire capacitor contact pad 30 is provided on the SOD film 17.

  Two cell capacitors C are arranged for each active region K in the upper layer of the stopper film 31. As shown in FIG. 6, each cell capacitor C includes a lower electrode 33, a capacitive insulating film 34, and upper electrodes 35 and 36. The lower electrode 33 is a conductive film having a cylindrical three-dimensional shape, and the lower part thereof penetrates the stopper film 31 and is in contact with the upper surface of the corresponding capacitor contact pad 30. The upper part of the lower electrode 33 is connected to the upper part of another lower electrode 33 adjacent thereto by a support film 32. The capacitive insulating film 34 is formed so as to cover the portion of the surface of the lower electrode 33 located above the stopper film 31 and the support film 32. The upper electrode 35 is a conductive film made of polysilicon and covers the surfaces of the lower electrode 33 and the support film 32 with a capacitive insulating film 34 interposed therebetween. The upper surface of the upper electrode 35 is provided at a position higher than the upper surface of the support film 32. The upper electrode 36 is composed of a tungsten film provided on the upper surface of the upper electrode 35.

  A wiring 37 made of a conductive film such as aluminum is disposed on the upper surface of the upper electrode 36. Further, the upper surface of the upper electrode 36 is covered with an interlayer insulating film 38 having a film thickness covering the entire wiring 37, and a surface protective film 39 is formed on the upper surface of the interlayer insulating film 38.

  Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. The process described below is performed in a state where the semiconductor substrate 2 is a wafer before being singulated. First, the outline of this manufacturing method will be described. In this manufacturing method, an amorphous silicon film is used when forming the lower electrode 33. After the amorphous silicon film is formed, the above-described step S2 is performed. An annealing process (low temperature heat treatment) is performed at a temperature equal to or lower than the corresponding film forming temperature. As a result, in the present manufacturing method, it is possible to reduce the warpage of the wafer 101 while preventing the amorphous silicon film 103 from being peeled off. Further, after the low-temperature heat treatment, annealing treatment (high-temperature heat treatment) is performed at a temperature higher than the film forming temperature corresponding to step S3 described above. According to the present manufacturing method, the low-temperature heat treatment is performed before this high-temperature heat treatment. The possibility that the amorphous silicon film 103 is peeled during the high-temperature heat treatment is reduced. This will be described in detail below.

  The steps up to the formation of the stopper film 31 are the same as in the semiconductor device manufacturing method according to the background art. Outlined with reference to FIG. 7, first, an element isolation insulating film I, which is a silicon oxide film, is buried in the surface of the semiconductor substrate 2 by a well-known STI method. Thereby, the active region K is partitioned. Next, a trench 3 extending in the Y direction is provided on the surface of the semiconductor substrate 2 by dry etching, and a gate insulating film 6 is formed on the inner surface of the trench 3 using a thermal oxidation process. Then, for example, a titanium nitride film and a tungsten film are sequentially formed by using the CVD method, and further etched back to form a laminated film of the titanium nitride film 7 and the tungsten film 8 in the middle to the lower part of the trench 3. A word line WL is formed.

  After the word line WL is formed, the inner surface of the space portion above the trench 3 is covered with a liner film (not shown) made of a silicon nitride film or the like, for example, by CVD. Then, a cap insulating film 9 is formed on the liner film so as to fill the trench 3, and the surface is flattened to such an extent that the liner film is exposed by CMP (Chemical Mechanical Polishing). Further, unnecessary liner film and cap insulating film 9 are further removed by etching, so that the height of the upper surface of the cap insulating film 9 coincides with the height of the surface of the semiconductor substrate 2.

  Next, an interlayer insulating film 10 is formed by forming a silicon oxide film on the entire surface, and a bit line contact hole 11 penetrating the interlayer insulating film 10 is formed by photolithography and dry etching. As shown in FIG. 5, the bit line contact hole 11 is preferably a line-shaped opening pattern extending in the Y direction. In the region where the bit line contact hole 11 and the active region K intersect, the surface of the semiconductor substrate 2 is exposed. An N-type impurity diffusion layer 12 is formed near the surface of the semiconductor substrate 2 by ion-implanting N-type impurities such as arsenic into the exposed surface of the semiconductor substrate 2.

  Next, a laminated film of a polysilicon film 13, a tungsten film 14, and an insulating film 15 that is a silicon nitride film is formed on the entire surface by, eg, CVD, and patterned into the shape of the bit line BL. Thereby, the bit line BL extending in the X direction and connected to the impurity diffusion layer 12 on the lower surface, and the insulating film 15 covering the upper surface of the bit line BL are formed.

Next, a silicon nitride film is formed on the entire surface by, eg, CVD, so that the entire surface including the side surfaces of the bit line BL and the insulating film 15 is covered with the liner film 16. Further, an SOD film 17 that is a coating film is deposited so as to fill a space between the bit lines BL, and an annealing process is performed in a high-temperature water vapor (H ₂ O) atmosphere, so that the SOD film 17 becomes a solid film. Reform. Subsequently, planarization is performed by CMP until the upper surface of the insulating film 15 is exposed.

  Next, a capacitor contact hole 20 penetrating the SOD film 17, the liner film 16, and the interlayer insulating film 10 is formed by photolithography and dry etching. The surface of the semiconductor substrate 2 is exposed at the bottom surface of the capacitor contact hole 20. An N-type impurity diffusion layer 21 is formed in the vicinity of the surface of the semiconductor substrate 2 by ion-implanting N-type impurities such as phosphorus into the exposed surface of the semiconductor substrate 2. Thereafter, the capacitance contact plugs 22a and 22b are formed by embedding the capacitance contact hole 20 with a conductive film such as tungsten.

  Next, a wiring material layer made of titanium nitride, tungsten, or the like is formed on the upper surfaces of the capacitor contact plugs 22a and 22b by CVD. Then, this wiring material layer is patterned using photolithography and dry etching, thereby forming the capacitor contact pad 30. Thereafter, a stopper film 31 that is a silicon nitride film is formed with a film thickness that covers the capacitor contact pad 30.

  Up to this point, the process is the same as in the background art. When the formation up to the formation of the stopper film 31 is completed, an amorphous silicon film 40 is then formed as shown in FIG. The film thickness of this amorphous silicon film 40 is preferably 1500 nm. The amorphous silicon film 40 is formed in the same procedure as the amorphous silicon film 103 described in the first embodiment. The film formation temperature is preferably set to 550 ° C., which is an upper limit value capable of maintaining an amorphous state.

  Here, when the amount of warpage of the semiconductor substrate 2 (wafer) was actually measured before the amorphous silicon film 40 was formed, it was 10 μm or less. On the other hand, when the same measurement was performed after the amorphous silicon film 40 was formed with the film thickness and the film forming temperature set to 1500 nm and 550 ° C., respectively, the semiconductor substrate 2 changed to a convex shape and the amount of warpage became 170 μm. It was. This means that the semiconductor substrate 2 is warped by forming the amorphous silicon film 40. In the subsequent steps, the cylinder hole 41 is provided in the amorphous silicon film 40. However, since the exposure focus position cannot be adjusted well in a state where the warp of 170 μm is generated, the cylinder hole 41 is accurately formed. It is impossible.

  The amorphous silicon film 40 is formed with the semiconductor substrate 2 set in a plasma CVD apparatus. After the amorphous silicon film 40 is formed, the semiconductor substrate 2 is then set in a batch processing apparatus, and an annealing process (low temperature) in a nitrogen atmosphere for a predetermined time at a temperature not higher than the deposition temperature of the amorphous silicon film 40. Heat treatment). As described in the first embodiment, the movement from the plasma CVD apparatus to the batch processing apparatus does not correspond to the low temperature heat treatment process that constitutes the feature of the present invention. When the film forming temperature is 550 ° C., the temperature and processing time of the low-temperature heat treatment are preferably 545 ° C. and 60 minutes, respectively. Thereby, as described in detail in the first embodiment, warping of the semiconductor substrate 2 is reduced. When the measurement was actually performed on the semiconductor substrate 2 in which the warp of 170 μm was generated, it was confirmed that the warp amount was reduced to 60 μm. Further, no peeling of the amorphous silicon film 40 was confirmed.

  When the low-temperature heat treatment is completed, the semiconductor substrate 2 is returned to the plasma CVD apparatus, and a support film 32 that is a silicon nitride film is formed on the upper surface of the amorphous silicon film 40.

  Next, using lithography and dry etching, as shown in FIG. 8, a cylinder penetrating the support film 32, the amorphous silicon film 40, and the stopper film 31 at a position overlapping the capacitor contact pad 30 in plan view. The hole 41 is opened. In this etching, first, the support film 32 and the amorphous silicon film 40 are etched by etching with a low etching rate with respect to the stopper film 31. Thereafter, the stopper film 31 is etched to expose the upper surface of the capacitor contact pad 30. By performing such two-stage etching, it is possible to prevent the etching from reaching the portion below the stopper film 30. Since the warp of the semiconductor substrate 2 is reduced by the low-temperature heat treatment described above, the formation of the cylinder hole 41 in this step can be performed with high accuracy.

  Next, a conductive film such as titanium nitride is formed and etched back to form a lower electrode 33 that covers the inner surface of the cylinder hole 41. Since it is necessary to set the growth temperature to 650 ° C., for example, in the formation of this conductive film, in this embodiment, the formation process of the lower electrode 33 is the high-temperature heat treatment in step S3 described in the second embodiment. Equivalent to. If the lower electrode 33 is formed while the semiconductor substrate 2 is warped by 170 μm, the amorphous silicon film 40 is peeled off by exposure to a high temperature of 650 ° C. However, in the present embodiment, the low-temperature heat treatment described above is performed before the formation of the lower electrode 33 to reduce the warp of the semiconductor substrate 2 to 60 μm, so that the amorphous silicon film 40 does not peel off.

  Next, the amorphous silicon film 40 is removed by wet etching using a potassium hydroxide solution, thereby exposing the lower electrode 33 as shown in FIG. The support film 32 is provided to prevent the lower electrode 33 from collapsing at this time. Then, as shown in FIG. 6, a cell capacitor C is formed by sequentially forming a capacitive insulating film 34 that covers the surface of the lower electrode 33, an upper electrode 35 that is a polysilicon film, and an upper electrode 36 that is a tungsten film. To do. Thereafter, a wiring 37 made of a conductive film such as aluminum is formed, and an interlayer insulating film 38 and a surface protective film 39 are sequentially formed, whereby the semiconductor device 1 is completed.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, when the semiconductor device 1 which is a DRAM is formed, the semiconductor substrate 2 (wafer) is prevented while preventing the amorphous silicon film 40 from being peeled off. ) Can be reduced. In addition, the low-temperature heat treatment can be terminated as quickly as possible to shorten the manufacturing time. Further, when applying a temperature of, for example, 650 ° C. to form the lower electrode 33, it is possible to reduce the possibility that the amorphous silicon film 40 is peeled off.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Trench 4 Bit line contact region 5 Capacitance contact region 6 Gate insulating film 7 Titanium nitride film 8 Tungsten film 9 Cap insulating film 10 Interlayer insulating film 11 Bit line contact holes 12, 21 Impurity diffusion layer 13 Polysilicon Film 14 Tungsten film 15 Insulating film 16 Liner film 17 SOD film 20 Capacitance contact holes 22a and 22b Capacitance contact plug 30 Capacitance contact pad 31 Stopper film 32 Support film 33 Lower electrode 34 Capacitance insulating films 35 and 36 Upper electrode 37 Wiring 38 Interlayer insulation Film 39 Surface protective film 40 Amorphous silicon film 41 Cylinder hole 101 Wafer 102 Insulating film 103 Amorphous silicon film BL Bit line C Cell capacitor I Element isolation insulating film K Active region WL Word line

Claims (7)

A step of forming an amorphous silicon film on the semiconductor substrate by a plasma CVD method using silane gas as a raw material and maintaining the temperature of the semiconductor substrate at a predetermined film formation temperature;
And a step of performing a heat treatment on the semiconductor substrate at a first temperature equal to or lower than the predetermined film-forming temperature after forming the amorphous silicon film. 2. The method comprising: applying a second heat treatment to the semiconductor substrate at a second temperature higher than the predetermined film-forming temperature after performing the heat treatment at the first temperature. Semiconductor device manufacturing method. Forming a plurality of cell transistors on a surface of a semiconductor substrate;
Forming a plurality of capacitive contact pads respectively connected to one controlled electrode of the plurality of cell transistors;
Forming an amorphous silicon film on the plurality of capacitive contact pads by a plasma CVD method using silane gas as a raw material and maintaining the temperature of the semiconductor substrate at a predetermined film formation temperature;
Applying a heat treatment to the semiconductor substrate at a first temperature not higher than the predetermined film-forming temperature after forming the amorphous silicon film;
Forming a plurality of cylinder holes that are provided for each of the capacitor contact pads, penetrate the amorphous silicon film and the stopper film, and expose the upper surface of the capacitor contact pad corresponding to the bottom surface;
Forming a conductive film at a growth temperature higher than the predetermined film formation temperature, and forming a lower electrode that covers the inner surface of each of the plurality of cylinder holes by etching back; and
Removing the amorphous silicon film;
Forming a capacitive insulating film covering the surface of the lower electrode;
Forming an upper electrode that covers the surface of the lower electrode with the capacitive insulating film interposed therebetween.   4. The method of manufacturing a semiconductor device according to claim 1, wherein both the predetermined film forming temperature and the first temperature are 400 ° C. or higher and 550 ° C. or lower. 5.   The method of manufacturing a semiconductor device according to claim 4, wherein both the predetermined film forming temperature and the first temperature are 500 ° C. or higher.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the silane gas is a gas that does not contain an element other than silicon and hydrogen as a composition.   The formation of the amorphous silicon film and the heat treatment at the first temperature are performed in a state where the semiconductor substrate is set in different apparatuses. The manufacturing method of the semiconductor device as described in 2. above.

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