JP2014049929A - Transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a direct RF modulation transmitter for reducing a circuit area by suppressing the number of bits of digital/analog conversion, and for achieving noise reduction.SOLUTION: The transmitter includes: a plurality of direct RF modulators 302a to 302c and 306a to 306c connected in parallel; delay circuits 304a to 304c and 307a to 307c for delaying digital baseband input signals IBB Data and QBB Data to be input to the direct RF converters; an addition circuit 305 for adding output signals to be respectively output from the direct RF converters; a power control circuit 902 for controlling the output power of each of the direct RF converters; an operation/non-operation control circuit 904 for controlling the operational state/non-operational state of each of the direct RF converters. The transmitter is configured to input the digital baseband input signals and RF signal, and to modulate the RF signals in accordance with the digital baseband input signals, and to output it as an output signal.

Description

  The present invention relates to a transmitter, and more particularly to a transmitter that reduces the circuit area by reducing the number of bits for digital / analog conversion and realizes low noise.

Currently, there are portable communication terminal devices (hereinafter referred to as portable terminals) that can support a plurality of wireless communication standards and a plurality of frequency bands. Supporting a plurality of standards is called multi-mode support, and supporting a plurality of frequency bands is called multi-band support.
As a configuration related to transmission of such a multimode / multiband-compatible terminal, when a digital baseband signal is converted into an analog signal (digital / analog conversion), it is directly converted to an RF (Radio Frequency) transmission carrier frequency. Recently, transmitters that also perform frequency conversion and directly modulate from digital to RF frequencies are known. Such a transmitter is described in Patent Document 1, for example.

  In the invention described in Patent Document 1, an RF frequency conversion circuit having a configuration similar to a Gilbert cell mixer is incorporated into a part of a vertically stacked transistor in a widely known current control type digital / analog conversion circuit. . According to such a configuration, the digital / analog converter and the RF frequency converter or the RF modulator are formed as independent circuits, and the digital / analog conversion and the RF frequency conversion can be combined and performed simultaneously. .

  Further, the transmitter described in Patent Document 1 described above is a digital / RF converter (Digital / RF converter), a direct RF converter (Direct RF converter; DRC), or a direct RF modulation transmitter configured by the digital / RF converter. (Direct RF Modulation Transmitter), etc., which omits the analog baseband filter circuit between the digital / analog converter and the RF frequency converter, which is usually required in a conventional transmitter that performs separation operation. It has several advantages such as being able to.

FIG. 1 is a configuration diagram of a direct RF modulation transmitter described in Patent Document 1. In FIG. This direct RF modulation transmitter is composed of two digital / RF converters 1, 2, a frequency divider 3, and an output matching circuit 4.
The frequency divider 3 is externally supplied with an RF signal for frequency multiplication (hereinafter referred to as a transmission local RF signal) Lo _{in +} and a transmission local RF signal Lo _in− in which the phase of the transmission local RF signal Lo _{in +} is inverted _. ing. The frequency divider 3 receives the transmission local RF signals Lo _{in +} and Lo _in− , generates two pairs of differential local signals TxLoI ⁺ , TxLoI ⁻ , TxLoQ ⁺ , and TxLoQ ⁻ that are 90 degrees out of phase to generate DRC1, 2 respectively. In this example, since the differential local signals of 0 degree and 90 degrees are generated by the frequency divider 3, the frequency of the transmission local RF signals Lo _{in +} and Lo _in− is twice the frequency of the target transmission carrier wave. Become. The frequencies of the differential local signals TxLoI ⁺ , TxLoI ⁻ , TxLoQ ⁺ , and TxLoQ ⁻ are the frequencies of the transmission carrier waves. There is a phase difference of 90 degrees between the differential local signals TxLoI ⁺ , TxLoI ⁻ , TxLoQ ⁺ , and TxLoQ ⁻ .

DRC1 and DRC2 have the same configuration. A direct RF modulation transmitter is configured by supplying differential local signals TxLoI ⁺ , TxLoI ⁻ , TxLoQ ⁺ , and TxLoQ ⁻ to DRC1 and DRC2 with the same phase relationship as a so-called IQ quadrature modulator. In other words, an I (In-Phase) digital baseband signal (IBBDData) is input to DRC1. In addition, a Q (Quadrature) digital baseband signal (QBBData) is input to DRC2.

Further, the sampling clock signal CLK _BB is input to the DRCs 1 and 2. Each of the DRCs 1 and 2 is a signal conversion circuit having a function in which a digital / analog conversion function and a frequency multiplication function for frequency-converting a baseband signal into an RF signal are integrated. With such a function, the DRC 1 outputs an output differential signal from the clock signal CLK _BB , the I digital baseband signal, and the differential local signal. The DRC 2 outputs an output differential signal from the clock signal CLK _BB , the Q digital baseband signal, and the differential local signal. The output differential signals output from the DRCs 1 and 2 are added and output as a carrier wave through the output matching circuit 4 and the power amplifier (PA) 5 at the next stage.

  The output matching circuit 4 is composed of passive elements such as capacitors and inductor elements, and is a circuit having a bandpass type gain characteristic having the frequency of the transmission carrier wave as the center frequency. In the direct RF modulation transmitter shown in FIG. 1, it is assumed that DRC1 and DRC2 output current, and the addition of the output differential signal output by DRC1 and the output differential signal output by DRC2 Is realized by directly coupling the signal paths.

  FIG. 2 is a circuit configuration diagram of the DRC described in Patent Document 1 described above. DRC1 and DRC2 include a block that processes a signal on the LSB (Least Significant Bit) side and a block that processes a signal on the MSB (Most Significant Bit) side. .., 20k in which unit cells are binary weighted, local signal switches 220, 221,... 22k arranged in a Gilbert cell type, and data signal switches 240, 241. ,... 24k.

  In addition, the MSB (Most Significant Bit) side block includes a current source 210 weighted to the same value, a local signal switch 230 arranged in a Gilbert cell type, and a data signal switch 250 in parallel for the necessary bits. It has the structure connected to. With such a configuration, the direct RF modulation transmitter described in Patent Document 1 described above can simultaneously perform digital / analog conversion and frequency multiplication. In the example shown in FIG. 2, the current outputs of all the cells are voltage-converted by an external load provided outside the DRC.

  FIGS. 3A to 3C are diagrams for explaining the circuit operation of the digital / RF converter or the direct RF converter. FIG. 3A is a transmission carrier wave, FIG. 3B is a digital baseband signal, FIG. 3C shows the output signal after modulation. In such a circuit, an RF signal and a digital baseband signal are input, and the RF signal is modulated by the digital baseband signal and output. The modulated signal outputs a signal obtained by inverting the phase of the transmission carrier wave at the timing when the digital baseband signal is switched.

  Here, the noise of the output signal output directly from the RF modulation transmitter will be described. In a direct RF modulation transmitter, the main factors that determine the noise floor near the carrier wave of the output signal are thermal noise and flicker noise generated from internal elements, and quantization noise generated in the digital / analog conversion process. In a transmitter that performs digital / analog conversion and frequency multiplication in separate circuit blocks, an analog filter can be installed immediately after digital / analog conversion. For this reason, the quantization noise is hardly included in the signal after frequency conversion.

  However, the conventional DRC shown in FIG. 2 has a function in which the digital / analog conversion function and the frequency multiplication function are integrated as described above. For this reason, the quantization noise generated by the digital / analog conversion is directly output as noise near the carrier wave. For this reason, in the conventional DRC shown in FIG. 2, it is necessary to suppress the generation of quantization noise in digital / analog conversion.

  Equation (1) below shows the amount of quantization noise generated by digital / analog conversion when a normal digital / analog converter outputs a full-scale desired wave signal. Expression (1) is the amount of noise when the desired wave signal level is used as a reference, B is the number of bits, and fs is the sampling frequency.

  Equation (2) shows the amount of quantization noise when the digital / analog converted signal is frequency-multiplied when the DRC shown in FIG. Show. From equations (1) and (2), it can be seen that in order to reduce noise, it is necessary to increase the number of bits B or increase the sampling frequency fs. When realizing low quantization noise in a CMOS (Complementary Metal Oxide Semiconductor) circuit, it is necessary to make the sampling frequency the maximum frequency that can be realized, and to compensate for the shortage in noise reduction by increasing the number of bits.

  When the DRCs 1 and 2 shown in FIG. 2 are realized by MOS transistors, the current sources 200 to 20 k and 210 occupy most of the area of the DRCs 1 and 2. The areas of the current sources 200 to 20k and 210 are determined by the accuracy of current variations calculated from the number of bits of the input digital signal and the required linearity (distortion characteristics). Here, the number of bits of the input digital signal and the required linearity depend on the quantization noise level targeted by the direct RF modulation transmitter.

The relative variation of the current output from the MOS transistor is shown in Equation (3). In the formula (3), σI / I is a standard deviation of relative variation in current. A _{β and} A _VT are parameters of variation depending on the semiconductor process, V _GS is the voltage between the gate and source of the MOS transistor, V _t is the threshold voltage of the MOS transistor, W is the channel width of the MOS transistor, and L is the channel width of the MOS transistor Indicates the channel length.

Here, when the number of bits of the digital signal to be converted increases, it is considered to maintain the same linearity performance before and after the increase. Considering that the required value of the relative variation in current becomes 1/2 ^1/2 , it is necessary to double the area occupied by the current source by increasing 1 bit of the digital signal according to the above-described equation (3). . Furthermore, since the number of elements required for the configuration of DRC 1 and 2 is doubled by an increase of 1 bit, the current source area is quadrupled as a whole. Therefore, the method of increasing the number of bits for reducing the quantization noise causes a disadvantage that the area of DRC 1 and 2 is increased.

  In addition, the RF transmitter for wireless communication devices generally does not require a uniform value for the noise of the output RF signal. The belt is mixed. For example, W-CDMA, which is a cellular phone standard, is applied to an FDD (Frequency Division Duplex) system in which reception and transmission are performed at the same time, and the requirements regarding noise near the reception frequency are the strictest.

US2005 / 0111573 (A1)

  However, when a conventional direct RF modulation transmitter is realized with a CMOS semiconductor, it is necessary to increase the number of bits for digital / analog conversion in order to reduce quantization noise. Therefore, it is necessary to suppress a relative variation in current between elements serving as current sources. In order to suppress the relative variation in current, it is difficult to directly use a fine element that easily causes variation in characteristics in an RF modulation transmitter. For this reason, in the direct RF modulation transmitter, the circuit area increases as the number of bits increases. An increase in circuit area is a big problem because it directly leads to an increase in manufacturing cost.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a transmitter that reduces the circuit area by reducing the number of bits for digital / analog conversion and realizes low noise. There is to do.

The present invention has been made to achieve such an object, and the invention according to claim 1 includes a plurality of direct RF converters (302a to 302c, 306a to 306c) connected in parallel, and A plurality of delay circuits (304a to 304c, 307a to 307c) for delaying digital baseband input signals (IBBData, QBBData) inputted to a plurality of direct RF converters, and respective outputs outputted from the plurality of direct RF converters An adder circuit (305) for adding output signals, a power control circuit (902) for individually controlling the output power of the plurality of direct RF converters, and an operation / non-operation state of the plurality of direct RF converters individually The direct RF converter inputs the RF signal together with the digital baseband input signal. The modulated RF signals by the digital baseband input signal, and outputs as the output signal. (FIG. 9; Example 2)
According to a second aspect of the present invention, in the first aspect of the present invention, the plurality of delay circuits are connected to the plurality of direct RF converters on a one-to-one basis.

  According to a third aspect of the present invention, in the first aspect of the present invention, the plurality of direct RF converters include a first block including N direct RF converters, and M number of the direct RF converters. A second block including an RF converter, wherein the direct RF converter included in the first block inputs a first RF signal together with an in-phase digital baseband input signal, and the in-phase digital baseband input signal To modulate the first RF signal and output the first RF signal as a first output signal. The direct RF converter included in the second block has a phase with the first RF signal together with an orthogonal digital baseband input signal. A second RF signal that is 90 degrees different is input, the second RF signal is modulated by the quadrature digital baseband input signal, and is output as a second output signal. The first output signal output from each of the N (N is a natural number) direct RF converters included in the first block, and M (M is a natural number) included in the second block. The second output signal output from each of the direct RF converters is added.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the delay control circuit (309) further sets a delay amount of the digital baseband input signal for each of the plurality of delay circuits. It is characterized by having.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the delay control circuit includes a delay circuit connected to the N direct RF converters included in the first block. Each sets a delay amount for delaying the in-phase digital baseband signal, and each of the delay circuits connected to the M direct RF converters included in the second block receives the quadrature digital baseband signal. A delay amount to be delayed is set.

  The invention described in claim 6 is the invention described in claim 5, wherein each of the first block and the second block includes the N direct RF converters (M = N). The delay control circuit is included in the i-th direct RF converter (i is a natural number of 1 or more and N or less) of the direct RF converter included in the first block and in the second block. The same delay amount is set to the i-th direct RF converter of the direct RF converter.

According to a seventh aspect of the present invention, in the invention according to any one of the first to sixth aspects, the delay circuit determines the period of the signal rate of the digital baseband input signal from the digital baseband input signal. A delayed digital signal delayed by an integral multiple according to the delay amount is generated.
The invention according to claim 8 is the invention according to claim 7, wherein the delay circuit includes a number of flip-flop circuits equal to the integer.

According to the present invention, it is possible to set a notch frequency to be described later to an arbitrary frequency by using a plurality of direct RF converters with input signal delay function in parallel, and accordingly, filtering of quantization noise is appropriately performed. It becomes possible to carry out for a necessary frequency band.
For this reason, when such a transmitter is realized by a semiconductor integrated circuit, the demand for increasing the number of bits with respect to quantization noise is eased, and the number of bits for digital / analog conversion can be reduced as compared with the conventional one. Can be planned.

  From the above, according to the present invention, it is possible to provide a direct RF modulation transmitter that has low noise and can avoid an increase in circuit area.

1 is a configuration diagram of a direct RF modulation transmitter described in Patent Document 1. FIG. It is a circuit block diagram of DRC described in the patent document 1 mentioned above. (A) thru | or (c) is explanatory drawing of the circuit operation | movement of a digital / RF converter or a direct RF converter. It is a circuit block diagram for demonstrating Example 1 of the direct RF modulation transmitter which concerns on this invention. It is explanatory drawing of the input data input into DDRC shown in FIG. FIG. 6 is a configuration diagram of one delay circuit shown in FIG. 5. It is the figure which showed the equivalent functional characteristic in Example 1 of this invention. It is the figure which illustrated the gain characteristic which the quantization noise in Example 1 of this invention receives. It is a circuit block diagram for demonstrating Example 2 of the direct RF modulation transmitter which concerns on this invention. FIG. 10 is a relationship diagram between a transmitter output power setting signal and a transmitter output power of the direct RF modulation transmitter illustrated in FIG. 9. It is explanatory drawing of the transmitter output power control of the direct RF modulation transmitter shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 is a circuit configuration diagram for explaining the first embodiment of the direct RF modulation transmitter according to the present invention. The direct RF modulation transmitter according to the first embodiment is input to a plurality of direct RF converters (Direct RF Converters) 302a to 302n and 306a to 306m connected in parallel. A plurality of delay circuits 304a to 304n and 307a to 307m that delay the digital baseband input signals IBBData and QBBData, and an output matching circuit (adder circuit) 305 that adds the output signals output from the plurality of direct RF converters. I have.

The direct RF converter inputs an RF signal together with a digital baseband input signal, modulates the RF signal with the digital baseband input signal, and outputs it as an output signal.
The direct RF modulation transmitter of the first embodiment is an IQ orthogonal modulation type (CARTESIAN type) direct RF modulation transmitter. The direct RF modulation transmitter according to the first embodiment includes N direct RF converters 302a to 302n to which an I digital baseband signal is input and M DRCs 306a to 306m to which a Q digital baseband signal is input. I have.

In the first embodiment, the DRCs 302a to 302n constitute a DRC first block, and the DRCs 306a to 306m constitute a DRC second block.
That is, the plurality of direct RF converters includes a first block including N direct RF converters and a second block including M direct RF converters, and the direct blocks included in the first block. The RF converter receives the first RF signal together with the in-phase digital baseband input signal, modulates the first RF signal with the in-phase digital baseband input signal, and outputs the first RF signal as a first output signal. The direct RF converter included in the circuit inputs a quadrature digital baseband input signal and a second RF signal that is 90 degrees out of phase with the first RF signal, and the quadrature digital baseband input signal converts the second RF signal. It modulates and outputs as a 2nd output signal.

  The DRCs 302a to 302n are connected to the corresponding delay circuits 304a to 304n, respectively, to constitute the direct-RF converters (Delay-attached Direct RF Converters) 301a to 301n with an input signal delay function. Further, the DRCs 306a to 306m are connected to the corresponding delay circuits 307a to 307m, respectively, to constitute DDRCs 308a to 308m.

That is, the plurality of delay circuits 304a to 304n and 307a to 307m are connected to the plurality of direct RF converters 302a to 302n and 306a to 306m on a one-to-one basis.
Furthermore, the direct RF modulation transmitter according to the first embodiment receives the transmission local RF signals Lo _{in +} and Lo _in− , a pair of differential local signals TxLoI ⁺ and TxLoI ⁻ having a phase difference of 90 degrees from each other, and the other pair. Delay control circuit for controlling the amount of delay of input data input to the two frequency dividers 303 that generate the differential local signals TxLoQ ⁺ and TxLoQ ⁻ , the output matching circuit 305, the N DDRCs 301, and the M DDRCs 308. 309.

  The output matching circuit 305 is composed of passive elements such as capacitors and inductor elements, and is a circuit having a band-pass gain characteristic with the frequency of the transmission carrier wave as the center frequency. In the direct RF modulation transmitter according to the first embodiment, it is assumed that the DRCs 302a to 302n and DRCs 306a to 306m output current, and the output differential signals output from the DRCs 302a to 302n and the DRCs 306a to 306m output Although the addition with the output differential signal is realized by directly coupling the signal paths, the addition may be performed by the output matching circuit 305.

The output matching circuit (adder circuit) 305 includes a first output signal output from each of N (N is a natural number) direct RF converters included in the first block, and M included in the second block. The second output signal output from each of the direct RF converters (M is a natural number) is added.
Further, a delay control circuit 309 is further provided for setting a delay amount of the digital baseband input signal for each of the plurality of delay circuits.

The delay control circuit 309 can independently set the delay amounts of the input data of the DDRCs 301a to 301n and the DDRCs 308a to 308m. The delay amounts of the input data of DDRCs 301a to 301n are D1, D2,... DN, respectively, and the delay amounts of the input data of DDRCs 308a to 308m are D1, D2,.
In addition, the delay control circuit 309 sets a delay amount by which each of the delay circuits connected to the N direct RF converters included in the first block delays the in-phase digital baseband signal, and is set in the second block. Each of the delay circuits connected to the included M direct RF converters sets a delay amount for delaying the orthogonal digital baseband signal.
Each of the first block and the second block includes N direct RF converters (M = N), and the delay control circuit 309 includes the i-th direct RF converter included in the first block. The same delay amount is set in the direct RF converter (i is a natural number of 1 or more and N or less) and the i-th direct RF converter of the direct RF converter included in the second block.

FIG. 5 is an explanatory diagram of input data input to the DDRC shown in FIG. The DDRC301a, the I digital baseband signal (IBBData), and a sampling clock signal _{CLK BB} inputted. The I digital baseband signal is delayed by the delay control signal output from the delay control circuit 309 shown in FIG. 4, and then input to the DRC 302a.

4, the I digital baseband signal, the sampling clock signal CLK _BB , and the delay control signal are input to the DDRRCs 301b to 301n shown in FIG. 5 and the delayed I digital baseband signal. Are input to the corresponding DRCs. Also, Q digital baseband signals to DDRC308a to 308m shown in FIG. 4, the sampling clock signal _{CLK BB,} the delay control signal is input, Q digital baseband signal delayed is input respectively to the corresponding DRC.

FIG. 6 is a configuration diagram of one delay circuit shown in FIG. Note that the delay circuits 304a to 304n and the delay circuits 307a to 307m are all configured similarly. The delay circuit 304 a includes k flip-flop circuits 501 a to 501 k and k + 1 input terminals, and is configured by a multiplexer 502 that is selectively controlled by a delay control signal output from the delay control circuit 309. . _Assuming that one clock of the sampling clock CLK _BB is T _CLKBB , the delay circuit 304a has a delay of time T _CLKBB from 0 to k × T _CLKBB , that is, an I digital baseband signal of any sampling clock CLK _BB . It is possible to delay by an integer (0 to k) times.

That is, the delay circuit generates a delayed digital signal obtained by delaying the digital baseband input signal by an integer multiple of the signal rate period of the digital baseband input signal according to the delay amount. The delay circuit includes a number of flip-flop circuits equal to an integer.
For example, the delay amounts of the input data of the DDRRCs 301a to 301n illustrated in FIG. 4 are set as follows by the delay control signal output from the delay control circuit 309. In the following formula, “a” is an arbitrary natural number.

D1 = 0
D2 = T _{CLKBB xa}
D3 = 2 × T _CLKBB × a...
DN = (N−1) × T _CLKBB × a

  Further, the delay amounts of the input data of the DDRCs 308a to 308m shown in FIG. 1 are set as follows by the delay control signal output from the delay control circuit 309, for example. In the following formula, “a” is an arbitrary natural number.

D1 = 0
D2 = T _{CLKBB xa}
D3 = 2 × T _CLKBB × a...
DM = (M−1) × T _CLKBB × a

  Next, quantization noise generated in the direct RF modulation transmitter shown in FIG. 4 will be described. The quantization noise generated by the digital / analog conversion in the DDRRCs 301a to 301n shown in FIG. 4 is expressed by the following equation (4) starting from the transmission carrier frequency at the higher frequency side than the transmission carrier frequency in the output of the direct RF modulation transmitter. Receive the indicated filtering effect. On the lower frequency side than the transmission carrier frequency, a filtering effect is applied to the low frequency side by turning back the transmission characteristic on the high frequency side starting from the transmission carrier frequency.

Equation (4) expresses this filtering effect using a Z function with the sampling clock frequency fs as a reference. In Expression (4), a is a natural number obtained by normalizing the delay amount in units of the sampling clock (T _CLKBB ), and n is an integer such that n = N−1 with respect to the number N of DDRCs 301a to 301n shown in FIG. The delays applied to the N DDRCs are 0, T _CLKBB × a, 2 × T _CLKBB × a,..., N × T _CLKBB × a for the 1st to Nth DDRRCs, respectively. Note that f _off is a detuning frequency from the transmission carrier frequency.

The above equation (4) can also be applied to DDRCs 308a to 308m by setting n to n = M-1.
The filtering effect is expressed by the equation (4) when the frequency of the differential local signals TxLoI ⁺ , TxLoI ⁻ , TxLoQ ⁺ , TxLoQ ⁻ is zero in the direct RF modulation transmitter shown in FIG. If you think about it, the explanation will be easy and clear. In this case, the DRCs 302a to 302n and the DRCs 306a to 306m are simple digital / analog converters that do not perform frequency conversion. The digital / analog conversion is an equivalent conversion with a gain of 1, and when attention is paid to the I digital baseband signal, an equivalent functional characteristic expressed using a transfer function of Z conversion can be considered as shown in FIG.

FIG. 7 is a diagram showing equivalent functional characteristics in Example 1 of the present invention. This is a generally well-known FIR (Finite Impulse Response) filter. From this, it can be seen that the quantization noise is directly suppressed by the RF modulation transmitter as shown in Equation (4). .
FIG. 8 is a diagram exemplifying gain characteristics that are affected by quantization noise in Embodiment 1 of the present invention. As an example, the quantization noise when fs = 1 Hz, local frequency = 100 Hz, N = 2, and a = 1 is shown. It is a figure which shows the gain characteristic which receives. The vertical axis in FIG. 8 indicates the gain of the direct RF modulation transmitter, and the horizontal axis indicates the frequency of the signal. The frequency at which the gain shown on the vertical axis is minimized is generally called a notch frequency. In the vicinity of the notch frequency, the quantization noise calculated from the number of bits of digital / analog conversion is largely filtered, so that low quantization noise can be realized.

The notch frequency can be arbitrarily set by a combination of the number N of DDRC stages and the sampling frequency fs. In the present embodiment, the number of bits for digital / analog conversion required for each DRC can be suppressed by adjusting the notch frequency for a frequency band in which low noise is required in wireless communication.
Further, in the direct RF modulation transmitter shown in FIG. 4, the number N of DRCs 302a to 302n and the number M of DRCs 306a to 306m are the same (for convenience of explanation, it is assumed that both DRCs 302a to 302n and DRCs 306a to 306m are N. The delay control circuit 309 sets the same delay amount for the i-th DRC (i is a number not less than 1 and not more than N) of the DRCs 302a to 302n and the i-th DRC of the DRCs 306a to 306m. And

At this time, the filtering characteristics of the filtering received by the quantization noise generated by the digital / analog conversion of the I digital baseband signal and the quantization noise generated by the digital / analog conversion of the Q digital baseband signal are the same. At this time, it can also be seen from the nature of the FIR filter that the filtering effect at a predetermined detuning frequency is the highest.
Next, the area of the entire current source of the direct RF modulator circuit using the conventional DRC and the area of the entire current source of the direct RF modulator composed of the DRC and the delay control circuit to which the present invention is applied are specifically described. Compare using various numerical values.

  Let S0 be the total area of a 10-bit DRC current source in a conventional direct modulation RF transmitter. If the number of bits is increased by one bit to reduce quantization noise, the total area of the current source is 4 × S0. When the number of bits is increased by 2 bits, the area of the entire current source is 16 times 16 × S0. The noise reduction effect by these becomes 6 dB and 12 dB, respectively, from the above-described equation (2).

On the other hand, when the present invention is applied and two 10-bit DRCs are arranged in parallel, that is, when the frequency is partially reduced by setting N = M = 2, the total area of the current source is the original. 2 × S0, which is twice the area S0, is sufficient. Even when N = M = 4, it is only four times the original area S0.
According to the first embodiment, a low-noise transmitter can be realized with a smaller area than that in the above-described example in which the conventional direct modulation RF transmitter is configured by simply adding bits. In the case of the first embodiment, since noise is reduced by noise filtering, the entire noise floor cannot be reduced. However, as described above, the communication system is strongly required to reduce noise in a predetermined frequency band. For this reason, if the sampling frequency is adjusted using Equation (4) according to the frequency band in which noise reduction is required, the number N of DRCs can be suppressed to a relatively small number.

In many cases, as described above, the noise near the target band (frequency band in which noise reduction is required) is significantly reduced by the notches as shown in FIG. 8 even when compared to the above-mentioned 6 dB and 12 dB. It becomes possible. From the above, according to the present embodiment, it is possible to realize a direct RF modulation transmitter having a smaller area and lower noise than the conventional method.
By the way, in many cases, it is necessary for the transmitter to variably control the transmitter output power over a wide range. The transmitter output power changes from moment to moment according to system requirements, but the important point here is to keep the power consumption at the maximum transmitter output power low and to keep the time average power consumption low. That is. On the other hand, generally in a mobile terminal, the required transmitter output noise is the absolute value of the noise. This is because the relative value between the desired signal level and noise floor is large when the transmitter output power is large, and the relative value between the desired signal level and noise floor is small when the transmitter output power is small. Means a small value. This is because the relative value of the desired signal level and the noise level of the quantization noise generated inside the transmitter is constant, as shown in equation (2). For this reason, the most severe condition in the quantization noise design of the transmitter is when the transmitter output is maximum. Therefore, it can be said that the quantization noise filtering that can be performed at an arbitrary detuning frequency in the first embodiment is particularly necessary in a state of a large transmitter output power.

Next, the transmission output power control method of the direct RF modulation transmitter of the present invention will be described by taking an example in which three DRCs are arranged in parallel.
In the second embodiment, a power control circuit 902 and an operation / non-operation control circuit 904 are added to the first embodiment described above.
FIG. 9 is a circuit configuration diagram for explaining the embodiment 2 of the direct RF modulation transmitter according to the present invention, and shows a case where the direct RF modulation transmitter is set to N = M = 3.

  The direct RF modulation transmitter according to the second embodiment is input to a plurality of direct RF converters (Direct RF Converters) 302a to 302c, 306a to 306c connected in parallel, and the plurality of direct RF converters. A plurality of delay circuits 304a to 304c and 307a to 307c that delay the digital baseband input signals IBBData and QBBData, and an output matching circuit (adder circuit) 305 that adds the output signals output from the plurality of direct RF converters. I have.

  Furthermore, a power control circuit 902 that individually controls output power of the plurality of direct RF converters, and an operation / non-operation control circuit 904 that individually controls operation / non-operation states of the plurality of direct RF converters, The direct RF converter inputs an RF signal together with a digital baseband input signal, modulates the RF signal with the digital baseband input signal, and outputs it as an output signal.

Further, DRC 302a and DRC 306a are connected to a divide-by-2 303a, and DRCs 302b, 303c, 306b, 306c are connected to a divide-by-2 divider 303b. A common local RF signal Lo _{in +} and a transmission local RF signal Lo _in− which is a phase-inverted signal are externally supplied to the two frequency dividers 303a and 303b. The DRCs 302a, 302b, 302c, 306a, 306b, and 306c can variably control their output currents. For example, in the DRC of FIG. 2, the current sources 200, 201,. By changing the unit current I, the output current can be increased while maintaining the relationship of the current ratio between bits.

  The transmitter output power is set by a transmitter output power setting signal 901 from the outside. It is desirable for the transmitter output power setting signal 901 and the transmitter output power to have a constant slope. The transmitter output power setting signal 901 is input to the power control circuit 902 in FIG. 9, and the power control circuit 902 generates power control signals Ca, Cb, and Cc that are input to the DRCs 302a to 302c and 306a to 306c. The power control circuit 902 is realized by a logical table, for example.

  FIG. 10 is a relationship diagram between the transmitter output power setting signal and the transmitter output power of the direct RF modulation transmitter shown in FIG. For simplicity of explanation, the transmitter output power is divided into three areas of large / medium / small according to the magnitude of the transmitter output power. When the total differential current of the paired DRCs 301a and 306a is Ia, the total differential current of 302b and 306b is Ib, and the total differential current of 302c and 306c is Ic, the relationship between the power control signals Ca, Cb, and Cc is It is shown by Formula (5). Here, A is a conversion gain, which is a fixed value, and the sum of differential output currents from all DRCs is I.

  Transmitter output power is given by equation (6). For simplicity, the impedance including the output matching 305 is standardized as 1.

As described above, it is desirable that the slope is constant over the entire range of the transmitter output power setting signal 901. In the direct RF modulation transmitter of FIG. 9, the power control circuit 902 provides power setting signals Ca, Cb, Cc so as to realize the relationship of FIG. The power setting signals Ca, Cb, and Cc may be the same control (Ca = Cb = Cc) in the entire range of the transmitter output power setting signal 901 or may be different controls.
When the power setting signals Ca, Cb, and Cc are controlled according to, for example, Table 1 according to the three areas of the transmitter output power, average power consumption can be reduced. The reason will be described below.

  FIG. 11 is an explanatory diagram of the transmitter output power control of the direct RF modulation Soshinki shown in FIG. 9 and shows an example of the relationship in Table 1. Here, the filtering effect expressed by Equation (4) appears only in the region where the transmitter output power is large, and the filtering effect gradually decreases from the middle region to the small region of the transmitter output power, and eventually disappears. As described above, in a mobile terminal, in general, the required transmitter output noise is the absolute value of the noise, while the noise floor due to the quantization noise expressed by Equation (2) depends on the transmitter output power level. The relative value of the desired wave signal level and the noise level is constant. Therefore, it does not matter that the filtering effect is reduced or disappeared from the middle region to the small region of the transmitter output power. Therefore, the transmitter output power control method shown in Table 1 and FIG. 11 is established.

  Here, when the transmitter output power is small, the power setting signals Cb = 0 and Cc = 0, so that the differential current flows Ib and Ic of the DRCs 302b, 302c, 306b, and 306c are zero. Therefore, the circuits that need to be operated are only the DDRRCs 301a and 308a, the frequency divider 303a, the output matching 305, the delay control circuit 309, and the power control circuit 902 in FIG. 9, and the other circuits operate. There is no need, and the power consumed here is wasted. Therefore, the operation / non-operation of the circuit in the non-operation state in FIG. 9 is controlled by the operation / non-operation control circuit 904, and the circuit that does not require operation is deactivated when the transmitter output power is small. It becomes possible to reduce power consumption.

As described above, since the transmitter output power changes from moment to moment, the operation / non-operation control of the circuit in combination with the transmitter output power should keep the average power consumption of the transmitter low. Make it possible.
It should be noted that the technical scope of the present invention described above is not limited to the illustrated and illustrated exemplary embodiments, and includes all the embodiments that provide the same effects as those intended by the present invention. Contains. Further, the technical scope of the present invention is not limited to the combinations of features of the invention defined by the claims, but any desired combination of specific features among all the disclosed features. Is included.

  9 illustrates the case where the direct RF modulation transmitter is set to N = M = 3, the first direct RF converter includes N direct RF converters as in the case of FIG. And a second block including M direct RF converters may be provided.

  The direct RF modulation transmitter according to the present invention reduces the circuit area by reducing the number of bits for digital / analog conversion and realizes low noise. Suitable for small devices such as telephones.

301a-301n, 308a-308m DDRC
302a-302n, 306a-306m DRC
303, 303a, 303b Dividers 304a to 304n, 307a to 307m Delay circuit 305 Output matching circuit (adder circuit)
309 Delay control circuit 501a to 501k Flip-flop circuit 502 Multiplexer 902 Power control circuit 904 Operation / non-operation control circuit

Claims (8)

A plurality of direct RF converters connected in parallel;
A plurality of delay circuits for delaying digital baseband input signals input to the plurality of direct RF converters;
An addition circuit for adding output signals output from the plurality of direct RF converters;
A power control circuit for individually controlling the output power of the plurality of direct RF converters;
An operation / non-operation control circuit for individually controlling the operation / non-operation state of the plurality of direct RF converters;
The direct RF converter inputs an RF signal together with the digital baseband input signal, modulates the RF signal by the digital baseband input signal, and outputs the modulated RF signal as the output signal. .   The direct RF modulation transmitter according to claim 1, wherein the plurality of delay circuits are connected to the plurality of direct RF converters on a one-to-one basis. The plurality of direct RF converters includes a first block including N number of the direct RF converters and a second block including M number of the direct RF converters,
The direct RF converter included in the first block inputs a first RF signal together with an in-phase digital baseband input signal, modulates the first RF signal with the in-phase digital baseband input signal, and outputs a first RF signal. 1 as an output signal,
The direct RF converter included in the second block inputs a quadrature digital baseband input signal and a second RF signal having a phase difference of 90 degrees from the first RF signal, and the quadrature digital baseband input. Modulating the second RF signal with a signal and outputting it as a second output signal;
The adder circuit includes the first output signal output from each of the N (N is a natural number) of the direct RF converters included in the first block and the M blocks included in the second block. 2. The direct RF modulation transmitter according to claim 1, wherein the second output signal output from each of the direct RF converters (M is a natural number) is added. 3.   The direct RF modulation transmitter according to claim 1, further comprising a delay control circuit that sets a delay amount of the digital baseband input signal for each of the plurality of delay circuits.   The delay control circuit sets a delay amount by which each of the delay circuits connected to the N direct RF converters included in the first block delays the in-phase digital baseband signal, and 5. The direct RF according to claim 4, wherein each of the delay circuits connected to the M direct RF converters included in the block sets a delay amount for delaying the orthogonal digital baseband signal. Modulation transmitter. Both the first block and the second block comprise the N direct RF converters (M = N),
The delay control circuit includes an i-th direct RF converter (i is a natural number of 1 or more and N or less) of the direct RF converter included in the first block, and the second block includes the direct RF converter. 6. The direct RF modulation transmitter according to claim 5, wherein the same delay amount is set for the i-th direct RF converter of the direct RF converter.   The delay circuit generates a delayed digital signal obtained by delaying the digital baseband input signal by an integer multiple of a signal rate period of the digital baseband input signal according to a delay amount. The direct RF modulation transmitter according to claim 6.   8. The direct RF modulation transmitter of claim 7, wherein the delay circuit includes a number of flip-flop circuits equal to the integer.

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