JP2014041977A - Electronic component and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component capable of inhibiting disconnection of a conductor pattern at an outer peripheral part of a semiconductor element, and to provide a manufacturing method of the electronic component.SOLUTION: An electronic component 100 includes: multiple interlayer resin insulation layers 50; a wiring board 20 which has conductor patterns 58 formed on the interlayer resin insulation layers 50 and includes a first surface F and a second surface S at the opposite side of the first surface F; first bumps 76 for mounting semiconductor elements which are respectively formed on the conductive patterns of a first surface side outermost layer of the interlayer resin insulation layers 50; second bumps 77 for external substrate connection which are formed on the conductor patterns on a second surface side outermost layer of the interlayer resin insulation layers 50; and semiconductor elements 90A, 90B mounted on the wiring board through the first bumps. The semiconductor elements and a peripheral part of the wiring board are coated by a metal layer 97.

Description

The present invention relates to an electronic component comprising a wiring board having a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, and a semiconductor element mounted on the wiring board, and its manufacture It is about the method.

Patent Document 1 discloses an electronic component including a coreless wiring board and a semiconductor element mounted on the upper surface of the wiring board. Usually, such an electronic component has an underfill resin filled between the wiring board and the semiconductor element and a sealing resin for sealing the semiconductor element.

JP 2010-118635 A

As a result of intensive studies, the present inventors have found that the above-described electronic components are susceptible to disconnection of the inner layer conductor pattern by receiving a thermal history. Details will be described below.
FIG. 7 is an explanatory view showing a result of simulating thermal expansion and stress generated in the above-described electronic component. The electronic component includes a wiring board 530 having resin insulating layers 550, 650, 750 and conductor patterns 534, 558, 658, and a semiconductor element 590 mounted on the wiring board 530 via solder bumps 576. An underfill resin 598 is filled between the wiring board 530 and the semiconductor element 590 and on the side of the semiconductor element. The semiconductor element is sealed with a sealing resin 594.

7A1 and 7A2 illustrate a state in which heat of about 260 ° C. is applied to the electronic component, and FIGS. 7B1 and 7B2 illustrate the electronic component at room temperature.
With respect to the wiring board constituting such an electronic component, when heat is applied, the region R1 immediately below the semiconductor element is constrained by the semiconductor element via the bumps, and thus normally expands in a substantially horizontal direction (FIG. 7). (See (A1)). On the other hand, in the region R2 other than directly below the semiconductor element, the restraint by the semiconductor element is relatively weak, and the underfill resin expands, and is easily swelled by the stress in the arrow Y direction generated at that time.

Thereby, thermal stress is likely to occur in the vicinity of the virtual plane K including the side surface of the semiconductor element. As a result, the conductor pattern 558 located near the virtual plane K (the outer peripheral portion of the semiconductor element) is easily disconnected or peeled off.
Even when the electronic component is returned to room temperature from such a heated state, thermal stress is likely to occur near the virtual plane K as the underfill resin contracts, and the same problem is considered to occur (FIG. 7 (B1)). (See (B2)).

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic component capable of suppressing disconnection of a conductor pattern at an outer peripheral portion of a semiconductor element and a method for manufacturing the same. Is to provide.

The electronic component according to claim 1 has a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, and the first surface and the second surface opposite to the first surface. A first bump for mounting a semiconductor element formed on a conductor pattern on the first surface side outermost interlayer resin insulation layer, and a second surface side outermost interlayer resin insulation layer. An electronic component comprising: a second bump for connecting an external substrate formed on an upper conductive pattern; and a semiconductor element mounted on the wiring board via the first bump, wherein the semiconductor element and the semiconductor element A technical feature is that the peripheral edge of the wiring board is covered with a metal layer.

In the electronic component according to the first aspect, the peripheral portion of the wiring board (the outer peripheral portion of the semiconductor element) is covered with the metal layer. In the metal layer having a smaller thermal expansion coefficient than the underfill resin in the prior art, it is possible to reduce the influence on the wiring board, in particular, the conductor pattern inside the wiring board even when a thermal history occurs. . For this reason, it is considered that the conductor pattern is less likely to be disconnected in the region immediately below the side surface of the semiconductor element.
In addition, since the metal layer made of a metal having high thermal conductivity is provided on the upper layer of the semiconductor element, the heat dissipation of the heat generated in the semiconductor element can be improved.

It is a manufacturing-process figure of the electronic component of this invention. It is a manufacturing-process figure of the electronic component of this invention. It is a manufacturing-process figure of the electronic component of this invention. It is a manufacturing-process figure of the electronic component of this invention. It is a manufacturing-process figure of the electronic component of this invention. It is sectional drawing of the electronic component of this invention. It is explanatory drawing which shows the result of having simulated the thermal expansion and stress which arise in an electronic component.

FIG. 6 is a cross-sectional view of the electronic component 100 according to the embodiment.
The electronic component 100 includes a wiring board 20 in which a conductor pattern and a resin insulating layer are laminated, a first semiconductor element (logic chip) 90A and a second semiconductor element (memory chip) 90B mounted on the wiring board 20. It consists of. The wiring board 20 has a first surface F and a second surface S opposite to the first surface, and is formed on the first resin insulating layer 50 and the first resin insulating layer 50. Conductive pattern 58, first resin insulating layer 50, second resin insulating layer 150 formed on first conductive pattern 58, and second conductive pattern 158 formed on second resin insulating layer 150. Have. A solder resist layer 70 is formed on the second resin insulating layer 150. In addition, from the viewpoint of reducing the height of the electronic component 100, the thickness of the wiring board 20 is preferably about 100 μm.

The pad 60P and the first conductor pattern 58 are connected via a first via conductor 60 formed in the first resin insulation layer 50. The first conductor pattern 58 and the second conductor pattern 158 are connected via a second via conductor 160 formed in the second resin insulation layer 150. Solder bumps 76 are formed on the second conductor pattern 158 through the openings 71 of the solder resist layer 70. The solder bumps 76 connect the pads 92 of the first semiconductor element 90A and the second semiconductor element 90B. A solder bump 77 is formed on the pad 60 </ b> P at the bottom of the first via conductor 60.
The outer periphery of the first semiconductor element 90A and the outer periphery of the second semiconductor element 90B are filled with a sealing resin 94. The sealing resin 94 is also filled between the first semiconductor element 90 </ b> A and the wiring board 20 and between the second semiconductor element 90 </ b> B and the wiring board 20. The upper surface of the first semiconductor element 90 </ b> A and the upper surface of the second semiconductor element 90 </ b> B are not covered with the sealing resin 94 and are exposed from the sealing resin 94. The upper surface of the first semiconductor element 90A and the upper surface of the second semiconductor element 90B exposed from the sealing resin 94 are covered with a metal layer 97 described later.

The first resin insulation layer 50 and the second resin insulation layer 150 are a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added to a part of the thermosetting resin, a thermoplastic resin, or these resins. Is a layer made of a resin composite or the like. The sealing resin 94 is made of an epoxy resin containing an inorganic filler such as silica or alumina having a maximum diameter of less than 30 μm and an average particle diameter of 5 μm. Since the sealing resin 94 is made of an epoxy resin, it is easy to adjust the thermal expansion coefficient by adjusting the amount of the inorganic filler.

A metal layer 97 is provided so as to cover the upper surfaces of the semiconductor elements 90 </ b> A and 90 </ b> B, the sealing resin 94, and the peripheral edge of the wiring board 20. The metal layer 97 is formed of a sputter layer 96A provided on the upper surfaces of the semiconductor elements 90A and 90B, the sealing resin 94, and the peripheral edge of the wiring board 20, and an electrolytic plating layer 96B on the sputter film 96A. Yes. The sputter layer 96A and the electrolytic plating layer 96B are made of copper.

In the electronic component 100, the peripheral portion of the wiring board 20 (the outer peripheral portions of the semiconductor elements 90 </ b> A and 90 </ b> B) is covered with the metal layer 97. In the metal layer 97 having a smaller thermal expansion coefficient than the underfill resin in the prior art, even when a thermal history occurs, the influence on the wiring board 20, particularly the conductor pattern inside the wiring board 20, can be reduced. It becomes possible. That is, the peripheral portion of the wiring board 20 is not deformed due to the thermal expansion (thermal contraction) of the metal layer 97, and the reliability of the conductor pattern can be ensured. For this reason, it is considered that the conductor pattern is hardly disconnected in the region immediately below the side surfaces of the semiconductor elements 90A and 90B.
Furthermore, since the metal layer 97 made of a metal having high thermal conductivity is provided on the upper layer of the semiconductor element, it is possible to improve the heat dissipation of the heat generated in the semiconductor element.

The manufacturing method of the electronic component of embodiment is shown by FIGS.
(1) First, a glass plate 30 having a thickness of about 1.1 mm is prepared (FIG. 1A).
The glass plate has a CTE of about 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the mounted silicon IC chip is small. It is desirable that the transmittance is 90% or more.

(2) A release layer 32 mainly made of a thermoplastic polyimide resin is provided on the glass plate 30 (FIG. 1B).

(3) The first insulating layer 50 is formed on the release layer 32 (FIG. 1C).

(4) An electrode body opening 51 that penetrates the first insulating layer 50 and reaches the release layer 32 is provided by a CO2 gas laser (see FIG. 1D).

(5) A conductor layer 52 made of TiN, Ti, and Cu is formed on the first insulating layer 50 by sputtering (FIG. 2A).

(6) A commercially available photosensitive dry film is affixed on the conductor layer 52, and after the photomask film is placed and exposed, it is developed with sodium carbonate to provide a plating resist 54 having a thickness of about 15 μm. (FIG. 2 (B)).

(7) Using the conductor layer 52 as a power feeding layer, electrolytic plating is performed to form an electrolytic plating film 56 (FIG. 2C).

(8) The plating resist 54 is peeled and removed. Then, the conductor layer 52 under the peeled plating resist is removed, and the first conductor pattern 58 and the first via conductor 60 including the conductor layer 52 and the electrolytic plating film 56 are formed (FIG. 2D).

(9) In the same manner as (3) to (8) above, the second resin insulation layer 150, the second conductor pattern 158, and the second via conductor 160 are formed on the first resin insulation layer 50 and the first conductor pattern 58. (FIG. 3A, FIG. 3B, FIG. 3C).

(10) A solder resist layer 70 having an opening 71 is formed (FIG. 3D).

(11) By forming solder bumps 76 in the openings 71 of the solder resist layer 70, the intermediate 100α is manufactured (FIG. 3E). This intermediate 100α is formed of a glass plate 30 and a wiring board 20 formed on the glass plate 30.

(12) The first semiconductor element 90A and the second semiconductor element 90B are mounted on the intermediate body 100α via the solder bumps 76 (FIG. 4A). At this time, since the glass plate 30 has a thermal expansion coefficient close to that of the first semiconductor element 90A and the second semiconductor element 90B, the stress applied to the wiring board 20 is reduced.

(13) The sealing resin 94 is filled between the first semiconductor element 90A, the second semiconductor element 90B, and the wiring board 20 (FIG. 4B). At this time, after providing the sealing resin 94 so as to cover the first semiconductor element 90A and the second semiconductor element 90B, the upper surface of the first semiconductor element 90A and the upper surface of the second semiconductor element 90B are exposed. The sealing resin 94 is polished.

(14) The SiN / Cu layer 96A, that is, the insulating ceramic film (SiN) and the seed film for electrolytic plating are sputtered on the upper surfaces of the semiconductor elements 90A and 90B, the sealing resin 94, and the peripheral edge of the wiring board 20. (Cu) is formed (FIG. 4C).

(15) On the first semiconductor element 90A, the second semiconductor element 90B, and the wiring board 20 provided with the SiN / Cu layer 96A, electrolytic copper plating is performed using the Cu layer as a power feeding layer. Thereby, the electrolytic copper plating layer 96B is provided on the sputter layer 96A. That is, a metal layer 97 is provided to cover the upper surfaces of the semiconductor elements 90A and 90B, the sealing resin 94, and the peripheral edge of the wiring board 20 (FIG. 5A).
Next, an aluminum heat sink is attached to the upper surface of the metal layer 97 (not shown). When further strength is required, the metal layer may be formed by Ni plating.

(16) A 308 nm laser beam is transmitted through the glass plate 30 and irradiated to the release layer 32, and the release layer 32 is softened. And the glass plate 30 is slid with respect to the wiring board 20, and the glass plate 30 peels (FIG.5 (B)).

(17) The peeling layer 32 is removed by ashing, and the pad 60P constituted by the bottom of the via conductor 60 is exposed (FIG. 5C).

(18) The solder bumps 77 are formed on the pads 60P, and the electronic component 100 is completed (FIG. 6).

(19) The electronic component 100 is mounted on the printed wiring board 200 through the solder bumps 77 by reflow (not shown).

In the above-described embodiment, an example in which two semiconductor elements are mounted on an electronic component has been described. However, in the configuration of the present invention, three or more semiconductor elements are mounted even when one semiconductor element is mounted. Even in such a case, the effect of preventing disconnection of the conductor pattern can be achieved.

DESCRIPTION OF SYMBOLS 100 Electronic component 20 Wiring board 50 1st resin insulation layer 58 1st conductor pattern 60 1st via conductor 77 Solder bump 90A, 90B Semiconductor element 96A Sputtered film 96B Electroplating layer 97 Metal layer

Claims (9)

A wiring board having a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, the wiring board comprising a first surface and a second surface opposite to the first surface; First bumps for mounting semiconductor elements formed on the conductor pattern on the interlayer resin insulation layer on the outermost layer on the first surface side, and formed on the conductor pattern on the interlayer resin insulation layer on the outermost layer on the second surface side. A second bump for connecting to an external substrate, a semiconductor element mounted on the wiring board via the first bump,
An electronic component comprising:
The electronic device according to claim 1, wherein peripheral portions of the semiconductor element and the wiring board are covered with a metal layer. The electronic component of claim 1, wherein:
The upper surface of the semiconductor element is in contact with the metal layer. The electronic component of claim 1, wherein:
The side surface of the semiconductor element is covered with a sealing resin. The electronic component of claim 3, wherein:
The metal layer covers the sealing resin. The electronic component of claim 1, wherein:
The metal layer includes a plating layer. The electronic component of claim 3, wherein:
The metal layer includes a sputter layer provided on the semiconductor element, the sealing resin, and a peripheral portion of the wiring board, and an electroplating layer on the sputter film. The electronic component according to claim 6, wherein:
The electrolytic plating layer is made of copper. The electronic component of claim 1, wherein:
The wiring board has a thickness of 100 μm or less. A wiring board having a plurality of interlayer resin insulation layers and a conductor pattern formed on the interlayer resin insulation layer, the wiring board comprising a first surface and a second surface opposite to the first surface; First bumps for mounting semiconductor elements formed on the conductor pattern on the interlayer resin insulation layer on the outermost layer on the first surface side, and formed on the conductor pattern on the interlayer resin insulation layer on the outermost layer on the second surface side. A second bump for connecting to an external substrate, a semiconductor element mounted on the wiring board via the first bump,
A method of manufacturing an electronic component comprising:
A method of manufacturing an electronic component, wherein a peripheral portion of the semiconductor element and the wiring board is covered with a metal layer.

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