JP2014041968A - Photovoltaic device and method of manufacturing the same - Google Patents

Abstract

Photovoltaic device excellent in photoelectric conversion efficiency and current manufacturing method in which current leakage at substrate end face is prevented and output reduction due to collection loss of optical carrier generated in substrate peripheral region is suppressed To get.
On a first main surface of a crystalline semiconductor substrate, a first amorphous semiconductor thin film layer having a conductivity type opposite to that of the substrate, a first transparent electrode layer, and a first collector electrode are provided in this order. And a second amorphous semiconductor thin film layer having the same conductivity type as the substrate, a second transparent electrode layer, and a second collector electrode in this order on the second main surface of the substrate, The second transparent electrode layer is formed only in a region smaller than the formation region of the first amorphous semiconductor thin film layer in the surface direction of the substrate, and the second transparent electrode layer is formed from the formation region of the second amorphous semiconductor thin film layer in the surface direction of the substrate. An impurity doping layer having a conductivity type opposite to that of the substrate is formed in a region including at least a region where the first transparent electrode layer is not formed in the surface direction of the substrate in the first main surface. ing.
[Selection] Figure 1-1

Description

  The present invention relates to a photovoltaic device and a manufacturing method thereof, and more particularly, a photovoltaic device in which an amorphous semiconductor thin film having a conductivity type opposite to that of the crystalline semiconductor substrate is formed on the crystalline semiconductor substrate. And a manufacturing method thereof.

  Among photovoltaic devices using a crystalline silicon substrate, an amorphous semiconductor thin film having a conductivity type opposite to that of the substrate is formed on one main surface of a crystalline semiconductor substrate such as single crystal silicon and then on the other main surface. It is known that a photovoltaic device in which an amorphous semiconductor thin film having the same conductivity type as that of a substrate has a particularly high photoelectric conversion performance. Furthermore, it is known that the photoelectric conversion performance of a photovoltaic device is improved by forming an intrinsic amorphous semiconductor thin film at each interface between the semiconductor substrate and the amorphous semiconductor thin film on each main surface. Yes.

  In the photovoltaic device having such a structure, light is incident on the inside of a crystalline semiconductor substrate which is a main light absorption layer through an amorphous semiconductor thin film formed on at least one main surface. At this time, in order to suppress light absorption loss due to the amorphous semiconductor thin film formed on the light incident surface side to the maximum, the formation thickness needs to be reduced to about 10 nm. Further, it is desirable that the thickness of the amorphous semiconductor thin film formed on both main surfaces be approximately the same in order to minimize structural distortion. That is, an amorphous semiconductor thin film of about 10 nm at most is formed on both main surfaces of the crystalline semiconductor substrate, and it is impossible to efficiently collect generated optical carriers as they are. .

  Therefore, in order to reduce the effective sheet resistance value, it is common to form transparent electrode layers having the same thickness on the amorphous semiconductor thin films formed on both main surfaces. The transparent electrode layer is usually formed by sputtering or the like. However, when the transparent electrode layer is formed without protecting the end face of the crystalline semiconductor substrate, the transparent electrode layer wraps around the end face of the crystalline semiconductor substrate. The transparent electrode layer on the first main surface side is in direct contact with the end surface of the crystalline semiconductor substrate, or the transparent electrode layer on the first main surface side and the transparent electrode layer on the second main surface side are in contact through the end surface. By doing so, a path through which current leaks occurs, which causes the photoelectric conversion performance of the photovoltaic device to deteriorate.

  In order to solve such a problem, Patent Document 1 describes a structure in which a transparent electrode is formed only in a central region of the substrate excluding the vicinity of the substrate end surface to prevent current leakage through the substrate end surface.

Japanese Patent No. 4194379

  However, in the structure described in Patent Document 1, photogenerated carriers generated in the peripheral region of the end portion of the crystalline semiconductor in the photovoltaic device are collected through a region where the transparent electrode is not formed. In particular, in the photogenerated carrier collection on the first main surface side where an amorphous semiconductor film having a conductivity type opposite to that of the crystalline semiconductor is formed, the sheet resistance in the region where the transparent electrode is not formed is larger than that in the region where the transparent electrode is formed. 1000 times higher. For this reason, there existed a problem that a short circuit current value and a fill factor will be reduced greatly, and it will become a factor which restricts the photoelectric conversion output of a photovoltaic device.

  The present invention has been made in view of the above, and is capable of preventing current leakage at the substrate end face and suppressing output decrease due to collection loss of optical carriers generated in the peripheral region of the substrate end. It is an object of the present invention to obtain a photovoltaic device having excellent efficiency and a method for manufacturing the photovoltaic device.

  In order to solve the above-mentioned problems and achieve the object, a photovoltaic device according to the present invention has a first conductivity type opposite to that of the crystalline semiconductor substrate on the first main surface of the crystalline semiconductor substrate. A first electrode having an amorphous semiconductor thin film layer, a first transparent electrode layer, and a first collector electrode in this order, and having the same conductivity type as the crystalline semiconductor substrate on the second main surface of the crystalline semiconductor substrate. A second amorphous semiconductor thin film layer, a second transparent electrode layer, and a second collector electrode in this order, and the first transparent electrode layer is arranged in the plane direction of the crystalline semiconductor substrate. The second transparent electrode layer is formed only in a region smaller than the region where the second amorphous semiconductor thin film layer is formed in the plane direction of the crystalline semiconductor substrate. Of the first main surface in the plane direction of the crystalline semiconductor substrate. The region encompassing free area of at least the first transparent electrode layer you are, the impurity-doped layer having the crystalline semiconductor substrate and the opposite conductivity type is formed, characterized by.

  According to the present invention, there is provided a photovoltaic device excellent in photoelectric conversion efficiency, in which current leakage at the substrate end face is prevented and output decrease due to collection loss of optical carriers generated in the peripheral region of the substrate end is suppressed. The effect is obtained.

FIG. 1-1 is a schematic cross-sectional view illustrating the configuration of the photovoltaic device according to the first embodiment of the present invention. FIG. 1-2 is a schematic plan view illustrating the configuration of the first main surface side in the photovoltaic device according to the first embodiment of the present invention. FIG. 1-3 is a schematic plan view showing the configuration of the second main surface side in the photovoltaic device according to the first embodiment of the present invention. FIGS. 2-1 is a schematic cross section which shows the process of the manufacturing method of the photovoltaic apparatus concerning Embodiment 1 of this invention. FIGS. FIG. 2-2 is a schematic cross-sectional view illustrating a process of the method for manufacturing a photovoltaic device according to the first embodiment of the present invention. FIGS. 2-3 is a schematic cross section which shows the process of the manufacturing method of the photovoltaic apparatus concerning Embodiment 1 of this invention. FIGS. FIGS. 2-4 is a schematic cross section which shows the process of the manufacturing method of the photovoltaic apparatus concerning Embodiment 1 of this invention. FIGS. FIGS. 2-5 is a schematic cross section which shows the process of the manufacturing method of the photovoltaic apparatus concerning Embodiment 1 of this invention. FIGS. 2-6 is a schematic cross-sectional view illustrating a process of the method for manufacturing the photovoltaic device according to the first embodiment of the present invention. FIG. 3 is a flowchart showing the steps of the method for manufacturing the photovoltaic device according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the configuration of the photovoltaic device according to the second embodiment of the present invention. FIGS. 5-1 is a schematic cross section which shows the manufacturing method of the photovoltaic apparatus concerning Embodiment 2 of this invention. FIGS. FIG. 5-2 is a schematic cross-sectional view illustrating the method for manufacturing the photovoltaic device according to the second embodiment of the present invention. FIGS. 5-3 is a schematic cross section which shows the manufacturing method of the photovoltaic apparatus concerning Embodiment 2 of this invention. FIGS. FIGS. 5-4 is a schematic cross section which shows the manufacturing method of the photovoltaic apparatus concerning Embodiment 2 of this invention. FIGS. 5-5 is a schematic cross-sectional view illustrating the method for manufacturing the photovoltaic device according to the second embodiment of the present invention. FIGS. 5-6 is a schematic cross section which shows the manufacturing method of the photovoltaic apparatus concerning Embodiment 2 of this invention. FIGS. FIGS. 5-7 is a schematic cross section which shows the manufacturing method of the photovoltaic apparatus concerning Embodiment 2 of this invention. FIGS.

  Embodiments of a photovoltaic device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.

Embodiment 1 FIG.
FIG. 1-1 is a schematic cross-sectional view illustrating a configuration of a heterojunction solar battery cell (hereinafter sometimes referred to as a solar battery cell) that is the photovoltaic device according to the first embodiment. FIG. 1-2 is a schematic plan view illustrating the configuration of the first main surface side of the heterojunction solar cell that is the photovoltaic device according to the first embodiment. FIG. 1-3 is a schematic plan view illustrating a configuration of a second main surface side in the heterojunction solar battery cell which is the photovoltaic device according to the first embodiment. Hereinafter, the structure of the solar cell according to the first embodiment will be described with reference to FIGS. 1-1 to 1-3.

  The solar cell according to the first embodiment includes an n-type single crystal silicon substrate 1 having a p-type impurity doping layer 2 on the first main surface side, and sequentially on the first main surface side of the n-type single crystal silicon substrate 1. The first intrinsic amorphous silicon layer 3, the p-type amorphous silicon layer 4, the first transparent electrode layer 5, and the first collector electrode 6 are provided. In addition, this solar cell includes a second intrinsic amorphous silicon layer 7, which is sequentially stacked on the second main surface side opposite to the first main surface (back surface) of the n-type single crystal silicon substrate 1, n-type. An amorphous silicon layer 8, a second transparent electrode layer 9, and a second collector electrode 10 are provided. In FIG. 1-2, attention is paid to the arrangement of the n-type single crystal silicon substrate 1, the p-type impurity doped layer 2, the p-type amorphous silicon layer 4, and the first transparent electrode layer 5. The illustration of the members is omitted. In FIG. 1-3, the arrangement of the n-type amorphous silicon layer 8 and the second transparent electrode layer 9 is shown with attention, and the illustration of other members is omitted.

  The n-type single crystal silicon substrate 1 is a 200 μm-thick n-type single crystal silicon substrate whose main surface has a plane orientation of (100), and has a pyramid shape formed by anisotropic etching using an alkaline solution. The surface has a texture structure composed of minute irregularities 1a. The n-type single crystal silicon substrate 1 has a low sheet resistance value of less than 200 Ω / □ in the surface layer of the entire peripheral area of the outer peripheral edge (end peripheral area) at least near the substrate end on the first main surface side. A p-type impurity doping layer 2 is formed. The p-type impurity doping layer 2 is formed on the surface layer of the first main surface in a region including at least a region where the first transparent electrode layer 5 is not formed in the plane direction of the n-type single crystal silicon substrate 1.

  In the solar cell according to the first embodiment, the n-type single crystal silicon substrate 1 is used as the crystalline semiconductor substrate. However, the n-type polycrystalline silicon substrate, the p-type single crystal silicon substrate, and the p-type silicon substrate are used. A polycrystalline silicon substrate may be used. In the case where a p-type silicon substrate is used, the conductivity type of each member in the solar battery cell according to the first embodiment may be reversed.

  The p-type amorphous silicon layer 4 is a conductive amorphous semiconductor layer made of an amorphous silicon thin film doped with impurities and having a conductivity type opposite to that of the n-type single crystal silicon substrate 1. The n-type amorphous silicon layer 8 is a conductive non-conductive layer made of an amorphous silicon thin film having an impurity doped at a higher concentration than the n-type single crystal silicon substrate 1 and having the same conductivity type as that of the n-type single crystal silicon substrate 1. It is a crystalline semiconductor layer.

  The first transparent electrode layer 5 is made of an indium tin oxide (ITO) film having a thickness of about 80 nm. In the present embodiment, the first transparent electrode layer 5 is a region smaller than the region where the p-type amorphous silicon layer 4 is formed in the plane direction of the n-type single crystal silicon substrate 1, and is a p-type impurity. It is formed only in a region larger than the unformed region of the doping layer 2. That is, the first transparent electrode layer 5 overlaps with the p-type impurity doping layer 2 in the entire peripheral region near the end face of the n-type single crystal silicon substrate 1 in the plane direction of the n-type single crystal silicon substrate 1. ing. Therefore, the first transparent electrode layer 5 is formed on the p-type amorphous silicon layer 4 in an inner region separated from the end of the p-type amorphous silicon layer 4, and the n-type single crystal silicon substrate 1, The p-type impurity doped layer 2, the first intrinsic amorphous silicon layer 3, and the p-type amorphous silicon layer 4 are not in contact with the end faces.

  The second transparent electrode layer 9 is made of an ITO film having a thickness of about 80 nm. In the present embodiment, the second transparent electrode layer 9 is formed only in a region smaller than the region where the n-type amorphous silicon layer 8 is formed in the plane direction of the n-type single crystal silicon substrate 1. Accordingly, the second transparent electrode layer 9 is formed on the n-type amorphous silicon layer 8 in an inner region separated from the end portion of the n-type amorphous silicon layer 8, and the n-type single crystal silicon substrate 1, The end faces of the second intrinsic amorphous silicon layer 7 and the n-type amorphous silicon layer 8 are not in contact with each other.

  The first transparent electrode layer 5 and the second transparent electrode layer 9 are formed in the region as described above, so that the first transparent electrode layer 5 on the first main surface side is the end face of the n-type single crystal silicon substrate 1. Of the current leakage due to the direct contact with the first transparent electrode layer 5 on the first main surface side and the second transparent electrode layer 9 on the second main surface side through the end surface. It is prevented. Thereby, the fall of the photoelectric conversion efficiency resulting from the current leak in an end surface is prevented.

  The first collector electrode 6 includes a finger silver electrode having a thickness of about 50 μm and a width of 100 μm, a bus bar electrode having a thickness of about 50 μm and a width of 2 mm for collecting current collected using the finger silver electrode, Are provided in a predetermined region on the first transparent electrode layer 5. In addition, in FIG. 1-1, only the finger silver electrode is shown. In addition, in FIG. 1-1, two finger silver electrodes are used, but a larger number of finger silver electrodes are actually used.

  The second collector electrode 10 includes a finger silver electrode having a thickness of about 50 μm and a width of 100 μm, a bus bar electrode having a thickness of about 50 μm and a width of 2 mm for collecting current collected using the finger silver electrode, Are provided in a predetermined region on the second transparent electrode layer 9. In addition, in FIG. 1-1, only the finger silver electrode is shown.

  In this solar cell, a thin first intrinsic amorphous silicon layer 3 and a thin p-type amorphous silicon layer 4 are laminated in this order on an n-type single crystal silicon substrate 1. Thus, a heterojunction between the n-type single crystal silicon substrate 1 and the thin p-type amorphous silicon layer 4 is formed via the first intrinsic amorphous silicon layer 3. By forming the p-type amorphous silicon layer 4 as a thin film, the impurity concentration distribution of the p-type amorphous silicon layer 4 can be freely set, and since the p-type amorphous silicon layer 4 is thin, Thus, recombination of carriers and light absorption can be suppressed, and a large generated current can be obtained. The first intrinsic amorphous silicon layer 3 inserted between the n-type single crystal silicon substrate 1 and the p-type amorphous silicon layer 4 suppresses impurity diffusion between heterojunctions and has a steep impurity profile. Since a junction can be formed, a high open-circuit voltage can be obtained by forming a good junction interface.

  In the solar cell according to the first embodiment configured as described above, the first transparent electrode layer 5 and the second transparent electrode layer 9 are formed on the first main surface side of the n-type single crystal silicon substrate 1. The region is limited to the region near the center on the first main surface side excluding the outer peripheral edge near the substrate end surface. Thereby, the first transparent electrode layer 5 and the second transparent electrode layer 9 are in contact with the end face of the n-type single crystal silicon substrate 1 and the end faces of the first transparent electrode layer 5 and the second transparent electrode layer 9 are interposed. The formation of a current leak path due to the contact is prevented.

  In the solar cell according to the first embodiment, the p-type impurity doping layer 2 is formed in the peripheral region corresponding to the unformed region of the first transparent electrode layer 5 on the first main surface side of the n-type single crystal silicon substrate 1. Exists. For this reason, in the region where the first transparent electrode layer 5 is not formed, the p-type impurity doping layer 2 having a low sheet resistance value of less than 200 Ω / □ may be responsible for light carrier collection instead of the first transparent electrode layer 5. Is possible. Thereby, compared with the case where the p-type impurity doping layer 2 is not formed, the collection efficiency of the photocarriers generated in the outer peripheral edge region of the n-type single crystal silicon substrate 1 can be improved, and the short-circuit current value and the curve can be improved. The effect of improving the factor is obtained.

  Therefore, according to the solar cell according to the first embodiment, the formation of a current leak path through the end face of the n-type single crystal silicon substrate 1 is prevented, and carriers in the peripheral area of the end portion of the n-type single crystal silicon substrate 1 are prevented. A photovoltaic device excellent in photoelectric conversion efficiency in which collection loss is suppressed has been realized.

  Next, a method for manufacturing the solar battery cell according to the first embodiment configured as described above will be described with reference to FIGS. 2-1 to 2-6 and FIG. FIGS. 2-1 to 2-6 are schematic cross-sectional views illustrating steps of a method for manufacturing a solar battery cell that is the photovoltaic device according to the first embodiment. FIG. 3 is a flowchart illustrating steps of a method for manufacturing a solar battery cell that is the photovoltaic device according to the first embodiment.

  First, in the first step, an n-type single crystal silicon substrate 1 having a thickness of (100) on the main surface and having a thickness of (100) is immersed in an alkaline solution to remove wire saw damage during slicing and a pyramid shape. A texture structure composed of minute irregularities 1a having a surface is formed on the surface (FIG. 2-1, step S10). As the alkaline solution, for example, a 5 weight percent sodium hydroxide aqueous solution containing 10 volume percent isopropyl alcohol and heated to 75 ° C. can be used.

  In the next second step, p-type impurity doping layer 2 is formed in the entire peripheral region of the outer peripheral edge (end peripheral region) near the substrate end on the first main surface of n-type single crystal silicon substrate 1. The p-type impurity doping layer 2 can be formed by applying a diffusion material containing a p-type dopant to a desired position and then performing a heat treatment. First, a boron diffusing material 11 containing boron (B) element is applied by screen printing to the entire peripheral region of the edge peripheral region (outer peripheral edge) on the first main surface side of the n-type single crystal silicon substrate 1 (FIG. 2). 2).

  Next, the n-type single crystal silicon substrate 1 coated with the boron diffusion material 11 is heated using a quartz furnace in a nitrogen atmosphere. Thereafter, the n-type single crystal silicon substrate 1 is immersed in a hydrofluoric acid aqueous solution, and the boron diffusion material 11 applied to the n-type single crystal silicon substrate 1 is removed. As a result, the p-type impurity having a sheet resistance value of less than 200 Ω / □ in the entire peripheral region (end peripheral region) near the substrate end on the first main surface side of the n-type single crystal silicon substrate 1 The doping layer 2 is formed (FIG. 2-3, step S20).

As the boron diffusion material 11, for example, a material containing boron, such as boron oxide (B ₂ O ₃ ), a glass component, a resin component, an organic solvent component, or the like can be used. As a coating method of the boron diffusing material 11, a gravure printing method, an ink jet method, a dispensing method, or the like may be used besides screen printing.

  The heating temperature of the n-type single crystal silicon substrate 1 in the quartz furnace is, for example, 900 ° C., and the heating time is, for example, 40 minutes. However, the heating condition is not limited to this, and the boron component contained in the boron diffusing material 11 can be thermally diffused in the n-type single crystal silicon substrate 1, and the sheet resistance value of the p-type impurity doped layer 2 after heating is Any condition can be set as long as it is less than 200Ω / □. In this case, the p-type impurity doping layer 2 can be formed in a desired region only by the application of the boron diffusion material 11 and the heat treatment process, and the process can be simplified.

  The p-type impurity doping layer 2 can also be formed using an ion implantation method. In this case, a mask film using a photoresist is formed in a region near the center of the n-type single crystal silicon substrate 1 on the first main surface side, that is, a region where ions are not implanted, and then ion implantation is performed on the first main surface. Boron atoms are introduced and the mask film is removed. Thereby, boron atoms are implanted into the entire peripheral region around the end portion (outer peripheral edge portion) of the n-type single crystal silicon substrate 1 on the first main surface side. Furthermore, by performing a rapid heating process for repairing crystal defects generated in the n-type single crystal silicon substrate 1 by the ion implantation process, the entire peripheral region around the end (outer peripheral edge) on the first main surface side is obtained. A p-type impurity doping layer 2 is formed.

  The ion acceleration conditions in the ion implantation process, the heating temperature in the rapid heat treatment process, the time, and the like can be freely set within a range in which the sheet resistance value of the p-type impurity doping layer 2 is less than 200Ω / □. In this case, a mask film forming step and a removing step are required, and the number of steps increases, but it is possible to form the p-type impurity doping layer 2 controlled to a desired impurity concentration condition and depth condition. .

In the following third step and fourth step, monosilane (SiH ₄ ) gas, hydrogen (H ₂ ) gas, diborane (B ₂ H ₆ ) gas, phosphine (PH ₃ ) are formed on both main surface sides of the n-type single crystal silicon substrate 1. ) An amorphous silicon layer made of an amorphous silicon thin film is formed using a plasma CVD method using a gas as a source gas. Note that the execution order of the third step and the fourth step may be switched.

  In the third step, after the first intrinsic amorphous silicon layer 3 is formed on the first main surface side of the n-type single crystal silicon substrate 1 including the p-type impurity doped layer 2, the first intrinsic amorphous silicon is formed. A p-type amorphous silicon layer 4 is formed on the layer 3 (FIG. 2-4, step S30). The film thickness of the first intrinsic amorphous silicon layer 3 is, for example, 5 nm, and the film thickness of the p-type amorphous silicon layer 4 is, for example, 10 nm.

  In the fourth step, after the second intrinsic amorphous silicon layer 7 is formed on the second main surface side of the n-type single crystal silicon substrate 1, the n-type amorphous silicon layer 7 is formed on the second intrinsic amorphous silicon layer 7. The silicon layer 8 is formed (FIG. 2-4, step S40). The film thickness of the second intrinsic amorphous silicon layer 7 is 5 nm, for example, and the film thickness of the n-type amorphous silicon layer 8 is 10 nm, for example.

  In the subsequent fifth and sixth steps, a transparent electrode layer made of an ITO thin film is formed on the p-type amorphous silicon layer 4 and the n-type amorphous silicon layer 8 by sputtering. In addition, the execution order of the fifth step and the sixth step may be switched.

  In the fifth step, a first transparent electrode layer 5 made of an ITO film having a thickness of 80 nm is formed on the p-type amorphous silicon layer 4. The first transparent electrode layer 5 limits the formation region on the p-type amorphous silicon layer 4 using a mask, so that the p-type amorphous silicon layer 4 is aligned in the plane direction of the n-type single crystal silicon substrate 1. Is formed only in a region that is smaller than the region where p is formed and spaced from the end of the p-type amorphous silicon layer 4 and larger than the region where the p-type impurity doping layer 2 is not formed (FIG. 2). 5, Step S50).

  In the sixth step, a second transparent electrode layer 9 made of an ITO film having a thickness of 80 nm is formed on the n-type amorphous silicon layer 8. The second transparent electrode layer 9 limits the formation region on the n-type amorphous silicon layer 8 using a mask, so that the n-type amorphous silicon layer 8 is aligned in the plane direction of the n-type single crystal silicon substrate 1. It is formed only in a region that is smaller than the formation region and spaced from the end of the n-type amorphous silicon layer 8 (FIG. 2-5, step S60).

  In the subsequent seventh and eighth steps, a paste containing silver is applied onto the first transparent electrode layer 5 and the second transparent electrode layer 9 by using a screen printing method, and is cured and dried in an atmosphere of 200 ° C., for example. Thus, a collector electrode made of metal is formed. The execution order of the seventh step and the eighth step may be switched.

  In the seventh step, a first collector electrode 6 comprising a finger silver electrode having a thickness of about 50 μm and a width of 100 μm, and a bus bar electrode having a thickness of about 50 μm and a width of 2 mm is formed on the first transparent electrode layer 5. (FIG. 2-6, step S70). 2-6, only the finger silver electrode is shown among the 1st collector electrodes 6. FIG.

  In the eighth step, a second collector electrode 10 comprising a finger silver electrode having a thickness of about 50 μm and a width of 100 μm and a bus bar electrode having a thickness of about 50 μm and a width of 2 mm is formed on the second transparent electrode layer 9. (FIG. 2-6, step S70). 2-6, only the finger silver electrode is shown among the 2nd collector electrodes 10. FIG.

  By performing the above steps, the heterojunction solar cell according to the first embodiment having the structure shown in FIG. 1 is produced.

  In the heterojunction solar cell according to the first embodiment described above, the region where the first transparent electrode layer 5 is formed is near the center of the substrate in the plane direction of the n-type single crystal silicon substrate 1 on the p-type amorphous silicon layer 4. Is limited to. That is, the first transparent electrode layer 5 is an area smaller than the formation area of the p-type amorphous silicon layer 4 on the p-type amorphous silicon layer 4 and the first main surface side of the n-type single crystal silicon substrate 1. The p-type impurity doped layer 2 formed in the second step is formed in a region larger than the unformed region.

  In the manufacturing method of the solar cell according to the first embodiment described above, the formation region of the first transparent electrode layer 5 and the second transparent electrode layer 9 is the substrate on the first main surface side of the n-type single crystal silicon substrate 1. The region is limited to the vicinity of the central portion on the first main surface side excluding the outer peripheral edge near the end surface. Thereby, the first transparent electrode layer 5 and the second transparent electrode layer 9 are in contact with the end face of the n-type single crystal silicon substrate 1 and the end faces of the first transparent electrode layer 5 and the second transparent electrode layer 9 are interposed. It is possible to prevent the formation of a current leak path due to the contact.

  In the method for manufacturing the solar cell according to the first embodiment, the p-type impurity is present in the peripheral region corresponding to the unformed region of the first transparent electrode layer 5 on the first main surface side of the n-type single crystal silicon substrate 1. A doping layer 2 is formed. For this reason, in the region where the first transparent electrode layer 5 is not formed, the p-type impurity doping layer 2 can take charge of collecting optical carriers in place of the first transparent electrode layer 5. Thereby, compared with the case where the p-type impurity doping layer 2 is not formed, the collection efficiency of the photocarriers generated in the outer peripheral edge region of the n-type single crystal silicon substrate 1 can be improved, and the short-circuit current value and the curve can be improved. The effect of improving the factor is obtained.

  Therefore, according to the method for manufacturing the solar cell according to the first embodiment, the formation of a current leak path through the end face of the n-type single crystal silicon substrate 1 is prevented, and it corresponds to the region where the first transparent electrode layer 5 is not formed. A photovoltaic device excellent in photoelectric conversion efficiency in which carrier collection loss in the peripheral region of the end portion of the n-type single crystal silicon substrate 1 is suppressed can be manufactured by a simple method.

  In the above description, the configuration including the first intrinsic amorphous silicon layer 3 and the second intrinsic amorphous silicon layer 7 has been described. However, the first intrinsic amorphous silicon layer 3 and the second intrinsic amorphous silicon layer have been described. Even when the silicon layer 7 is not provided, there is no influence on the effect in the first embodiment. However, from the viewpoint of improving the photoelectric conversion performance, it is preferable to include the first intrinsic amorphous silicon layer 3 and the second intrinsic amorphous silicon layer.

Embodiment 2. FIG.
FIG. 4 is a schematic cross-sectional view illustrating a configuration of a heterojunction solar battery cell (hereinafter sometimes referred to as a solar battery cell) that is the photovoltaic device according to the second embodiment. The structure of the solar cell according to the second embodiment is such that the n-type single crystal silicon substrate 1 in the inner region surrounded by the p-type impurity doping layer 2 in the plane direction of the n-type single crystal silicon substrate 1 is removed, and the portion 1 except that a first intrinsic amorphous silicon layer 3 and a p-type amorphous silicon layer 4 are formed, and a first transparent electrode layer 5 is formed thereon. This is substantially the same as the structure of the solar battery cell. That is, the solar cell according to the second embodiment is different in the shapes of the n-type single crystal silicon substrate 1, the first intrinsic amorphous silicon layer 3, the p-type amorphous silicon layer 4, and the first transparent electrode layer 5. Except for this, the structure of the solar battery cell according to the first embodiment shown in FIG.

  Therefore, in the solar cell according to the second embodiment, the limitation on the formation region of the first transparent electrode layer 5 and the second transparent electrode layer 9 is the same as the structure of the solar cell according to the first embodiment shown in FIG. It is almost the same. Thereby, the photovoltaic cell concerning Embodiment 2 has the same effect as the photovoltaic cell concerning Embodiment 1. FIG. In FIG. 4, detailed description is omitted by attaching the same reference numerals as the structure of the solar battery cell according to the first embodiment, and a manufacturing method thereof will be described in the present embodiment. 5-1 to 5-7 are schematic cross-sectional views illustrating a method for manufacturing a solar battery cell that is the photovoltaic device according to the second embodiment.

  First, in the first step, an n-type single crystal silicon substrate 1 having a thickness of 200 μm and having a main surface orientation of (100) is prepared and immersed in an alkaline solution to remove wire saw damage during slicing. Then, a texture structure composed of minute irregularities 1a having a pyramid shape is formed on the surface (FIG. 5-1). As the alkaline solution, for example, a 5 weight percent sodium hydroxide aqueous solution containing 10 volume percent isopropyl alcohol and heated to 75 ° C. can be used.

  In the next second step, the p-type impurity doping layer 2 is formed in the entire peripheral region of the outer peripheral edge portion (end peripheral region) in the vicinity of the substrate end on the first main surface of the n-type single crystal silicon substrate 1, and An n-type impurity doping layer 21 is formed in a region where the p-type impurity doping layer 2 is not formed on the first main surface, that is, an inner region (region near the center) on the first main surface. The p-type impurity doping layer 2 can be formed by applying a diffusion material containing a p-type dopant to a desired position and then performing a heat treatment. The n-type impurity doping layer 21 can be formed by applying a diffusion material containing an n-type dopant to a desired position and then performing a heat treatment.

  That is, first, boron diffusing material 11 containing boron (B) element is applied by screen printing to the entire peripheral region of the edge peripheral region of the first main surface of n-type single crystal silicon substrate 1 (FIG. 5-2). Further, a phosphorus diffusing material 12 containing a phosphorus (P) element is applied by screen printing to an uncoated region of the boron diffusing material 11 on the first main surface, that is, an inner region (region near the center) on the first main surface (see FIG. 5-2).

  Next, the n-type single crystal silicon substrate 1 coated with the boron diffusing material 11 and the phosphorus diffusing material 12 is heated using a quartz furnace in a nitrogen atmosphere. Thereafter, the n-type single crystal silicon substrate 1 is immersed in a hydrofluoric acid aqueous solution, and the boron diffusion material 11 and the phosphorus diffusion material 12 applied to the n-type single crystal silicon substrate 1 are removed. As a result, the p-type impurity doping having a sheet resistance value of less than 200Ω / □ is applied to the entire peripheral region of the first peripheral surface of the first main surface of the n-type single crystal silicon substrate 1 near the end of the substrate (end peripheral region). A layer 2 is formed, and an n-type impurity doped layer 21 is formed in a region where the p-type impurity doped layer 2 is not formed on the first main surface, that is, an inner region (region near the center) on the first main surface (FIG. 5). -3).

As the boron diffusion material 11, for example, a material containing boron, such as boron oxide (B ₂ O ₃ ), a glass component, a resin component, an organic solvent component, or the like can be used. Further, as the phosphorus diffusing material 12, for example, a material containing phosphorus such as diphosphorus pentoxide (P ₂ O ₅ ), a glass component, a resin component, an organic solvent component, or the like can be used. As a method for applying the boron diffusing material 11 and the phosphorus diffusing material 12, a gravure printing method, an ink jet method, a dispensing method, or the like may be used in addition to screen printing.

The heating temperature of the n-type single crystal silicon substrate 1 in the quartz furnace is, for example, 900 ° C., and the heating time is, for example, 40 minutes. However, the heating condition is not limited to this, and the boron component contained in the boron diffusing material 11 is thermally diffused into the n-type single crystal silicon substrate 1 and is electrically active at least on the outermost surface of the n-type single crystal silicon substrate 1. The impurity concentration is 5 × 10 ¹⁹ cm ⁻³ or more, the sheet resistance value of the p-type impurity doped layer 2 after thermal diffusion is less than 200Ω / □, and the phosphorus component contained in the phosphorus diffusion material 12 is an n-type single crystal The temperature and time can be freely set as long as the conditions allow heat diffusion in the silicon substrate 1.

  In the second step, the p-type impurity doping layer 2 is formed in the peripheral region of the end portion of the first main surface of the n-type single crystal silicon substrate 1, and at the same time, in the inner region (region near the center) of the first main surface. Since a metal impurity trapping effect (gettering effect) is caused by the diffusion of phosphorus atoms, the minority carrier lifetime in the n-type single crystal silicon substrate 1 is improved.

In the third step, the n-type single crystal silicon substrate 1 from which the boron diffusing material 11 and the phosphorus diffusing material 12 have been removed contains 10 volume percent of an alkaline aqueous solution, for example, isopropyl alcohol, and is heated to 75 ° C. to 5 weight percent hydroxylation. The n-type impurity doping layer 21 is removed by etching by dipping in an aqueous sodium solution for 20 minutes. At this time, due to the difference in the surface potential at the contact surface with the alkaline aqueous solution, etching hardly progresses at a location where electrically active boron atoms are contained at a concentration of 5 × 10 ¹⁹ cm ⁻³ or more. For this reason, the p-type impurity doping layer 2 is not etched, and only the n-type impurity doping layer 21 is selectively etched. Therefore, the n-type single crystal silicon substrate 1 has its surface removed from the first main surface side of the n-type single crystal silicon substrate 1 after the end of the third step in the region near the center. The p-type impurity doping layer 2 is left exposed in the entire peripheral region of the edge peripheral region (FIG. 5-4).

  Note that it is not always necessary to immerse the n-type single crystal silicon substrate 1 in an alkaline aqueous solution, and an alkali is provided on the first main surface side of the n-type single crystal silicon substrate 1 so that only the n-type impurity doping layer 21 can be selectively etched. An aqueous solution may be supplied.

  In addition, the texture structure previously formed on the n-type single crystal silicon substrate 1 proceeds through the third step because the etching reaction proceeds while the shape is maintained by the effect of isopropyl alcohol added to the aqueous sodium hydroxide solution. However, the light confinement effect does not decrease.

  The type, concentration, temperature, type, concentration, etching time, etc. of the alkaline aqueous solution used in the third step are within the range where the n-type impurity doping layer 21 is removed and the texture structure is maintained. It is possible to set freely.

  In the above description, the p-type impurity doping layer 2 and the n-type impurity doping layer 21 are formed simultaneously. However, the p-type impurity doping layer 2 and the n-type impurity doping layer 21 are not necessarily formed simultaneously. Absent. The p-type impurity doping layer 2 and the n-type impurity doping layer 21 may be formed in either the same process or different processes between the first process and the third process, and either may be formed first.

In the subsequent fourth and fifth steps, monosilane (SiH ₄ ) gas, hydrogen (H ₂ ) gas, diborane (B ₂ H ₆ ) gas, phosphine (PH ₃ ) are formed on both main surfaces of the n-type single crystal silicon substrate 1. ) An amorphous silicon layer made of an amorphous silicon thin film is formed using a plasma CVD method using a gas as a source gas. Note that the execution order of the fourth step and the fifth step may be switched.

  In the fourth step, after the first intrinsic amorphous silicon layer 3 is formed on the first main surface side of the n-type single crystal silicon substrate 1 including the p-type impurity doped layer 2, the first intrinsic amorphous silicon is formed. A p-type amorphous silicon layer 4 is formed on the layer 3 (FIGS. 5-5). The film thickness of the first intrinsic amorphous silicon layer 3 is, for example, 5 nm, and the film thickness of the p-type amorphous silicon layer 4 is, for example, 10 nm. Here, first intrinsic amorphous silicon layer 3 and p-type amorphous silicon layer 4 are formed in a shape along the surface shape on the first main surface side of n-type single crystal silicon substrate 1. That is, the first intrinsic amorphous silicon layer 3 and the p-type amorphous silicon layer 4 are formed on the inner surface of the concave region where the n-type impurity doping layer 21 is removed on the first main surface side of the n-type single crystal silicon substrate 1. To the p-type impurity doped layer 2.

  In the fifth step, after the second intrinsic amorphous silicon layer 7 is formed on the second main surface of the n-type single crystal silicon substrate 1, the n-type amorphous silicon layer 7 is formed on the second intrinsic amorphous silicon layer 7. A silicon layer 8 is formed (FIGS. 5-5). The film thickness of the second intrinsic amorphous silicon layer 7 is 5 nm, for example, and the film thickness of the n-type amorphous silicon layer 8 is 10 nm, for example.

  In the subsequent sixth and seventh steps, a transparent electrode layer made of an ITO thin film is formed on the p-type amorphous silicon layer 4 and the n-type amorphous silicon layer 8 by sputtering. Note that the execution order of the sixth step and the seventh step may be switched.

  In the sixth step, a first transparent electrode layer 5 made of an ITO film having a thickness of 80 nm is formed on the p-type amorphous silicon layer 4. The first transparent electrode layer 5 limits the formation region on the p-type amorphous silicon layer 4 using a mask, so that the p-type amorphous silicon layer 4 is aligned in the plane direction of the n-type single crystal silicon substrate 1. Is formed only in a region that is smaller than the region where p is formed and spaced from the end of the p-type amorphous silicon layer 4 and larger than the region where the p-type impurity doped layer 2 is not formed (FIG. 5). 6).

  In the seventh step, a second transparent electrode layer 9 made of an ITO film having a thickness of 80 nm is formed on the n-type amorphous silicon layer 8. The second transparent electrode layer 9 limits the formation region on the n-type amorphous silicon layer 8 using a mask, so that the n-type amorphous silicon layer 8 is aligned in the plane direction of the n-type single crystal silicon substrate 1. It is formed only in a region that is smaller than the region where the n-type amorphous silicon layer 8 is formed and spaced from the end of the n-type amorphous silicon layer 8 (FIGS. 5-6).

  In the subsequent 8th and 9th steps, a paste containing silver is applied onto the first transparent electrode layer 5 and the second transparent electrode layer 9 using a screen printing method, and is cured and dried in an atmosphere of, for example, 200 ° C. Thus, a collector electrode made of metal is formed. In addition, the execution order of the 8th process and the 9th process may be switched.

  In the eighth step, the first collector electrode 6 composed of finger silver electrodes and bus bar electrodes is formed on the first transparent electrode layer 5 (FIGS. 5-7). In FIG. 5-7, only the finger silver electrode is shown.

  In the ninth step, the second collector electrode 10 composed of finger silver electrodes and bus bar electrodes is formed on the second transparent electrode layer 9 (FIGS. 5-7). In FIG. 5-7, only the finger silver electrode is shown.

  In the solar cell manufacturing method according to the second embodiment described above, the first transparent electrode layer 5 and the second transparent electrode layer 9 are formed on the substrate on the first main surface side of the n-type single crystal silicon substrate 1. The region is limited to the vicinity of the central portion on the first main surface side excluding the outer peripheral edge near the end surface. Thereby, the first transparent electrode layer 5 and the second transparent electrode layer 9 are in contact with the end face of the n-type single crystal silicon substrate 1 and the end faces of the first transparent electrode layer 5 and the second transparent electrode layer 9 are interposed. It is possible to prevent the formation of a current leak path due to the contact.

  In the method for manufacturing a solar battery cell according to the second embodiment, the p-type impurity doping is performed on the peripheral region corresponding to the region where the first transparent electrode layer 5 is not formed on the first main surface side of the n-type single crystal silicon substrate 1. Layer 2 is formed. For this reason, in the region where the first transparent electrode layer 5 is not formed, the p-type impurity doping layer 2 can take charge of collecting optical carriers in place of the first transparent electrode layer 5. Thereby, compared with the case where the p-type impurity doping layer 2 is not formed, the collection efficiency of the photocarriers generated in the outer peripheral edge region of the n-type single crystal silicon substrate 1 can be improved, and the short-circuit current value and the curve can be improved. The effect of improving the factor is obtained.

  And in the manufacturing method of the photovoltaic cell concerning Embodiment 2, it is p in the all-around area | region of the outer periphery part (edge part periphery area | region) near the board | substrate edge part of the 1st main surface of the n-type single crystal silicon substrate 1. FIG. At the same time when the type impurity doping layer 2 is formed, an n type impurity doping layer 21 in which phosphorus is diffused is formed in the inner region (region near the center) on the first main surface. Then, the n-type impurity doping layer 21 is selectively removed using hot alkali. Therefore, gettering of metal impurities in the inner region (near the center region) in the first main surface can be performed with a small number of processes simultaneously with the formation of the p-type impurity doping layer 2 in the peripheral region of the end portion of the first main surface. Is possible.

  Therefore, according to the method for manufacturing a solar battery cell according to the second embodiment, the formation of a current leak path through the end face of the n-type single crystal silicon substrate 1 is prevented, and it corresponds to the region where the first transparent electrode layer 5 is not formed. The carrier collection loss in the peripheral region of the end portion of the n-type single crystal silicon substrate 1 is suppressed, and the deterioration of power generation characteristics is suppressed by effective gettering of metal contamination inside the n-type single crystal silicon substrate 1. A photovoltaic device having excellent conversion efficiency can be manufactured by a simple method.

  In addition, by forming a plurality of solar cells having the configuration described in the above embodiment and connecting adjacent solar cells electrically in series or in parallel, it has a good light confinement effect and is reliable. The solar cell module excellent in the property and photoelectric conversion efficiency can be realized. In this case, for example, one first collector electrode 6 and the other second collector electrode 10 of adjacent solar cells may be electrically connected.

  Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention. Furthermore, the constituent elements over different embodiments may be appropriately combined.

  As described above, the photovoltaic device according to the present invention is useful for realizing a heterojunction photovoltaic device excellent in photoelectric conversion efficiency.

  1 n-type single crystal silicon substrate, 1a minute unevenness, 2 p-type impurity doping layer, 3 first intrinsic amorphous silicon layer, 4 p-type amorphous silicon layer, 5 first transparent electrode layer, 6 first collecting electrode 7 Second intrinsic amorphous silicon layer, 8 n-type amorphous silicon layer, 9 Second transparent electrode layer, 10 Second collector electrode, 11 Boron diffuser, 12 Phosphorus diffuser, 21 n-type impurity doped layer.

Claims (8)

On the first main surface of the crystalline semiconductor substrate, a first amorphous semiconductor thin film layer having a conductivity type opposite to that of the crystalline semiconductor substrate, a first transparent electrode layer, and a first collector electrode are provided in this order. And a second amorphous semiconductor thin film layer having the same conductivity type as the crystalline semiconductor substrate, a second transparent electrode layer, and a second collector electrode in this order on the second main surface of the crystalline semiconductor substrate. And
The first transparent electrode layer is smaller than a region where the first amorphous semiconductor thin film layer is formed in a plane direction of the crystalline semiconductor substrate, and only in a region separated from an end of the first amorphous semiconductor thin film layer. Formed,
The second transparent electrode layer is smaller than a formation region of the second amorphous semiconductor thin film layer in a plane direction of the crystalline semiconductor substrate, and only in a region spaced from an end of the second amorphous semiconductor thin film layer. Formed,
An impurity doping layer having a conductivity type opposite to that of the crystalline semiconductor substrate is provided in a region including at least a region where the first transparent electrode layer is not formed in the plane direction of the crystalline semiconductor substrate in the first main surface. Being formed,
A photovoltaic device characterized by the above. Having a first intrinsic amorphous semiconductor thin film layer between the first main surface and the first amorphous semiconductor thin film layer;
The photovoltaic device according to claim 1. Having a second intrinsic amorphous semiconductor thin film layer between the second main surface and the second amorphous semiconductor thin film layer;
The photovoltaic device according to claim 1, wherein: A first step of forming a first impurity doping layer having a conductivity type opposite to the conductivity type of the crystalline semiconductor substrate in at least the entire peripheral region of the outer peripheral edge of the first main surface of the crystalline semiconductor substrate;
A second step of forming a first amorphous semiconductor thin film layer having a conductivity type opposite to that of the crystalline semiconductor substrate on the first main surface including the first impurity doping layer;
A third step of forming a second amorphous semiconductor thin film layer having the same conductivity type as the crystalline semiconductor substrate on the second main surface of the crystalline semiconductor substrate;
On the first amorphous semiconductor thin film layer, the first amorphous semiconductor thin film layer is smaller than the region where the first amorphous semiconductor thin film layer is formed in the plane direction of the crystalline semiconductor substrate, and is separated from the end of the first amorphous semiconductor thin film layer. A fourth step of forming the first transparent electrode layer only in a region which is a region larger than a region where the first impurity doping layer is not formed,
On the second amorphous semiconductor thin film layer, the second amorphous semiconductor thin film layer is smaller than the region where the second amorphous semiconductor thin film layer is formed in the plane direction of the crystalline semiconductor substrate, and is separated from the end of the second amorphous semiconductor thin film layer. A fifth step of forming the second transparent electrode layer only in the region formed,
A sixth step of forming a first collector electrode on the first transparent electrode layer;
A seventh step of forming a second collector electrode on the second transparent electrode layer;
A method for manufacturing a photovoltaic device, comprising: In the first step, forming the first impurity doping layer containing at least 5 × 10 ¹⁹ cm ⁻³ of electrically active impurity atoms at least on the outermost surface;
Before the second step and at the same time before or after the first step,
Forming a second impurity doping layer having the same conductivity type as that of the crystalline semiconductor substrate in a region where the first impurity doping layer is not formed in the plane direction of the crystalline semiconductor substrate on the first main surface; 8 steps,
The first main surface is formed by performing wet etching on the first main surface on which the first impurity doping layer and the second impurity doping layer are formed, and selectively removing only the second impurity doping layer. A ninth step of exposing
Further comprising
The method for manufacturing a photovoltaic device according to claim 4. The crystalline semiconductor substrate is an n-type silicon substrate;
The second impurity doped layer is an n-type impurity doped layer in which phosphorus is diffused as an impurity element;
In the ninth step, only the second impurity doping layer is selectively removed by supplying an alkaline aqueous solution to the first main surface side of the crystalline semiconductor substrate;
The method for manufacturing a photovoltaic device according to claim 5. Forming a first intrinsic amorphous semiconductor layer on the first main surface on which the first impurity doping layer is formed between the first step and the second step;
Forming the first amorphous semiconductor thin film layer on the first intrinsic amorphous semiconductor layer in the second step;
A method for manufacturing a photovoltaic device according to any one of claims 4 to 6. Forming a second intrinsic amorphous semiconductor layer on the second main surface;
Forming the second amorphous semiconductor thin film layer on the second intrinsic amorphous semiconductor layer in the third step;
A method for manufacturing a photovoltaic device according to any one of claims 4 to 7.

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