JP2013236360A - Printed board and technique for designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce jitter in a clock signal output from a PLL circuit by suppressing voltage fluctuations of an analog power supply.SOLUTION: Filter circuit elements comprise only capacitors, and differential coupling power wiring referred to both voltages of a power supply and a ground at one point just close to capacitor terminals enhances coupling between the analog power supply and the ground to suppress crosstalk noise. If the coupling power wiring covers different layers of a printed board, a via is used and further a clearance is ensured against connection to power supplies on other layers and a ground plane. If a plurality of PLLs are mounted on a semiconductor integrated circuit and there are a plurality of analog power supplies and ground terminals, coupling power wiring is arranged for every power supply pair.

Description

High-speed, high-performance semiconductor integrated circuits (LSIs) are equipped with a phase-locked loop (PLL) used for clock signal generation, and are equipped with an analog power supply (AVcc) dedicated to PLL supply and an analog ground (AGnd) terminal It has been. When noise caused by digital operation circulates to the PLL power supply, jitter increases and LSI operation becomes unstable. The present invention is a power supply wiring method in which AVcc and AGnd on a printed circuit board (PCB) suppress the influence of external noise and reduce clock jitter.

In order to separate the digital power supply and the analog power supply, a filter circuit composed of elements such as ferrite beads, capacitors, and resistors is used. In PCB pattern design, a wiring method is adopted in which a gap is provided between the analog power plane and the digital system so that noise does not wrap around. Also, PCB design guides from LSI manufacturers recommend that filter circuit elements be placed as close to the LSI as possible, and that short and thick power wiring be used.

Japanese Patent Laid-Open No. 9-8633 Japanese Patent Laid-Open No. 2004-221962 Altera Corporation, “AN-583-1.0, 2,2009,“ AN563: Arria IIGX Design Guidelines ” Altera Corporation, “High-Speed Board Layout Guidelines” AN-224-1.1, 9,2003,

In general, analog circuits such as PLLs use analog power lines that are thicker than necessary in conformity with the PCB manufacturer's recommended PCB design guide, despite the low current consumption. If the wiring becomes thicker, the structure will be more susceptible to the effects of crosstalk noise from other high-speed signals on the PCB and the digital power supply. Also, because of the ease of PCB pattern design, the ground terminal often does not separate the digital and analog systems. When the PLL circuit is biased by the potential difference between AVcc and AGnd supplied from the PCB to the LSI, and this potential difference fluctuates due to noise, jitter in the clock signal will increase.

The circuit element for the filter is composed only of a capacitor, and it is a differential power supply wiring that uses both the AVcc and AGnd voltages at one point in the immediate vicinity of the capacitor terminal as a reference. When this power supply wiring crosses different layers on the PCB, Use a via, but provide clearance so that it is not connected to the power / ground plane in other layers. The wiring width and length reflect the DC voltage drop caused by the current consumption and resistance component of the PLL circuit in the LSI allowable power supply voltage.

When wiring near a digital power supply or signal due to PCB constraints, etc., the crosstalk noise is estimated as the AC noise amount and determined as a parameter that satisfies Equation 3, and multiple PLLs are mounted on the LSI, and AVcc, AGnd When there are a plurality of terminals, combined power supply wiring is applied to each power supply pair.

Even if crosstalk noise wraps around the coupled power supply wiring, coupling between AVcc and AGnd is strong, and common-mode noise is applied to both wirings, so the potential difference between AVcc and AGnd does not change, resulting in noise being applied. Even if this is done, the bias voltage to the PLL circuit is constant, and jitter can be suppressed.

This is a filter circuit element, and shows a case where a pattern is formed on the component surface of the PCB surface layer by the differential coupling power supply wiring method for supplying PLL. The case where two types of PLL power supplies exist in LSI is shown. The pattern of the surface layer when the combined power supply wiring is applied in a layer different from the component surface of the surface layer is shown. This shows the inner layer pattern (only the left side of the LSI is displayed) when the combined power supply wiring is applied in a layer different from the surface part surface. The pattern of the inner layer (including the lowermost layer) when the combined power supply wiring is applied in a layer different from the surface of the surface part is shown. It is sectional drawing for verifying the influence of the crosstalk noise from other signal and power supply to coupling power supply wiring. It is a top view for verifying the influence of the crosstalk noise from other signal and power supply to coupling power supply wiring. The voltage waveforms of AVcc and AGnd by the conventional method are shown. The voltage waveforms of AVcc and AGnd according to the method of the present invention are shown. The LSI is not mounted and shows the measured waveform of the analog power supply voltage when 125MHz noise is applied. The measured waveform of the analog power supply voltage when LSI is mounted and 50MHz noise is applied is shown.

  Hereinafter, a description will be given based on the embodiment.

Capacitors are mounted on the surface layer, and AVcc is connected in the order of one-point connected inner layer power supply (Vcc), capacitor power supply (Vcc) terminal, coupled power supply wiring, and LSI AVcc terminal. Similarly, AGnd is connected in the order of one-point inner layer ground (Gnd), capacitor ground (Gnd) terminal, coupled power wiring, and LSI AGnd terminal. Capacitor mounting and coupled power supply wiring are performed on the same surface layer as the LSI mounting surface, and the layer immediately below is covered with a Gnd plane. To maximize the coupling between power lines, the gap between AVcc and AGnd should be the smallest dimension allowed by the PCB manufacturing process.

When the number of LSI terminals increases as in a BGA package or the like, it becomes difficult to lead out the terminals, so the coupled power supply wiring is formed in a wiring layer other than the surface layer as shown in FIGS. In FIG. 2, a via is provided on the left side of the capacitor in order to move to one layer of the inner layer power supply / ground and to the other layer of the right coupling wiring. In FIG. 3, only the leftmost via is connected to Vcc and Gnd of the inner layer plane, and the other vias are not connected. In FIG. 4, the coupled power supply wiring is returned to the component surface by the right via. In these cases, if the coupling balance between the differential coupled power supply wiring and the other power source / signal that becomes the noise source is lost, the noise cannot be completely controlled by the potential difference between AVcc and AGnd.

The capacitive component to be coupled is proportional to the area of the surface where the two conductors overlap, and inversely proportional to the distance.

Each power source, signal positional relationship, and each coupling coefficient shown in FIGS. 5 and 6 are defined as in Equations 1 and 2, and parameters satisfying Equation 3 are calculated. However, n is the allowable noise voltage fluctuation rate of the analog power supply, and is the sum of the DC component n _dc and the AC component _nac .

Where L: analog power supply (AVcc), analog ground (AGnd) wiring length, W: AVcc, AGnd wiring width, S: gap between AVcc and AGnd, t: copper thickness of substrate wiring layer, SIG_1 _, 2 _{, 3,} 4: the signal as a noise source, L _{l, 2,4: SIG_1,} distance _2, 4 running parallel AVcc, and AGnd, S _1: SIG _{_ 1} and the gap between the AGND, S _2: SIG _{_} distance and 2 and the AGnd is overlap, S _3: the gap between the SIG_3 and AVcc, W _3: distance SIG _{_} 3 is running in parallel with the AVcc, W _4: SIG _{_} 2 and the distance and the overlap AGnd, H _2: SIG _{_} 2 and AVcc, insulating layer thickness between AGnd, H _4: SIG _{_ 4} and AVcc, insulating layer thickness between AGND, a.

For example, when n = 5% and n _dc = 1%, the coupling coefficient of the coupled power supply wiring itself is 3 to 25, and the total unbalanced coupling coefficient between the coupled power supply wiring and the noise source is 25 times or more. Set parameters.
1 / (n−n _dc) = 1 / (5% −1%) = 1 / (0.05−0.01) = 1 / 0.04 = 25

Next, specific parameters are set for the LSI design specifications in Table 1 and the PCB layer configuration parameters in Table 2.

SIG_4 is excluded because the combined power supply wiring is assigned to the lowermost surface layer. First, the wiring width (W) of AVcc and AGnd is set to 0.2 mm, the wiring length (L) is set to 30 mm, and the gap (S) is set to 0.1 mm. The loop resistance of AVcc−AGnd is from 0.14 to 0.121Ω, the voltage drop due to DC current is 0.1A × 0.121Ω = 12 mV (n _dc = 1.2%), and 12mV is subtracted from the allowable noise voltage 50mV (n = 5%) 38 mV (n _ac = 3.8%) is allocated to the AC noise component.

As a result, the coupling coefficient between the power supply and ground wiring is> 26, and the total unbalanced coupling coefficient between the coupled power supply wiring and the noise source is set to 26 times or more.
1 / (n−n _dc) = 1 / (5% −1.2%) = 1 / (0.05−0.012) = 1 / 0.038> 26

When the parameters shown in FIGS. 5 and 6 are set to the parameters shown in Table 3, the ratio of the coupling coefficient is 5 and does not satisfy Equation 1, so that the crosstalk noise will also circulate even in the coupled power supply wiring. SIG _{_} 2 is run in parallel layers immediately above the analog power supply wiring, noise coupling is large because the insulating layer thickness 0.1mm and thinner. Therefore, the analog supply and non-overlapping wiring pattern as shown in Table 4 as a countermeasure, a large SIG _{_} 1 of the noise coupling noise is reduced by widening the gap from 1.0mm to 1.5 mm, the ratio of coupling coefficients 27 becomes , Satisfying Equation 1.

Fig. 7 shows the voltage waveforms of AVcc and AGnd according to the conventional method. AGnd has a low impedance, so ground voltage fluctuation due to noise is small, but AVcc is designed to be easily affected by crosstalk noise (a ), The potential difference between AVcc and AGnd, which is close to the voltage waveform of AVcc (b).

FIG. 8 is a voltage waveform of AVcc and AGnd according to the method of the present invention. AGnd also has a voltage waveform almost in phase with AVcc (a), noise cancels out, and the potential difference of AVcc-AGnd is stabilized (b).

As shown in FIG. 9, the measured waveform of the analog power supply voltage when the LSI is not mounted and a noise of 125 MHz is applied, the voltage fluctuates at 60 mV in the conventional method, whereas according to the method of the present invention, the voltage is 29 mV. Yes, power supply noise is reduced compared to the conventional method.

Also, when the LSI is mounted and the PLL circuit is operated at 50 MHz and noise is applied, the voltage fluctuates at 501 mV in the conventional method as shown in the measured waveform in FIG. 10, whereas according to the method of the present invention, the voltage is 145 mV. Thus, the power supply noise is reduced as compared with the conventional method.

Finally, an accurate coupling parameter is calculated using an electromagnetic simulator and reflected in the PCB pattern design.

In this way, the circuit element for the filter is composed only of a capacitor, and the potential difference between AVcc and AGnd is established by using a differential coupled power supply wiring with the AVcc and AGnd voltages at one point in the immediate vicinity of the capacitor terminal as a reference. As a result, even if noise is applied, the bias voltage to the PLL circuit is constant, and jitter is reduced.

U1: Semiconductor package substrate
AVcc1, AVcc2: Analog power supply
AGnd1, AGnd2: Analog ground
Vcc: Power supply
Gnd: Grand
C1, C2, C3, C4, C5, C6: Capacitors
SIG: Signal
_{SIG _ 1, SIG _ 2,} SIG _ 3, SIG _ 4: signal sources of noise
W: AVcc, AGnd wiring width
L :: AVcc, AGnd wiring length
S: Gap between AVcc and AGnd
t: Copper thickness of substrate wiring layer
L _1: distance SIG _{_} 1 is running in parallel AVcc, and AGnd
L ₂ : Distance that SIG_2 runs parallel to AVcc and AGnd
L ₄ : Distance that SIG_4 runs parallel to AVcc and AGnd
S _1: the gap between the SIG _{_} 1 and AGnd
S ₂ : Distance where SIG_2 and AGnd overlap
S _3: the gap between the SIG _{_} 3 and AVcc
W _3: distance SIG _{_} 3 is running in parallel with the AVcc
W ₄ : Distance where SIG_4 and AGnd overlap
H ₂ : Insulating layer thickness between SIG_2 and AVcc, AGnd
H _4: SIG _{_ 4} and AVcc, insulating layer thickness between AGnd

Claims (3)

An analog power supply / ground terminal separated from a digital power supply / ground on a semiconductor integrated circuit, and a power supply / ground paired with a capacitor of a filter circuit element with a differential coupled power supply wiring pattern based on the voltage near the capacitor A printed circuit board characterized by suppressing power supply noise. The filter circuit element is composed only of a capacitor, and the analog power source and the ground are coupled by a differential type coupled power source wiring using both a single power source and a ground voltage in the vicinity of the capacitor terminal as a reference. 2. The printed circuit board according to claim 1. A printed circuit board design method in which the combined power supply wiring pattern uses the analog power supply, the analog ground wiring width, the wiring length, and the gap between the analog power supply and the analog ground as parameters.