JP2013229468A - Semiconductor integrated circuit device - Google Patents

Abstract

In a DRAM having a COB type memory array using a cylinder type MIM capacitor, over-etching is generally performed at the time of forming a capacitor hole for reliable connection between a capacitor lower electrode and a contact plug. Therefore, there is a high possibility that the upper end of the contact plug protrudes from the bottom surface of the capacitor hole, and the lower electrode film and the capacitor insulating film are formed in a portion having severe irregularities, and there is a concern about leakage or the like.
The present invention relates to a memory capacitor forming insulating film layer provided on a device main surface of a semiconductor substrate, from the upper surface thereof to the inside thereof from the bottom surface of the memory capacitor forming hole. In a semiconductor integrated circuit device having a protruding metal plug, a memory capacitor is not substantially formed on the upper and side surfaces of the metal plug.
[Selection] Figure 5

Description

  The present application relates to a semiconductor integrated circuit device (or a semiconductor device), and more particularly to a technology effective when applied to a DRAM (Dynamic Random Access Memory) technology.

  Japanese Laid-Open Patent Publication No. 2008-130981 (Patent Document 1) or US Pat. No. 7,745,868 (Patent Document 2) corresponding thereto discloses a DRAM having a COB (Capacitor Over Bitline) type memory array (Memory Array). An example is shown. Therefore, a device having a memory capacitor polysilicon contact plug (Memory Capacitor Polysilicon Contact Plug) having an upper surface wider than a cylinder type memory capacitor hole (Memory Capacitor Hall) is disclosed.

  Japanese Unexamined Patent Publication No. 2007-317742 (Patent Document 3) shows an example of a RAM (Random Access Memory) having a relatively flat stack type ferroelectric capacitor. In view of this, a structure in which the upper end of the contact plug protrudes upward from the lower surface of the memory capacitor hole is disclosed.

  Japanese Patent Laid-Open No. 10-173148 (Patent Document 4) discloses a DRAM having a COB type memory array in which a lower electrode of a cylinder type capacitor is formed on a memory capacitor polysilicon contact plug.

JP 2008-130981 A U.S. Pat. No. 7,745,868 JP 2007-317742 A Japanese Patent Laid-Open No. 10-173148

  In a DRAM having a COB type memory array using a cylinder type MIM (Metal Insulator Metal) capacitor, it is common to apply overetching when forming a capacitor hole for reliable connection between a capacitor lower electrode and a contact plug. . Therefore, there is a high possibility that the upper end of the contact plug protrudes from the bottom surface of the capacitor hole, and the lower electrode film and the capacitor insulating film are formed in a portion having severe irregularities, and there is a concern about leakage or the like.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the outline of one embodiment of the present application is as follows. From the top surface of the memory capacitor forming insulating film layer provided on the device main surface of the semiconductor substrate, from the bottom surface of the memory capacitor forming hole formed toward the inside thereof. In a semiconductor integrated circuit device having a metal plug protruding into the inside thereof, a memory capacitor is not substantially formed on the upper surface and side surface of the metal plug.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the embodiment of the present application, it is possible to reduce the leakage of the memory capacitor.

Entire semiconductor chip for explaining a device structure of an example of an embedded DRAM (DRAM embedded logic device) in a semiconductor integrated circuit device according to an embodiment of the present application, that is, a memory capacity structure (simple cylinder type memory capacity structure) It is a top view. FIG. 2 is a schematic circuit diagram of a memory area 3 in FIG. 1. FIG. 2 is a plan layout diagram of a memory region corner portion peripheral cutout region R1 of FIG. 1. FIG. 2 is a device cross-sectional view substantially corresponding to the A-A ′ cross section of FIG. 1. FIG. 5 is an enlarged sectional view of a memory capacity peripheral sectional cutout region R2 of FIG. 4; FIG. 6 is a wafer cross-sectional view (resist film processing step for forming a capacitor hole) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (capacitor hole forming step) corresponding to FIG. 5 in the middle of the process for describing an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (capacitor lower electrode film forming step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (resist film patterning step for processing a capacitor lower electrode) corresponding to FIG. 5 in the middle of the process for explaining an example of a manufacturing process main part of the semiconductor integrated circuit device according to the embodiment of the present application; FIG. 6 is a wafer cross-sectional view (capacitor lower electrode processing step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the embodiment of the present application. FIG. 6 is a wafer cross-sectional view (capacitor upper electrode film forming step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (capacitor upper electrode processing step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the embodiment of the present application. FIG. 6 is a wafer cross-sectional view (in-capacitor insulating film embedding step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (in-capacitor embedded insulating film planarization step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 6 is a wafer cross-sectional view (capacitor plate deposition process) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application; For explaining a device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure, etc. FIG. 6 is an enlarged cross-sectional view of a memory capacity peripheral cross-sectional cutout region R2 of FIG. 4 corresponding to FIG. 5; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (additional capacity insulating film forming step) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (additional capacity insulating film processing step) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (capacitor lower additional electrode film forming step) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (resist film processing step for processing a capacitor lower additional electrode) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (capacitor lower additional electrode processing step) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (in-capacitor insulating film embedding step) corresponding to FIG. 16 in the middle of the process for explaining an example; In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a cross-sectional view of a wafer corresponding to FIG. 16 in the middle of a process for explaining an example (planarization process of a buried insulating film in a capacitor). In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure FIG. 17 is a wafer cross-sectional view (capacitor plate deposition process) corresponding to FIG. 16 in the middle of the process for explaining an example; A device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (memory capacity structure in a premetal layer) related to the formation position of a memory capacity will be described. FIG. 5 is a device cross-sectional view of AA ′ of FIG. 1 corresponding to FIG. FIG. 5 is a schematic enlarged sectional view of a memory capacitor peripheral sectional cutout region R2 of FIG. 4 for explaining the outline of the semiconductor integrated circuit device of the embodiment of the present application.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface;
(B) a memory area provided on the first main surface;
(C) a memory array area provided in the memory area;
(D) a memory capacitor forming insulating film layer provided on the first main surface;
(E) a memory capacitor formation hole formed in the memory array region from the upper surface of the memory capacitor formation insulating film layer toward the inside thereof;
(F) a metal plug protruding from the bottom surface of the memory capacity forming hole into the inside;
(G) a first lower electrode of a memory capacitor provided on the side surface and the bottom surface of the memory capacitor forming hole;
(H) a first capacitor insulating film of the memory capacitor provided on the side surface of the memory capacitor forming hole and on the first lower electrode;
(I) an upper electrode of the memory capacitor provided on the capacitor insulating film on the side surface of the memory capacitor forming hole;
Here, the memory capacity is not substantially formed on the upper and side surfaces of the metal plug.

  2. In the semiconductor integrated circuit device according to Item 1, the first lower electrode is formed on the upper surface and the side surface of the metal plug.

3. The semiconductor integrated circuit device according to Item 1 or 2 further includes the following:
(J) a second capacitor insulating film of the memory capacitor provided on the side electrode of the memory capacitor forming hole and on the upper electrode;
(K) A second lower electrode provided on the second capacitor insulating film on the side surface of the memory capacitor formation hole and connected to the first lower electrode.

  4). In the semiconductor integrated circuit device according to the item 3, the inside of the memory capacitor forming hole and the inside of the second lower electrode are substantially filled with an insulating member.

  5. In the semiconductor integrated circuit device according to any one of Items 1 to 4, the memory array region has a COB cell structure.

  6). In the semiconductor integrated circuit device according to any one of Items 1 to 5, the memory array region has a folded bit line layout.

  7). In the semiconductor integrated circuit device according to item 1, 2, 5, or 6, the inside of the memory capacitor forming hole and the inside of the upper electrode is substantially filled with an insulating member.

  8). In the semiconductor integrated circuit device according to any one of Items 1 to 7, the memory area is of a buried type DRAM.

  9. In the semiconductor integrated circuit device according to any one of Items 1 to 8, the memory capacity is a wiring layer intrusion memory capacity.

  10. In the semiconductor integrated circuit device according to any one of Items 1 to 9, the memory capacitor forming insulating film layer includes a wiring layer having a low-k silicon oxide based interlayer insulating film layer.

  11. In the semiconductor integrated circuit device according to Item 10, the low-k silicon oxide based interlayer insulating film layer is a porous low-k silicon oxide based interlayer insulating film layer.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). A silicon substrate) or a semiconductor chip packaged. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  The wafer process of today's semiconductor integrated circuit device, that is, LSI (Large Scale Integration), is usually considered in two parts. That is, the first is from the introduction of a silicon wafer as a raw material to the premetal process (formation of an interlayer insulation film between the lower end of the first layer wiring layer and the gate electrode structure, contact hole formation, tungsten plug, embedding, etc. FEOL (Front End of Line) process. The second is BEOL (Back End of) which starts from the formation of the first layer wiring layer and extends to the formation of the pad opening in the final passivation film on the aluminum-based pad electrode (including the process in the wafer level package process). Line) process.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OS), or OSG (Organic Silicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Although SiC has properties similar to SiN, SiON should be classified as a silicon oxide insulating film in many cases, but in the case of an etch stop film, it is close to SiC, SiN, or the like.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  Similarly, the term “nickel silicide” usually refers to nickel monosilicide, but includes not only relatively pure ones but also alloys, mixed crystals, and the like whose main components are nickel monosilicide. Further, the silicide is not limited to nickel silicide, but may be cobalt silicide, titanium silicide, tungsten silicide, or the like that has been proven in the past. In addition to the Ni (nickel) film, for example, a Ni-Pt alloy film (Ni and Pt alloy film), a Ni-V alloy film (Ni and V alloy film), A nickel alloy film such as a Ni—Pd alloy film (Ni—Pd alloy film), a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) is used. be able to. These silicides having nickel as a main metal element are collectively referred to as “nickel-based silicide”.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the “memory array area” refers to an area where memory cells are arranged in a matrix, and the “non-memory array area” refers to a “memory peripheral area” and a “non-memory area”. Here, the memory peripheral area refers to an area in the vicinity of the periphery of the memory array area where a sense amplifier, a word line driver, and the like are provided. The non-memory area refers to an area other than the target “memory area”, for example, an area provided with a logic area, another memory area, or the like.

  In addition, “low dielectric constant interlayer insulating film”, “Low-k interlayer insulating film” and the like are insulating materials having a lower dielectric constant than, for example, ordinary TEOS-based silicon oxide CVD films represented by SiOC, SiOCH, etc. Say the membrane. In particular, “porous low dielectric constant interlayer insulating film”, “porous low-k interlayer insulating film” and the like are structures derived from molecular porous, porogen, etc. Both porous (or physically porous).

  7). In the present application, when “insulating film layer for forming a memory capacitor” is used, a memory capacitor (basically a region composed of a lower electrode, a capacitor insulating film, and a portion actually acting as an upper electrode of the capacitor) is formed. A certain insulating film layer or layer group corresponding to the layer is shown.

  The “memory capacitor forming hole” is a hole having a circular, elliptical, or other horizontal cross section formed in the memory capacitor forming insulating film layer.

  Further, the “lower electrode of the memory capacitor” refers to a portion that is electrically connected to the metal plug regardless of the microscopic positional top and bottom. On the other hand, the “upper electrode of the memory capacitor” refers to an electrode facing the lower electrode. In the present application, the capacitor plate and the upper electrode have different concepts.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

  An example of a prior patent application disclosing a buried DRAM having a COB type memory array is, for example, Japanese Patent Application No. 2011-191983 (Japan filing date September 2, 2011).

1. Description of an example of an embedded DRAM (DRAM embedded logic device) in a semiconductor integrated circuit device according to an embodiment of the present application, that is, a memory capacity structure (simple cylinder type memory capacity structure) (mainly from FIG. 1 to FIG. 1) 5)
In the following example, a DRAM layout with a folded bit line (Folded Bitline) structure will be specifically described as an example, but it goes without saying that a DRAM layout with an open bit line (Open Bitline) structure may be used. In the following example, a so-called close packed folded bit line layout will be specifically described by way of example, but a so-called half pitch folded bit line layout may be used. Needless to say.

  In the following, specific description will be given mainly using an embedded DRAM as an example, but it is needless to say that a dedicated DRAM may be used.

  In the present application, the display of impurity structures such as a well region and a source / drain region in a semiconductor substrate is omitted in principle in order to avoid complexity.

  Further, in the following cross-sectional views, when only a portion having a different structure cannot be cut out because of a repeated structure (including a target structure), a part of the repeated portion is omitted as appropriate.

  FIG. 1 is a semiconductor for explaining an example of a device structure of an embedded DRAM (DRAM embedded logic device) in a semiconductor integrated circuit device according to an embodiment of the present application, that is, a memory capacity structure (simple cylinder memory capacity structure). It is the whole chip top view. FIG. 2 is a schematic circuit diagram of the memory area 3 of FIG. FIG. 3 is a plan layout diagram of the memory area corner portion peripheral cutout area R1 of FIG. FIG. 4 is a device sectional view substantially corresponding to the A-A ′ section of FIG. 1. FIG. 5 is an enlarged cross-sectional view of the memory capacity peripheral cross-sectional cutout region R2 of FIG. Based on these, a device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device of one embodiment of the present application, that is, a memory capacity structure (simple cylinder memory capacity structure) and the like will be described.

  First, as shown in FIG. 1, the upper surface 1 a of the semiconductor chip 2 can generally be divided into a chip peripheral region 5 and a chip internal region 6 in many cases. A memory region 3 such as a DRAM region is provided in the internal region 6 of the upper surface 1a of the semiconductor chip 2, and other non-memory regions 4g include, for example, a CMOS logic circuit region (logic region), analog A circuit area, another memory area (SRAM area, nonvolatile memory area), an I / O circuit area, an electrode pad formation area, and the like are provided. The memory area 3 is divided into a memory array area 3c in which unit memory cells UC (see FIG. 2, the same applies hereinafter) are spread in a matrix and a peripheral memory peripheral area 3p. In the memory peripheral area 3p, for example, memory peripheral circuits such as sense amplifiers SA1 and SA2 (see FIG. 2, the same applies hereinafter), word line drivers WD1, WD2, WD3, and WD4 are provided. The memory peripheral area 3p and the non-memory area 4g are collectively referred to as a non-memory array area 4. A device is provided in the internal region 6 of the upper surface 1 a of the semiconductor chip 2.

  Next, FIG. 2 shows a schematic circuit diagram of the memory area 3 of FIG. As shown in FIG. 2, in the memory array region 3c, a plurality of word lines WL1, WL2, WL3, WL4 are provided in the vertical direction, and a plurality of bits are orthogonally crossed in the horizontal direction. Lines BL1, BL2, BL3, and BL4 are provided. In this example, for example, the word lines WL1, WL2, WL3, WL4 are alternately controlled by word line drivers WD1, WD2, WD3, WD4 arranged in the memory peripheral area 3p on the opposite side of the memory array area 3c. ing. On the other hand, every other bit line BL1, BL2, BL3, BL4 forms a pair, and the sense amplifiers SA1, SA1 are alternately arranged in the memory peripheral region 3p on the opposite side of the memory array region 3c. Connected to SA2. Note that the arrangement of the word line drivers WD1, WD2, WD3, and WD4, the arrangement of the sense amplifiers SA1 and SA2, and the pair formation method of the bit lines BL1, BL2, BL3, and BL4 are not limited to those shown here. Not too long.

  Near a predetermined intersection of the word lines WL1, WL2, WL3, WL4 and the bit lines BL1, BL2, BL3, BL4, N-type MISFETs (access transistors) Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 and A unit memory cell UC composed of pairs of memory capacitors C1, C2, C3, C4, C5, C6, C7, and C8 is connected to each bit line and each word line. Here, one terminal of each of the memory capacitors C1, C2, C3, C4, C5, C6, C7, and C8 is connected to a plate potential Vp (in the half precharge method, an intermediate potential that is 1/2 of the power supply potential). ing.

  Next, FIG. 3 shows an enlarged plan view of the memory region corner portion peripheral cutout region R1 of FIG. As shown in FIG. 3, a plurality of active areas AC in the memory array are provided in a matrix on the surface 1a (first main surface) of the semiconductor substrate 1s. Here, an area other than the active area AC in the memory array is, for example, an STI (Shallow Trench Isolation) area 7 (element isolation area).

  On the surface 1a of the semiconductor substrate 1s, for example, a plurality of word lines WL are arranged in the vertical direction, and a plurality of bit lines BL are arranged in the horizontal direction so as to be substantially orthogonal to each other. A bit line contact W plug 12 is provided below these bit lines BL and in a predetermined portion on the active area AC in the memory array. On the other hand, a capacitor contact W plug 14 is provided in the vicinity of a predetermined intersection of the plurality of word lines WL and the plurality of bit lines BL, and on the active area AC in the memory array. A lower electrode 32 is provided. Above these capacitor lower electrodes 32, a capacitor plate 35 is provided so as to substantially cover the memory array region 3c.

  Next, FIG. 4 shows a chip cross-sectional view corresponding to the A-A ′ cross section of FIG. 1. As shown in FIG. 4, on the surface 1a (first main surface) side of the semiconductor substrate portion 1s (for example, P-type single crystal silicon substrate portion), that is, on the surface side opposite to the back surface 1b (second main surface). The device is mainly formed.

  The surface 1a of the semiconductor substrate portion 1s is a premetal layer PM, and in this example, it is composed of, for example, three layers of premetal insulating films 26a, 26b, and 26c. When these layers are particularly distinguished, they are referred to as a premetal layer lower layer P1, a premetal layer intermediate layer P2, and a premetal layer upper portion P3, respectively.

  The premetal insulating film 26a is composed of, for example, a silicon nitride film as a relatively thin etch stop film in the lower layer and a relatively thick silicon oxide insulating film in the upper layer. As this silicon oxide-based insulating film, for example, a non-Low-k insulating film made of HDP (High Density Plasma) can be exemplified as a suitable one. The premetal insulating film 26b is composed of, for example, a relatively thin premetal auxiliary insulating film 26bb as a lower layer and a relatively thick premetal main insulating film 26ba as an upper layer. Here, the premetal auxiliary insulating film 26bb is, for example, a non-low-k silicon oxide insulating film by TEOS-based plasma CVD, and the premetal auxiliary insulating film 26bb is, for example, non-low by HDP (High Density Plasma). A -k silicon oxide insulating film or the like can be exemplified as a preferable one. Further, as the premetal insulating film 26c, for example, a non-low-k silicon oxide insulating film formed by TEOS-based plasma CVD can be exemplified as a preferable one.

  In the premetal insulating film 26a, a bit line contact W plug 12 (for example, substantially cylindrical shape), a capacitance contact W plug 14a (for example, substantially cylindrical shape), a wiring contact W plug 15a, and the like are embedded. These tungsten plugs have, for example, a titanium film and a titanium nitride film from the lower layer as barrier metal films and the like. However, since they are complicated, they are not mentioned unless particularly necessary. This also applies to tantalum-based barrier films (such as tantalum nitride films) and titanium-based barrier films (such as titanium nitride films) related to copper-embedded wiring.

  Similarly, in the premetal insulating film 26b, the capacitor contact W plug 14b (for example, substantially cylindrical shape), the wiring contact W plug 15b, and the bit line BL (for example, non-embedded wiring) (for example, a tungsten film) Embedded wiring).

  Further, a wiring contact W plug 15 c is embedded in the premetal insulating film 26 c in the non-memory array region 4.

  On the premetal layer PM, there is a multi-layer embedded metal wiring layer M. For example, a first embedded metal wiring layer M1, a second embedded metal wiring layer M2, a third embedded metal wiring layer M3, and a fourth embedded layer. It is composed of a metal wiring layer M4, a fifth-layer buried metal wiring layer M5, and the like (further upper-layer wiring is not described because it is repeated).

  As the structure of the insulating film of each multilayer wiring layer, that is, the buried wiring interlayer insulating films 29a, 29b, 29c, 29d, and 29e, for example, a relatively thin insulating diffusion barrier film (for example, SiCN film) of the lower layer and an upper layer A relatively thick Low-k silicon oxide-based main interlayer insulating film (for example, a SiOC film) can be exemplified as a preferable one. In this example, for example, the low-k silicon oxide main interlayer insulating film of the buried wiring interlayer insulating film 29a is a non-porous low-k silicon oxide-based insulating film (for example, a non-porous SiOC film). This is to ensure the workability of the fine wiring. On the other hand, the low-k silicon oxide-based main interlayer insulating film of the buried wiring interlayer insulating films 29b, 29c, 29d, 29e is used as a porous low-k silicon oxide-based insulating film (for example, a molecular porous SiOC film, the same applies hereinafter). Yes. The low-k silicon oxide main interlayer insulating film of the buried wiring interlayer insulating film 29a may be, for example, a porous low-k silicon oxide-based insulating film (for example, a porous SiOC film). The porous low-k silicon oxide insulating film is not limited to a molecular porous film but may be a porous film having other attributes. However, the molecular porous membrane has advantages such as higher permeation-preventing ability of undesired ions, gases and other components.

  In the embedded wiring interlayer insulating film 29a in the non-memory array region 4, the first layer embedded metal wiring 21 is embedded. These first-layer embedded metal wirings 21 are copper-based embedded wirings by, for example, a single damascene method.

  Similarly, in the embedded wiring interlayer insulating film 29b in the non-memory array region 4, the second layer embedded metal wiring 22 (including vias) is embedded. These second-layer embedded metal wirings 22 are copper-based embedded wirings by, for example, a dual damascene method.

  Further, in the embedded wiring interlayer insulating film 29c in the memory array region 3c and the non-memory array region 4, the third layer embedded metal wiring 23 (including vias) is embedded. These third layer embedded metal wirings 23 are copper-based embedded wirings by, for example, a dual damascene method.

  Similarly, in the embedded wiring interlayer insulating film 29d in the memory array region 3c and the non-memory array region 4, a fourth layer embedded metal wiring 24 (including vias) is embedded. These fourth-layer embedded metal wirings 24 are copper-based embedded wirings by, for example, a dual damascene method. The same applies to the buried wiring interlayer insulating film 29e.

  In this example, for example, the memory capacitor C is embedded in the insulating film from the premetal insulating film 26b to the embedded wiring interlayer insulating film 29b in the memory array region 3c, that is, the memory capacitor forming insulating film layer 8. The memory capacitor C (this portion corresponds to the memory capacity forming hole 39 in FIG. 7) has, for example, a so-called MIM (Metal Insulator Metal) structure, and the capacitor lower electrode 32 (FIG. 5) divided into individual electrodes. Is at the bottom. A capacitive insulating film 33 (for example, a zirconium oxide film) is formed on the lower electrode 32, on which a capacitive upper electrode 34 (see FIG. 5) and a capacitive plate 35 (tungsten) covering the upper part integrally therewith. Membrane). The capacitive insulating film 33 may be a single-layer film of alumina, tantalum oxide or the like, or a composite film thereof other than the zirconium oxide film.

  Note that the multi-layer wiring layer intrusion memory capacity structure as shown in FIG. 4 can reduce the thickness of the premetal layer PM and is effective in reducing the resistance of the wiring contact W plugs 15a, 15b, and 15c. is there. This is because, in the COB type cell structure, in particular, when the memory capacity C is to be included in the premetal layer PM, its thickness tends to become extremely hot. In the embedded DRAM, it is necessary for the semi-global wiring of the middle layer and the global wiring of the upper layer to penetrate the memory array region 3c, but the local wiring of the lower layer is not necessary. Therefore, for example, even if the memory capacitor C is inserted into the lower local wiring layer, no wiring problem occurs. Needless to say, if no wiring problem occurs, the memory capacitor C may be penetrated to the middle semi-global wiring layer.

  Next, FIG. 5 shows an enlarged cross-sectional view of the memory capacity peripheral cross-sectional cutout region R2 of FIG. As shown in FIG. 5, the capacitor contact W plug 14b extends upward from the lower part of the memory capacitor forming insulating film layer 8 and protrudes from the bottom of the capacitor hole 39 (memory capacitor forming hole) to the inside. The bottom surface of the capacitor hole 39, the upper surface 14bt of the capacitor contact W plug 14b, the portion of the side surface of the capacitor contact W plug 14b that protrudes into the capacitor hole 39, and almost the entire side surface of the capacitor hole 39 (in this example, the vicinity of the upper end) The capacitor lower electrode 32 (first lower electrode) is provided. As a material of the capacitor lower electrode 32, for example, a titanium nitride film or the like can be exemplified as a suitable material.

  A capacitor insulating film 33 (first capacitor insulating film) is formed on almost the entire side surface of the capacitor hole 39 including on the capacitor lower electrode 32. In this example, a part of the bottom surface of the capacitor hole 39 is There is a capacitive insulating film remaining portion 33d remaining at the time of etching.

  A capacitor upper electrode 34 is formed on the capacitor insulating film 33 over almost the entire side surface of the capacitor hole 39. In this example, the capacitor upper portion remaining at the time of etching on a part of the bottom surface of the capacitor hole 39 is formed. There is an electrode remaining portion 34d. As a material of the capacitor upper electrode 34, for example, a titanium nitride film or the like can be exemplified as a suitable material. Note that the capacitive insulating film residual portion 33d and the capacitive upper electrode residual portion 34d are not part of the memory capacitor C in terms of function. Accordingly, in this example, the memory capacitor C is not provided on the side surface 14bs extending from the bottom surface of the capacitor hole 39 (memory capacity forming hole) to the upper surface 14bt of the capacitor contact W plug 14b. In other words, although there is the capacitor lower electrode 32 in the inner region of the bottom surface of the capacitor hole 39, the capacitor insulating film 33 and the capacitor upper electrode 34 are not substantially present.

  It should be noted that either or both of the capacitive insulating film remaining portion 33d and the capacitive insulating film remaining portion 33d are preferably removed, and may be removed. However, the process may be complicated accordingly.

  The capacitor hole 39 inside the capacitor upper electrode 34 is substantially filled with, for example, a non-Low-k silicon oxide insulating film. However, partial voids 7 and the like are allowed. However, since it is preferable not to have the void 7, it may be completely filled. However, the process is complicated accordingly.

  On the upper surface of each capacitor hole 39 and on the almost entire memory capacitance forming insulating film layer 8 of the memory array region 3c, an integrated capacitor plate base metal film 9 (acts as a part of the capacitor plate or a barrier film). Is provided. As a material of the capacitor plate base metal film 9, for example, a titanium nitride film or the like can be exemplified as a suitable material.

  An integral capacitor plate 35 is provided on the capacitor plate base metal film 9 on the upper surface of each capacitor hole 39 and almost the entire surface of the memory array region 3c. As a material of the capacity plate 35, for example, a tungsten film or the like (in addition, copper, aluminum, copper-added aluminum, or the like) can be exemplified as a suitable material.

  In order to clarify a specific image of the memory capacity C, an example of the dimensions of the main part is as follows, for example. That is, the diameter of the capacitor hole 39 is, for example, about 150 nm, the same depth is, for example, about 400 nm, the diameter of the metal plug 14b is, for example, about 70 nm, and the protruding length is, for example, about 10-20 nm. The thickness of the lower electrode 32 is, for example, about 5 nm, the thickness of the capacitive insulating film 33 is, for example, about 7 nm, and the thickness of the capacitive upper electrode 34 is, for example, about 15 to 30 nm. The receding length of the upper end of the capacitor lower electrode 32 from the upper end of the capacitor hole 39 is, for example, about 40 nm.

  Here, in this example, the capacitor-embedded insulating member 10 ensures insulation between the capacitor electrodes.

  In the case of a cylinder type (substantially elliptic cylinder shape in this example) memory capacitor, when the capacitor hole 39 (capacity cylinder) is formed, the upper end of the capacitor contact W plug 14b (metal plug) protrudes from the bottom surface of the capacitor hole 39. Thus, it is common to perform overetching. Theoretically, the etching may be stopped (so-called just etching) so that the bottom surface of the capacitor hole 39 and the top surface of the capacitor contact W plug 14b are the same surface. Due to this variation, the just etch inevitably generates a large amount of the insulating film remaining on the upper surface of the capacitor contact W plug 14b. This is inconvenient because the memory capacitor C (see FIG. 4) and the capacitor contact W plug 14b become non-conductive. Usually, the memory contact C is slightly over-etched so that the upper surface of most of the capacitor contact W plug 14b is a capacitor hole. It processes so that it may protrude from the bottom face of 39. In such a memory capacitor C (see FIG. 4) connected to the protruding metal plug, uniform capacitance insulation is provided on the upper surface 14bt and the side surface 14bs of the capacitor contact W plug 14b and the periphery thereof (part where uniform film formation is difficult). It is difficult to form the film 33 and the capacitor upper electrode 34. Therefore, in this example, the memory capacity C (see FIG. 4) is not formed in this uniform film formation difficult portion. “Preventing the formation of the memory capacitor” means that the memory capacitor lower electrode, the memory capacitor insulating film, and the memory capacitor upper electrode are not arranged in this portion. In this example, as an example, although there is a memory capacitor lower electrode in a portion where uniform film formation is difficult, the memory capacitor insulating film and the memory capacitor upper electrode are not present. This reduces memory capacity leakage and improves refresh characteristics. In general, the reliability of the device can be improved.

2. Description of an example of a main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 6 to 15)
It goes without saying that the manufacturing process described in this section is an example corresponding to the device structure described in Section 1 and can be variously changed. In addition, this manufacturing process is basically applicable to the structures of sections 3 and 5 almost as they are, so that the manufacturing process for them will not be repeatedly described in principle.

  FIG. 6 is a wafer cross-sectional view (resist film processing step for forming capacitor holes) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. . FIG. 7 is a wafer cross-sectional view (capacitor hole forming step) corresponding to FIG. 5 during the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. 8 is a wafer cross-sectional view (capacitor lower electrode film forming step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 9 is a wafer cross-sectional view (resist film patterning step for processing the capacitor lower electrode) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of the one embodiment of the present application. is there. FIG. 10 is a wafer cross-sectional view (capacitor lower electrode processing step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 11 is a wafer cross-sectional view (capacitor upper electrode film forming step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. 12 is a wafer cross-sectional view (capacitor upper electrode processing step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 13 is a cross-sectional view of the wafer (in-capacitor insulating film embedding step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device of one embodiment of the present application. 14 is a wafer cross-sectional view (in-capacitor embedded insulating film planarization step) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention. . FIG. 15 is a wafer cross-sectional view (capacitor plate deposition process) corresponding to FIG. 5 in the middle of the process for explaining an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application. Based on these, an example of the main part of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the outline of the process leading to FIG. 6 will be outlined with reference to FIG. As shown in FIG. 4, for example, a P-type single crystal silicon wafer 1 (the wafer diameter is about 300 millimeters, for example, other wafer systems may be used) is prepared, and the FEOL process is completed. Thereafter, a non-low-k silicon oxide insulating film 26bb is formed on the premetal insulating film 26a by, for example, plasma CVD, and a bit line connection hole is formed by, for example, ordinary lithography. Next, for example, a titanium nitride film and a tungsten film are sequentially deposited by, for example, CVD (ordinary CVD, MOCVD, ALD, sputtering film formation including ionized sputtering, etc.), and a tungsten-based bit is formed by ordinary lithography. The line BL is patterned. Thereafter, a non-low-k silicon oxide insulating film 26ba is formed on the non-low-k silicon oxide insulating film 26bb and the tungsten bit line BL by, for example, HDP-CVD. Next, a plug buried hole is formed in the non-low-k silicon oxide insulating film 26b by, for example, ordinary lithography, and a titanium nitride film and a tungsten film, for example, are sequentially deposited by CVD or the like, and are formed outside the plug buried hole. The metal member is removed by, for example, CMP. Thereby, the capacitor contact W plug 14b and the wiring contact W plug 15b are formed. Next, a premetal insulating film 26c made of a relatively thin SiON film, a relatively thick non-low silicon oxide insulating film 26c, etc. is formed on the non-Low-k silicon oxide insulating film 26b by, for example, plasma CVD. Film. Thereafter, the wiring contact W plug 15c is embedded as in the previous case. Next, an embedded wiring interlayer insulating film 29a made of a relatively thin SiCN film and a relatively thick non-porous SiOC film is formed on the premetal insulating film 26c by, for example, plasma CVD. Next, a wiring groove is formed by, for example, ordinary lithography, and a first layer embedded metal wiring 21 made of, for example, a tungsten nitride barrier film and a copper wiring film is formed by, for example, a single damascene method. Next, an embedded wiring interlayer insulating film 29b made of a relatively thin SiCN film and a relatively thick porous SiOC film is formed on the embedded wiring interlayer insulating film 29a, for example, by plasma CVD. Next, when a wiring trench is formed by, for example, ordinary lithography, and a second layer embedded metal wiring 22 made of, for example, a tungsten nitride barrier film and a copper wiring film is formed by, for example, a dual damascene method, the state of FIG. It becomes.

  Next, as shown in FIG. 6, a capacitor hole forming resist film 44 is formed on the memory capacitor forming insulating film layer 8 by ordinary lithography or the like.

  Next, as shown in FIG. 7, a capacitor hole 39 (memory capacity forming hole) is formed by, for example, anisotropic dry etching using a fluorocarbon-based etching gas. Thereafter, the capacitor hole forming resist film 44 which has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 8, a TiN film 32 is formed on almost the entire surface including the inner surface of the capacitor hole 39 on the surface 1a side by MOCVD (Metal Organic CVD) or ALD (Atomic Layer Deposition), for example. Form a film.

  Next, as shown in FIG. 9, for example, a positive resist is applied to almost the entire surface of the wafer 1 on the surface 1a side, exposed to the entire surface, and developed. The film 45 remains.

  Next, as shown in FIG. 10, the TiN film 32 above and outside the capacitor hole 39 is removed by, for example, dry etching back in the presence of the residual resist film 45. Thereafter, the residual resist film 45 that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 11, a zirconium oxide film 33 is formed almost entirely on the surface 1a side of the wafer 1 by, for example, ALD. Next, a TiN film 34 is formed on almost the entire surface of the zirconium oxide film 33 by, for example, ALD or MOCVD.

Next, as shown in FIG. 12, when etching back is performed on almost the entire surface on the surface 1a side of the wafer 1 by anisotropic dry etching using, for example, an etching gas based on BCl ₃ , a horizontal portion is obtained. The TiN film 34 and the zirconium oxide film 33 are almost removed.

  Next, as shown in FIG. 13, for example, a plasma TEOS-based non-low-k silicon oxide insulating film 10 is formed on almost the entire surface 1 a side of the wafer 1 to fill the capacitor hole 39.

  Next, as shown in FIG. 14, the plasma TEOS non-low-k silicon oxide insulating film 10 outside the capacitor hole 39 is removed by performing a dry etch back process using, for example, a fluorocarbon etching gas or the like. To do.

  Next, as shown in FIG. 15, a relatively thin titanium nitride film 9 is formed on almost the entire surface of the wafer 1 on the surface 1a side by, for example, sputtering film formation. Subsequently, a relatively thick tungsten film 35 is formed on almost the entire surface of the titanium nitride film 9 by, for example, thermal CVD.

  Thereafter, as shown in FIG. 4, the titanium nitride film 9 and the tungsten film 35 are patterned by, for example, ordinary lithography (for example, including anisotropic dry etching). Next, an embedded wiring interlayer insulating film 29c made of a relatively thin SiCN film and a relatively thick porous SiOC film is formed on the embedded wiring interlayer insulating film 29b by, for example, plasma CVD. Next, a wiring trench is formed by, for example, ordinary lithography, and a third layer embedded metal wiring 23 made of, for example, a tungsten nitride barrier film and a copper wiring film is formed by, for example, a dual damascene method. Next, an embedded wiring interlayer insulating film 29d made of a relatively thin SiCN film and a relatively thick porous SiOC film is formed on the embedded wiring interlayer insulating film 29c by, for example, plasma CVD. Next, a wiring trench is formed by, for example, ordinary lithography, and a fourth layer embedded metal wiring 24 made of, for example, a tungsten nitride barrier film and a copper wiring film is formed by, for example, a dual damascene method. Next, a buried wiring interlayer insulating film 29e made of a relatively thin SiCN film and a relatively thick porous SiOC film is formed on the buried wiring interlayer insulating film 29d by, for example, plasma CVD.

  Thereafter, in the same procedure, an uppermost buried metal wiring layer is formed from the fifth buried metal wiring layer M5, and subsequently an underpad interlayer insulating film is formed, and an upper tungsten layer is formed in the same manner as the premetal region PM. Embed the plug. Further, an aluminum-based metal electrode pad is formed on the interlayer insulating film below the pad as a part of the non-embedded wiring. Next, a non-low-k silicon oxide insulating film is formed on the interlayer insulating film under the pad and the aluminum metal electrode pad, for example, by plasma CVD or the like. A pad opening is formed. Thereafter, when it is divided into chips 2 by dicing or the like, it becomes as shown in FIG.

3. Description of a device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure (mainly (Fig. 16)
The example described in this section is a modification example of the structure of the memory capacity described in FIG. 5 and is basically based on the same basic structure. Therefore, only different parts will be described below in principle.

  FIG. 16 illustrates an example of a device structure of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (multi-cylinder memory capacity structure) of the memory capacity structure. FIG. 6 is an enlarged cross-sectional view of a memory capacity peripheral cross-sectional cutout region R2 of FIG. 4 corresponding to FIG. Based on this, a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device of the embodiment of the present application, that is, a modified example of a memory capacity structure (multi-cylinder memory capacity structure), etc. Will be explained.

  As shown in FIG. 16, the difference from FIG. 5 is that two capacitor lower electrodes, a capacitor lower electrode 32 (first lower electrode) and a capacitor lower additional electrode 42 (second lower electrode) are prepared. It is. The lower capacitor additional electrode 42 is provided on the additional capacitor insulating film 43 (second capacitor insulating film) provided on the upper capacitor electrode 34 and on the lower capacitor electrode 32. The capacitor lower additional electrode 42 is electrically connected to the capacitor lower electrode 32.

  For this reason, compared with the structure of FIG. 5, the capacity | capacitance near twice can be obtained. However, the process becomes complicated accordingly.

  Similarly to the structure of FIG. 5, this structure also has a memory capacitor lower electrode (capacitor lower electrode 32 and capacitor lower additional electrode 42) in a portion where uniform film formation is difficult. The capacitor insulating film 43) and the memory capacitor upper electrode are not present. As a result, the reliability of the device can be improved.

  In order to clarify a specific image of the memory capacity C, an example of the dimensions of the main part is as follows, for example. That is, the diameter of the capacitor hole 39 is, for example, about 150 nm, the same depth is, for example, about 400 nm, the diameter of the metal plug 14b is, for example, about 70 nm, and the protruding length is, for example, about 10-20 nm. The thickness of the lower electrode 32 is, for example, about 5 nm, the thickness of the capacitive insulating film 33 is, for example, about 7 nm, and the thickness of the capacitive upper electrode 34 is, for example, about 5 to 10 nm. The receding length of the upper end of the capacitor lower electrode 32 from the upper end of the capacitor hole 39 is, for example, about 40 nm.

  Further, the thickness of the additional capacitor insulating film 43 is, for example, about 7 nm, and the thickness of the lower capacitor additional electrode is, for example, about 15 to 30 nm.

  Here, in this example, the capacitor-embedded insulating member 10 ensures insulation between the capacitor electrodes.

4). In the semiconductor integrated circuit device of the one embodiment of the present application, an example of a device structure of an embedded DRAM (DRAM-embedded logic device), that is, a main part of a manufacturing process for a modified example (multi-cylinder memory capacity structure) related to a memory capacity structure Explanation of an example (mainly FIGS. 17 to 24)
The process in this section is a manufacturing method for the structure described in Section 3 and is a modification of the process described in Section 2 and is basically the same as the process in Section 2. Therefore, in the following, only different parts will be described in principle. For example, the processes of FIGS. 6 to 12 are exactly the same, FIG. 13 corresponds to FIG. 22, FIG. 14 corresponds to FIG. 23, and FIG. As a flow, FIG. 17 to FIG. 24 come after FIG.

  FIG. 17 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (additional capacitance insulating film forming step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 18 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present invention, that is, a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (additional capacity insulating film processing step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 19 shows an example of a device structure of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present invention, that is, a manufacturing process for a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (capacitor lower additional electrode film forming step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 20 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modification regarding a memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (resist film processing step for processing a capacitor lower additional electrode) corresponding to FIG. 16 in the middle of the process for describing an example of a main part; FIG. 21 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (capacitor lower additional electrode processing step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 22 shows an example of a device structure of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present invention, that is, a manufacturing process for a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (in-capacitor insulating film embedding step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 23 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present invention, that is, a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (in-capacitance embedded insulating film planarization step) corresponding to FIG. 16 in the middle of the process for describing an example of the main part. FIG. 24 shows a manufacturing process for a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example of the memory capacity structure (multi-cylinder memory capacity structure). FIG. 17 is a wafer cross-sectional view (capacitor plate deposition process) corresponding to FIG. 16 in the middle of the process for explaining an example of the main part. Based on these, the device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modification regarding the memory capacity structure (multi-cylinder memory capacity structure) An example of the main part of the manufacturing process will be described.

  Similar to section 2, the process of FIG. 17 is performed on wafer 1 on which the processes of FIGS. 6 to 12 have been completed. As shown in FIG. 17, a zirconium oxide film 43 is formed on almost the entire surface 1a of the wafer 1 including the inner surface of the capacitor hole 39 (memory capacity forming hole) by, for example, MOCVD or ALD.

Next, as shown in FIG. 18, when etch back is performed on almost the entire surface 1a of the wafer 1 by anisotropic dry etching using a BCl ₃ based etching gas, a horizontal portion (horizontally The zirconium oxide film 43 (including the close portion) is removed. At this time, the capacitor upper electrode remaining portion 34d and the capacitor insulating film remaining portion 33d are also removed at the same time.

  Next, as shown in FIG. 19, a titanium nitride film 42 is formed on almost the entire surface 1a of the wafer 1 including the inner surface of the capacitor hole 39 (memory capacity forming hole) by, for example, MOCVD or ALD.

  Next, as shown in FIG. 20, for example, a positive resist is applied to almost the entire surface on the surface 1a side of the wafer 1, and the entire surface is exposed and developed. The resist film 46 remains.

  Next, as shown in FIG. 21, the TiN film 42 above and outside the capacitor hole 39 is removed by, for example, dry etching back in the presence of the residual resist film 46. Thereafter, the residual resist film 46 that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 22, for example, a plasma TEOS-based non-Low-k silicon oxide insulating film 10 is formed on almost the entire surface 1 a side of the wafer 1 to fill the capacitor hole 39.

  Next, as shown in FIG. 23, the plasma TEOS non-low-k silicon oxide insulating film 10 outside the capacitor hole 39 is removed by performing a dry etch back process using, for example, a fluorocarbon etching gas or the like. To do.

  Next, as shown in FIG. 24, a relatively thin titanium nitride film 9 is formed on almost the entire surface of the wafer 1 on the surface 1a side by, for example, sputtering film formation. Subsequently, a relatively thick tungsten film 35 is formed on almost the entire surface of the titanium nitride film 9 by, for example, thermal CVD.

  After that, it is exactly the same as described in Section 2.

5. Description of a device structure of an example of an embedded DRAM (DRAM embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (memory capacity structure in a premetal layer) regarding a position where a memory capacity is formed ( Mainly Fig. 25)
In the example described in this section, a modification (memory capacity structure in the premetal layer) related to the formation position of the memory capacity with respect to the example (multilayer wiring layer intrusion memory capacity structure) described in FIG. 4 will be described. Therefore, it is basically the same as that described with reference to FIG. 4, and in the following, only different parts will be described in principle.

  As the memory capacity structure, either FIG. 5 or FIG. 16 may be adopted. Hereinafter, a specific description will be given based on the structure of FIG.

  FIG. 25 shows an example of a device structure of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device according to the embodiment of the present application, that is, a modified example (memory capacity structure in a premetal layer) related to the formation position of a memory capacity, etc. FIG. 5 is a device cross-sectional view taken along the line AA ′ of FIG. 1 corresponding to FIG. Based on this, a device structure of an example of an embedded DRAM (DRAM-embedded logic device) in the semiconductor integrated circuit device of the one embodiment of the present application, that is, a modified example regarding a memory capacitor formation position (memory capacity structure in a premetal layer) ) Etc.

  As shown in FIG. 25, the difference from FIG. 4 is that the layer in which the memory capacity C is provided is included in the premetal layer PM. In terms of manufacturing, after the formation of the premetal insulating film 26c, the formation of the memory capacitor C is started. After the patterning of the capacitor plate 35, the upper surface is covered with the cap insulating film 26d (non-low-k film silicon oxide insulating film). After the planarization, the wiring contact W plug 15c is embedded, and subsequently, the formation of the multilayer embedded wiring is started, but the other points are basically the same.

  In this memory capacity structure in the premetal layer, the memory capacity C is formed in the premetal layer PM that does not use the low-k film. Therefore, undesired ions and gases caused by etching or the like when the memory capacity C is formed. There is a merit that components and other ripples to the non-memory array region 4 can be avoided. On the other hand, the multilayer wiring layer interstitial memory capacity structure can reduce the thickness of the premetal layer PM and is effective in reducing the resistance of the wiring contact W plugs 15a, 15b, and 15c.

6). Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIG. 26)
26 is a schematic enlarged sectional view of the memory capacitor peripheral sectional cutout region R2 of FIG. 4 for explaining the outline of the semiconductor integrated circuit device according to the embodiment of the present application. Based on this, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Description of outline of semiconductor integrated circuit device of one embodiment:
As shown in FIG. 26, the memory capacity C described in FIG. 5 and the like is basically in a capacitor hole 39 (memory capacity forming hole) formed from the upper surface of the memory capacity forming insulating film layer 8 to the inside. An area 16 having no memory capacity is formed on the upper surface 14bt and the side surface 14bs of the metal plug 14b protruding from the bottom surface. In other words, substantially no memory capacity is formed on the upper surface 14bt and the side surface 14bs of the metal plug 14b.

(2) Consideration of problems peculiar to embedded DRAM:
Generally, in a dedicated DRAM, silicidation of the source and drain of a MISFET in a memory cell is avoided to reduce leakage in the memory array (referred to as “non-silicided memory array”). However, in each of the above-described embodiments (including modifications), for example, a nickel-based silicide layer is formed on the source and drain of the MISFET in the memory cell (of course, non-silicide) as in the peripheral circuit and the logic circuit. It goes without saying that a memory array can be used). This is referred to as a “silicided memory array”. Therefore, in this silicidated memory array, ensuring refresh characteristics is an important issue compared to a non-silicided memory array. For this purpose, the height of the memory capacitor C is desired to be sufficiently high. However, if this is done, the wiring contact W plugs 15a, 15b, and 15c become long, and the operation of the logic circuit and the like deteriorates. In order to solve this problem, it is only necessary to increase the intrusion height by adopting a multi-layer wiring layer intrusive memory capacity structure. However, there is a limit inherent in the embedded DRAM, and it passes over the memory array. It is difficult to eliminate global wiring and the like. Then, it is necessary to eliminate the capacity leak derived from the memory structure as much as possible. Each structure of each embodiment (including the modified example) described in the sections 1, 3 and 5 is effective in eliminating a capacity leak resulting from this type of memory structure.

7). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the specific description has been given mainly by taking the embedded metal wiring as an example. However, the present invention is not limited to this, and non-embedded metal wiring such as aluminum-based metal wiring is used. Needless to say, it can also be applied to the used ones.

  Further, in the above-described embodiment, the description has been specifically given mainly by taking the case of forming a device on a P-type single crystal silicon substrate as an example. However, the present invention is not limited to this, and N-type or It goes without saying that it may be formed on various semiconductor layers on a P-type silicon single crystal substrate, various N-type or P-type epitaxial substrates, insulating substrates (including SOI substrates) and other semiconductor substrates. Absent.

1 Semiconductor wafer 1a Wafer or chip surface (device main surface or first main surface)
1b Back surface of wafer or chip (second main surface)
1s Semiconductor substrate (P-type single crystal silicon substrate)
2 Semiconductor chip or chip area 3 Memory area 3c Memory array area 3p Memory peripheral area 4 Non-memory array area 4g Non-memory area 5 Chip peripheral area 6 Chip internal area 7 Void 8 Insulating film layer for forming memory capacity
9 Capacitor base metal film 10 Capacitor internal buried insulating member 12 Bit line contact W plug 14a, 14b Capacitor contact W plug 14bs Capacitor contact W plug side face 14bt Capacitor contact W plug upper surface 15a, 15b, 15c Wiring contact W plug 16 Memory capacity No area 21 First layer embedded metal wiring 22 Second layer embedded metal wiring (including vias)
23 Third layer buried metal wiring (including vias)
24 4th layer embedded metal wiring (including vias)
26a, 26b, 26c Premetal insulating film 26ba Premetal main insulating film 26bb Premetal auxiliary insulating film 26d Cap insulating film 29a, 29b, 29c, 29d, 29e Embedded wiring interlayer insulating film 32 Capacitor lower electrode (first lower electrode)
33 capacitive insulating film (first capacitive insulating film)
33d Capacitor insulating film remaining portion 34 Capacitor upper electrode 34d Capacitor upper electrode remaining portion 35 Capacitor plate 39 Capacitor hole (memory capacitor forming hole)
42 Capacitor lower additional electrode (second lower electrode)
43 Additional capacitor insulating film (second capacitor insulating film)
44 Capacitor hole forming resist film 45 Capacitor lower electrode processing resist film 46 Capacitor lower additional electrode processing resist film AC Active area in memory array BL, BL1, BL2, BL3, BL4 Bit lines C, C1, C2, C3, C4 , C5, C6, C7, C8 Memory capacitor M Multilayer embedded metal wiring layer M1 First layer embedded metal wiring layer M2 Second layer embedded metal wiring layer M3 Third layer embedded metal wiring layer M4 Fourth layer embedded metal wiring layer M5 First 5-layer buried metal wiring layer P1 Pre-metal layer lower layer P2 Pre-metal layer intermediate layer P3 Pre-metal layer upper layer PM Pre-metal layer R1 Memory area corner peripheral cut-out area R2 Memory capacity peripheral cross-cut area SA1, SA2 Sense amplifier UC Unit memory cell Vp Plate potential W 1, WD2, WD3, WD4 word line driver WL, WL1, WL2, WL3, WL4 word line

Claims (11)

Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface;
(B) a memory area provided on the first main surface;
(C) a memory array area provided in the memory area;
(D) a memory capacitor forming insulating film layer provided on the first main surface;
(E) a memory capacitor formation hole formed in the memory array region from the upper surface of the memory capacitor formation insulating film layer toward the inside thereof;
(F) a metal plug protruding from the bottom surface of the memory capacity forming hole into the inside;
(G) a first lower electrode of a memory capacitor provided on the side surface and the bottom surface of the memory capacitor forming hole;
(H) a first capacitor insulating film of the memory capacitor provided on the side surface of the memory capacitor forming hole and on the first lower electrode;
(I) an upper electrode of the memory capacitor provided on the capacitor insulating film on the side surface of the memory capacitor forming hole;
Here, the memory capacity is not substantially formed on the upper and side surfaces of the metal plug.     2. The semiconductor integrated circuit device according to claim 1, wherein the first lower electrode is formed on the upper surface and the side surface of the metal plug. 3. The semiconductor integrated circuit device according to claim 2, further comprising:
(J) a second capacitor insulating film of the memory capacitor provided on the side electrode of the memory capacitor forming hole and on the upper electrode;
(K) A second lower electrode provided on the second capacitor insulating film on the side surface of the memory capacitor formation hole and connected to the first lower electrode.     4. The semiconductor integrated circuit device according to claim 3, wherein the inside of the memory capacitor forming hole and the inside of the second lower electrode are substantially filled with an insulating member.     3. The semiconductor integrated circuit device according to claim 2, wherein the memory array region has a COB type cell structure.     6. The semiconductor integrated circuit device according to claim 5, wherein the memory array region has a folded bit line layout.     7. The semiconductor integrated circuit device according to claim 6, wherein the inside of the memory electrode forming hole and the inside of the upper electrode is substantially filled with an insulating member.     6. The semiconductor integrated circuit device according to claim 5, wherein the memory area is of an embedded DRAM.     9. The semiconductor integrated circuit device according to claim 8, wherein the memory capacity is a wiring layer penetration type memory capacity.     10. The semiconductor integrated circuit device according to claim 9, wherein the memory capacitor forming insulating film layer includes a wiring layer having a low-k silicon oxide-based interlayer insulating film layer.     11. The semiconductor integrated circuit device according to claim 10, wherein the low-k silicon oxide based interlayer insulating film layer is a porous low-k silicon oxide based interlayer insulating film layer.

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