JP2013229440A - Semiconductor device and semiconductor wafer for use in production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an identification part can be recognized reliably, even if the dicing area becomes thin due to high density.SOLUTION: An identification marking 3 is formed from the outer peripheral region 1b to the dicing area 2 of a device region 1. Consequently, the identification marking 3 is left in the outer peripheral region 1b without fail. In other words, although a dicing line may be shifted in the dicing area 2 due to displacement of a dicing saw, the dicing line is confined in the dicing area 2. Consequently, at least a portion of the identification marking 3 formed in the outer peripheral region 1b can be left, as it is. Device characteristics of a semiconductor element, or the manufacturing number of a semiconductor device can be recognized by utilizing the identification marking 3.

Description

  The present invention relates to a semiconductor device in which an identification marking is left on a semiconductor chip on which a semiconductor element is formed even after dicing cut, and a semiconductor wafer used for manufacturing the semiconductor device.

  Conventionally, in Patent Document 1, a semiconductor device has been proposed in which an identification portion including a concave portion or a convex portion is provided inside the dicing area so that the identification portion remains inside the dicing area even after the dicing cut. Specifically, an identification portion wider than the dicing line is formed inside the dicing area of the semiconductor wafer, that is, in a portion other than the device region where the semiconductor element is formed. For this reason, when it divides | segments into a chip unit by a dicing cut, an identification part can remain in parts other than a dicing line, ie, the outer periphery of the device area | region of a semiconductor device.

  Therefore, the device region in which the semiconductor element is formed can be configured not to include the identification portion, so that the semiconductor device having the identification portion can be provided without sacrificing the device region. By using this identification unit, the semiconductor device can be identified.

JP 2011-29268 A

  However, since the dicing area becomes thinner as the density of semiconductor elements in the semiconductor wafer becomes higher, there is a problem that the identification portion becomes minute and the range of the identification portion remaining after dicing becomes narrow and cannot be confirmed.

  Specifically, dicing cut is performed in the dicing area J1 shown in FIG. At this time, as shown in FIG. 7B, the width of the dicing line (the portion removed by the dicing cut) J2 becomes narrower than the width of the dicing area J1, and the identification portion J3 is formed in the portion remaining without being cut. Will remain. However, the dicing area J1 becomes narrow, so that the portion that remains without being cut becomes narrow. Therefore, the range of the identification part J3 becomes narrow. Further, due to variations in the cut location by the dicing saw, the dicing line J2 may be displaced from the center of the dicing area J1 as shown in FIG. 7C, and the identification portion J3 may disappear. Further, as shown in FIG. 7D, when chipping occurs in which the chip end portion J4 is chipped on the opposite side of the dicing line J2 from where the identification portion J3 is left, the width of the identification portion J3 is narrow. In some cases, the identification unit J3 cannot be recognized.

  In view of the above points, an object of the present invention is to provide a semiconductor device capable of reliably recognizing an identification marking even if a dicing area becomes thinner as the density increases, and a semiconductor wafer used for manufacturing the semiconductor device.

  In order to achieve the above object, in the invention according to any one of claims 1 to 6, a device including a cell region (1a) in which a semiconductor element is formed and an outer peripheral region (1b) formed in an outer periphery surrounding the cell region. It has a region (1) and a dicing area (2) provided around the device region, and an identification marking (3) is formed from the outer peripheral region to the dicing area in the device region.

  Thus, since the identification marking is formed from the outer peripheral area of the device area to the dicing area, the identification marking can always remain in the outer peripheral area even after the dicing cut. In other words, the dicing line may be displaced within the dicing area due to the displacement of the dicing saw or the like, but even if the dicing line is displaced, the dicing line is within the dicing area. For this reason, even if the dicing line is shifted, at least a portion of the identification marking formed in the outer peripheral region can remain.

  Therefore, identification markings can always remain on the semiconductor device, and this identification marking can be used to recognize information indicated by the identification marking, such as device characteristics such as semiconductor elements or the manufacturing number of the semiconductor device. Is possible.

  According to a sixth aspect of the present invention, there is provided a semiconductor wafer used for manufacturing the semiconductor device according to any one of the first to sixth aspects, wherein a plurality of device regions are arranged and the adjacent devices are arranged. A dicing area is provided between the areas, and the identification marking is formed by connecting adjacent device areas across the dicing area, and is parallel to two orthogonal sides constituting the rectangular shape of the device area and the device area It is characterized by being arranged asymmetrically with respect to two straight lines (X, Y) passing through the center of the two.

  In this way, when the identification marking is formed so as to connect adjacent device regions across the dicing area, the number of identification marking formation positions can be reduced. For this reason, for example, when forming an identification marking by marking processing such as machining or laser processing, marking processing is performed in comparison with the case of forming identification markings one by one corresponding to each device region. The number of times can be halved.

  In addition, when forming such an identification mark, when divided into chips by dicing cut to make a semiconductor device, the position of the identification marking is different between those adjacent in the wafer state. Become. However, in the present embodiment, the identification marking is arranged so as to be asymmetric with respect to the two straight lines X and Y passing through the center of the device region. For this reason, the position of the identification marking does not become the same when each semiconductor device after dicing cut is turned upside down or left and right. Therefore, even if the position of the identification marking is different, the correct direction of the semiconductor device can be confirmed based on the position of the identification marking.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a top surface layout figure of the semiconductor device after a dicing cut concerning a 1st embodiment of the present invention. It is sectional drawing when the semiconductor device shown in FIG. 1 is cut | disconnected on the II-II line. It is the figure which showed the upper surface layout of the semiconductor wafer before and after dicing cut. It is sectional drawing of the semiconductor wafer before and after dicing cut. It is the figure which showed the upper surface layout of the semiconductor wafer before and after the dicing cut concerning 2nd Embodiment of this invention. It is a comparison figure of the position of the identification marking 3 in a semiconductor device. It is sectional drawing which showed the mode at the time of the conventional identification part and dicing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the semiconductor device according to the present embodiment has a cell region 1a in which semiconductor elements are formed and an outer peripheral region 1b formed so as to surround the cell region 1a as a device region 1, and a dicing area 2 around the device region 1. The structure is equipped with.

  The semiconductor element formed in the cell region 1a is formed by performing a well-known element manufacturing process on a semiconductor wafer made of, for example, silicon carbide (hereinafter referred to as SiC), and is composed of, for example, a MOSFET or a diode. An electrode 1c is formed in the cell region 1a, and an outer peripheral region 1b is provided so as to surround the electrode 1c. For example, the electrode 1c is connected to a semiconductor element, and is constituted by a source electrode in the case of a MOSFET and an anode electrode in the case of a diode. In FIG. 1, the electrode 1c is illustrated as being formed over the entire cell region 1a, but may be a part of the cell region 1a or may be divided into a plurality of electrodes. For example, in the case of a MOSFET, a gate electrode or various electrodes for sensing may be formed in addition to the source electrode.

  The outer peripheral region 1b is a region provided with an outer peripheral withstand voltage structure or the like. For example, the outer peripheral region 1b includes a RESURF layer, a guard ring layer, or the like formed so as to surround the cell region 1a in the surface layer portion of the semiconductor substrate. . The outer peripheral pressure-resistant structure does not need to be formed in the entire outer peripheral region 1b, and may be formed only in the inner portion of the outer peripheral region 1b.

  The dicing area 2 is an area provided so as to surround the periphery of the device area 1 including the cell area 1a and the outer peripheral area 1b. A dicing cut is performed in the dicing area 2 using a dicing saw or the like, and the semiconductor wafer on which the semiconductor elements and the outer peripheral breakdown voltage structure are formed is divided into chips. A portion of the dicing area 2 other than the dicing line that has been removed by the dicing cut remains, but the remaining portion may become a different location depending on the displacement of the dicing line. Note that, unlike the dicing area 2, the device region 1 is a portion that is always left even if a dicing cut is performed.

  In the semiconductor device configured as described above, the identification marking 3 is formed from the outer peripheral region 1b of the device region 1 to the dicing area 2. Specifically, the identification marking 3 is formed from the position away from the electrode 1c toward the dicing area 2 in the outer peripheral region 1b of the device region. For this reason, the influence by forming the identification marking 3 in a semiconductor element more reliably is prevented. In the case of the present embodiment, a plurality of markings are configured to extend in the vertical direction with respect to one side of the cell region 1a configured by a rectangle.

  The identification marking 3 can be recognized at least through an optical microscope or the like, and records device characteristics including a semiconductor element, a manufacturing number of a semiconductor device, or the like. For example, the identification marking 3 is constituted by a barcode as shown in the figure.

  Specifically, the identification marking 3 is, for example, a concave portion formed on the surface of the semiconductor substrate as shown in FIG. 2, any one of a convex portion, a light and shade, a metal, etc., or any of these including a concave portion. Or composed of multiple combinations. Concerning the shading, it may be configured by the color difference between the identification marking 3 and its surroundings, but it appears as shading when the identification marking 3 is confirmed through an optical microscope or the like. For example, it may be uneven. Also, the metal is different from the surrounding area of the identification marking 3 in material, and the color is different or the gloss is different, or the metal can be recognized as the identification marking 3 by changing the unevenness based on the presence or absence of metal. It is. For example, as the metal, at least a part of an electrode material constituting the electrode 1c formed in the device region 1, for example, metal plating such as gold for bonding can be used. If the identification marking 3 is formed using such an electrode material such as metal plating, the identification marking 3 can be formed by the same process as the electrode 1c.

  Next, a method for manufacturing the semiconductor device configured as described above will be described with reference to FIGS. 3 and 4, only a part of the semiconductor wafer when the semiconductor device shown in FIGS. 1 and 2 is manufactured is shown, but the structure shown in FIGS. 3 and 4 is actually used. A large number of semiconductor wafers are formed.

  First, a semiconductor element is formed by performing a well-known element formation process with respect to a semiconductor wafer. And the process of forming the identification marking 3 is performed during the element forming process or after the element forming process.

  For example, when the identification marking 3 is constituted by a recess, the identification marking 3 can be formed by performing etching using a mask having an opening in the recess formation region. In addition, when the identification marking 3 is constituted by a convex portion, by performing etching using a mask having an opening around the convex portion forming region, a convex portion surrounded by the concave portion is formed, and the identification marking 3 is Can be formed. When the element manufacturing process includes a step of forming a trench or a recess, for example, when a MOSFET is formed as a semiconductor element and the MOSFET is a trench gate type, the identification marking 3 is formed by the trench forming process for the gate. It may also serve as a formation process. This makes it possible to simplify the manufacturing process by sharing the manufacturing process.

  Further, when the identification marking 3 is composed of light and shade, the identification marking 3 can be formed by patterning after depositing a material different from the surface (SiC) of the semiconductor substrate. Even when the identification marking 3 is made of metal, by patterning after forming a metal material on the surface of the semiconductor substrate or the surface of the interlayer insulating film, or by performing metal plating on the surface of the metal material after patterning The identification marking 3 can be formed. Since the process for forming the electrode 1c is included in the element manufacturing process, when the density of the identification marking 3 is made of metal or when the identification marking 3 is made of metal, the formation of the identification marking 3 is performed by the process of forming the electrode 1c. It can also serve as a formation process. Even in this case, it is possible to simplify the manufacturing process by sharing the manufacturing process.

  As a result, a semiconductor wafer having the structure shown in FIGS. 3 and 4 before the dicing cut is formed. That is, a semiconductor wafer in which a plurality of device regions 1 are formed, the periphery of each device region 1 is surrounded by a dicing area 2, and an identification marking 3 is formed from the outer peripheral region 1 b of the device region 1 to the dicing area 2. Is formed.

  Then, a dicing cut is performed in the dicing area 2 in parallel with each side of the cell region 1a by a dicing saw or the like. As a result, as shown in FIGS. 3 and 4 after the dicing cut, the plurality of device regions 1 are divided into chips in the dicing line, and the semiconductor device shown in FIG. 1 is completed. In the semiconductor device thus completed, the identification marking 3 is formed from the outer peripheral region 1b of the device region 1 to the dicing area 2, so that the identification marking 3 can always remain in the outer peripheral region 1b. That is, the dicing line may be shifted in the dicing area 2 due to the shift of the dicing saw, but the dicing line is within the dicing area 2 even if the dicing line is shifted. For this reason, even if the dicing line is shifted, at least a portion of the identification marking 3 formed in the outer peripheral region 1b can be left.

  Accordingly, the identification marking 3 can always remain in the semiconductor device, and the identification marking 3 can be used to recognize device characteristics such as a semiconductor element or a manufacturing number of the semiconductor device.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the identification marking 3 is changed with respect to the first embodiment, and other parts are the same as those in the first embodiment, and therefore only the parts different from the first embodiment will be described.

  As shown in FIG. 5, in the present embodiment, the device regions 1 arranged adjacent to each other with the dicing area 2 sandwiched on the semiconductor wafer are connected. That is, the identification marking 3 is formed so as to extend from the outer peripheral region 1b of one device region 1 to the outer peripheral region 1b of the other device region 1 across the dicing area 2.

  Then, the identification marking 3 passes through the center of the device region 1 in parallel with each of the two orthogonal sides constituting the dicing area 2 (parallel to the two orthogonal sides of the rectangular cell region 1a). They are arranged so as to be asymmetric with respect to the two straight lines X and Y. In the case of this embodiment, the identification marking 3 is formed at a position shifted from the two straight lines X and Y. That is, in the adjacent device region 1a, the identification marking 3 is formed from the lower right position of one device region 1a shown on the left side in the drawing to the lower left position of the other device region 1a shown on the right side in the drawing. .

  As described above, when the identification marking 3 is formed so as to connect the adjacent device regions 1 across the dicing area 2, the number of formation positions of the identification marking 3 can be reduced. For this reason, for example, when forming the identification marking 3 by marking processing such as machining or laser processing, compared to the case where the identification marking 3 is formed at the same position one by one corresponding to each device region 1. The number of marking processes can be halved.

  Further, when such an identification marking 3 is formed, when the semiconductor device is divided into chips by dicing cut as shown in FIG. 5, the adjacent ones in the wafer state are distinguished from each other. The position of the marking 3 is different. However, in this embodiment, the identification marking 3 is arranged so as to be asymmetric with respect to the two straight lines X and Y passing through the center of the device region 1. For this reason, for example, as shown in FIG. 6, the position of the identification marking 3 does not become the same position when each semiconductor device after dicing cut is turned upside down or left and right. Therefore, even if the position of the identification marking 3 is different, the correct direction of the semiconductor device can be confirmed based on the position of the identification marking 3.

(Other embodiments)
In each of the above embodiments, a barcode is shown as an example of the identification marking 3, but other configurations, for example, any one of figures, symbols, numbers, characters and QR codes, or a barcode is included in these. You may be comprised by the marking group which consists of a some combination. Moreover, although the identification marking 3 is extended in the perpendicular direction with respect to one side of the cell area | region 1a, it is not restricted to a perpendicular direction. In addition, since the identification marking 3 may be partially lost at the time of dicing cut, it is preferable that the same information is not shown as a whole but the same information is repeatedly expressed. Of course, even if one piece of information is shown as a whole, there is no problem if the information represented by the identification marking 3 can be recognized by the remaining portion.

1 Device area 1a Cell area 1b Outer peripheral area 1c Electrode 2 Dicing area 3 Identification marking

Claims (6)

A device region (1) including a cell region (1a) in which a semiconductor element is formed and an outer peripheral region (1b) formed on an outer periphery surrounding the cell region;
A dicing area (2) provided around the device region,
An identification marking (3) is formed from the outer peripheral region to the dicing area in the device region. The device region is provided with an electrode (1c) connected to the semiconductor element,
The semiconductor device according to claim 1, wherein the identification marking is formed from a position away from the electrode toward the dicing area.   3. The semiconductor device according to claim 1, wherein the identification marking records a device characteristic including a semiconductor element or a manufacturing number. 4.   4. The semiconductor device according to claim 1, wherein the identification marking is configured by one or a combination of a concave portion, a convex portion, a light and shade, or a metal material.   5. The identification marking according to claim 1, wherein the identification marking is configured by one or a combination of any one of a figure, a symbol, a number, a character, a bar code, and a QR code. Semiconductor device. A semiconductor wafer used for manufacturing a semiconductor device according to any one of claims 1 to 5,
The device region has a rectangular shape,
A plurality of the device regions are arranged, and the dicing area is provided between the adjacent device regions,
The identification marking is formed by connecting adjacent device regions across the dicing area, and is parallel to two orthogonal sides constituting the rectangular shape of the device region and passes through the center of the device region. A semiconductor wafer, which is disposed asymmetrically with respect to a straight line (X, Y).

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