JP2013229074A - Sram - Google Patents

Abstract

Memory cell connection configuration in an SRAM cell in which two inverters are connected to each other, and SRAM cells for inputting / outputting data and inverted data from their respective outputs via a transfer gate are arranged in a matrix By taking this into consideration, the number of wirings is reduced and an SRAM having a small area is provided.
The SRAM cells adjacent in the row direction share the bit line and the inverted bit line, the word lines differ between the SRAM cells adjacent in the row direction, and a series of SRAMs adjacent in the row direction. The word lines of SRAM cells adjacent in the column direction are wired differently from any of the word lines.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory SRAM.

An SRAM (Static Random Access Memory) is a memory that constantly stores data, unlike a DRAM (Dynamic Random Access Memory). Unlike a DRAM, it is not necessary to periodically refresh data in order to retain data, and the control is easy and convenient. There are a wide range of applications from large systems to small systems.

  FIG. 2 shows a typical SRAM cell having a 6-transistor configuration. Two inverters, an inverter composed of a P channel transistor P1, an N channel transistor N1, an inverter composed of a P channel transistor P2, and an N channel transistor N2, are connected to each other. Then, the bit data BL and the inverted bit data BLB are output from the respective outputs V0 and V1 to the data line and the inverted data line via the transfer gates T1 and T2, respectively. FIG. 3 shows the configuration of the SRAM in which the SRAM cells are arranged on the array in the row and column directions.

JP 05-198183 A JP 05-225788 A

  However, as illustrated in FIG. 2 and FIG. 3, the SRAM is composed of 6 transistors, and two data lines and an inverted data line are necessary. There is a drawback that the area becomes large.

  An object of the present invention is to provide an SRAM having a small area by reducing the number of wirings by considering the connection configuration of memory cells.

The present invention has been made in view of the problems, and the invention of claim 1
In an SRAM in which two inverters are connected to each other, and SRAM cells that input and output data and inverted data from the respective outputs via a transfer gate are arranged in a matrix, between adjacent SRAM cells in the row direction. The bit lines and the inverted bit lines are shared, the word lines are different between the SRAM cells adjacent in the row direction, and the word lines of the SRAM cells adjacent in the column direction with respect to the series of SRAM cells adjacent in the row direction are: The SRAM is characterized in that it is wired differently from any of the word lines.

The invention of claim 2 of the present invention
The SRAM data read circuit is
Of the SRAM cells selected in the row direction by the word signal output from the word decoder,
An SRAM cell in the column direction is selected via a switch transistor selected by a selection signal output from the column decoder,
The shared line of the bit line and the inverted bit line is further connected to the positive input or the inverted input of the sense amplifier according to the data or the inverted data of the selected SRAM cell via the switch transistor. 1 is obtained.

  The SRAM of the present invention has the above-described configuration. By considering the connection configuration of the memory cells, the arrangement of the memory array can be substantially reduced, and a low-cost SRAM can be provided.

It is explanatory drawing which shows the example of embodiment of SRAM of this invention. It is explanatory drawing which shows the example of the conventional SRAM cell. It is explanatory drawing which shows the example of the conventional SRAM.

  Hereinafter, modes for carrying out the present invention will be described.

  1 and 2 show an embodiment of the SRAM of the present invention. In the SRAM of the present invention, two inverters are connected to each other, and SRAM cells for inputting / outputting data BL and inverted data BLB from their outputs via transfer gates T1, T2 are arranged in a matrix. Assuming The SRAM cells adjacent in the row direction share the bit line and the inverted bit line (BLk), and the SRAM cells adjacent in the row direction are connected to different word lines. The word lines of the SRAM cells adjacent in the column direction with respect to the series of SRAM cells adjacent in the row direction are wired differently from the word lines.

  Regarding the reading of SRAM data, among the SRAM cells selected in the row direction by the word signal output from the word decoder, the column direction is passed through the switch transistor CG selected by the selection signals COL0 and COL1 output from the column decoder. SRAM cells are selected. Further, the shared line BLk of the bit line and the inverted bit line is connected to the positive input + or the inverted input − of the sense amplifier S / A according to the data or the inverted data of the selected SRAM cell via the switch transistor CG. SRAM data is read out.

  In the SRAM of the present invention, the bit lines and the inverted bit lines are shared (BLk) between the SRAM cells adjacent in the row direction as described above. However, the word lines differ between SRAM cells adjacent in the row direction. Further, the wiring is different from the word line of the SRAM cell adjacent in the column direction. Because of this configuration, the SRAM cell bit line and the inverted bit line shared line selected in the row direction by the word signal are disconnected from the left and right SRAM cells by the transfer gate when reading and writing data. Yes. Further, the upper and lower SRAM cells in the column direction and the left and right SRAM cells are also disconnected by the transfer gate. From such a configuration and circuit operation, the SRAM cell data can be read and written even if the bit line and the inverted bit line are shared by the shared line.

  As described above, since the bit line and the inverted bit line can be shared by one shared line, the wiring of the SRAM cell is reduced, the arrangement of the memory array is substantially reduced, and a low-cost SRAM can be provided.

  In the present invention, there are two word lines between the SRAM cells. However, since the word line generally forms a transfer gate by disposing polysilicon on the diffusion pattern, there is almost one polysilicon pattern. And wiring by adding a diffusion pattern therefor. The bit line is formed by providing a contact hole on the diffusion pattern and connecting it to a conductor (generally aluminum). Due to the size of the contact hole, the margin of the conductor with respect to the contact hole (allowance), the width of the conductor, the distance between the conductors, etc., the bit line requires a larger space than the word line. Therefore, even if the number of word lines increases, the present invention can substantially reduce the arrangement of the memory array.

  Hereinafter, the configuration and circuit operation of the present invention will be described more specifically with reference to FIGS.

  FIG. 1 shows an example of a memory array in which the arrangement and connection of the SRAM of the present invention are devised. The bit line BL and the inverted bit line BLB of the memory cells arranged in the direction (horizontal) along the row are shared to reduce the bit line wiring.

  The inverted bit line of M00 and the bit line of M01 are shared to make BL1, and the inverted bit line of M01 and the bit line of M02 are shared to make BL2. Similarly, the inverted bit lines and bit lines of M02 and M03 are shared. The word lines alternately connect the word line outputs of the memory cells in the direction (vertical) along the column so that adjacent cells are not simultaneously selected. With this configuration, the number of bit lines and inverted bit lines can be halved.

  The bit line BL0 is connected to the positive output of M00 (the output terminal of T1, the “data” above), and the inverted output (the output terminal of T2, the above “inverted data”) is connected to the bit line BL1. The positive output of M01 is connected to BL1, and the inverted output is connected to BL2.

Similarly, M02 is connected to BL2 and BL3, and M03 is connected to BL3 and BL4.
BL0 and BL1 corresponding to the bit line and the inverted bit line of M00 are sense amplifiers S / A0 via selection gate transistors CG00 and CG01, respectively, to which a column selection signal COL0 output from the column decoder is input. Are connected to the positive input (+ side) and the inverting input (− side).

  BL1 and BL2 corresponding to the bit line and the inverted bit line of M01 are respectively connected to the positive input side and the inverting input side of the sense amplifier S / A0 via selection gates CG10 and CG11 to which the selection signal of COL1 is input. Connected.

  Similarly, bit line BL2 and inverted bit line BL3 of M02 are selected by COL0 and connected to sense amplifier S / A1, and bit line BL3 and inverted bit line BL4 of M03 are selected by COL1 and sense amplifier Connected to S / A1.

  For the output of the row decoder, WL0 is connected to M00 and M02, and WL1 is connected to M01 and M03. Similarly, WL2 is connected to M10 and M12, and WL3 is connected to M11 and M13.

  Next, the selection operation will be described.

  When WL0 and COL0 are selected by a row address and a column address (not shown), M00 is selected, a positive output of M00 is output to BL0 via T1, and an inverted output is read to BL1 via T2. BL0 and BL1 are input to the sense amplifier S / A0 via CG00 and CG01 to which COL0 is input, and the data of M00 is read out.

  At this time, since WL1 is 0 V, T1 of M01 is off, and only M00 is connected to BL1, so there is no influence of the adjacent M01 cell.

  Similarly, when M01 is selected, WL1 and COL1 become High, BL1 is connected to the positive input side of the sense amplifier S / A0, and BL2 is connected to the inverting input side. At this time, since WL0 is not selected and is 0 V, there is no influence of the cells of M00 and M02.

  The same applies to the operations of M02 and M03.

  In this way, even if the bit line BL and the inverted bit line BLB are shared, the operation is possible without deteriorating the characteristics.

Claims (2)

  In an SRAM in which two inverters are connected to each other, and SRAM cells that input and output data and inverted data from the respective outputs via a transfer gate are arranged in a matrix, between adjacent SRAM cells in the row direction. The bit lines and the inverted bit lines are shared, the word lines are different between the SRAM cells adjacent in the row direction, and the word lines of the SRAM cells adjacent in the column direction with respect to the series of SRAM cells adjacent in the row direction are: An SRAM, wherein the SRAM is wired differently from any of the word lines. The SRAM data read circuit is
Of the SRAM cells selected in the row direction by the word signal output from the word decoder,
An SRAM cell in the column direction is selected via a switch transistor selected by a selection signal output from the column decoder,
The shared line of the bit line and the inverted bit line is further connected to the positive input or the inverted input of the sense amplifier according to the data or the inverted data of the selected SRAM cell via the switch transistor. The SRAM according to 1.

Images