JP2013211400A - Manufacturing method of print circuit board and print circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a print circuit board allowing formation of a conductor land with a small diameter, and provide a manufacturing method of the print circuit board.SOLUTION: A first conductor land 36a on a first face F of a core substrate is formed by forming a first opening 35a in a plated resist film 35 by means of a laser having high location accuracy and plating the inside of the opening. Therefore, even if the first conductor land 36 is formed in a small diameter, resulting in a not-aligned formation relative to a through-hole hole 31 by the maximum of a precision error, the first conductor land is formed with a through-hole opening 31 covered.

Description

The present invention relates to a method for manufacturing a printed wiring board on which an electronic component such as an IC chip is mounted, and a printed wiring board.

An example of a method for manufacturing a multilayer build-up wiring board is disclosed in Patent Document 1. Here, after the through hole for the through hole is formed, a seed film is provided on the surface of the substrate and the inner wall of the through hole, and a photosensitive plating resist is coated on the core substrate. Thereafter, exposure development is performed to form openings for conductor lands and conductor patterns in the plating resist, and through plating, through-hole conductors are formed on the side walls of the through-hole openings, and conductor lands and conductor patterns are formed in the openings. Form. Then, the plating resist is peeled off, and the seed film under the plating resist film is removed.

JP 2001-244605 A

In recent years, the performance of electronic devices has been rapidly improved and used in a wide range of fields such as information and communication. In addition, with the advent and popularization of portable personal computers, mobile terminals, mobile phones, etc., there is a demand for miniaturization and weight reduction along with higher density of electronic components mounted on printed wiring boards. In connection with this, since the printed wiring board mounted in an electronic device is also required to be reduced in size and weight, the thickness of the printed wiring board itself is also reduced.
That is, the number of build-up layers is also reduced, and it is necessary to route the conductor pattern with a smaller number of layers. As a result, it is essential to increase the density of the conductor pattern even on the surface of the core substrate.
According to the printed wiring board described in the above-mentioned conventional document 1, due to the alignment accuracy when forming the through hole for the through hole and the exposure alignment accuracy when forming the plating resist, It was difficult to reduce the diameter.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board manufacturing method and a printed wiring board capable of forming a conductor land with a small diameter.

The invention according to claim 1 is a core substrate comprising a first surface and a second surface opposite to the first surface;
A first conductor pattern provided on the first surface of the core substrate;
A second conductor pattern provided on the second surface of the core substrate;
A through-hole conductor provided inside the core substrate and connecting the first conductor pattern and the second conductor pattern;
A method of manufacturing a printed wiring board comprising:
Forming a through-hole for the through-hole conductor in the core substrate;
Forming a plating film on the first surface, the second surface and the inner wall of the through hole of the core substrate;
Forming a dry film on the first surface and the second surface of the core substrate so as to cover the through hole;
Forming a plating resist by providing the dry film with a first opening that exposes the through hole and a second opening that exposes a portion of the plating film;
Filling the inside of the through hole with the plating through the first opening;
Removing the plating resist;
And removing the plating film under the plating resist.

In the present invention, the diameter of the conductor pattern (conductor land) connected by the through-hole conductor can be made as small as possible, and a high-density pattern can be routed on the core substrate.

It is a manufacturing-process figure of the printed wiring board of 1st Example of this invention. It is a manufacturing-process figure of the printed wiring board of 1st Example. It is a manufacturing-process figure of the printed wiring board of 1st Example. It is a manufacturing-process figure of the printed wiring board of 1st Example. It is a manufacturing-process figure of the printed wiring board of 1st Example. It is sectional drawing of the printed wiring board which concerns on 1st Example. It is sectional drawing of the printed wiring board which concerns on 1st Example of the state which mounted the IC chip. It is sectional drawing of the printed wiring board which concerns on 2nd Example. FIG. 9A is an enlarged view of the circle C1 in FIG. 1E, FIG. 9B is an enlarged view of the circle C2 in FIG. 2C, and FIG. 9C is the third embodiment. It is a figure of the conductor land concerning.

[First embodiment]
The configuration of the printed wiring board 10 according to the first embodiment of the present invention is shown in FIGS. 6 shows a cross-sectional view of the printed wiring board 10, and FIG. 7 shows a state where the IC chip 90 is attached to the printed wiring board 10 shown in FIG. As shown in FIG. 6, in the printed wiring board 10, the first conductor pattern 34A is provided on the first surface F (upper surface: IC chip mounting side) side of the core substrate 30, and the second surface S (lower surface: external connection substrate mounting). The second conductor pattern 34B is formed on the (side) side. The first conductor pattern 34 </ b> A on the first surface of the core substrate 30 and the second conductor pattern 34 </ b> B on the second surface are connected via a through-hole conductor 36. Of the end portions of the through-hole conductors 36, the first conductor land 36a is formed on the first surface F side, and the second conductor land 36b is formed on the second surface S side. A first interlayer insulating layer 50A in which a via hole 60A and a conductor circuit 58A are formed is disposed on the first surface F of the core substrate 30, and a second hole S in which a via hole 60B and a conductor circuit 58B are formed on the second surface S. A two-layer insulating layer 50B is provided. A solder resist layer 70A is formed on the via hole 60A and the conductor circuit 58A, and a solder resist layer 70B is formed on the via hole 60B and the conductor circuit 58B. Solder bumps 76U are formed in the openings 71A of the solder resist layer 70A on the first surface F side, and solder bumps 76D are formed in the openings 71B of the solder resist 70B on the second surface S side. As shown in FIG. 7, the pads 92 of the IC chip 90 are connected to the solder bumps 76D on the upper surface side. The L / S (line space) of the first conductor pattern 34A is 30 μm / 30 μm or less.

9B shows the through-hole conductor 36, the first conductor land 36a, and the second conductor land 36b in FIG. 1 in an enlarged manner.
The diameter d3 of the through hole 31 for the through hole of the core substrate 30 and the outer diameter d1 of the first conductor land 36a on the first surface F side are set to substantially the same diameter. The outer diameter d2 of the second conductor land 36b on the second surface S side is formed larger than the outer diameter d1 of the first conductor land 36a described above.

In the printed wiring board of the first embodiment, the first conductor land 36a on the first surface F side that is required to be highly integrated in order to fan out the wiring from the IC chip is formed to the minimum diameter that can provide reliability. Thus, a fine pitch and high integration of the first conductor pattern are achieved.

The manufacturing method of the printed wiring board 10 in FIG. 6 is shown in FIGS.
(1) An insulating substrate 30 having a thickness of 0.2 mm obtained by impregnating a glass cloth or other core material with glass epoxy resin or BT (bismaleimide triazine) resin is used as a starting material (FIG. 1A). Through-holes 31 for through holes are formed from the upper surface (first surface F) side and the lower surface (second surface S) side by, for example, laser (FIG. 1B).

(2) A palladium catalyst (manufactured by Atotech) is applied to the upper surface of the substrate 30 and electroless copper plating is performed, so that an electroless copper plating with a thickness of 0.6 μm is formed on the upper surface of the substrate and the side wall of the through hole 31. A film (shield layer) 32 is formed (FIG. 1C).

(3) Then, a commercially available dry film is pasted on both surfaces of the substrate 30 so as to close the opening of the through hole 31, and a plating resist 35 is formed (FIG. 1D).

(4) The laser is irradiated so as to pass through the through hole 31 from the second surface S side, and the second opening 35b for the second conductor land is formed on the second surface S side in the plating resist 35, and the first surface A first opening 35a for the first conductor land is formed on the F side (FIG. 1E).

The inside of the cycle C1 in FIG. 1 (E) is enlarged and shown in FIG. 9 (A).
Here, for example, a case where the diameter d3 of the through hole 31 of the substrate 30 is 250 μm will be described as an example. An inner diameter d1 of the first opening 35a for the first conductor land on the first surface F side is formed to be 250 μm, which is substantially the same diameter as the through hole. An inner diameter d2 of the second opening 35b for the second conductor land on the second surface S side is 380 μm. In the first embodiment, as described above, the laser is irradiated so as to pass through the through-hole 31 from the second surface S side, so that the first conductor land for the first surface F on the laser light emission side is used. The inner diameter d1 of the first opening 35a is formed smaller than the inner diameter d2 of the second opening 35b for the second conductor land on the second surface S on the laser beam incident side.

(5) Further, a laser is irradiated to form a conductor circuit forming groove 35c on the first surface F side of the substrate 30 in the plating resist 35, and a conductor circuit forming groove 35d is formed on the second surface S side. (FIG. 2A).

(6) Electrolytic plating is performed under the following conditions, and in the through hole 31 for the through hole and in the portion where the plating resist 35 is not formed (first opening 35a, second opening 35b, grooves 35c, 35d) of the substrate 30. An electrolytic copper plating film 33 is formed (FIG. 2B).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm2
Time 70 minutes Temperature Room temperature

(7) Then, after the plating resist 35 is peeled off with 5% KOH, the electroless plating film 32 where the plating resist was formed is dissolved and removed with an etching solution mainly containing cupric chloride. The first conductor pattern 34A and the second conductor pattern 34B including the first conductor land 36a and the second conductor land 36b are formed (FIG. 2C). In the through-hole conductor 36, the upper surfaces of the first conductor land 36a, the second conductor land 36b, the first conductor pattern 34A, and the second conductor pattern 34B are roughened with an etching solution to form a roughened layer (not shown). . As described above with reference to FIG. 9B, the diameter d3 of the through hole 31 for the through hole of the core substrate 30 is formed to be 250 μm. The outer diameter d1 of the first conductor land 36a on the first surface F side is 250 μm, which is the same as the inner diameter of the first opening 35a. The outer diameter d2 of the second conductor land 36b on the second surface S side is formed to be 380 μm, similarly to the inner diameter of the second opening 35b.

In the first embodiment, an opening is formed in the plating resist film with a laser having higher position (alignment) accuracy than exposure, and then the first conductor land on the first surface F side of the core substrate is formed in the opening by plating. Is done. For this reason, the land has a small diameter (the inner diameter of the through hole 31 is 250 μm + the drill alignment accuracy (± 50 μm = 100 μm) + the laser alignment accuracy (± 5 μm = 10 μm) = 360 μm), and the maximum accuracy error is 110 (100 + 10) μm. Even if the split land 36 a is displaced with respect to the through-hole through hole 31, the end portion of the first conductor land is not greatly displaced from the through-hole through hole 31, so that the conductor land covers the through-hole through hole 31. Can be formed. That is, since the laser is irradiated so as to pass through the through hole 31, the first opening is formed around the first surface side opening of the through hole, so that the first opening is formed adjacent to the through hole 31. The For this reason, the diameter of the first conductor land can be reduced while ensuring the reliability of the first conductor land, and the fine pitch and high integration of the printed wiring board can be achieved.

(8) On the upper surface (first surface) and lower surface (second surface) of the substrate 30, there is a resin film for an interlayer insulating layer (made by Ajinomoto Co., Inc .; trade name; ABF-45SH) that is slightly smaller than the substrate without the core material. After being placed and temporarily crimped and cut under the conditions of a pressure of 0.45 MPa, a temperature of 80 ° C., and a crimping time of 10 seconds, the through-hole conductor 36 is attached by using a vacuum laminator device by the following method. The hollow portion is filled with the resin 50 to form the first interlayer insulating layer 50A and the second interlayer insulating layer 50B (FIG. 2D). That is, the interlayer insulating layer resin film is subjected to main pressure bonding on the substrate under the conditions of a degree of vacuum of 67 Pa, a pressure of 0.47 MPa, a temperature of 85 ° C., and a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 40 minutes.

(9) Next, via hole openings 51A and 51B are formed in the interlayer insulating layers 50A and 50B by a CO2 gas laser (FIG. 3A).

(10) The substrate on which the via holes 51A and 51B are formed is dipped in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to remove particles present on the upper surfaces of the interlayer insulating layers 50A and 50B. As a result, the upper surfaces of the interlayer insulating layers 50A and 50B including the inner wall of the via hole opening 51 are roughened to form a roughened surface (not shown).

(11) Next, the substrate after the above treatment is immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Furthermore, by applying a palladium catalyst to the upper surface of the roughened substrate, catalyst nuclei are attached to the upper surface of the interlayer insulating layer and the inner wall surface of the via hole opening.

(12) Next, the substrate provided with the catalyst is immersed in an electroless copper plating aqueous solution (Sulcup PEA) manufactured by Uemura Kogyo Co., Ltd., and the entire surface is electroless copper plated with a thickness of 0.3 to 3.0 μm. A film is formed, and a substrate on which the electroless copper plating film 52 is formed on the upper surfaces of the first interlayer insulating layer 50A and the second interlayer insulating layer 50B including the inner walls of the via hole openings 51A and 51B is obtained (FIG. 3 ( B)).

(13) A commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, a mask is placed, exposed at 110 mJ / cm @ 2, and developed with a 0.8% aqueous sodium carbonate solution. Thus, a plating resist 54 having a thickness of 25 μm is provided (FIG. 3C).

(14) The substrate is washed with water at 50 ° C., degreased, washed with water at 25 ° C., then further washed with sulfuric acid, and then subjected to electrolytic plating under the same conditions as in (6) above. An electrolytic copper plating film 56 having a thickness of 15 μm is formed in the non-formed part 54 (FIG. 4A).

(15) Further, after the plating resist 54 is peeled and removed with 5% KOH, the electroless plating film under the plating resist is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the conductor circuits 58A, 58B and Via holes 60A and 60B are formed (FIG. 4B). Next, the same processing as in (7) is performed, and the upper surfaces of the conductor circuits 58A and 58B and the via holes 60A and 60B are roughened to form roughened surfaces (not shown).

(16) Next, a commercially available solder resist composition is applied to both surfaces of the multilayer wiring board in a thickness of 20 μm, and after drying treatment, a pattern of the solder resist opening is drawn to a thickness of 5 mm. A photomask is brought into close contact with the solder resist layer, exposed to ultraviolet light, and developed with a DMTG solution to form a small-diameter opening 71A on the upper surface side and a large-diameter opening 71B on the lower surface side (FIG. 5A). Furthermore, the solder resist layer is cured by heat treatment, and solder resist layers 70A and 70B having openings and a thickness of 15 to 25 μm are formed.

(17) Next, the substrate on which the solder resist layers 70A and 70B are formed is dipped in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 μm in the openings 71A and 71B. Further, the substrate is immersed in an electroless gold plating solution, and a gold plating layer 74 having a thickness of 0.03 μm is formed on the nickel plating layer 72 (FIG. 5B). In addition to the nickel-gold layer, a single layer of tin or a noble metal layer (gold, silver, palladium, platinum, etc.) may be formed.

(18) After a flux (not shown) is applied in the openings 71A and 71B, small diameter solder balls 77U are mounted in the openings 71A of the upper surface side solder resist layer 70A, and large in the openings 71B of the lower surface side solder resist layer 70B. A diameter solder ball 77D is mounted (FIG. 5C), and solder bumps 76U are formed on the upper surface and solder bumps 76D are formed on the lower surface side by reflow (FIG. 6).

(19) The IC chip 90 is placed on the printed wiring board 10 and reflowed, whereby the connection pads of the printed wiring board and the electrodes 82 of the IC chip 90 are connected via the solder bumps 76U (FIG. 7).

[Second Embodiment]
FIG. 8 shows a cross-sectional view of the printed wiring board 10 according to the second embodiment of the present invention.
A first interlayer insulating layer 50A in which a via hole 60A and a conductor circuit 58A are formed is disposed on the first surface F of the core substrate 30, and a second hole S in which a via hole 60B and a conductor circuit 58B are formed on the second surface S. A two-layer insulating layer 50B is provided. A third interlayer insulating layer 150A in which a via hole 160A and a conductor circuit 158A are formed is disposed on the first interlayer insulating layer 50A. A fourth interlayer insulating layer 150B in which via holes 160B and conductor circuits 158B are formed is disposed above the second interlayer insulating layer 50B. A solder resist layer 70A is formed on the via hole 160A and the conductor circuit 158A, and a solder resist layer 70B is formed on the via hole 160B and the conductor circuit 158B. Solder bumps 76U are formed in the openings 71A of the solder resist layer 70A on the first surface F side, and solder bumps 76D are formed in the openings 71B of the solder resist 70B on the second surface S side.

In the second embodiment, the diameter d3 of the through hole 31 for the through hole of the core substrate 30 is obtained by the same manufacturing method as that of the first embodiment, as in the first embodiment described above with reference to FIG. 9B. Is formed to 250 μm. The outer diameter d1 of the first conductor land 36a on the first surface F side is 250 μm. The outer diameter d2 of the second conductor land 36b on the second surface S side is 380 μm.

[Third embodiment]
FIG. 9C shows a conductor land according to the third embodiment.
An inner surface of the through hole 31 having an inner diameter d3 of 250 μm is formed with an electroless copper plating film 32 having a thickness of 1 μm and filled with an electrolytic plating film 33.

In the third embodiment, the outer diameter d1 'of the first conductor land 36a on the first surface F side is 240 μm. The outer diameter d2 of the second conductor land 36b on the second surface S side is 380 μm. In the third embodiment, the first conductor land on the first surface F side of the core substrate is represented by (the inner diameter 250 μm of the through hole 31 + the drill alignment accuracy (± 50 μm = 100 μm) + the laser alignment accuracy (± 5 μm = 10 μm) = 360 μm) to 240 μm. Even when the diameter d1 ′ of the first conductor land 36a is set to 240 μm and the land 36a is displaced from the through hole 31 for the through hole 31 by the maximum accuracy error of 110 (100 + 10) μm, the end of the first conductor land 36 The first conductor land 36 a can be formed so as to cover the through-hole conductor 36 without shifting from the through-hole conductor 36 filled in the through-hole through hole 31. For this reason, it is possible to reduce the diameter of the conductor land while ensuring the reliability of the conductor land, and to achieve a fine pitch and high integration of the printed wiring board.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 30 Insulating board 31 Through-hole for through holes 34A 1st conductor pattern 34B 2nd conductor pattern 35 Plating resist 35a 1st opening part 35b 2nd opening part 36 Via-hole conductor 36a 1st conductor land 36b 2nd conductor Land 50A First interlayer insulating layer 50B Second interlayer insulating layer 58A, 58B Conductor circuit 60A, 60B Via hole 70A, 70B Solder resist layer

Claims (10)

A core substrate comprising a first surface and a second surface opposite to the first surface;
A first conductor pattern provided on the first surface of the core substrate;
A second conductor pattern provided on the second surface of the core substrate;
A through-hole conductor provided inside the core substrate and connecting the first conductor pattern and the second conductor pattern;
A method of manufacturing a printed wiring board comprising:
Forming a through-hole for the through-hole conductor in the core substrate;
Forming a plating film on the first surface, the second surface and the inner wall of the through hole of the core substrate;
Forming a dry film on the first surface and the second surface of the core substrate so as to cover the through hole;
Forming a plating resist by providing the dry film with a first opening that exposes the through hole and a second opening that exposes a portion of the plating film;
Filling the inside of the through hole with the plating through the first opening;
Removing the plating resist;
Removing the plating film under the plating resist;
A method of manufacturing a printed wiring board including: A method of manufacturing a printed wiring board according to claim 1, wherein:
The first opening is formed by a laser. A method of manufacturing a printed wiring board according to claim 1, wherein:
The diameter of the first opening is substantially the same as the diameter of the through hole. A method of manufacturing a printed wiring board according to claim 1, wherein:
The first opening provided in the dry film on the first surface side of the core substrate and the first opening provided in the dry film on the second surface side are provided continuously. A method of manufacturing a printed wiring board according to claim 4, wherein:
The first opening is formed by irradiating a laser from the second surface side of the core substrate. A method of manufacturing a printed wiring board according to claim 5, comprising:
The diameter of the first opening on the first surface side is smaller than the diameter of the opening on the second surface side. A method of manufacturing a printed wiring board according to claim 6, comprising:
The first surface of the core substrate is a surface on which a semiconductor element is mounted. A method of manufacturing a printed wiring board according to claim 6, comprising:
L / S (line space) of the first conductor pattern is 30 μm / 30 μm or less. A method of manufacturing a printed wiring board according to claim 1, wherein:
The through hole is formed by a laser. A core substrate comprising a first surface and a second surface opposite to the first surface;
A first conductor land provided on the first surface side of the core substrate;
A second conductor land provided on the second surface side of the core substrate;
A printed wiring board comprising a through-hole conductor provided inside the core substrate and connecting the first conductor land and the second conductor land:
The diameter of the first conductor land is smaller than the diameter of the second land.

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