JP2013125895A - Nonvolatile semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

[PROBLEMS] To manufacture a non-volatile semiconductor memory device using a plurality of non-volatile memory chips from which a power supply circuit or the like is omitted and a power supply chip having a power supply circuit or the like. Reduce.
In a manufacturing stage, a master chip having a power supply circuit for generating power used for operation of a nonvolatile memory cell array is manufactured by being arranged in a predetermined direction on the surface of a semiconductor wafer and supplied from the master chip. A plurality of slave chips 1 each of which operates using a power source and has a non-volatile memory cell array are arranged around the master chip 2 on the surface of the semiconductor wafer 100 on which the columns of the master chips 2 are arranged. The non-volatile semiconductor memory device is manufactured from the master chip 2 and the plurality of slave chips 1 manufactured as described above.
[Selection] Figure 4

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

In a memory system in which a plurality of nonvolatile memory chips such as SSD (Solid State Drive) are simultaneously mounted, a peripheral circuit such as a power supply circuit has generally been mounted on all the nonvolatile memory chips.
However, there is one that realizes reduction in area and low consumption of the nonvolatile memory chip by sharing the power circuit as a power chip on the system board and deleting the power circuit from each nonvolatile memory chip (for example, Patent Document 1, Non-patent document 1 etc.).

  The memory system described in Patent Document 1 and Non-Patent Document 1 includes, for example, an MCP that stores a plurality of nonvolatile memory chips from which a power supply circuit is deleted and a power supply chip having a power supply circuit in one package. (Multi-chip package). In this configuration, the power supply chip is arranged as a common circuit on the system board, and the stacked power supply chip and the plurality of nonvolatile memory chips are connected via a TSV (Through Silicon Via) or a bonding wire. .

JP 2009-3991 A

Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: "A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD," pp.238-239, IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009.

  In the memory systems described in Patent Document 1 and Non-Patent Document 1, since a power supply chip is provided, a power supply circuit does not exist on the nonvolatile memory chip. For this reason, when evaluating a nonvolatile memory chip, an external tester is used to connect the power supply chip and the nonvolatile memory chip, or power is supplied from the external tester to the nonvolatile memory chip, or it is actually assembled into the system. There is a problem that accurate evaluation is not possible unless it is from. Many non-volatile memories such as NAND flash memories require a very high voltage and complicated timing adjustment during testing, and require expensive testers, which increases the manufacturing cost. Further, when evaluation is performed after the system is assembled, if any of the memory chips is defective, there is a possibility that the system will not be established, resulting in an increase in manufacturing cost.

  The present invention has been made in consideration of the above circumstances, and uses a plurality of nonvolatile memory chips in which a power supply circuit and the like are omitted and a power supply chip having a power supply circuit and the like, and a nonvolatile semiconductor memory device (memory system). It is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can reduce the cost and manufacturing cost required for evaluation in the manufacturing stage.

  In order to solve the above problems, a nonvolatile semiconductor memory device of the present invention is manufactured by being arranged in a predetermined direction on the surface of a semiconductor wafer, and generates a power source used for the operation of the nonvolatile memory cell array. A master chip having a circuit and a surface of the semiconductor wafer that is arranged as a parallel row adjacent to the row of the master chips, and is manufactured to have the same width in the column direction as the master chip. And a plurality of slave chips each having a non-volatile memory cell array that operates using a power source supplied from.

  A method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a semiconductor wafer that is manufactured by being arranged in a predetermined direction on the surface of a semiconductor wafer, and has a power supply circuit that generates a power supply used for the operation of the nonvolatile memory cell array. Chips are arranged on the surface of the semiconductor wafer as parallel rows adjacent to the rows of the master chips, and are manufactured to have the same width in the row direction as the master chips, and are supplied from the master chips. A plurality of slave chips each having a nonvolatile memory cell array that operates using a power supply are assembled in a single package in a stacked or flat manner.

  According to the present invention, a master chip having a power supply circuit for generating a power supply used for the operation of the nonvolatile memory cell array and a semiconductor chip arranged around the master chip on the semiconductor wafer in which the master chip is arranged in the center are manufactured. A nonvolatile semiconductor memory device is manufactured using a plurality of slave chips each having a nonvolatile memory cell array that operates using power supplied from a master chip. Therefore, by supplying the power generated by the master chip on the wafer to the slave chip, the nonvolatile memory can be easily evaluated without using an expensive tester. In addition, since each chip can be evaluated on the wafer before being assembled into the system, it is possible to prevent the occurrence of a problem of failure as a system due to a defective memory chip.

1 is a schematic diagram showing a structure of a nonvolatile semiconductor memory device as one embodiment of the present invention. It is a mimetic diagram for explaining one embodiment of the present invention. It is a mimetic diagram for explaining one embodiment of the present invention. It is a schematic diagram showing an arrangement example of the nonvolatile semiconductor memory device as one embodiment of the present invention in the semiconductor wafer manufacturing stage.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing the structure of a nonvolatile semiconductor memory device 10 as an embodiment of the present invention. FIG. 2 is a schematic diagram for explaining a configuration example of the slave chip 1 shown in FIG. FIG. 3 is a schematic diagram for explaining a configuration example of the master chip 2 shown in FIG. FIG. 4 is a schematic diagram showing an arrangement example of the slave chip 1 shown in FIG. 2 and the master chip 2 shown in FIG. 3 on the semiconductor wafer 100.

  As shown in the schematic side view of FIG. 1, the nonvolatile semiconductor memory device 10 as one embodiment of the present invention includes a plurality of slave chips 1 and a single master chip 2. It is assembled in a form sealed in a package. The plurality of slave chips 1 have a connection pad portion 13 having a plurality of pads serving as connection terminals with other chips and the like, and one master chip 2 has a plurality of connection terminals with other chips and the like. It has the connection pad part 22 provided with a pad. In the example shown in FIG. 1, the connection pad portion 13 and the connection pad portion 22 are connected to a connection portion 3 consisting of a bonding pad or a bonding area on a package substrate or a lead frame (not shown). Are connected using a connector 4 consisting of Note that the shape of the multi-chip package is not limited to that shown in FIG. 1. For example, a plurality of chips are not limited to being stacked, and can be placed flat and packed in the same package, and the shape and manufacturing method are known. Can be adopted. In the nonvolatile semiconductor memory device 10 of FIG. 1, the master chip 2 is manufactured by being arranged in a predetermined direction on the surface of the semiconductor wafer in the manufacturing stage, and the slave chip 1 includes the nonvolatile memory cell array and A power supply circuit for generating a power supply used for the operation of each circuit is provided. The plurality of slave chips 1 are manufactured by being arranged around the master chip 2 on the semiconductor wafer on which the master chip 2 is arranged, and operate using the power supplied from the master chip 2. Each includes a non-volatile memory cell array. Here, a plurality of rows of the plurality of slave chips 1 are arranged so as to be parallel to the row of the master chips 2 with respect to the row in which the master chips 2 are arranged. In the column direction in which the chips are arranged, the width of the master chip 2 and the width of the slave chip 1 are the same. A plurality of slave chips 1 that are perpendicular to the arrangement direction of the master chips 2 are connected to each master chip 2 by the uppermost wiring layer.

  As shown in FIG. 2, the slave chip 1 of FIG. 1 includes a first circuit block 11, a second circuit block 12, and a connection pad unit 13. The first circuit block 11 includes circuits such as a nonvolatile memory cell array, a row decoder, a sense amplifier circuit, and a page buffer. This non-volatile memory cell array has a plurality of non-volatile memory cells. The row decoder is a circuit that selects and drives a word line connected to control gates of a plurality of nonvolatile memory cells. The sense amplifier circuit is a circuit that amplifies and detects a potential representing a stored value of each nonvolatile memory cell. The page buffer temporarily stores data for one page, which is a unit for reading and programming a plurality of nonvolatile memory cells.

  The second circuit block 12 includes circuits such as a slave control circuit, an address decoder, a column redundancy circuit, and a block redundancy circuit. The slave control circuit generates a control signal for controlling each part in the slave chip 1 by exchanging a predetermined control signal with a master control circuit in the master chip 2 described later. The operation of the driving circuit for each cell is controlled. Note that the driving circuit for each cell includes at least a decoder circuit and a sense amplifier circuit for driving each cell included in the nonvolatile memory cell array. The address decoder decodes an address signal input from, for example, the master chip 2 and generates a selection signal corresponding to a predetermined memory cell array in the nonvolatile memory cell array in the first circuit block 11. The column redundancy circuit is a circuit that performs address conversion when a nonvolatile memory cell is replaced in bit units. The block redundancy circuit is a circuit that performs address conversion when a nonvolatile memory cell is replaced in units of blocks (that is, erase units).

  The connection pad portion 13 includes a plurality of pads that serve as connection terminals with other chips and the like.

  The master chip 2 in FIG. 1 includes a first circuit block 21 and a connection pad portion 22 as shown in FIG. The first circuit block 21 includes circuits such as a master control circuit, a command decoder, a scheduler, an address decoder, and a power supply circuit. The master control circuit generates a control signal corresponding to a command signal or an address signal to be transmitted (or transmitted / received) to the slave chip 1 based on the output of the command decoder, scheduler and address decoder. The command decoder decodes a command signal input from the outside such as a tester and inputs it to the master control circuit. The scheduler generates a control signal and the like for controlling the operation timing of each unit. The address decoder decodes an address signal input from the outside such as a tester and inputs it to the master control circuit. The power supply circuit is a circuit that generates power supplies of various voltage levels used during program, read, and erase operations of the nonvolatile memory cell array in the slave chip 1.

  The connection pad portion 22 includes a plurality of pads that serve as connection terminals with other chips or the like.

  Next, with reference to FIG. 4, the example of arrangement | positioning on the semiconductor wafer 100 in the manufacture stage of the slave chip 1 and the master chip 2 shown in FIGS. 1-3 is demonstrated. FIG. 4 schematically shows a plan view of the semiconductor wafer 100. In the example shown in FIG. 4, each of the plurality of master chips 2 has a planar rectangular shape, and is arranged on the surface of the semiconductor wafer 100 in the long side direction of the rectangular shape of the master chip 2 on the semiconductor wafer 100. Yes. On the other hand, the slave chip 1 has a planar rectangular shape, and a plurality of slave chips 1 are arranged on the semiconductor wafer 100 in the short side direction of the rectangular shape of the master chip 2. By arranging in such a direction, when the master chip 2 has a rectangular shape smaller than the slave chip 1, the master chip 2 and the slave chip 1 can be arranged efficiently.

  Further, the power supply circuit and master control circuit in the master chip 2 and the slave control circuit in the slave chip 1 are the wirings 5 formed in the uppermost wiring layer on the semiconductor wafer 100 in the manufacturing stage, The master chip 2 is connected by a plurality of wirings 5 arranged in the rectangular short side direction (in the column direction of FIG. 4). In FIG. 4, the wiring 5 is schematically shown, and the wiring 5 includes a plurality of wirings.

As shown in FIG. 4, by arranging and wiring each slave chip 1 and each master chip 2 on the semiconductor wafer 100, a plurality of slave chips can be obtained using the power supply and control signals generated in the master chip 2. It becomes possible to perform 1 evaluation. Therefore, since each slave chip 1 and each master chip 2 can be evaluated on the semiconductor wafer 100, it becomes easy to select defective products before assembly, eliminating the need for unnecessary memory system assembly and assembly. Later, it is possible to suppress the yield reduction due to the failure of the slave chip 1 and to reduce the manufacturing cost of the memory system.
In addition, since the defective slave chip 1 can be detected in advance, the yield of the memory system can be expected to be improved as compared with the conventional case by setting the non-defective slave chip 1 as a new group in the group of assembly units. Moreover, since evaluation (all or most) of the slave chip 1 on the semiconductor wafer 100 can be performed by control from the master chip 2, for example, a tester probe card, an evaluation jig, etc. can be manufactured at low cost. It is also possible to do.

  The embodiment of the present invention is not limited to the above-described one. For example, a part of the internal circuit shown in FIG. 2 or FIG. 3 is replaced with the slave chip 1 and the master chip 2 or is provided on both. In addition, in the arrangement on the semiconductor wafer 100, for example, a change such as arranging a plurality of rows of master chips 2 instead of one row can be appropriately performed.

100 Semiconductor wafer 10 Non-volatile semiconductor device (multi-chip package)
1 Slave chip 2 Master chip

Claims (6)

A master chip that is manufactured by being arranged in a predetermined direction on the surface of a semiconductor wafer and has a power supply circuit that generates a power supply used for the operation of the nonvolatile memory cell array,
On the surface of the semiconductor wafer, it is arranged as a parallel row adjacent to the row of master chips, and is manufactured with the same width in the row direction as the master chip, using a power source supplied from the master chip And a plurality of slave chips each having a non-volatile memory cell array that operates in a non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of rows in which the slave chips are arranged are manufactured with respect to one row of the master chips. 3. The master chip includes the power supply circuit and a master control circuit that generates a control signal transmitted to the slave chip,
The slave chip has the nonvolatile memory cell array and a slave control circuit that controls the operation of the driving circuit of each cell included in the nonvolatile memory cell array in accordance with a control signal received from the master control circuit. The nonvolatile semiconductor memory device according to claim 1 or 2. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the driving circuit includes at least a decoder circuit and a sense amplifier circuit for driving each cell included in the nonvolatile memory cell array. 5. The power supply circuit, the master control circuit, and the slave control circuit are connected to each other at the uppermost wiring layer on the semiconductor wafer in a manufacturing stage. 5. The non-volatile semiconductor memory device described in 1. A master chip that is manufactured by being arranged in a predetermined direction on the surface of a semiconductor wafer and has a power supply circuit that generates a power supply used for the operation of the nonvolatile memory cell array,
On the surface of the semiconductor wafer, it is arranged as a parallel row adjacent to the row of master chips, and is manufactured with the same width in the row direction as the master chip, using a power source supplied from the master chip And a plurality of slave chips each having a non-volatile memory cell array operating in the same package, and assembled in a stacked or flat manner.

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