JP2013123779A - Electronic device and oscillator - Google Patents

Abstract

An electronic device including an enclosure wall that can be reduced in size and has high rigidity is provided.
In an electronic device according to the present invention, an enclosure wall intersects a first wall portion and a second wall portion extending in a first direction in a plan view. A third wall part 33 and a fourth wall part 34 extending in the second direction and connected to the first wall part 31 and the second wall part 32; An opening 35 is formed, a second opening 36 is formed in the second wall portion 32, and the first wiring layer 26 extends from the inside to the outside of the surrounding wall 30 through the first opening 35. The second wiring layer 28 extends from the inside to the outside of the surrounding wall 30 through the second opening 36, and the width of the first wall portion 31 and the width of the second wall portion 32 are the same as the third wall portion 33. And the width of the fourth wall 34 is larger.
[Selection] Figure 1

Description

  The present invention relates to an electronic device and an oscillator.

  MEMS (Micro Electro Mechanical Systems) is one of micro structure forming techniques, and refers to, for example, a technique for producing a micro electro-mechanical system of micron order and its product. There is known an electronic device in which such a functional element such as MEMS is arranged in a cavity provided on a substrate. In recent years, such electronic devices are required to be further downsized.

  For example, in Patent Document 1, a surrounding wall is formed around a functional element, an interlayer insulating layer surrounded by the surrounding wall is etched to expose the functional element, and then a covering layer is formed above the functional element. The formation of a cavity is described.

JP 2008-114354 A

  An opening for passing wiring connected to the functional element is formed in the surrounding wall formed around the functional element. The opening portion reduces the rigidity of the surrounding wall. For example, the surrounding wall may be deformed by an external force applied to the surrounding wall.

  One of the objects according to some aspects of the present invention is to provide an electronic device including an enclosure wall that can be reduced in size and has high rigidity. Another object of some aspects of the present invention is to provide an oscillator having the electronic device described above.

An electronic device according to the present invention includes:
A substrate,
A functional element formed above the substrate;
An enclosing wall formed above the substrate and defining a cavity in which the functional element is disposed;
A first wiring layer and a second wiring layer formed above the substrate and connected to the functional element;
Including
The surrounding wall is in plan view,
A first wall and a second wall extending in a first direction;
A third wall portion and a fourth wall portion extending in a second direction intersecting with the first direction and connected to the first wall portion and the second wall portion;
Have
A first opening is formed in the first wall,
A second opening is formed in the second wall,
The first wiring layer extends from the inside to the outside of the surrounding wall through the first opening,
The second wiring layer extends from the inside to the outside of the surrounding wall through the second opening.
The width of the first wall portion and the width of the second wall portion are larger than the width of the third wall portion and the width of the fourth wall portion.

  According to such an electronic device, the width of the first wall portion in which the first opening is formed is larger than the width of the third wall portion and the width of the fourth wall portion, and the second opening portion is formed. The width of the second wall portion is larger than the width of the third wall portion and the width of the fourth wall portion. For example, when the width of the surrounding wall is the same, the wall portion with the opening is less rigid than the wall portion with no opening, and the external force applied to the surrounding wall (for example, inside the cavity) May be deformed by the external force applied by the pressure difference between However, in such an electronic device, since the width of the first wall portion and the second wall portion is larger than the width of the third wall portion and the fourth wall portion, the rigidity of the first wall portion and the second wall portion is increased. And the deformation of the first wall and the second wall can be suppressed.

  Further, in such an electronic device, the size can be reduced as compared with the case where the widths of the third wall portion and the fourth wall portion are the same as the widths of the first wall portion and the second wall portion.

  As described above, in such an electronic device, it is possible to reduce the size and to include the surrounding wall having high rigidity.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the electronic device according to the present invention,
A plurality of the functional elements are provided,
The plurality of functional elements may be arranged side by side in the first direction.

  According to such an electronic device, it is possible to reduce the size and provide the surrounding wall having high rigidity.

The oscillator according to the present invention is
An electronic device according to the present invention;
A circuit portion electrically connected to the first wiring layer and the second wiring layer of the electronic device;
including.

  According to such an oscillator, since the electronic device according to the present invention is included, the size can be reduced and high reliability can be achieved.

FIG. 3 is a plan view schematically showing the electronic apparatus according to the embodiment. FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. The top view which shows typically the electronic device which concerns on the modification of this embodiment. The circuit diagram which shows the oscillator concerning this embodiment. The circuit diagram which shows the oscillator which concerns on the modification of this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituent requirements of the present invention.

1. Electronic Device First, an electronic device according to the present embodiment will be described with reference to the drawings. FIG. 1 is a plan view schematically showing an electronic device 100 according to this embodiment. 2 is a cross-sectional view taken along the line II-II of FIG. 1 schematically showing the electronic device 100 according to the present embodiment. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1 schematically showing the electronic device 100 according to the present embodiment. 4 is a cross-sectional view taken along line IV-IV in FIG. 1 schematically showing the electronic device 100 according to the present embodiment. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1 schematically showing the electronic device 100 according to the present embodiment.

  For convenience, in FIGS. 1 to 5, the X axis, the Y axis, and the Z axis are illustrated as three axes orthogonal to each other.

  As illustrated in FIGS. 1 to 5, the electronic device 100 includes a substrate 10, a functional element 20, a first wiring layer 26, a second wiring layer 28, and a surrounding wall 30. Further, the electronic device 100 can include a first covering layer 50, a second covering layer 54, interlayer insulating layers 60, 62, 64, and a passivation layer 70.

  For convenience, the covering layers 50 and 54 and the passivation layer 70 are not shown in FIG. In FIG. 5, the functional element 20 is not shown.

  The substrate 10 can include a support substrate 12, a first insulating layer 14, and a second insulating layer 16.

  As the support substrate 12, for example, a semiconductor substrate such as a silicon substrate is used. As the support substrate 12, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate may be used.

  The first insulating layer 14 is formed on the support substrate 12. As the first insulating layer 14, for example, a LOCOS (local oxidation of silicon) insulating layer, a semi-recessed LOCOS insulating layer, or a trench insulating layer is used. The first insulating layer 14 can electrically isolate the functional element 20 from other elements (for example, a transistor, not shown).

  The second insulating layer 16 is formed on the first insulating layer 14. For example, a silicon nitride layer is used as the second insulating layer 16. The second insulating layer 16 can function as an etching stopper layer in the release process for forming the cavity 1.

  The functional element 20 is formed on the substrate 10 and is accommodated in the cavity 1. The functional element 20 is, for example, a cantilever type MEMS vibrator. In the illustrated example, the functional element 20 includes a first electrode 22 formed on the substrate 10 and a second electrode 24 formed at a distance from the first electrode 22. Although the planar shape of the 1st electrode 22 and the 2nd electrode 24 is not specifically limited, In the example shown in FIG. 1, it is a rectangle.

  The second electrode 24 can include a support portion 24 a formed on the substrate 10 and a beam portion 24 b extending from the support portion 24 a and arranged to face the first electrode 22. Examples of the material of the first electrode 22 and the second electrode 24 include polycrystalline silicon imparted with conductivity by doping a predetermined impurity (for example, boron).

  In the functional element 20, when a voltage (alternating voltage) is applied between the first electrode 22 and the second electrode 24, the beam portion 24 b causes the electrostatic force generated between the electrodes 22 and 24 to generate a thickness direction of the substrate 10. It can vibrate in the (Z-axis direction). Thereby, for example, a signal (output signal) having a predetermined frequency (frequency corresponding to the natural frequency of the beam portion 24 b) can be output from the first electrode 22.

  The functional element 20 is not limited to the illustrated example, and may be, for example, a double-supported beam type vibrator in which both ends of the beam portion are fixed. In addition, the functional element 20 includes a first electrode portion and a second beam portion in which the second electrode includes a support portion, and a first beam portion and a second beam portion that extend in opposite directions from the support portion. A vibrator in which a first electrode is formed opposite to each of the first and second electrodes may be used. In addition, the functional element 20 may be various functional elements such as a quartz vibrator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyroscope, and a microactuator other than the vibrator. Thus, the electronic device 100 can include any functional element that can be accommodated in the cavity 1.

  The first wiring layer 26 is formed on the substrate 10 and connected to the first electrode 22. For example, the first wiring layer 26 is formed integrally with the first electrode 22. The first wiring layer 26 extends from the inside to the outside of the surrounding wall 30 through the first opening 35 formed in the first wall portion 31 of the first surrounding wall 30.

  The second wiring layer 28 is formed on the substrate 10 and connected to the support portion 24 a of the second electrode 24. For example, the second wiring layer 28 is formed integrally with the second electrode 24. The second wiring layer 28 extends from the inside to the outside of the surrounding wall 30 through the second opening 36 formed in the second wall portion 32 of the first surrounding wall 30.

  Examples of the material of the first wiring layer 26 and the second wiring layer 28 include polycrystalline silicon to which conductivity is imparted by doping a predetermined impurity (for example, boron). The wiring layers 26 and 28 are electrically connected to a power supply unit (not shown), and a voltage can be applied between the electrodes 22 and 24 via the wiring layers 26 and 28.

  The surrounding wall 30 defines the cavity 1 in which the functional element 20 is disposed. The surrounding wall 30 is formed on the substrate 10 and around the cavity 1. As shown in FIG. 1, the surrounding wall 30 has a planar shape surrounding the functional element 20 in a plan view from the thickness direction of the substrate 10 (hereinafter, also simply referred to as “plan view”).

  In the illustrated example, the surrounding wall 30 includes a conductive layer 40, a first metal layer 41 formed on the conductive layer 40 and the interlayer insulating layer 60, and a second metal layer formed on the first metal layer 41. 42 and a third metal layer 43 formed on the second metal layer 42.

  Examples of the material of the conductive layer 40 include polycrystalline silicon imparted with conductivity by doping a predetermined impurity (for example, boron). As the metal layers 41, 42, and 43, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer can be used.

  The surrounding wall 30 can include a first wall portion 31, a second wall portion 32, a third wall portion 33, and a fourth wall portion 34, which are configured by the conductive layer 40 and the metal layers 41, 42, and 43. .

  As shown in FIG. 1, the first wall portion 31 extends in the first direction (Y-axis direction in the illustrated example) in plan view. In the illustrated example, the first wall portion 31 has a certain width (length in the X-axis direction) and extends in the Y-axis direction.

  As shown in FIGS. 1 to 3, a first opening 35 is formed in the first wall portion 31. The first opening portion 35 penetrates the first wall portion 31 in the X-axis direction, for example. The first opening 35 is formed at a position overlapping the first wiring layer 26 in plan view.

  The second wall portion 32 extends in the first direction (Y-axis direction in the illustrated example) in plan view. In the illustrated example, the second wall portion 32 has a certain width (length in the X-axis direction) and extends in the Y-axis direction. The second wall portion 32 is disposed to face the first wall portion 31, and the functional element 20 is disposed between the first wall portion 31 and the second wall portion 32.

  A second opening 36 is formed in the second wall portion 32. The second opening 36 penetrates the second wall 32 in the X-axis direction, for example. The second opening 36 is formed at a position overlapping the second wiring layer 28 in plan view.

  In the illustrated example, the openings 35 and 36 are formed in the conductive layer 40 and the first metal layer 41. For example, two conductive layers 40 are separated by the openings 35 and 36, and a recess is provided in the first metal layer 41. In the openings 35 and 36, for example, an interlayer insulating layer 60 is formed. That is, the interlayer insulating layer 60 is formed between the first metal layer 41 and the wiring layers 26 and 28.

  The third wall portion 33 extends in a second direction (X-axis direction in the illustrated example) intersecting the first direction in plan view. In the illustrated example, the third wall portion 33 has a certain width (the length in the Y-axis direction) and extends in the X-axis direction. The third wall portion 33 is connected to the first wall portion 31 and the second wall portion 32.

  The fourth wall portion 34 extends in the second direction (X-axis direction in the illustrated example) in plan view. In the illustrated example, the fourth wall portion 34 has a constant width (length in the Y-axis direction) and extends in the X-axis direction. The fourth wall portion 34 is connected to the first wall portion 31 and the second wall portion 32. The fourth wall portion 34 is disposed to face the third wall portion 33, and the functional element 20 is disposed between the third wall portion 33 and the fourth wall portion 34.

  In the illustrated example, the length of the first wall portion 31 in the Y-axis direction is larger than the length of the third wall portion 33 in the X-axis direction and the length of the fourth wall portion 34 in the X-axis direction. Similarly, the length of the second wall portion 32 in the Y-axis direction is larger than the length of the third wall portion 33 in the X-axis direction and the length of the fourth wall portion 34 in the X-axis direction. That is, the cavity 1 has a length in the Y-axis direction that is longer than a length in the X-axis direction.

  As shown in FIGS. 4 and 5, the width L1 of the first wall portion 31 is larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34. Furthermore, the width L2 of the second wall portion 32 is larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34.

  Here, the widths L1 and L2 of the wall portions 31 and 32 are the lengths of the wall portions 31 and 32 in the first direction (the length in the X-axis direction in the illustrated example). This is the length of the portion having the minimum length in the first direction (the length in the first direction).

  In the example illustrated in FIG. 4, the widths L <b> 1 and L <b> 2 are the length of the first metal layer 41 between the interlayer insulating layer 60 and the cavity 1 (the length in the X-axis direction). In the example shown in FIG. 4, the widths L1 and L2 can be said to be the length of the contact surface between the first metal layer 41 and the conductive layer 40 (length in the X-axis direction). The widths L1 and L2 are, for example, the same length and about 32 μm.

  The widths L3 and L4 of the wall portions 33 and 34 are the lengths of the wall portions 33 and 34 in the second direction (the length in the Y-axis direction in the illustrated example). This is the length of the portion (the length in the second direction) that minimizes the length in the second direction.

  In the example shown in FIG. 5, the widths L3 and L4 are the lengths of the first metal layer 41 between the interlayer insulating layer 60 and the cavity 1. In the example shown in FIG. 5, the widths L3 and L4 can be said to be the length of the contact surface between the first metal layer 41 and the conductive layer 40 (the length in the Y-axis direction). The widths L3 and L4 are, for example, the same length and about 12 μm.

  In the illustrated example, the length of the contact surface (length in the X-axis direction) between the first metal layer 41 and the second metal layer 42 constituting the walls 31 and 32 is the first of the walls 33 and 34. The length of the contact surface between the first metal layer 41 and the second metal layer 42 (the length in the Y-axis direction) is larger.

  The length of the contact surface between the second metal layer 42 and the third metal layer 43 (the length in the X-axis direction) constituting the walls 31 and 32 is the second metal layer constituting the walls 33 and 34. It is larger than the length of the contact surface between 42 and the third metal layer 43 (the length in the Y-axis direction).

  In the illustrated example, the surrounding wall 30 includes three metal layers 40, 41, and 42, but the number of metal layers is not particularly limited. Further, the surrounding wall 30 may not have the conductive layer 40.

  The interlayer insulating layers 60, 62, and 64 are formed above the substrate 10 and around the surrounding wall 30. As the interlayer insulating layers 60, 62, and 64, for example, silicon oxide layers are used. In the illustrated example, the electronic device 100 includes three interlayer insulating layers 60, 62, and 64. However, the number of interlayer insulating layers is not particularly limited. For example, the number of metal layers of the surrounding wall 30 is the same as the number of metal layers. It can be changed as appropriate.

  The first covering layer 50 is formed so as to cover the cavity 1 from above. For example, the first covering layer 50 is formed integrally with the third metal layer 43 and is made of the same material as the third metal layer 43. A through hole 52 that communicates with the cavity 1 is formed in the first coating layer 50. The through hole 52 penetrates the first coating layer 50 in the Z-axis direction. The number of through holes 52 is not particularly limited.

  The second coating layer 54 is formed on the first coating layer 50. The second coating layer 54 closes the through hole 52. As the 2nd coating layer 54, the laminated body of an aluminum layer, a titanium layer, or an aluminum layer and a titanium layer can be used, for example. The first coating layer 50 and the second coating layer 54 can function as a sealing member that covers the cavity 1 from above and seals the cavity 1.

  The cavity 1 is defined by, for example, the substrate 10, the surrounding wall 30, the interlayer insulating layer 60, and the covering layers 50 and 54. The inside of the cavity portion 1 is kept in a reduced pressure state, whereby the operation accuracy of the functional element 20 can be improved.

  It is desirable that a constant potential (for example, ground potential) is applied to the surrounding wall 30 and the covering layers 50 and 54. Thereby, the surrounding wall 30 and the coating layers 50 and 54 can be functioned as an electromagnetic shield. Therefore, the functional element 20 can be electrically shielded from the outside. Thereby, the functional element 20 can have more stable characteristics.

  The passivation layer 70 is formed on the interlayer insulating layer 64 and the third metal layer 43 so as to avoid the region where the second covering layer 54 is formed. For example, a silicon nitride layer is used as the passivation layer 70.

  As shown in FIGS. 2 and 3, a sacrificial layer 80 may be formed between the first wiring layer 26 and the interlayer insulating layer 60.

  The electronic device 100 according to the present embodiment has the following features, for example.

  According to the electronic device 100, the width L1 of the first wall 31 in which the first opening 35 is formed is larger than the width L3 of the third wall 33 and the width L4 of the fourth wall 34, and the second opening. The width L2 of the second wall portion 32 in which the portion 36 is formed is larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34. For example, when the width of the surrounding wall is the same, the wall portion with the opening is less rigid than the wall portion with no opening, and the external force applied to the surrounding wall (for example, inside the cavity) May be deformed by the external force applied by the pressure difference between Thereby, for example, reliability may be lowered. However, in the electronic device 100, since the widths L1 and L2 of the walls 31 and 32 are larger than the widths L3 and L4 of the walls 33 and 34, the rigidity of the walls 31 and 32 in which the openings 35 and 36 are formed is increased. It can be made high and it can control that wall parts 31 and 32 change.

  Furthermore, in the electronic device 100, the size can be reduced as compared with the case where the widths of the third wall portion and the fourth wall portion are the same as the widths of the first wall portion and the second wall portion.

  As described above, the electronic apparatus 100 can include the surrounding wall 30 that can be reduced in size and has high rigidity.

2. Next, a method for manufacturing an electronic device according to the present embodiment will be described with reference to the drawings. 6-11 is sectional drawing which shows typically the manufacturing process of the electronic device 100 which concerns on this embodiment. 6, 7, 10, and 11 show cross-sectional views corresponding to FIG. 2. 8 and 9, (a) in the drawing shows a cross-sectional view corresponding to FIG. 2, (b) in the drawing shows a cross-sectional view corresponding to FIG. 3, and (c) in the drawing shows FIG. 5 shows a cross-sectional view corresponding to FIG. 4.

  As shown in FIG. 6, the first insulating layer 14 and the second insulating layer 16 are formed in this order on the support substrate 12 to obtain the substrate 10. The first insulating layer 14 is formed by, for example, a LOCOS method or an STI (shallow trench isolation) method. The second insulating layer 16 is formed by, for example, a CVD (Chemical Vapor Deposition) method or a sputtering method.

  As shown in FIG. 7, the first electrode 22 and the first wiring layer 26 connected to the first electrode 22 are formed on the substrate 10. The first electrode 22 and the first wiring layer 26 can be integrally formed. More specifically, the first electrode 22 and the first wiring layer 26 are formed by being patterned by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. In the case where the first electrode 22 and the first wiring layer 30 are made of polycrystalline silicon, a predetermined impurity is doped to impart conductivity.

  Next, a sacrificial layer 80 is formed so as to cover the first electrode 22 and the first wiring layer 26 by performing, for example, thermal oxidation treatment.

  Next, the second electrode 24 is formed on the sacrificial layer 80 and the substrate 10, and further, the second wiring layer 28 connected to the second electrode 24 is formed on the substrate 10. The second electrode 24 and the second wiring layer 28 can be integrally formed. The second electrode 24 and the second wiring layer 28 are formed by, for example, a film forming process and a patterning process similar to the first electrode 22 and the first wiring layer 26. When the second electrode 24 and the second wiring layer 28 are made of polycrystalline silicon, a predetermined impurity is doped to impart conductivity. Through the above steps, the functional element 20 can be formed.

  In the step of forming the second electrode 24 and the second wiring layer 28, the conductive layer 40 can be formed. The conductive layer 40 may be formed in the step of forming the first electrode 22 and the first wiring layer 26.

  As illustrated in FIG. 8, an interlayer insulating layer 60 is formed over the substrate 10 so as to cover the second electrode 24, the second wiring 28, the conductive layer 40, and the sacrificial layer 80. The interlayer insulating layer 60 is formed by, for example, a CVD method or a coating (spin coating) method.

  Next, the interlayer insulating layer 60 is patterned so that the conductive layer 40 is exposed to form contact holes 61. The patterning is performed so that the wiring layers 26 and 28 are not exposed. The patterning is performed by, for example, a photolithography technique and an etching technique.

  As shown in FIG. 9, the first metal layer 41 is formed in the contact hole 61 and on the interlayer insulating layer 60. As described above, since the contact hole is not formed on the wiring layers 26 and 28, the first metal layer 41 is not formed immediately above the wiring layers 26 and 28. Thereby, the first metal layer 41 has a shape in which a recess is formed, and the openings 35 and 36 are formed. The first metal layer 41 is formed by, for example, forming a film by a sputtering method, a plating method or the like and then patterning the film by a photolithography technique and an etching technique.

  As shown in FIG. 10, an interlayer insulating layer 62 is formed above the interlayer insulating layer 60 so as to cover the first metal layer 41. Next, the interlayer insulating layer 62 is patterned so that the first metal layer 41 is exposed to form a contact hole 63. Next, the second metal layer 42 is formed in the contact hole 63.

  Next, an interlayer insulating layer 64 is formed above the interlayer insulating layer 62 so as to cover the second metal layer 42. Next, the interlayer insulating layer 64 is patterned so that the second metal layer 42 is exposed to form a contact hole 65. Next, the third metal layer 43 is formed in the contact hole 65. The surrounding wall 30 can be formed by the above process.

Further, the first covering layer 50 in which the through holes 52 are formed is formed on the interlayer insulating layer 64. The first covering layer 50 is formed integrally with the third metal layer 43.

  The interlayer insulating layers 62 and 64 are formed by, for example, a CVD method or a coating (spin coating) method. The metal layers 42 and 43 and the first coating layer 50 are formed by, for example, forming a film by a sputtering method, a plating method, or the like and then patterning the film by a photolithography technique and an etching technique. The through hole 52 can be formed simultaneously in the patterning for forming the third metal layer 43 and the first covering layer 50.

  As shown in FIG. 11, a passivation layer 70 is formed on the interlayer insulating layer 64 and the third covering layer 43. The passivation layer 70 is formed by, for example, forming a film by a CVD method or a sputtering method, and then patterning the film by a photolithography technique and an etching technique.

  Next, the interlayer insulating layers 60, 62, 64 and the sacrificial layer 80 surrounded by the surrounding wall 30 are etched through the through hole 52, for example, to form the cavity 1 (release process). Etching is performed by wet etching using, for example, hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride).

  As shown in FIG. 1, a second coating layer 54 is formed on the first coating layer 50. Thereby, the through-hole 52 can be closed and the cavity part 1 can be sealed. The second coating layer 54 is formed by, for example, forming a film by a CVD method, a sputtering method, or the like and then patterning the film by a photolithography technique and an etching technique.

  The electronic device 100 according to the present embodiment can be manufactured through the above steps.

  According to the method for manufacturing the electronic device 100, the width L1 of the first wall portion 31 in which the first opening 35 is formed is larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34. Further, the width L2 of the second wall portion 32 in which the second opening 36 is formed can be formed larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34. . Therefore, as described above, it is possible to reduce the size and form the electronic device 100 including the surrounding wall 30 having high rigidity.

3. Next, an electronic device according to a modification of the present embodiment will be described with reference to the drawings. FIG. 12 is a plan view schematically showing an electronic device 200 according to a modification of the present embodiment. For convenience, FIG. 12 illustrates an X axis, a Y axis, and a Z axis as three axes orthogonal to each other. In FIG. 12, the covering layers 50 and 54 and the passivation layer 70 are not shown.

  Hereinafter, in the electronic device 200, members having the same functions as those of the components of the electronic device 100 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  The electronic device 100 has one functional element 20 as shown in FIG. On the other hand, the electronic device 200 includes a plurality of functional elements 20 as shown in FIG.

  In the illustrated example, the electronic device 200 includes five functional elements 20, but the number is not particularly limited. The plurality of functional elements 20 are arranged side by side in the first direction (Y-axis direction in the illustrated example). A plurality of wiring layers 26 and 28 are provided according to the plurality of functional elements 20, and a plurality of openings 35 and 36 are provided according to the plurality of wiring layers 26 and 28.

  Although not shown, the plurality of first wiring layers 26 are electrically connected to each other, for example. The plurality of second wiring layers 28 are electrically connected to each other, for example.

  According to the electronic device 200, the number of the openings 35 and 36 formed in the surrounding wall 30 is larger than that of the electronic device 100. Therefore, for example, when the width of the surrounding wall is the same, the rigidity of the wall part in which the opening part is formed is further reduced as compared with the wall part in which the opening part is not formed. However, in the electronic device 200, the width L1 of the first wall portion 31 and the width L2 of the second wall portion 32 are larger than the width L3 of the third wall portion 33 and the width L4 of the fourth wall portion 34. Even if a plurality of each of 35 and 36 are formed, the walls 31 and 32 can have high rigidity.

  Furthermore, in the electronic device 200, a plurality of functional elements 20 are arranged side by side in the Y-axis direction. Therefore, compared with the electronic device 100, the length in the Y-axis direction is increased. Here, for example, the width (the length in the Y-axis direction) of the third wall portion and the fourth wall portion where the opening is not formed is the width of the first wall portion and the second wall portion where the opening is formed. In the case where it is the same as (the length in the X-axis direction), the length in the Y-axis direction is further increased. However, in the electronic device 200, since the widths L3 and L4 of the wall portions 33 and 34 are smaller than the widths L1 and L2 of the wall portions 31 and 32, the size can be reduced accordingly.

4). Oscillator Next, an oscillator according to this embodiment will be described with reference to the drawings. FIG. 13 is a circuit diagram showing an oscillator 600 according to the present embodiment.

  As shown in FIG. 13, the oscillator 600 includes, for example, an electronic device (for example, the electronic device 100) according to the present invention and an inverting amplifier circuit (circuit unit) 610.

  The electronic device 100 includes a first terminal 100 a that is electrically connected to the first wiring layer 26, and a second terminal 100 b that is electrically connected to the second wiring layer 28. The first terminal 100a of the electronic device 100 is connected to the input terminal 610a of the inverting amplifier circuit 610 at least in an AC manner. The second terminal 100b of the electronic device 100 is connected to the output terminal 610b of the inverting amplifier circuit 610 at least in an AC manner.

  In the illustrated example, the inverting amplifier circuit 610 is configured by one inverter, but may be configured by combining a plurality of inverters (inverting circuits) and amplifier circuits so that a desired oscillation condition is satisfied. .

  The oscillator 600 may include a feedback resistor for the inverting amplifier circuit 610. In the example shown in FIG. 13, the input terminal and the output terminal of the inverting amplifier circuit 610 are connected via a resistor 620.

  The oscillator 600 includes a first capacitor 630 connected between an input terminal 610a of the inverting amplifier circuit 610 and a reference potential (ground potential), and an output terminal 610b of the inverting amplifier circuit 610 and a reference potential (ground potential). And a second capacitor 632 connected to the second capacitor 632. As a result, the MEMS vibrator 100 and the capacitors 630 and 632 can form an oscillation circuit that forms a resonance circuit. The oscillator 600 outputs the oscillation signal f obtained by this oscillation circuit.

  Elements (not shown) such as transistors and capacitors constituting the oscillator 600 may be formed on the substrate 10 (see FIG. 2), for example. Thereby, the electronic device 100 and the anti-amplifier circuit 610 can be formed monolithically.

  When an element such as a transistor constituting the oscillator 600 is formed on the substrate 10, the element such as a transistor constituting the oscillator 600 may be formed in the same process as the process for forming the electronic device 100 described above. Specifically, in the step of forming the sacrificial layer 80 (see FIG. 7), a gate insulating layer of a transistor may be formed. Further, in the step of forming the second electrode 24 (see FIG. 7), a gate electrode of a transistor may be formed. In this way, by simplifying the manufacturing process of the electronic device 100 and the manufacturing process of the elements such as the transistors included in the oscillator 600, the manufacturing process can be simplified.

  The oscillator 600 includes the electronic device 100 including the surrounding wall 30 that can be reduced in size and has high rigidity. Therefore, the oscillator 600 can be reduced in size and can have high reliability.

  Note that the oscillator 600 may further include a frequency dividing circuit 640 as shown in FIG. The frequency dividing circuit 640 divides the output signal Vout of the oscillation circuit and outputs the oscillation signal f. Thereby, the oscillator 600 can obtain an output signal having a frequency lower than the frequency of the output signal Vout, for example.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 Cavity part, 10 board | substrate, 12 support substrate, 14 1st insulating layer, 16 2nd insulating layer
20 functional elements, 22 1st electrode, 24 2nd electrode, 24a support part, 24b beam part,
26 first wiring layer, 28 second wiring layer, 30 surrounding wall, 31 first wall portion,
32 2nd wall part, 33 3rd wall part, 34 4th wall part, 35 1st opening part,
36 second opening, 40 conductive layer, 41 first metal layer, 42 second metal layer,
43 third metal layer, 50 first coating layer, 52 through-hole, 54 second coating layer,
60 interlayer insulation layers, 61 contact holes, 62 interlayer insulation layers,
63 contact holes, 64 interlayer insulation layers, 65 contact holes,
70 passivation layer, 80 sacrificial layer, 100 electronic device, 100a first terminal,
100b second terminal, 200 electronic device, 600 oscillator, 610 inverting amplifier circuit,
610a input terminal, 610b output terminal, 620 resistor, 630 first capacitor,
632 Second capacitor, 640 frequency divider

Claims (3)

A substrate,
A functional element formed above the substrate;
An enclosing wall formed above the substrate and defining a cavity in which the functional element is disposed;
A first wiring layer and a second wiring layer formed above the substrate and connected to the functional element;
Including
The surrounding wall is in plan view,
A first wall and a second wall extending in a first direction;
A third wall portion and a fourth wall portion extending in a second direction intersecting with the first direction and connected to the first wall portion and the second wall portion;
Have
A first opening is formed in the first wall,
A second opening is formed in the second wall,
The first wiring layer extends from the inside to the outside of the surrounding wall through the first opening,
The second wiring layer extends from the inside to the outside of the surrounding wall through the second opening.
The width of the said 1st wall part and the width | variety of the said 2nd wall part are larger than the width | variety of the said 3rd wall part, and the width | variety of the said 4th wall part. In claim 1,
A plurality of the functional elements are provided,
The electronic device, wherein the plurality of functional elements are arranged side by side in the first direction. An electronic device according to claim 1 or 2,
A circuit portion electrically connected to the first wiring layer and the second wiring layer of the electronic device;
Including an oscillator.

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