JP2013120480A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the apparent number of permitted accesses and operation speed of a main memory (e.g., FeRAM).SOLUTION: A semiconductor memory device 10 comprises: a main memory 11 (e.g., FeRAM) that has a limitation on the number of permitted accesses thereto; and a successive access restriction section 12 that performs input/output of data on behalf of the main memory 11 so that successive accesses to an identical word of the main memory 11 do not occur.

Description

  The present invention relates to a semiconductor memory device.

  In recent years, ferroelectric memory (hereinafter referred to as FeRAM [ferroelectric random access memory]) has been put into practical use.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP-A-10-021689

  In the practical application of FeRAM, one of the problems to be solved is improvement of the number of times of access (endurance). This problem also applies to EEPROM (electrically erasable programmable read only memory) and flash memory.

  FeRAM belongs to a high-speed class as a nonvolatile semiconductor memory device, but its operation speed is slower than a general volatile semiconductor memory device (for example, SRAM [static RAM]). Therefore, in order to use FeRAM as a work memory of a sequencer (CPU [central processing unit] or the like), further improvement of the operation speed is necessary.

  However, due to the device structure of FeRAM, it has been difficult to improve the accessible number of times and the operation speed of FeRAM itself.

  In view of the above-mentioned problems found by the inventors of the present application, for example, a main object of the present invention is to provide a semiconductor memory device capable of improving the apparent number of accessible times and operating speed of FeRAM. And

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a main memory having a limited number of accessible times and a main memory in which the same word of the main memory is not continuously accessed. Instead, it has a configuration (first configuration) having a continuous access restriction unit that inputs and outputs data.

  In the semiconductor memory device having the first configuration, the continuous access restriction unit may be configured as a first cache memory (second configuration) having a high association and a small capacity.

  In the semiconductor memory device having the second configuration, the data storage method of the first cache memory may be a full associative configuration (third configuration).

  In the semiconductor memory device having the third configuration, the line replacement method of the first cache memory may be a configuration (fourth configuration) that is an LRU [least recently used] method.

  Further, the semiconductor memory device having the fourth configuration has a configuration (fifth configuration) having a second cache memory having a lower association and a larger capacity than the first cache memory, in addition to the first cache memory. Good.

  In the semiconductor memory device having the fifth configuration, the first cache memory may have a configuration (sixth configuration) including a nonvolatile logic for storing data in a nonvolatile manner.

  In the semiconductor memory device having the sixth configuration, the non-volatile logic includes a volatile memory unit that volatilely stores data using a plurality of logic gates connected in a loop, and a ferroelectric element. Using a hysteresis characteristic, a nonvolatile storage unit that nonvolatilely stores data volatilely stored in the volatile storage unit, and a circuit separation that electrically isolates the volatile storage unit and the nonvolatile storage unit And a configuration (seventh configuration).

  In the semiconductor memory device having any one of the first to seventh configurations, the main memory may be configured as a ferroelectric memory (eighth configuration).

  In the semiconductor memory device having any one of the first to eighth configurations, the main memory and the continuous access restricting unit may be integrated on the same chip (ninth configuration).

  Further, in the semiconductor memory device having the ninth configuration described above, the chip may have a configuration (tenth configuration) in which a sequencer that mainly accesses the main memory is also incorporated.

  In the semiconductor memory device having the tenth configuration, the sequencer may be a CPU (central processing unit) (an eleventh configuration).

  According to the present invention, for example, it is possible to provide a semiconductor memory device capable of improving the apparent number of accessible times and operation speed of FeRAM.

1 is a block diagram showing a first embodiment of a semiconductor memory device Block diagram for explaining the configuration and operation of the continuous access restriction unit 12 Block diagram showing a second embodiment of a semiconductor memory device The circuit diagram which shows one structural example of the non-volatile logic which forms the continuous access control part 12 Timing chart for explaining an operation example of nonvolatile logic Circuit diagram showing signal path during normal operation Circuit diagram showing signal path during data write operation Circuit diagram showing signal path during data read operation

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device. The semiconductor storage device 10 according to the first embodiment is a circuit block used as a work memory of a sequencer 20 (CPU or the like), and includes a main memory 11 and a continuous access restriction unit 12.

The main memory 11 is an FeRAM with a limited number of accessible times. The number of accessible times of FeRAM is about 10 ¹² to 10 ¹³ per word. The maximum operating frequency of FeRAM is about 5 to 8 MHz. Therefore, if the FeRAM is continuously operated at the maximum operating frequency, the worst case (when access is concentrated only on the same word) can be calculated only for about 10 days.

  The continuous access restriction unit 12 is a circuit block that inputs and outputs data in place of the main memory 11 so that continuous access to the same word in the main memory 11 does not occur.

  The main memory 11 and the continuous access restriction unit 12 may be integrated on the same chip or may be integrated on separate chips.

  Further, when the main memory 11 and the continuous access restriction unit 12 are integrated on the same chip, a sequencer 20 that is a main subject of accessing the main memory 11 may be incorporated in the chip. In this case, the semiconductor memory device 10 is provided as a memory (so-called mixed memory) incorporated in an LSI.

  In the semiconductor memory device 10 having the above configuration, the sequencer 20 accesses the semiconductor memory device 10 using an address signal ADDR (for example, 14 bits) and a data signal DATA (for example, 16 bits). At this time, the sequencer 20 outputs a memory access request signal MERQ to the continuous access restriction unit 12. The continuous access restriction unit 10 recognizes that the address signal ADDR and the data signal DATA flowing through the bus are addressed to the semiconductor memory device 10 based on the memory access request signal MERQ, and detects the chip enable signal of the main memory 11. Generate CEn. Further, the sequencer 20 outputs a read / write request signal R / W to the continuous access restriction unit 12. The continuous access restriction unit 12 determines whether to perform a data read operation or a write operation based on the read / write request signal R / W, and outputs the output enable signal OEn and the write enable signal of the main memory 11. Generate WEn. The continuous access restriction unit 12 outputs a wait signal WAIT to the sequencer 20 when accessing the main memory 11. Hereinafter, the configuration and operation of the continuous access restriction unit 12 will be described in detail.

  FIG. 2 is a block diagram for explaining the configuration and operation of the continuous access restriction unit 12. The continuous access restriction unit 12 is a type of cache memory that inputs and outputs data in place of the main memory 11 so that continuous access to the same word in the main memory 11 does not occur. In particular, in the continuous access restriction unit 12 of this configuration example, after the n-th word is accessed once, the n-th word is re-accessed unless a miss occurs continuously m times (for example, 10 times). A cache structure is used to ensure that no attempt is made.

  More specifically, the first cache memory used as the continuous access restriction unit 12 has a data associating method of m lines (for example, 10 lines) and is a fully associative method, and the line replacement method is LRU [least recently. used] method.

  In the continuous access restriction unit 12 in which the full associative method is adopted as the data storage method, all lines are searched without being sorted by address. In other words, the full associative method is more suitable for use as the continuous access restriction unit 12 than the other methods (direct map method or set associative method) in that it is easy to realize a high degree of association (association degree = number of lines). ing.

  Note that the first associative first cache memory is likely to have a large circuit scale because both the address (tag) and data must be stored. However, the continuous access restriction unit 12 is only intended to improve the apparent number of times the main memory 11 can be accessed, and the cache hit rate can be overlooked. Therefore, it is not necessary to design the number of lines m (circuit scale) of the first cache memory used as the continuous access restriction unit 12 so large.

  In addition, in the continuous access restriction unit 12 that adopts the LRU method as the line replacement method, once the nth word is accessed, the nth word is then used unless at least m consecutive misses occur. Are never discarded from the cache.

  As described above, by providing the continuous access restriction unit 12 (first cache memory having a small association capacity m) between the main memory 11 and the sequencer 20, after the nth word is accessed once, Since it is possible to guarantee that the nth word will not be re-accessed (= nth word is not discarded from the cache) unless there is a miss hit continuously (for example, 10 times). Even in the worst case, the apparent number of accessible times of the memory 11 can be improved to (m + 1) times.

Second Embodiment
FIG. 3 is a block diagram showing a second embodiment of the semiconductor memory device. The semiconductor memory device 10 of the second embodiment is characterized in that a second cache memory 13 is added to the first embodiment. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The first cache memory used as the continuous access restriction unit 12 has a high associativeness, but has a small effect of improving the operation speed of the main memory 11 because the number of lines m (number of words) is small and the hit rate is low. For example, when FeRAM is used as the work memory of the CPU, it is necessary to realize an operation speed of several tens of MHz.

  Therefore, the semiconductor memory device 10 according to the second embodiment includes a second cache memory 13 (for example, a 1-K word 4-way set associative system) that is lower in association with the first cache memory and larger in capacity than the first cache memory. It is set as the structure which has.

  When accessing the semiconductor memory device 10 from the sequencer 20, first, the memory access request signal MERQ 1 is output from the sequencer 20 to the second cache memory 13. Receiving the memory access request signal MERQ1, the second cache memory 13 searches the cache contents. If a miss hit occurs, a wait signal WAIT1 is output from the second cache memory 13 to the sequencer 20, while a memory access request signal is output from the second cache memory 13 to the continuous access restriction unit 12 (first cache memory). MERQ2 is output. Receiving the memory access request signal MERQ2, the continuous access restriction unit 12 (first cache memory) searches the cache contents. In this case, when a mishit occurs, the chip enable signal CEn, the output enable signal OEn, and the write enable signal WEn are generated to access the main memory 11. At this time, the data to be accessed is stored in both the continuous access restriction unit 12 and the cache memory 13. On the other hand, when the hit data is stored in the second cache memory 13 or the continuous access restriction unit 12 (first cache memory), it is not necessary to access the main memory 11.

  As described above, the circuit scale of the semiconductor memory device 20 can be obtained by using the high associative and small-capacity continuous access restriction unit 12 (first cache memory) and the low associative and large-capacity second cache memory 13 together. It is possible to improve both the apparent number of accessible times and the operation speed of the main memory 11 without unnecessarily increasing.

  A configuration having only the second cache memory 13 between the sequencer 20 and the main memory 11 is often found in existing systems. However, in the second cache memory 13 for the purpose of speed improvement, since the cache hit rate is important, a larger number of lines (number of words) is required. Therefore, in order to suppress the circuit scale of the second cache memory 13 to a realistic size, the association degree must be set low (for example, association degree 4).

  Therefore, in an existing system (a system that does not have the continuous access restriction unit 12), when a miss occurs continuously several times (for example, four times) after the nth word is accessed once, n The second word is accessed again. Of course, if the cache hit rate is increased by increasing the number of lines (number of words), it will be difficult for misses to occur. Therefore, the apparent accessible number of times in the main memory 11 is naturally improved beyond the expected value. obtain.

  However, in order to determine the specifications of the semiconductor memory device 10 assuming the worst case (case in which mishits continue), the nth word is accessed once and then m times (for example, 10 times). Unless a mishit occurs, it is essential to provide the continuous access restriction unit 12 that can guarantee that the nth word is not re-accessed.

<Non-volatile of continuous access restriction unit 12>
The cache memory used as the continuous access restriction unit 12 has a nonvolatile logic for storing data in a nonvolatile manner so that the cache data of the continuous access restriction unit 12 remains when power supply to the semiconductor memory device 10 is cut off. It is desirable to have a configuration including this.

  FIG. 4 is a circuit diagram showing a configuration example of the nonvolatile logic forming the continuous access restriction unit 12. The nonvolatile logic of this configuration example includes inverters INV1 to INV7, pass switches SW1 to SW4, multiplexers MUX1 and MUX2, N-channel field effect transistors Q1a, Q1b, Q2a, Q2b, and ferroelectric elements (ferroelectric elements). Capacitor) CL1a, CL1b, CL2a, and CL2b.

  The input end of the inverter INV1 is connected to the application end of the data signal (D). The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW1. The output terminal of the multiplexer MUX1 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the input terminal of the inverter INV5. The output end of the inverter INV5 is connected to the output end of the output signal (Q). The first input terminal (1) of the multiplexer MUX2 is connected to the output terminal of the inverter INV3. The output terminal of the multiplexer MUX2 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the first input terminal (1) of the multiplexer MUX1 via the pass switch SW2.

  As described above, the nonvolatile logic of this configuration example is volatile that holds the input data signal D in a volatile manner using two logic gates connected in a loop (inverters INV3 and INV4 in FIG. 4). A storage unit VM (loop structure unit) is included.

  The input terminal of the inverter INV6 is connected to the first input terminal (1) of the multiplexer MUX1. The output terminal of the inverter INV6 is connected to the second input terminal (0) of the multiplexer MUX2 via the pass switch SW3. The input terminal of the inverter INV7 is connected to the first input terminal (1) of the multiplexer MUX2. The output terminal of the inverter INV7 is connected to the second input terminal (0) of the multiplexer MUX1 via the pass switch SW4.

  The positive electrode end of the ferroelectric element CL1a is connected to the first plate line PL1. The negative end of the ferroelectric element CL1a is connected to the second input end (0) of the multiplexer MUX2. A transistor Q1a is connected between both ends of the ferroelectric element CL1a. The gate of the transistor Q1a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL1b is connected to the second input terminal (0) of the multiplexer MUX2. The negative electrode end of the ferroelectric element CL1b is connected to the second plate line PL2. A transistor Q1b is connected between both ends of the ferroelectric element CL1b. The gate of the transistor Q1b is connected to the application terminal of the F reset signal FRST.

  The positive electrode end of the ferroelectric element CL2a is connected to the first plate line PL1. The negative end of the ferroelectric element CL2a is connected to the second input end (0) of the multiplexer MUX1. A transistor Q2a is connected between both ends of the ferroelectric element CL2a. The gate of the transistor Q2a is connected to the application terminal of the F reset signal FRST.

  The positive terminal of the ferroelectric element CL2b is connected to the second input terminal (0) of the multiplexer MUX1. The negative electrode end of the ferroelectric element CL2b is connected to the second plate line PL2. A transistor Q2b is connected between both ends of the ferroelectric element CL2b. The gate of the transistor Q2b is connected to the application terminal of the F reset signal FRST.

  Thus, the nonvolatile logic of this configuration example uses the hysteresis characteristics of the ferroelectric elements (CL1a, CL1b, CL2a, CL2b) to store the data D held in the volatile storage unit VM in a nonvolatile manner. It has a sex storage unit NVM.

  Among the above-described components, the path switch SW1 is turned on / off in response to the clock signal CLK, and the path switch SW2 is turned on / off in response to the inverted clock signal CLKB (logic inverted signal of the clock signal CLK). The That is, the path switch SW1 and the path switch SW2 are turned on / off exclusively (complementarily) to each other.

  On the other hand, the path switches SW3 and SW4 are both turned on / off according to the control signal E1. Further, the signal paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2. That is, in the nonvolatile logic of this configuration example, the multiplexers MUX1 and MUX2, the inverters INV6 and INV7, and the path switches SW3 and SW4 are circuit separation units that electrically separate the volatile storage unit VM and the nonvolatile storage unit NVM. Functions as SEP.

  Next, the operation of the non-volatile logic having the above configuration will be described in detail. In the following description, the voltage appearing at the connection node of the ferroelectric elements CL1a and CL1b is V1, the voltage appearing at the connection node of the ferroelectric elements CL2a and CL2b is V2, the voltage appearing at the input terminal of the inverter INV4 is V3, The voltage appearing at the output terminal of the inverter INV4 is denoted by V4, the voltage appearing at the input terminal of the inverter INV3 is denoted by V5, and the voltage appearing at the output terminal of the inverter INV3 is denoted by V6.

  FIG. 5 is a timing chart for explaining an operation example of the nonvolatile logic. In order from the top, the power supply voltage VDD, the clock signal CLK, the data signal D, the control signal E1, the control signal E2, the F reset signal FRST, The voltage waveforms of the applied voltage of the first plate line PL1, the applied voltage of the second plate line PL2, the node voltage V1, the node voltage V2, and the output signal Q are shown.

  First, normal operation of the nonvolatile logic will be described.

  Until the time point W1, the F reset signal FRST is “1 (high level: VDD)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Since all of them are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. The first plate line PL1 and the second plate line PL2 are both “0 (low level: GND)”.

  Further, until the time point W1, the control signal E1 is “0 (GND)”, and the pass switch SW3 and the pass switch SW4 are turned off. Therefore, the data write drivers (inverters INV6 and INV7 in the example of FIG. 4) are used. ) Are all invalid.

  Further, until the time point W1, the control signal E2 is set to “1 (VDD)” and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. A loop is formed.

  Therefore, during the high level period of the clock signal CLK, the pass switch SW1 is turned on and the pass switch SW2 is turned off, so that the data signal D is directly passed as the output signal Q. On the other hand, since the pass switch SW1 is turned off and the pass switch SW2 is turned on during the low level period of the clock signal CLK, the data signal D is latched at the falling edge of the clock signal CLK.

  FIG. 6 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the normal operation described above.

  Next, a data write operation to the ferroelectric element will be described.

  At time points W1 to W3, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data write operation with respect to the ferroelectric element.

  At time points W1 to W3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned off, and voltage application to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b is performed. Possible state.

  Further, at time points W1 to W3, the control signal E1 is set to “1 (VDD)”, and the path switch SW3 and the path switch SW4 are turned on. Accordingly, the data write drivers (inverters INV6 and INV7 in the example of FIG. 4) are all valid.

  Note that at the time points W1 to W3, the control signal E2 is set to “1 (VDD)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. A normal loop is formed in the storage unit VM.

  Further, at the time points W1 to W2, the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, and at the time points W2 to W3, the first plate line PL1 and the second plate line PL2 are set to “1 ( VDD) ". That is, the same pulse voltage is applied to the first plate line PL1 and the second plate line PL2. By applying such a pulse voltage, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state.

  Specifically, referring to FIG. 5, at the time point W1, since the output signal Q is “1 (VDD)”, the node voltage V1 becomes “0 (GND)” and the node voltage V2 becomes “1 (VDD). ) ”. Therefore, at time points W1 to W2, while the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”, no voltage is applied across the ferroelectric elements CL1a and CL1b. Thus, a negative voltage is applied between both ends of the ferroelectric element CL2a, and a positive voltage is applied between both ends of the ferroelectric element CL2b. On the other hand, at time points W2 to W3, no voltage is applied across the ferroelectric elements CL2a and CL2b while the first plate line PL1 and the second plate line PL2 are set to “1 (VDD)”. Thus, a positive voltage is applied across the ferroelectric element CL1a, and a negative voltage is applied across the ferroelectric element CL1b.

  As described above, by applying the pulse voltage to the first plate line PL1 and the second plate line PL2, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. . Note that the remanent polarization state is reversed between the ferroelectric elements CL1a and CL1b and between the ferroelectric elements CL2a and CL2b. Further, the remanent polarization state is also reversed between the ferroelectric elements CL1a and CL2a and between the ferroelectric elements CL1b and CL2b.

  At the time point W3, the F reset signal FRST is set to “1 (VDD)” again, so that the transistors Q1a, Q1b, Q2a, and Q2b are turned on, and between both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”.

  At time point W3, the control signal E1 is again set to “0 (GND)”, and the pass switch SW3 and the pass switch SW4 are turned off, so that the data write driver (inverters INV6 and INV7 in the example of FIG. 4) Is also invalidated. Note that the control signal E2 is not questioned, but is “0 (GND)” in the example of FIG.

  At time W4, the supply of the power supply voltage VDD is interrupted. At this time, the F reset signal FRST is maintained at “1 (VDD)” from the time point W3, and the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Therefore, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if a voltage fluctuation occurs when the power is shut off, the ferroelectric elements CL1a, CL1b, CL2a, An unintended voltage is not applied to CL2b, and garbled data can be avoided.

  FIG. 7 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data write operation (particularly, time points W1 to W3).

  Next, a data read operation from the ferroelectric element will be described.

  At time points R1 to R5, the clock signal CLK is set to “0 (GND)”, and the inverted clock signal CLKB is set to “1 (VDD)”. Accordingly, the first path switch SW1 is turned off and the second path switch is turned on. As described above, by fixing the logic of the clock signal CLK and the inverted clock signal CLKB in advance, it is possible to improve the stability of the data reading operation from the ferroelectric element.

  At the time point R1, the F reset signal FRST is first set to “1 (VDD)”, the transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, CL2b. Both are short-circuited. Accordingly, since no voltage is applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b, even if voltage fluctuation occurs when the power is turned on, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b An unintended voltage is not applied, and garbled data can be avoided.

  At time R1, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”.

  At the time point R2, the control signals E1 and E2 are both set to “0 (GND)” (that is, the data write driver is invalidated, and the normal loop is invalidated in the volatile memory unit VM). Power supply voltage VDD is turned on. At this time, the signal line depicted by the thick line in FIG. 8 is floating.

  At the subsequent time point R3, the F reset signal FRST is set to “0 (GND)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned off, and a voltage can be applied to the ferroelectric elements CL1a, CL1b, CL2a, and CL2b. On the other hand, the first plate line PL1 is set to “1 (VDD)” while the second plate line PL2 is maintained at “0 (GND)”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric element appear as the node voltage V1 and the node voltage V2.

  Specifically, referring to the example of FIG. 5, a relatively low voltage signal (hereinafter, the logic is referred to as WL [Weak Low]) appears as the node voltage V1, and the node voltage V2 is relatively low. A high voltage signal (hereinafter, its logic is called WH [Weak Hi]) appears. That is, a voltage difference is generated between the node voltage V1 and the node voltage V2 according to the difference in the remanent polarization state in the ferroelectric element.

  At this time, at time points R3 to R4, the control signal E2 is set to “0 (GND)”, and the multiplexer MUX1 and the second input terminal (0) of the multiplexer MUX2 are selected, so that the logic of the node voltage V3 becomes WL. The logic of the node voltage V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 of each part of the device are still in an unstable state (the logic inversion in the inverter INV3 and the inverter INV4 is not completely performed, and the output logic is surely “0 (GND ) ”/“ 1 (VDD) ”.

  At the time point R4, the control signal E2 is set to “1 (VDD)”, and the multiplexer MUX1 and the first input terminal (1) of the multiplexer MUX2 are selected. Therefore, a normal loop is formed in the volatile memory unit VM. Yes. With such switching of the signal path, the output terminal (logic: WH) of the inverter INV4 and the input terminal (logic: WH) of the inverter INV3 are connected, and the output terminal (logic: WL) of the inverter INV3 and the input of the inverter INV4 The end (logic: WL) is connected. Accordingly, no mismatch occurs in the signal logic (WH / WL) of each node, and thereafter, while the normal loop is formed in the volatile memory unit VM, the inverter INV3 receives the input of the logic WL, The inverter INV4 tries to raise the output logic to “1 (VDD)”, and the inverter INV4 tries to lower the output logic to “0 (GND)” in response to the input of the logic WH. As a result, the output logic of the inverter INV3 is determined from the unstable logic WL to “0 (GND)”, and the output logic of the inverter INV4 is determined from the unstable logic WH to “1 (VDD)”.

  As described above, at the time point R4, the signal (potential difference between the node voltage V1 and the node voltage V2) read from the ferroelectric element in accordance with the volatile memory unit VM being in the normal loop is the volatile memory unit. The data is amplified by the VM, and the retained data (“1 (VDD)” in the example of FIG. 5) before the power interruption is restored as the output signal Q.

  Thereafter, at the time point R5, the F reset signal FRST is again set to “1 (VDD)”, the transistors Q1a, Q1b, Q2a, and Q2b are turned on, and both ends of the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are connected. Since both are short-circuited, no voltage is applied to these ferroelectric elements CL1a, CL1b, CL2a, CL2b. At this time, both the first plate line PL1 and the second plate line PL2 are set to “0 (GND)”. Therefore, the non-volatile logic is returned to the same state as before the time point W1, that is, the normal operation state.

  FIG. 8 is a circuit diagram showing a signal path (depicted as a thick line in the drawing) during the above-described data reading operation (particularly, at time points R3 to R4).

  As described above, the nonvolatile logic of this configuration example includes the volatile storage unit VM that holds data in a volatile manner using logic gates connected in a loop (inverters INV3 and INV4 in FIG. 4), and a strong memory. A nonvolatile storage unit NVM (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a, Q2b) that stores data held in the volatile storage unit VM in a nonvolatile manner using the hysteresis characteristics of the dielectric element, and a volatile Circuit separation unit SEP (MUX1, MUX2, INV6, INV7, SW3, SW4) for electrically separating the volatile memory unit VM and the non-volatile memory unit NVM. During the normal operation, the volatile memory unit VM is electrically operated while keeping the voltage applied to the ferroelectric element constant.

  As described above, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b are not directly driven from the signal line of the volatile memory unit VM, but the signal lines and the ferroelectric elements CL1a, CL1b, and CL2a of the volatile memory unit VM. , CL2b are provided with data write drivers (inverters INV6, INV7 in FIG. 4) that also function as buffers, so that the ferroelectric elements CL1a, CL1b, CL2a, CL2b are loaded in the volatile memory unit VM. It becomes possible not to become capacity.

  Further, if the path switches SW3 and SW4 are connected to the output terminals of the data write drivers (inverters INV6 and INV7), and the path switches SW3 and SW4 are turned on only when data is written according to the control signal E1, During normal operation, the ferroelectric elements CL1a, CL1b, CL2a, and CL2b can be prevented from being driven.

  When data is read, the input / output paths of the multiplexers MUX1 and MUX2 are switched according to the control signal E2, so that the logic gates (inverters INV3 and INV4 in FIG. 4) and the ferroelectrics in the volatile memory unit VM are switched. It is possible to control conduction / cutoff with the body elements CL1a, CL1b, CL2a, CL2b. Therefore, it is not necessary to add a large load clock line in order to place the specific node in a floating state, so that it is possible to avoid an increase in power consumption.

  In this way, with the nonvolatile logic of this configuration example, the ferroelectric element is not driven wastefully during normal operation. Therefore, the speed is increased to the same level as the volatile nonvolatile logic, and the consumption is reduced. Electricity can be achieved.

  In other words, since it can be handled in the same way as volatile non-volatile logic, the memory element portion of the existing circuit can be replaced with the non-volatile logic of this configuration example without performing redesign such as timing design and power consumption design. It becomes possible. Therefore, since the existing circuit can be easily made non-volatile, for example, the continuous access restriction unit 12 that can shut off the power without erasing data during standby or can immediately resume the operation after the power is turned on is realized. Is possible.

<Other variations>
In the above embodiment, the configuration using the FeRAM as the main memory 11 has been described as an example. However, the configuration of the present invention is not limited to this, and an EEPROM or a flash is used instead of the FeRAM. A memory or the like may be used.

  As described above, various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, the logic level inversion of various signals is arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used, for example, as a technique for using FeRAM as a work memory of a CPU.

10 Semiconductor memory device 11 Main memory (ferroelectric memory)
12 Continuous access restriction unit (first cache memory)
13 Second cache memory 20 Sequencer (CPU)
INV1 to INV7 Inverter SW1 to SW4 Path switch MUX1, MUX2 Multiplexer Q1a, Q1b, Q2a, Q2b N-channel field effect transistors CL1a, CL1b, CL2a, CL2b Ferroelectric element VM Volatile memory unit NVM Nonvolatile memory unit SEP Circuit isolation Part

Claims (11)

Main memory with a limited number of accesses,
A continuous access restriction unit that inputs and outputs data instead of the main memory so that continuous access to the same word in the main memory does not occur;
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, wherein the continuous access restriction unit is a first cache memory having a high association and a small capacity.   3. The semiconductor memory device according to claim 2, wherein a data storage method of the first cache memory is a full associative method.   4. The semiconductor memory device according to claim 3, wherein a line replacement method of the first cache memory is an LRU (least recently used) method.   5. The semiconductor memory device according to claim 4, further comprising a second cache memory having a lower capacity and a larger capacity than the first cache memory, apart from the first cache memory.   6. The semiconductor memory device according to claim 5, wherein the first cache memory includes a nonvolatile logic for storing data in a nonvolatile manner. The non-volatile logic is
A volatile storage unit that volatilely stores data using a plurality of logic gates connected in a loop; and
A nonvolatile memory unit that nonvolatilely stores data volatilely stored in the volatile memory unit using the hysteresis characteristics of the ferroelectric element;
A circuit separation unit for electrically separating the volatile storage unit and the nonvolatile storage unit;
The semiconductor memory device according to claim 6, comprising:   The semiconductor memory device according to claim 1, wherein the main memory is a ferroelectric memory.   The semiconductor memory device according to claim 1, wherein the main memory and the continuous access restriction unit are integrated on the same chip.   The semiconductor memory device according to claim 9, wherein a sequencer that is an access subject to the main memory is also incorporated in the chip.   The semiconductor memory device according to claim 10, wherein the sequencer is a CPU (central processing unit).

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