JP2013115210A - Manufacturing method for soi substrate and bonding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture an SOI substrate using a semiconductor substrate and a substrate with a different thermal expansion coefficient from the semiconductor substrate by performing thermal treatment after bonding the substrates to each other while suppressing the damage of the substrates or the separation of the bonded substrates caused due to the difference in thermal expansion coefficient.SOLUTION: A semiconductor substrate and a substrate with a different thermal expansion coefficient from the semiconductor substrate are bonded to each other with the temperature of the substrate having the larger thermal expansion coefficient set higher than that of the substrate having the smaller thermal expansion coefficient. Moreover, the substrates are bonded to each other with the temperatures of the substrates set higher than room temperature and set lower than the temperature of thermal treatment after the bonding of the substrates. Thus, the difference in expansion amount between the substrates can be reduced in the thermal treatment after the bonding of the substrates, so that the damage or separation of the substrates can be suppressed.

Description

The present invention relates to a method for manufacturing an SOI substrate and a bonding apparatus.

Instead of a silicon wafer produced by thinly slicing a single crystal silicon ingot, a substrate provided with a thin single crystal semiconductor layer on the surface of an insulating film is manufactured and used for manufacturing semiconductor integrated circuit elements.

As a method for manufacturing a substrate provided with a thin single crystal semiconductor layer on the surface of an insulating film, for example, there is a bonded SOI (Silicon On Insulator) technique in which a single crystal silicon thin film is formed on a substrate such as synthetic quartz.

As one of methods for manufacturing an SOI substrate, a method of irradiating accelerated hydrogen ions in a semiconductor substrate is known (see, for example, Patent Document 1). In this method, first, an insulating film (for example, a thermal oxide film) is formed on the surface of a semiconductor substrate (for example, a single crystal silicon substrate), and the semiconductor substrate is accelerated from the surface side on which the insulating film is formed. The microbubble region terminated by the irradiated hydrogen ions is formed at a predetermined depth near the surface. Next, another substrate (for example, a synthetic quartz substrate) is bonded to the surface side on which the microbubble region is formed, and heat treatment is performed. As a result, the hydrogen ions irradiated on the semiconductor substrate (in the semiconductor substrate, not only the form of hydrogen ions but also the form of hydrogen atoms and hydrogen molecules) are concentrated in the microbubble region, and the semiconductor substrate is microbubbles. The region can be easily separated. Then, by separating the semiconductor substrate from another bonded substrate, the semiconductor film and the insulating film formed in contact with the semiconductor film can be transferred to another substrate.

Japanese Patent Application Laid-Open No. 2000-124092

However, when a semiconductor substrate and another substrate are bonded together as described above, when the thermal expansion coefficients of the two substrates are different, the element irradiated to the semiconductor substrate becomes a microbubble region during the heat treatment after bonding the substrates. Concentration (Hereinafter, this phenomenon is called “element concentration.” The ions irradiated on the semiconductor substrate can take not only an ionic state but also an atomic or molecular state in the semiconductor substrate. Therefore, the term “element” is used. “Concentration of elements” described in the following text has the same meaning.) Before the semiconductor substrates can be easily separated, both substrates are peeled off, and the substrates are destroyed due to thermal strain. May occur.

For example, it is reported that when a synthetic quartz substrate and a silicon wafer are bonded together, the difference between the thermal expansion coefficients (also referred to as thermal expansion coefficients) of the two substrates is large, so that destruction occurs by heating at about 300 ° C. ( Takao Abe: Physical Properties and Application Seminar Text of the 24th Amorphous Material, p.25-32, 1997).

In view of the above-described problems, in this specification, in manufacturing an SOI substrate using a semiconductor substrate and a substrate having a different thermal expansion coefficient from that of the semiconductor substrate, suppression of peeling and destruction due to a difference in thermal expansion coefficient is described. Another object is to provide a method for manufacturing a manufactured SOI substrate.

Another object is to provide a structure of a bonding apparatus that can be used for manufacturing the above SOI substrate.

The destruction caused by the difference in thermal expansion coefficient is in a state where the semiconductor substrate can be easily separated by the concentration of elements in the microbubble region (hereinafter also referred to as “embrittlement region” in this specification). By the heat treatment (hereinafter, the heat treatment is referred to as “separation heat treatment”), there is a difference between the expansion amount of the semiconductor substrate and the expansion amount of the substrate to be bonded to the semiconductor substrate (hereinafter referred to as a bonding substrate). Occurs when the stress applied to the semiconductor substrate or the bonding substrate exceeds the strength of the semiconductor substrate or the bonding substrate due to the difference in expansion amount.

In addition, peeling due to the difference in thermal expansion coefficient causes a difference between the expansion amount of the semiconductor substrate and the expansion amount of the substrate to be bonded to the semiconductor substrate due to the separation heat treatment, and the difference between the expansion amounts causes the semiconductor substrate and the bonding substrate to be separated. This occurs when the stress on the interface exceeds the bonding force between the semiconductor substrate and the bonding substrate.

Therefore, breakage or peeling due to the above-described thermal expansion coefficient can be suppressed by reducing the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate when the separation heat treatment is performed.

That is, according to one embodiment of the present invention, an embrittlement region is formed inside a semiconductor substrate by forming an insulating film on the surface of the semiconductor substrate and irradiating the surface of the semiconductor substrate with accelerated ions through the insulating film. Forming and bonding the bonding substrate to one surface of the semiconductor substrate, performing a bonding process, heating the semiconductor substrate and the bonding substrate, and separating the bonding substrate from the semiconductor substrate, thereby providing a semiconductor on the bonding substrate through the insulating film A step of forming a film, the thermal expansion coefficient of the bonding substrate being smaller than the thermal expansion coefficient of the semiconductor substrate, and in the bonding process, the temperature of the semiconductor substrate is set higher than the temperature of the bonding substrate. Is a method for manufacturing an SOI substrate.

By using the above-described manufacturing method, the temperature increase amount of the semiconductor substrate is smaller than the temperature increase amount of the bonding substrate in the heat treatment after the bonding process, and thus the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate. Can be reduced.

In addition, in order to bond both substrates with the temperature of the semiconductor substrate higher than the temperature of the bonding substrate, heat treatment is performed on the semiconductor substrate to bond both substrates, and cooling processing is performed on the bonding substrate. There is a method of pasting together. Thereby, since the temperature rise amount of the bonding substrate can be made larger than the temperature rise amount of the semiconductor substrate, the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate can be reduced.

There is also a method in which a heat treatment is performed on a semiconductor substrate, and a cooling process is performed on a bonded substrate to bond both substrates together. Thereby, the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate can be further reduced.

Another embodiment of the present invention is to form an insulating film on a surface of a semiconductor substrate and irradiate accelerated ions to one surface of the semiconductor substrate through the insulating film to form an embrittled region in the semiconductor substrate. Forming and bonding a bonding substrate to one surface of the semiconductor substrate, performing a bonding process, heating the semiconductor substrate and the bonding substrate, and separating the bonding substrate from the semiconductor substrate, thereby providing a semiconductor over the bonding substrate via an insulating film A step of forming a film, the thermal expansion coefficient of the bonding substrate is smaller than the thermal expansion coefficient of the semiconductor substrate, and heat treatment is performed on both the semiconductor substrate and the bonding substrate in bonding, and the temperature of the semiconductor substrate and the bonding substrate is determined. A method for manufacturing an SOI substrate, in which a semiconductor substrate and a bonding substrate are attached to each other with a temperature higher than room temperature.

When the above-described manufacturing method is used, the temperature increase of the semiconductor substrate and the bonding substrate in the heat treatment after bonding is smaller than that in the case where the heat treatment is performed after bonding the semiconductor substrate and the bonding substrate at room temperature. Therefore, the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate can be reduced.

Note that in the above manufacturing method, the bonding strength between the semiconductor substrate and the bonding substrate can be improved by performing plasma treatment on the semiconductor substrate between the formation of the embrittlement region and the bonding treatment. When bonding is performed by performing heat treatment on one or both of the semiconductor substrate and the bonding substrate as in the above-described method for manufacturing an SOI substrate, the bonding strength between the semiconductor substrate and the bonding substrate is increased by the heat treatment. It can be said that it is preferable to perform a plasma treatment because of a decrease. Note that the plasma treatment may be performed using He gas, Ar gas, Kr gas, Xe gas, oxygen gas, nitrogen oxide gas, ammonia gas, nitrogen gas, hydrogen gas, or a mixed gas thereof.

Further, by performing ion beam irradiation treatment on the semiconductor substrate instead of or in addition to the plasma treatment, the bonding strength between the semiconductor substrate and the bonding substrate can be improved. Note that the ion beam treatment may be performed by irradiating the semiconductor substrate with an ion species obtained using a gas similar to the above plasma treatment with an acceleration voltage of 10 eV or more and 200 eV or less.

Further, in the above manufacturing method, a large-area SOI substrate can be obtained by bonding a plurality of semiconductor substrates to the bonding substrate using a bonding substrate larger in size than the semiconductor substrate and separating the semiconductor substrate from the bonding substrate. Can be produced.

In order to manufacture the above-described SOI substrate, in addition to the first installation base on which the semiconductor substrate is installed, the second installation base on which the bonding substrate is installed, and the driving device for bonding the semiconductor substrate and the bonding substrate, the semiconductor In order to heat a board | substrate, the bonding apparatus of a structure provided with the 1st temperature control apparatus which heats a 1st installation stand can be used. Further, instead of the first temperature adjustment device that heats the first installation table, a structure that includes a second temperature adjustment device that cools the second installation table and can cool the bonding substrate may be used. Desirably, it is preferable to include both a first temperature adjustment device that heats the first installation table and a second temperature adjustment device that cools the second installation table.

Note that the structure of the bonded substrate has a structure in which the surface on which the bonding substrate of the second installation table is installed is wider than the surface on which the semiconductor substrate of the first installation table is installed, and a plurality of first installation tables are provided. Accordingly, a plurality of semiconductor substrates can be attached to the bonding substrate, and thus the structure is suitable for manufacturing a large-area SOI substrate.

Further, when the bonding substrate is installed on the second installation table and the semiconductor substrate is installed on the first installation table, one surface of the bonding substrate facing the semiconductor substrate and one surface of the semiconductor substrate facing the bonding substrate The second installation table is inclined with respect to the first installation table so that the angle difference is more than 0 degrees and less than 3 degrees, and the semiconductor substrate installation surface of the first installation table is more than the semiconductor substrate. In addition, since the contact portion between the semiconductor substrate and the bonding substrate can be limited by using a small structure, stable bonding can be performed without an air layer entering the interface between the semiconductor substrate and the bonding substrate.

By applying the method and apparatus for manufacturing an SOI substrate described in the present invention, thermal expansion that occurs when an SOI substrate is manufactured by bonding a semiconductor substrate and a bonding substrate having a different thermal expansion coefficient from the semiconductor substrate. It is possible to suppress peeling of the semiconductor substrate and the bonding substrate, destruction of the semiconductor substrate or the bonding substrate, and the like caused by the coefficient.

10A and 10B illustrate a method for manufacturing an SOI substrate. 3A and 3B illustrate a method for manufacturing an SOI substrate and a manufacturing apparatus. 3A and 3B illustrate a method for manufacturing an SOI substrate and a manufacturing apparatus. 3A and 3B illustrate a method for manufacturing an SOI substrate and a manufacturing apparatus. 3A and 3B illustrate a method for manufacturing an SOI substrate and a manufacturing apparatus. 3A and 3B each illustrate a structure of a semiconductor element using an SOI substrate. 8A and 8B illustrate a method for manufacturing a semiconductor element using an SOI substrate. 8A and 8B illustrate a method for manufacturing a semiconductor element using an SOI substrate. 6A and 6B illustrate electronic devices each including a semiconductor element using an SOI substrate. The figure which shows the curvature amount of the sample which bonded the semiconductor substrate and the joining board | substrate.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that in the embodiments described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

In addition, ordinal numbers such as “first”, “second”, and “third” in this specification and the like are added to avoid confusion between components, and are not limited numerically. To do.

Further, in this specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, if the expression “B on A” is used, an expression including another component between A and B is not excluded.

Note that the word “SOI substrate” used in the present specification is used as a word indicating a structure in which a silicon thin film is provided on the surface of an insulating film (Silicon On Insulator). “Substrate” is not limited to the above-mentioned meaning, and is used as a word representing a structure (Semiconductor On Insulator) in which a semiconductor film is provided on an insulating film (or insulating substrate), and a silicon thin film is provided on a quartz substrate. In addition, a structure in which a gallium nitride (GaN) thin film or a silicon carbide (SiC) thin film is provided in place of the silicon thin film, or the like is also described in the present specification (Silicon On Quartz; sometimes abbreviated as “SOQ”). It is included in the “SOI substrate”.

(Embodiment 1)
In this embodiment, when an SOI substrate is manufactured using a semiconductor substrate and a substrate having a different thermal expansion coefficient from the semiconductor substrate, an SOI substrate in which peeling or destruction due to a difference in thermal expansion coefficient is suppressed is manufactured. A method and a manufacturing apparatus will be described with reference to FIGS.

First, the semiconductor substrate 100 is prepared, and the insulating film 102 is formed on the surface (see FIG. 1A).

As the semiconductor substrate 100, for example, a substrate made of a Group 14 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate can be used. Alternatively, a compound semiconductor substrate such as gallium nitride, gallium arsenide, or indium phosphide can be used. As a commercially available silicon substrate, a circular substrate having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (100 mm), a diameter of 12 inches (300 mm), and a diameter of 16 inches (700 mm) is representative. Is. Further, the shape of the semiconductor substrate 100 is not limited to a circle, and may be a shape processed into a rectangle, for example. The semiconductor substrate 100 can be manufactured using a CZ (Czochralski) method or an FZ (floating zone) method.

As the insulating film 102, for example, a silicon oxide film, a silicon oxynitride film, or the like may be formed as a single layer or a stacked layer. Note that examples of a method for manufacturing the film include a thermal oxidation method, a CVD method, and a sputtering method. In the case where the insulating film 102 is formed using a CVD method, an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ) is used in order to achieve good bonding. It is preferable to form a silicon oxide film.

Note that in the case where the insulating film 102 is formed by thermal oxidation treatment, halogen is preferably added to the oxidizing atmosphere. For example, by performing thermal oxidation treatment on the semiconductor substrate 100 in an oxidizing atmosphere to which chlorine (Cl) is added, the insulating film 102 that has been subjected to chlorine oxidation can be formed. In this case, the insulating film 102 is a film containing chlorine atoms. By such chlorine oxidation, after the semiconductor substrate 100 and the bonding substrate are bonded together in a later process, impurities such as Na mixed from the bonding substrate can be fixed to prevent the semiconductor substrate 100 from being contaminated. Note that the halogen atoms contained in the insulating film 102 are not limited to chlorine atoms. The insulating film 102 may contain fluorine atoms.

Before the insulating film 102 is formed, a hydrochloric acid hydrogen peroxide mixed solution (HPM), a sulfuric acid hydrogen peroxide mixed solution (SPM), an ammonia hydrogen peroxide mixed solution (APM), dilute hydrofluoric acid (DHF), It is preferable to clean the surface of the semiconductor substrate 100 using a mixed solution (FPM) of hydrofluoric acid, hydrogen peroxide solution, and pure water.

Next, an ion irradiation treatment 104 is performed from one surface of the semiconductor substrate 100, whereby an embrittled region 106 is formed at a predetermined depth in the semiconductor substrate 100 (see FIG. 1B).

As ion species to be irradiated, hydrogen ions may be used. In the case of irradiation with accelerated hydrogen ions, the ratio of H ₃ ⁺ is preferably increased. _{^{Specifically,}} H _^+, H 2 _^+, the proportion of _H ^{3 +} to the total amount of _H ^{3 +} is made to be 50% or more (more preferably 80% or more). Increasing the proportion of H ₃ ⁺ can improve the efficiency of ion irradiation. In addition to hydrogen ions, rare gas ions can also be used. Specifically, He ion, Ne ion, Ar ion, Kr pton ion, or Xe ion can be used.

The depth at which the embrittlement region 106 is formed can be adjusted by the kinetic energy, mass and charge, incident angle, and the like of the irradiated ions. The embrittlement region 106 is formed in a region having a depth substantially equal to the average penetration depth of ions. Therefore, the thickness of the semiconductor film 108 that is separated from the semiconductor substrate 100 in a later step can be adjusted by adjusting the ion species to be irradiated and the irradiation conditions.

Note that there is no particular limitation on the thickness of the semiconductor film 108; however, when the separated semiconductor film 108 is used for forming a high-performance semiconductor integrated circuit, the S value increases when the film thickness is too thick. In addition, since there is a possibility that the transistor is normally on, it is desirable that the transistor be 1 nm to 200 nm, preferably 3 nm to 100 nm. Therefore, the average penetration depth of the irradiated ions may be adjusted so that the formation depth of the embrittlement region 106 in the semiconductor substrate 100 is 1 nm to 200 nm, preferably 3 nm to 100 nm.

The ion irradiation treatment 104 can be performed using an ion doping apparatus or an ion implantation apparatus. In particular, in an ion implantation apparatus, ion species in plasma can be mass-separated and only a specific mass of ion species can be irradiated into a semiconductor substrate, so that contamination of impurities that affect transistor characteristics can be suppressed. desirable.

However, even when the ion irradiation treatment 104 is performed using an ion doping apparatus, the ion irradiation treatment 104 is performed through the insulating film 102 to trap a substance (such as heavy metal) that affects the characteristics of the transistor. Can do.

Note that heat treatment for recovering crystal defects may be performed after the ion irradiation treatment 104. The temperature of this heat treatment is a temperature at which separation due to element concentration does not occur in the embrittled region 106. Since the heating temperature varies depending on the material used for the semiconductor substrate 100, the ion species irradiated into the semiconductor substrate 100, and the like, the practitioner may adjust appropriately in consideration of the implementation conditions. For example, heating may be performed at 100 ° C. or higher and lower than 400 ° C. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used.

Next, the bonding substrate 110 is prepared. As the bonding substrate 110, a substrate made of an insulator can be used. Specific examples include various glass substrates used in the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, natural quartz substrates, and synthetic quartz substrates.

Further, as the bonding substrate 110, a film having a heat resistance of 300 ° C. or higher (for example, a polyimide film), a prepreg (for example, a glass fiber impregnated with a polyimide resin), or the like, a metal plate, Metal foil can also be used. Since these substrates have flexibility, a semiconductor device using an SOI substrate manufactured by the manufacturing method described in this embodiment can have flexibility.

Note that the bonding substrate 110 is desirably a substrate having a size larger than that of the semiconductor substrate 100. Specifically, it is desirable that a plurality of semiconductor substrates 100 be bonded to the bonding substrate 110 without overlapping, and more preferably, the area of the bonding substrate 110 is more than twice the area of the semiconductor substrate 100. Larger is desirable. Accordingly, a large-area SOI substrate can be manufactured, and many semiconductor devices can be manufactured from one SOI substrate, so that the cost of the semiconductor device can be reduced.

Note that the bonding substrate 110 is preferably cleaned in advance. Specifically, hydrochloric acid hydrogen peroxide solution mixed solution (HPM), sulfuric acid hydrogen peroxide solution mixed solution (SPM), ammonia hydrogen peroxide solution mixed solution (APM), dilute hydrofluoric acid (DHF) with respect to bonding substrate 110. ), Ultrasonic cleaning using a mixed solution (FPM) of hydrofluoric acid, hydrogen peroxide, pure water, or the like. By performing such a cleaning process, it is possible to improve the flatness of the surface of the bonding substrate 110 and to remove abrasive particles or organic substances remaining on the surface of the bonding substrate 110.

Further, before the semiconductor substrate 100 and the bonding substrate 110 are bonded together, it is preferable to perform a surface treatment on the surfaces related to the bonding. As the surface treatment, wet treatment, dry treatment, or a combination of wet treatment and dry treatment can be used. Different wet treatments may be used in combination, or different dry treatments may be used in combination. By this. The bonding strength at the interface between the semiconductor substrate 100 and the bonding substrate 110 can be improved.

Next, the semiconductor substrate 100 and the bonding substrate 110 are attached to each other with the temperature of the semiconductor substrate 100 and the temperature of the bonding substrate 110 being different (see FIG. 1C). Note that “with different temperatures” specifically indicates a state in which the temperature of the substrate having a large thermal expansion coefficient is set higher than the temperature of the substrate having a small thermal expansion coefficient.

Here, an apparatus for bonding the semiconductor substrate 100 and the bonding substrate 110 (hereinafter, simply referred to as “bonding apparatus”) and specific contents of the bonding will be described below.

As described in this specification, in order to make the temperature of the semiconductor substrate 100 different from the temperature of the bonding substrate 110, first, an installation base (hereinafter referred to as a first installation base) on which the semiconductor substrate 100 is installed. ) Or an installation table (hereinafter referred to as a second installation table) on which the bonding substrate 110 is installed, it is necessary to provide a temperature adjusting device capable of adjusting the temperature of the installation table on at least one, preferably both. As a temperature control device, for example, heating is performed by passing a current through a conductive wire having a large electrical resistance such as a nichrome wire or a tungsten wire (also called a resistance heating device), and light having a wavelength absorbed by the installation base is emitted. Various heating mechanisms such as heating using a light source (also referred to as a lamp heating device) can be used. Further, as a temperature adjusting device, for example, cooling is performed by circulating a coolant, and cooling is performed using a Peltier effect in which heat is transferred from one metal to the other by flowing an electric current through a metal joint (Peltier). Various cooling mechanisms such as an element can also be used.

In addition, in order to bond the two substrates in a state where the temperatures of the semiconductor substrate 100 and the bonding substrate 110 are different, it is necessary to provide a driving device that moves at least one of the first installation table and the second installation table. As the drive device, for example, a structure in which the installation table is moved up and down using a motor, a structure in which the installation table is moved up and down using an electromagnet that generates a magnetic force by energization, and the like may be used.

An example of a bonding apparatus having the temperature adjusting apparatus and the driving apparatus as described above is shown in FIG. Note that in the structure of the bonding apparatus described in this embodiment, up to nine semiconductor substrates 100 can be bonded to the bonding substrate 110 at the same time, but the number of bonding is not limited.

2 includes a first installation table 211, a second installation table 212, a temperature adjustment device 220 provided on the first installation table 211, and the second installation table 212, and a first installation table 212. Drive device 230 for moving the installation table 211 up and down. The semiconductor substrate 100 having the insulating film 102 and the embrittled region 106 is installed on the first installation table 211, and the bonding substrate 110 is installed on the second installation table 212. Note that the second installation base 212 preferably includes a substrate fixing mechanism 234 so that the installed bonded substrate 110 does not fall. As the substrate fixing mechanism 234, for example, an adsorption mechanism such as a vacuum chuck can be used. In addition, a temporary fixing material such as a heat release tape, a heat release adhesive, a UV release tape, or a UV release adhesive is provided on the surface on which the bonding substrate 110 of the second installation table 212 is installed, and this is used as the substrate fixing mechanism 234. Also good.

2A is a perspective view illustrating an example of a bonding apparatus according to the present specification, and FIG. 2B is a cross-sectional view when FIG. 2A is cut along a Z plane indicated by a dotted line. The first installation base 211 can move the first installation base 211 in the vertical direction (also referred to as the Z-axis direction) as shown by the arrow in FIG.

In FIG. 2A, a motor is used as the driving device 230, and the driving force of the motor is transmitted to the first installation table via the shaft 232, and the first installation table is moved up and down. Further, a resistance heating device is used as the temperature adjustment device 220.

A flow of a method for bonding the semiconductor substrate 100 and the bonding substrate 110 in FIG. 2 will be briefly described with reference to FIG. In the description of FIG. 3, a silicon substrate (thermal expansion coefficient is larger than the bonding substrate 110) is used as the semiconductor substrate 100, and a synthetic quartz substrate (thermal expansion coefficient is smaller than the semiconductor substrate 100) is used as the bonding substrate 110. Give an explanation.

First, the semiconductor substrate 100 is installed on the first installation table 211, and the bonding substrate 110 is installed on the second installation table 212 (see FIG. 3A). The material of the first installation table 211 and the second installation table 212 is not particularly limited. However, in the installation table provided with the temperature adjustment device, a material having good thermal conductivity, such as aluminum, copper, brass, nickel, It is preferable to use tungsten or the like. Thereby, an installation stand can be heated or cooled efficiently.

As shown in FIG. 3, the size of the bonding substrate 110 is preferably larger than that of the semiconductor substrate 100. Accordingly, since a plurality of semiconductor substrates 100 can be bonded to the bonding substrate 110, a large-area SOI substrate can be manufactured.

Next, the temperature of the semiconductor substrate 100 is set higher than that of the bonding substrate 110 by using the temperature adjustment device 220 provided on the first installation table 211 and the temperature adjustment device 220 provided on the second installation table 212. That is, the substrate temperature of the substrate (semiconductor substrate 100) having a large thermal expansion coefficient is made higher than that of the substrate having a small thermal expansion coefficient (bonding substrate 110). As a result, the temperature increase amount of the bonding substrate 110 is larger than the temperature increase amount of the semiconductor substrate 100 during the separation heat treatment after the semiconductor substrate 100 and the bonding substrate 110 are bonded together. The difference between the amount and the expansion amount of the bonding substrate 110 can be made closer.

In order to make the above concept easy to understand, the above contents will be described using simple numerical values.

For example, a silicon wafer having a square shape with a side length (L) of X mm and a thermal expansion coefficient (α1) of 2.5 [× 10 ⁻⁶ / K] is used as the semiconductor substrate 100. A synthetic quartz substrate having a square shape with a length (L) of X mm and a thermal expansion coefficient (α2) of 1.0 [× 10 ⁻⁶ / K] is used.

When the above-described semiconductor substrate 100 and the bonding substrate 110 are bonded together at room temperature (here, 20 ° C.) and heat treatment is performed on both the substrates at 400 ° C., the temperature difference between before and after the semiconductor substrate 100 is heated ( ΔT ₁ ) and the temperature difference (ΔT ₂ ) before and after heating the bonding substrate 110 are both 380 ° C.

The displacement amount ΔL of the substance due to the thermal expansion coefficient is generally a deformation amount according to the equation: ΔL = α × L × ΔT.

Therefore, the displacement (ΔL ₁ ) of the semiconductor substrate 100 is ΔL ₁ = α ₁ × L × ΔT _1, which is approximately 9.50 × 10 ⁻² [mm]. Further, the displacement amount (ΔL ₂ ) of the bonding substrate 110 is ΔL ₂ = α ₂ × L × ΔT ₂ , and is approximately 3.80 × 10 ⁻² [mm]. For this reason, the difference in the amount of expansion between the semiconductor substrate 100 and the bonding substrate 110 due to the difference in thermal expansion coefficient is approximately 5.70 × 10 ⁻² [mm].

On the other hand, the semiconductor substrate 100 is heated to, for example, 200 ° C. in advance and the bonding substrate 110 is, for example, previously set to 10 ° C. so that the temperature of the substrate having a large coefficient of thermal expansion becomes higher than the temperature of the substrate having a small coefficient of thermal expansion. When both substrates are bonded together in a cooled state and subjected to heat treatment at 400 ° C., the temperature difference (ΔT ₁ ) before and after heating the semiconductor substrate 100 is 200 ° C., and the temperature before and after heating the bonding substrate 110. The difference (ΔT ₂ ) is 390 ° C.

Therefore, the displacement amount (ΔL ₁ ) of the semiconductor substrate 100 is approximately 5.0 × 10 ⁻² [mm], and the displacement amount (ΔL ₂ ) of the bonding substrate 110 is approximately 3.9 × 10 ⁻² [mm]. It becomes. Therefore, the difference in expansion between the semiconductor substrate 100 and the bonding substrate 110 due to the difference in thermal expansion coefficient is approximately 1.1 × 10 ⁻² [mm], and the semiconductor substrate 100 is not heated and the bonding substrate 110 is not cooled. The value is 1/5 or less compared to the case.

In this way, the temperature of the substrate having a large thermal expansion coefficient is increased by using the temperature adjustment device 220 provided on the first installation table 211 and the temperature adjustment device 220 provided on the second installation table 212. By bonding the two substrates together in a state higher than the temperature of the small substrate, the difference between the expansion amount of the semiconductor substrate 100 and the expansion amount of the bonding substrate 110 can be made closer to each other when the separation heat treatment is performed.

In the present embodiment, both the temperature adjustment device 220 provided on the first installation base 211 and the temperature adjustment device 220 attached to the second installation table 212 are operated, but only one of them is operated. Also good. In that case, the temperature adjustment device 220 attached to the first installation base 211 so that the substrate temperature of the substrate (semiconductor substrate 100) having a larger thermal expansion coefficient becomes higher than that of the substrate having a small thermal expansion coefficient (bonding substrate 110). The bonding substrate 110 may be cooled by using the temperature adjusting device 220 attached to the second installation table 212 or by heating the semiconductor substrate 100 using the temperature.

Further, in the present embodiment, the temperature adjustment device 220 is installed on both the first installation table 211 and the second installation table 212. However, the temperature adjustment device 220 may have only one side. In the case where the large substrate is installed on the installation table side, the temperature adjustment device 220 having a heating mechanism is provided. In the case where the large temperature substrate is provided on the installation table side, a temperature adjustment device 220 having a cooling mechanism is provided. Just do it.

Note that as described above, when heat treatment is performed on the semiconductor substrate 100, a temperature at which separation due to element concentration does not occur in the embrittled region 106 (for example, 100 ° C. or more and less than 400 ° C.) is applied to the semiconductor substrate 100. Need to add. In this case, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used. Note that the temperature at which separation due to element concentration in the embrittlement region 106 varies depending on the material of the semiconductor substrate 100, the conditions of the ion irradiation treatment 104, and the like, and thus the above temperature condition is merely an example, and one embodiment of the disclosed invention However, this is not to be interpreted as limiting. However, the substrate temperature of the substrate (semiconductor substrate 100) having a larger thermal expansion coefficient than that of the substrate having a small thermal expansion coefficient (bonding substrate 110) is increased by 50 ° C. or more, more preferably by 100 ° C. or more, and further preferably by 200 ° C. It is desirable to make it higher.

Next, the driving force of the driving device 230 is transmitted to the first installation base 211 via the shaft 232 to move the first installation base 211, and the semiconductor substrate 100 and the bonding substrate 110 are bonded together (FIG. 3B). reference.). When a part of the semiconductor substrate 100 comes into contact with the bonding substrate 110, the bonding of the semiconductor substrate 100 and the bonding substrate 110 proceeds spontaneously by van der Waals force, hydrogen bonding, or the like.

The bonding apparatus described in this embodiment has a structure in which each of the first installation bases 211 is moved by a separate driving device. However, a structure in which a plurality of first installation bases 211 are moved by one driving apparatus, A structure may be adopted in which all the first installation bases 211 are moved by one drive device. With this structure, the number of driving devices 230 can be reduced, so that the manufacturing cost of the bonding device can be reduced. Further, the bonding apparatus described in this embodiment has a structure in which the first installation base 211 operates in the Z-axis direction, but the second installation base 212 is provided with a driving device 230 to provide a second installation base. It is good also as a structure where 212 moves. Moreover, it is good also as a structure where both the 1st installation stand 211 and the 2nd installation 2nd 212 move. In addition, one or both of the first installation table 211 and the second installation table 212 operate in the front-rear direction and the left-right direction (also referred to as the X-axis direction and the Y-axis direction) in order to adjust the bonding position. A mechanism may be provided.

In the case of a structure in which two or more first installation bases 211 are moved by one driving device 230 as described above, the thickness of the semiconductor substrate 100 installed on the first installation base 211 is different. The force (driving force of the driving device 230) concentrates on the specific semiconductor substrate 100, and the specific semiconductor substrate may be destroyed. For this reason, when two or more first installation bases 211 are moved by one drive device 230, it is preferable to provide a movable portion 236 on a part of the shaft 232 as shown in FIG. As the movable portion 236, for example, various cylinders such as a hydraulic cylinder and a pneumatic cylinder can be used as shown in FIG. Further, as shown in FIG. 4B, an elastic body such as urethane, sponge, rubber (natural rubber, synthetic rubber, etc.) or a spring may be sandwiched between a part of the shaft 232.

By bonding the semiconductor substrate 100 and the bonding substrate 110 using the bonding apparatus described above, the temperature of the semiconductor substrate 100 and the temperature of the bonding substrate 110 are different, specifically, the temperature of the substrate having a small thermal expansion coefficient. In addition, since the bonding can be performed in a state where the temperature of the substrate having a large thermal expansion coefficient is increased, the temperature increase amount of the bonding substrate 110 is higher than the temperature increase amount of the semiconductor substrate 100 in the separation heating process performed in a later process. Therefore, the difference between the expansion amount of the semiconductor substrate 100 and the expansion amount of the bonding substrate 110 can be made closer. Therefore, peeling or destruction of the substrate due to the difference in thermal expansion coefficient between the semiconductor substrate 100 and the bonding substrate 110 can be suppressed.

Note that in this embodiment mode, the semiconductor substrate 100 is bonded to the bonding substrate 110 in a parallel state, but the semiconductor substrate 100 is inclined with respect to the bonding substrate 110 as illustrated in FIG. 5A, for example. Even if pasted together with a corner. Here, “the semiconductor substrate 100 is bonded to the bonding substrate 110 with an inclination angle with respect to the installation angle of the bonding substrate 110” means that the X axis of the bonding substrate 110 is, as shown in FIG. When the inclination of the Y-axis in the Z-axis direction is defined as 0 degree, the X-axis of the semiconductor substrate 100 is in the range of more than 0 degree and less than 3 degrees in the Z-axis direction, preferably 0.01 degrees or more and 2 (The conceptual diagram is shown in the left diagram of FIG. 5B), or the Y axis of the semiconductor substrate 100 is larger than 0 degree and larger than 3 degrees in the Z axis direction. Satisfy at least one of the smaller ranges (preferably in the range of 0.01 degrees to 2 degrees) (the schematic diagram is shown in the right diagram of FIG. 5B). Is desirable. By bonding in this manner, an air layer (also referred to as an air void or the like) can be prevented from being mixed between the semiconductor substrate 100 and the bonding substrate 110.

In addition, when the bonding between the semiconductor substrate 100 and the bonding substrate 110 is started, after the spontaneous bonding starting from the contact point between the semiconductor substrate 100 and the bonding substrate 110 starts, the movement of the first installation base (that is, the first mounting table) It is desirable to stop the operation of bringing the first installation table 211 and the second installation table 212 closer. This is because the semiconductor substrate 100 is strongly pressed against the bonding substrate 110 when the movement of the first mounting base 211 is continued after the spontaneous bonding starts, and the semiconductor substrate 100 and the bonding substrate 110 are spontaneously bonded. This is because the air layer (also referred to as an air void) may be mixed between the semiconductor substrate 100 and the bonding substrate 110.

Note that plasma treatment is preferably performed in advance on at least one of the semiconductor substrate 100 and the bonding substrate 110 before bonding. Thereby, since the bonding strength between the semiconductor substrate 100 and the bonding substrate 110 can be increased, peeling of the semiconductor substrate 100 and the bonding substrate 110 due to the thermal expansion coefficient can be suppressed. In particular, when one or both of the semiconductor substrate 100 and the bonding substrate 110 are bonded in a heated state, the bonding strength between the semiconductor substrate 100 and the bonding substrate 110 is reduced by heating, and thus it is preferable to perform plasma treatment in advance. . Note that the plasma treatment can be performed using, for example, a rare gas such as He, Ar, Kr, or Xe, a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen, or a mixed gas thereof. In particular, it is preferable to use oxygen gas, argon gas, or the like.

Next, the bonding substrate 110 to which the semiconductor substrate 100 is bonded is removed from the second installation table 212, and the semiconductor substrate 100 is subjected to separation heating treatment. Thereby, element concentration occurs in the embrittled region 106, and the semiconductor substrate 100 can be easily separated. Note that the separation heat treatment changes depending on the material used for the semiconductor substrate 100, the ion species irradiated into the semiconductor substrate 100, and the like, and therefore, the practitioner may adjust appropriately in consideration of the implementation conditions. For example, when a silicon wafer is used as the semiconductor substrate 100, heating may be performed at 400 ° C. or higher and 600 ° C. or lower as an example.

Note that, in order to increase the bonding strength between the semiconductor substrate 100 and the bonding substrate 110, the bonding strength between the semiconductor substrate 100 and the bonding substrate 110 is increased between the bonding and the separation heating treatment. It is preferable to perform heat treatment (this heat treatment may be referred to as “joining heat treatment” below). Note that the bonding heat treatment is desirably performed at a temperature of 100 ° C. or higher and lower than 400 ° C., preferably 100 ° C. or higher and 350 ° C. or lower.

For the bonding heat treatment and the separation heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used.

Thus, as described in this embodiment, a substrate (semiconductor substrate 100) having a larger thermal expansion coefficient than a substrate having a smaller thermal expansion coefficient (bonding substrate 110) is bonded in advance while the semiconductor substrate 100 and the bonding substrate 110 are bonded to each other. The two substrates are bonded together in a state in which the substrate temperature is high, and then the semiconductor substrate 100 is separated and heated, whereby both substrates are peeled off before separating the semiconductor substrate 100 from the bonded substrate 110. It is possible to suppress the phenomenon that the substrate is broken due to thermal strain.

Then, by separating the semiconductor substrate 100 from the bonding substrate 110, the semiconductor film 108 separated from the semiconductor substrate 100 is transferred onto the bonding substrate 110 with the insulating film 102 interposed therebetween (see FIG. 1D). .

Note that after the semiconductor film 108 is separated from the semiconductor substrate 100, the bonding substrate 110 on which the semiconductor film 108 is transferred is subjected to heat treatment at a temperature of 100 ° C. or more and below the strain point of the bonding substrate 110, and remains in the semiconductor film 108. The concentration of hydrogen may be reduced.

Through the above steps, when manufacturing an SOI substrate using a semiconductor substrate and a substrate having a thermal expansion coefficient different from that of the semiconductor substrate, a high-quality SOI substrate in which peeling and destruction due to a difference in thermal expansion coefficient are suppressed. 120 can be manufactured (see FIG. 1E).

Note that in FIG. 1, the description has been given of bonding one semiconductor substrate 100 to the bonding substrate 110 and performing heat treatment and separation. However, a plurality of semiconductor substrates are bonded to the bonding substrate 110 as illustrated in FIG. 2 and the like. 100 may be attached, and heat treatment and separation may be performed to manufacture an SOI substrate. Thus, a plurality of semiconductor films 108 are formed over the bonding substrate 110 with the insulating film 102 interposed therebetween, and more semiconductor devices can be manufactured from one bonding substrate 110. That is, one substrate Therefore, the cost of the semiconductor device can be reduced.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, the difference between the expansion amount of the semiconductor substrate 100 and the expansion amount of the bonding substrate 110 is brought close by using a method different from the method described in Embodiment 1, and peeling due to the difference in thermal expansion coefficient is reduced. A method for manufacturing an SOI substrate in which destruction is suppressed will be described.

First, with reference to FIGS. 1A and 1B described in Embodiment 1 and the contents of Embodiment 1 corresponding to the description of the drawings, the insulating film 102 and the embrittlement region 106 are formed. The provided semiconductor substrate 100 is manufactured. Then, as shown in FIG. 3A, the semiconductor substrate 100 is installed on the first installation table 211 of the bonding apparatus, and the bonding substrate 110 is installed on the second installation table 212. Note that as the bonding apparatus used here, the same bonding apparatus as that described in Embodiment Mode 1 can be used.

Next, using the temperature adjustment device 220 provided on the first installation table 211 and the temperature adjustment device 220 provided on the second installation table 212, the temperature of both the semiconductor substrate 100 and the bonding substrate 110 is lower than room temperature. Both substrates are heated so as to be high. As a result, during the separation heating process after the semiconductor substrate 100 and the bonding substrate 110 are bonded together, the amount of temperature increase of the semiconductor substrate 100 and the bonding substrate 110 is smaller than when both substrates are heated from room temperature. For this reason, the difference between the expansion amount of the semiconductor substrate and the expansion amount of the bonding substrate when performing the separation heat treatment can be made closer.

In order to make the above concept easy to understand, the above contents will be described using simple numerical values.

For example, a silicon wafer having a square shape with a side length (L) of X mm and a thermal expansion coefficient (α1) of 2.5 [× 10 ⁻⁶ / K] is used as the semiconductor substrate 100. A synthetic quartz substrate having a square shape with a length (L) of X mm and a thermal expansion coefficient (α2) of 1.0 [× 10 ⁻⁶ / K] is used.

When the above-described semiconductor substrate 100 and the bonding substrate 110 are bonded together at room temperature (here, 20 ° C.) and heat treatment is performed on both the substrates at 400 ° C., the temperature difference between before and after the semiconductor substrate 100 is heated ( Both ΔT1) and the temperature difference (ΔT2) before and after heating the bonding substrate 110 are 380 ° C.

The displacement amount ΔL of the substance due to the thermal expansion coefficient is generally a deformation amount according to the formula α × L × ΔT.

Therefore, the displacement amount (ΔL ₁ ) of the semiconductor substrate 100 is approximately 9.50 × 10 ⁻² [mm], and the displacement amount (ΔL ₂ ) of the bonding substrate 110 is approximately 3.80 × 10 ⁻² [mm]. It becomes. For this reason, the difference in expansion amount (ΔL ₁ −ΔL ₂ ) between the semiconductor substrate 100 and the bonding substrate 110 due to the difference in thermal expansion coefficient is approximately 5.70 × 10 ⁻² [mm].

On the other hand, when the semiconductor substrate 100 and the bonding substrate 110 are bonded together in a state of being heated to 150 ° C. in advance, and a heat treatment at 400 ° C. is performed on both the substrates, the temperature difference (ΔT ₁₎ before and after the semiconductor substrate 100 is heated. ) And the temperature difference (ΔT ₂ ) before and after heating the bonding substrate 110 are both 250 ° C.

Therefore, the displacement amount (ΔL ₁ ) of the semiconductor substrate 100 is approximately 6.25 × 10 ⁻² [mm], and the displacement amount (ΔL ₂ ) of the bonding substrate 110 is approximately 2.50 × 10 ⁻² [mm]. It becomes. Therefore, the difference in expansion amount (ΔL ₁ −ΔL ₂ ) between the semiconductor substrate 100 and the bonding substrate 110 due to the difference in thermal expansion coefficient is about 3.75 × 10 ⁻² [mm], which is heated from room temperature. In this case, the difference is a little over 60% of the difference in expansion amount (ΔL ₁ −ΔL ₂ ).

Thus, before the semiconductor substrate 100 and the bonding substrate 110 are bonded together, the temperature adjustment device 220 provided on the first installation table 211 and the temperature adjustment device 220 provided on the second installation table 212 are used. By making the temperature of both the substrates higher than room temperature in advance, the difference between the expansion amount of the semiconductor substrate 100 and the expansion amount of the bonding substrate 110 when performing the separation heat treatment can be made closer.

For the following steps, the thermal expansion coefficient is determined by referring to FIGS. 1D and 1E described in Embodiment 1 and the contents of Embodiment 1 corresponding to the description of the drawings. A high-quality SOI substrate 120 in which peeling or breakage due to the difference is suppressed can be manufactured.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, a semiconductor element using an SOI substrate manufactured by the method described in Embodiment 1 will be described.

FIG. 6 illustrates a structure of a transistor 720 as an example of a semiconductor element using the SOI substrate 120 manufactured by the method of Embodiment 1.

The transistor 720 includes a base film 701 provided over the substrate 700, a low resistance region 702a functioning as a source region or a drain region provided on the base film 701, and a channel formation region 702b sandwiched between the low resistance regions 702a. A gate insulating film 704 provided over the low resistance region 702a and the channel formation region 702b, a gate electrode 706 provided over the gate insulating film 704, and over the gate insulating film 704 and the gate electrode 706. The first insulating film 708 and the second insulating film 710 provided, the gate insulating film 704, the low resistance region 702a through the opening formed in the first insulating film 708 and the second insulating film 710, A wiring layer 712 that functions as a source wiring or a drain wiring is provided.

As a method for manufacturing the transistor 720 using the SOI substrate 120, first, a known technique such as a photolithography method or an etching method is used for the semiconductor film 108 of the SOI substrate 120 manufactured by the method described in Embodiment 1. Then, a semiconductor layer 702 is formed over the base film 701 (see FIG. 7A). Note that the bonding substrate 110 of the SOI substrate 120 corresponds to the substrate 700 of this embodiment, and the insulating film 102 of the SOI substrate 120 corresponds to the base film 701 of this embodiment. Note that the base film 701 has a function of suppressing diffusion of impurities such as sodium that adversely affect the characteristics of the transistor, such as sodium, from the substrate 700 to the semiconductor layer 702.

Next, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is added to the semiconductor layer 702 using a known technique such as an ion implantation method. To do. In the case where the semiconductor layer 702 is silicon, phosphorus (P), arsenic (As), or the like can be used as the impurity element imparting n-type conductivity, for example. As the impurity element imparting p-type conductivity, for example, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

Next, a gate insulating film 704 that covers the semiconductor layer 702 is formed using a known technique such as a CVD method or a sputtering method (see FIG. 7B). The gate insulating film 704 is doped with silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x> 0, y> 0)), or nitrogen. A single-layer structure or a stacked structure including a hafnium silicate (HfSixOy (x> 0, y> 0)), a hafnium aluminate added with nitrogen (HfAlxOy (x> 0, y> 0)), or the like. desirable. Note that the thickness of the gate insulating film 704 may be, for example, not less than 1 nm and not more than 200 nm, preferably not less than 10 nm and not more than 100 nm. For example, as the gate insulating film 704, What is necessary is just to form and use by 50 nm thickness.

Next, a conductive layer is formed over the gate insulating film 704 using a known technique such as sputtering or vapor deposition, and then the conductive layer is patterned using a known technique such as photolithography or etching. A gate electrode 706 is formed (see FIG. 7C). The conductive layer used for the gate electrode 706 can be formed using a single layer or multiple layers using a metal material such as aluminum, copper, titanium, tantalum, or tungsten, or a nitride of the metal material. Alternatively, the conductive layer may be formed using a semiconductor material such as polycrystalline silicon. Note that the thickness of the gate electrode may be, for example, 10 nm to 1000 nm, preferably 50 nm to 500 nm. For example, as the gate electrode 706, a stacked film of tantalum, copper, and titanium is formed to a thickness of 300 nm by a sputtering method. It may be formed and used.

Next, using the gate electrode 706 as a mask, an impurity element imparting one conductivity type is added to the semiconductor layer 702 using a known technique such as an ion implantation method, so that the low resistance region 702a and the channel formation region 702b are formed. (See FIG. 7D.) For example, an impurity element such as phosphorus (P) or arsenic (As) may be added to form an n-type transistor, and boron (B) or aluminum (Al) may be formed to form a p-type transistor. Or an impurity element such as gallium (Ga) may be added. Note that heat treatment for activation may be performed after the impurity element is added.

Next, a first insulating film 708 and a second insulating film 710 are formed so as to cover the gate insulating film 704 and the gate electrode 706 by using a known technique such as a sputtering method, a CVD method, or a spin coating method ( (See FIG. 8A.) As the first insulating film 708 and the second insulating film 710, a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide can be used. Alternatively, an organic insulating material such as polyimide or acrylic can be used for the first insulating film 708 and the second insulating film 710. Note that the thickness of the first insulating film 708 and the second insulating film 710 may be, for example, 100 nm to 5000 nm, preferably 300 nm to 3000 nm. For example, the first insulating film 708 may be formed by a CVD method. After the silicon oxide film is formed with a thickness of 300 nm, a polyimide resin with a thickness of 1000 nm may be used as the second insulating film 710 by spin coating.

Next, an opening reaching the low resistance region 702a is formed in the gate insulating film 704, the first insulating film 708, and the second insulating film 710 by using a known technique such as a photolithography method or an etching method. .

Next, after forming a conductive layer using a known technique such as sputtering or vapor deposition so as to cover the opening, the conductive layer is patterned using a known technique such as photolithography or etching. Thus, the wiring layer 712 is formed. As a conductive layer for forming the wiring layer 712, a method and a material similar to those of the gate electrode 706 can be used. Note that the thickness of the conductive layer may be, for example, 100 nm or more and 1000 nm or less, preferably 200 nm or more and 800 nm or less. For example, as the conductive layer, a stacked structure in which aluminum is sandwiched between titanium by a sputtering method is formed with a thickness of 500 nm. Can be used.

Through the above steps, the transistor 720 can be formed (see FIG. 8B). The transistor 720 using the SOI substrate 120 manufactured in Embodiment 1 can use a semiconductor film having a single crystal structure as an active layer (also referred to as a semiconductor layer) in which a channel region is formed; A transistor having high and stable electric characteristics can be obtained. In addition, by using the bonding method described in Embodiment Mode 1, a single crystal semiconductor substrate and a substrate having a thermal expansion coefficient different from that of the single crystal semiconductor (for example, a glass substrate or the like can be inexpensive and large) A large SOI substrate to which a large substrate is attached can be manufactured, so that more transistors can be formed over one substrate.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 4)
The semiconductor device disclosed in this specification and the like can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (a mobile phone or a mobile phone). Large-sized game machines such as portable game machines, portable information terminals, sound reproduction apparatuses, and pachinko machines. Examples of electronic devices each including the liquid crystal display device described in the above embodiment will be described.

FIG. 9A illustrates a portable personal computer, which includes a housing 1011, a housing 1012, a first display portion 1013a, a second display portion 1013b, and the like. Various electronic components (eg, a CPU, an MPU, a memory element, and the like) are incorporated in the housing 1011 and the housing 1012. The first display portion 1013a and the second display portion 1013b are equipped with electronic circuits (for example, a drive circuit and a selection circuit) necessary for displaying an image. By applying the semiconductor device described in any of the above embodiments to these electronic components and electronic circuits, a highly reliable portable information terminal can be obtained. Note that the semiconductor device described in any of the above embodiments may be provided in at least one of the housing 1011 and the housing 1012.

Note that at least one of the first display portion 1013a and the second display portion 1013b is a panel having a touch input function. For example, as shown in the left diagram of FIG. 9A, the first display portion 1013a It is possible to select whether to perform “touch input” or “keyboard input” using a selection button 1014 displayed on the screen. Since the selection buttons can be displayed in various sizes, a wide range of people can feel ease of use. Here, for example, when “touch input” is selected, a keyboard 1015 is displayed on the first display portion 1013a as shown in the right diagram of FIG. As a result, as in the conventional information terminal, quick character input by key input and the like are possible.

In addition, the portable information terminal illustrated in FIG. 9A can separate the housing 1011 and the housing 1012 as illustrated on the right in FIG. 9A. Accordingly, it is possible to perform operations such as controlling the screen information with the housing 1012 while sharing the screen information with a large number of people by hanging the housing 1011 on the wall, which is very convenient. Note that in the case where the device is not used, the housing 1011 and the housing 1012 are preferably overlapped so that the first display portion 1013a and the second display portion 1013b face each other. Accordingly, the first display portion 1013a and the second display portion 1013b can be protected from an impact applied from the outside. The first display portion 1013a is also a panel having a touch input function, and can be further reduced in weight when carried, and can be operated with the other hand while holding the housing 1012 with one hand. Convenient.

FIG. 9A illustrates a function for displaying various types of information (still images, moving images, text images, etc.), a function for displaying a calendar, date, time, or the like on the display unit, and operating or editing information displayed on the display unit. A function, a function of controlling processing by various software (programs), and the like can be provided. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

Further, the portable information terminal illustrated in FIG. 9A may have a structure in which information can be transmitted and received wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Further, the housing 1011 or the housing 1012 illustrated in FIG. 9A may have an antenna, a microphone function, or a wireless function, and may be used as a mobile phone.

FIG. 9B illustrates an example of an electronic book 1020. For example, the electronic book 1020 includes two housings, a housing 1021 and a housing 1023. The housing 1021 and the housing 1023 are integrated with a shaft portion 1022, and can be opened and closed with the shaft portion 1022 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 1025 is incorporated in the housing 1021 and a display portion 1027 is incorporated in the housing 1023. The display unit 1025 and the display unit 1027 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text is displayed on the right display unit (display unit 1025 in FIG. 9B) and an image is displayed on the left display unit (display unit 1027 in FIG. 9B). Can be displayed. By applying the semiconductor device described in any of the above embodiments, a highly reliable e-book reader 1020 can be provided.

FIG. 9B illustrates an example in which the housing 1021 is provided with an operation portion and the like. For example, the housing 1021 is provided with a power source 1026, operation keys 1028, a speaker 1029, and the like. Pages can be sent with the operation keys 1028. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing. Further, the e-book reader 1020 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 1020 may be configured to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

FIG. 9C illustrates a smartphone, which includes a housing 1030, a button 1031, a microphone 1032, a display portion 1033 including a touch panel, a speaker 1034, and a camera lens 1035, and is a mobile phone. As a function. By applying the semiconductor device described in Embodiment 1 or 2, the smartphone can have high reliability.

In the display portion 1033, the display direction can be appropriately changed depending on a usage pattern. In addition, since the camera lens 1035 is provided on the same surface as the display portion 1033, a videophone can be used. The speaker 1034 and the microphone 1032 can be used for videophone calls, recording and playing sound, and the like as well as voice calls.

The external connection terminal 1036 can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with a personal computer are possible. Further, a recording medium can be inserted into an external memory slot (not shown), and a larger amount of data can be stored and moved.

In addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

FIG. 9D illustrates a digital video camera which includes a main body 1041, a display portion 1042, operation switches 1043, a battery 1044, and the like. By applying the semiconductor device described in any of the above embodiments, a highly reliable digital video camera can be obtained.

FIG. 9E illustrates an example of the television device 1050. In the television device 1050, a display portion 1053 is incorporated in a housing 1051. An image can be displayed on the display portion 1053. Here, a configuration in which the housing 1051 is supported by a stand 1055 is shown. By using the semiconductor device described in any of the above embodiments, a highly reliable television set 1050 can be provided.

The television device 1050 can be operated with an operation switch provided in the housing 1051 or a separate remote controller. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

Note that the television set 1050 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

In this embodiment, a single crystal silicon wafer (crystal orientation: (100), thickness: 0.7 mm, shape: a side of 126.6 mm, substantially square, thermal expansion coefficient: 2.551 [× 10 ⁻⁶ / K] as the semiconductor substrate 100. ] (20 ° C.) to 4.335 [× 10 ⁻⁶ / K] (727 ° C.)) as a bonded substrate 110, a synthetic quartz substrate (thickness: 1.1 mm, a substantially rectangular shape with a side of 126.6 mm), thermal expansion coefficient : 0.55 [× 10 ⁻⁶ / K] (20 ° C. to 320 ° C.)), a sample in which both substrates are bonded to each other without performing temperature adjustment treatment (hereinafter abbreviated as sample A). ) And a temperature adjustment process to prepare a sample (hereinafter abbreviated as sample B) in which the two substrates are bonded together, and both the samples are subjected to a heat treatment (separation heat treatment). Depending on whether or not Peeling of the semiconductor substrate and the bonding substrate to a temperature of the order of, or destruction of the semiconductor substrate or the bonded substrate was investigated whether it is possible to heat without generating.

<Method for Manufacturing SOI Substrate>
First, a silicon oxide film was formed on the surface of the single crystal silicon wafer by performing thermal oxidation treatment on the single crystal silicon wafer. The silicon oxide film was formed to a thickness of 100 nm by performing heat treatment at 950 ° C. in an oxygen atmosphere containing 3% HCl.

Next, an embrittled region was formed in the single crystal silicon wafer by irradiating accelerated hydrogen ions into the single crystal silicon wafer through the silicon oxide film. An ion doping apparatus was used for irradiation with hydrogen ions. 100% hydrogen gas was used as the source gas, and plasma was generated by exciting the hydrogen gas. The generated plasma includes three types of ion species (H ⁺ , H ₂ ⁺ and H ₃ ⁺ ). The three types of ion species were accelerated by an electric field without being separated, and irradiated to a single crystal silicon wafer. The flow rate of hydrogen gas was 50 sccm, the acceleration voltage was 50 kV, the current density was 6.35 μA / cm ² , and the dose was 2.9 × 10 ¹⁶ ions / cm ² .

Next, a cleaning process was performed on the silicon wafer. In the cleaning process, cleaning was performed for 60 seconds using an alkaline chemical solution, and then the silicon wafer was dried using IPA (Isopropyl Alcohol).

Next, the single crystal silicon wafer and the synthetic quartz substrate were bonded together. Note that the bonding is performed by bonding the two substrates without adjusting the temperature (hereinafter referred to as sample A), and as a temperature adjusting process, the single crystal silicon wafer is subjected to a resistance heating apparatus in an air atmosphere. The synthetic quartz substrate was set at room temperature (about 20 ° C.) and the two substrates were bonded together (hereinafter referred to as sample B). .

Sample A and Sample B produced by the above-described steps were subjected to a stage temperature from room temperature to 7 ° C./min using a warpage measuring device (KLA Tencor Corporation, Tencor FLX-2320) having a stage equipped with a heating mechanism. While changing the temperature, the transition of the amount of warpage of Sample A and Sample B was measured. The sample was placed in the warpage measurement device with the silicon wafer having a large thermal expansion coefficient down (that is, in contact with the heating stage) and the synthetic quartz substrate having a small thermal expansion coefficient facing up. . Further, the silicon wafer and the synthetic quartz substrate were bonded to each other so that the four corners of the both substrates were substantially aligned.

FIG. 10 shows the relationship between the substrate temperature and the amount of warpage of Sample A and Sample B. In FIG. 10, the horizontal axis represents the substrate heating temperature, and the vertical axis represents the amount of warpage of the substrate. The amount of warpage of the substrate is 0 [μm] when the shape of the sample is parallel to the stage of the warpage amount measuring device. When the sample is deformed into a U-shape, the value is negative, and when the sample is deformed into an inverted U-shape, the value is positive. In FIG. 10, since the silicon wafer and the synthetic quartz substrate are bonded to each other at 200 ° C. in the sample B, the substrate temperature is about 200 ° C., and the amount of warpage is approximately 0 [μm]. In the temperature range where the substrate temperature is lower than that, the warpage amount becomes a positive value due to the shrinkage of the silicon wafer.

In sample A, until the substrate temperature is about 200 ° C., the amount of warpage of the sample increases linearly in the negative direction (the direction in which the sample is deformed into a U-shape), but when the substrate temperature is about 200 ° C., The expansion amount of the synthetic quartz substrate cannot follow the expansion amount of the silicon wafer, and the force that the synthetic quartz substrate suppresses the expansion of the silicon wafer starts to work strongly. The amount of warpage in the market is almost flat. When the substrate temperature reaches about 350 ° C., the amount of warping of the sample becomes 0 [μm] at a stretch. This is because the force generated by the difference in expansion between the silicon wafer and the synthetic quartz substrate is larger than the bonding force between the silicon wafer and the synthetic quartz substrate, so that the silicon wafer and the synthetic quartz substrate are separated.

Heating at a temperature of about 400 ° C. is necessary in order to concentrate the hydrogen ions irradiated to the silicon wafer in the embrittled region so that the silicon ion can be easily separated in the embrittled region. However, when the silicon wafer and the synthetic quartz substrate are bonded together without performing the temperature adjustment process as described above, the substrates are separated at a substrate temperature of about 350 ° C.

On the other hand, in sample B, the amount of warpage of the sample increases linearly in the negative direction (the direction in which the sample is deformed into a U-shape) until the substrate temperature is about 300 ° C., and then the silicon wafer is increased to about 460 ° C. The sample can be heated without peeling off the synthetic quartz substrate. For this reason, the separation heat treatment can be performed without peeling off the silicon wafer and the synthetic quartz substrate.

From the above results, even when the difference between the thermal expansion coefficient of the semiconductor substrate and the thermal expansion coefficient of the bonding substrate is large, the temperature adjustment processing is performed on both substrates before bonding the semiconductor substrate and the bonding substrate. Thus, an SOI substrate can be manufactured while suppressing peeling and destruction of the substrate.

100 Semiconductor substrate 102 Insulating film 104 Ion irradiation treatment 106 Embrittlement region 108 Semiconductor film 110 Bonding substrate 120 SOI substrate 211 First installation table 212 Second installation table 220 Temperature adjustment device 230 Drive device 232 Axis 234 Substrate fixing mechanism 236 Movable Part 700 Substrate 701 Base film 702 Semiconductor layer 702a Low resistance region 702b Channel formation region 704 Gate insulating film 706 Gate electrode 708 First insulating film 710 Second insulating film 712 Wiring layer 720 Transistor 1011 Housing 1012 Housing 1013a First Display unit 1013b Second display unit 1014 Select button 1015 Keyboard 1020 Electronic book 1021 Case 1022 Shaft unit 1023 Case 1025 Display unit 1026 Power supply 1027 Display unit 1028 Operation key 1029 Speaker 1030 Case 103 Button 1032 microphone 1033 display unit 1034 speaker 1035 camera lens 1036 external connection terminal 1041 body 1042 display unit 1043 operation switch 1044 battery 1050 television device 1051 housing 1053 display unit 1055 stand

Claims (15)

Forming an insulating film on the surface of the semiconductor substrate;
Forming an embrittled region inside the semiconductor substrate by irradiating accelerated ions to one surface of the semiconductor substrate through the insulating film,
Bonding a bonding substrate to the insulating film formed on one surface of the semiconductor substrate, performing a bonding process,
Heating the semiconductor substrate and the bonding substrate;
Separating the bonding substrate from the semiconductor substrate to form a semiconductor film on the bonding substrate via the insulating film;
The thermal expansion coefficient of the bonding substrate is smaller than the thermal expansion coefficient of the semiconductor substrate,
In the bonding process, the semiconductor substrate and the bonding substrate are bonded to each other with the temperature of the semiconductor substrate being higher than the temperature of the bonding substrate. 2. The bonding process according to claim 1, wherein in the bonding process, the semiconductor substrate and the bonding substrate are bonded together by performing a heat treatment on the semiconductor substrate so that the temperature of the semiconductor substrate is higher than the temperature of the bonding substrate. A manufacturing method of the described SOI substrate. In the bonding process, the semiconductor substrate and the bonding substrate are bonded to each other by performing a cooling process on the bonding substrate so that the temperature of the semiconductor substrate is higher than the temperature of the bonding substrate. A manufacturing method of the described SOI substrate. In the bonding process, the semiconductor substrate is heated to a temperature, and the bonding substrate is cooled to make the temperature of the semiconductor substrate higher than the temperature of the bonding substrate. The method for manufacturing an SOI substrate according to claim 1, wherein the substrate and the bonding substrate are bonded together. Forming an insulating film on the surface of the semiconductor substrate;
Forming an embrittled region inside the semiconductor substrate by irradiating accelerated ions to one surface of the semiconductor substrate through the insulating film,
Bonding a bonding substrate to the insulating film formed on one surface of the semiconductor substrate, performing a bonding process,
Heating the semiconductor substrate and the bonding substrate;
Separating the bonding substrate from the semiconductor substrate to form a semiconductor film on the bonding substrate via the insulating film;
The thermal expansion coefficient of the bonding substrate is smaller than the thermal expansion coefficient of the semiconductor substrate,
In the bonding, heat treatment is performed on both the semiconductor substrate and the bonding substrate, and the semiconductor substrate and the bonding substrate are bonded to each other with the temperature of the semiconductor substrate and the bonding substrate being higher than room temperature. And manufacturing method of SOI substrate.   6. The SOI substrate according to claim 1, wherein plasma processing is performed on the insulating film on the semiconductor substrate between the formation of the embrittlement region and the bonding process. Manufacturing method.   The plasma treatment is performed using any one of He gas, Ar gas, Kr gas, Xe gas, oxygen gas, nitrogen oxide gas, ammonia gas, nitrogen gas, hydrogen gas, or a mixed gas thereof. 7. The method for manufacturing an SOI substrate according to claim 6. 8. The SOI according to claim 1, wherein an ion beam irradiation process is performed on the insulating film on the semiconductor substrate between the formation of the embrittlement region and the bonding process. A method for manufacturing a substrate. The ion beam irradiation treatment is performed using He gas, Ar gas, Kr gas, Xe gas, oxygen gas, nitrogen oxide gas, ammonia gas, nitrogen gas, hydrogen gas, or a mixed gas thereof, and acceleration of 10 eV or more and 200 ev or less. The method for manufacturing an SOI substrate according to claim 1, wherein irradiation is performed with a voltage. The bonded substrate is larger than the semiconductor substrate,
The method for manufacturing an SOI substrate according to claim 1, wherein a plurality of the semiconductor substrates are bonded to the bonding substrate. A first installation base for installing a semiconductor substrate;
A second installation base for installing the bonding substrate;
A driving device for bonding the semiconductor substrate and the bonding substrate;
A laminating apparatus comprising a first temperature adjusting device for heating the first installation table. A first installation base for installing a semiconductor substrate;
A second installation base for installing the bonding substrate;
A driving device for bonding the semiconductor substrate and the bonding substrate;
A laminating apparatus comprising a second temperature adjusting device for cooling the second installation table. A first installation base for installing a semiconductor substrate;
A second installation base for installing the bonding substrate;
A driving device for bonding the semiconductor substrate and the bonding substrate;
A first temperature adjusting device for heating the first installation table;
A laminating apparatus comprising a second temperature adjusting device for cooling the second installation table. The surface of the second installation table on which the bonding substrate is installed is wider than the surface of the first installation table on which the semiconductor substrate is installed,
The bonding apparatus according to any one of claims 11 to 13, comprising a plurality of the first installation tables. The first installation table has an inclination with respect to the second installation table;
The inclination includes the one surface of the bonding substrate facing the semiconductor substrate when the bonding substrate is installed on the second installation table and the semiconductor substrate is installed on the first installation table, and the bonding substrate. The angle difference with one surface of the semiconductor substrate facing the substrate is more than 0 degree and less than 3 degrees,
The bonding apparatus according to any one of claims 11 to 14, wherein a surface of the first installation base on which the semiconductor substrate is installed is smaller than the semiconductor substrate.

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