JP2013114369A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an information processing device that improves IO performance without adjusting an old generation S/W to up-to-date H/W when implementing the old generation S/W on the up-to-date H/W.SOLUTION: In an information processing device, a prefetch capability 102 that operates independently from OS 100 operating on a hypervisor 101 is provided with the hypervisor 101 operating on a CPU 103. The prefetch capability 102 prefetches data in an HDD 106 and stores it in a prefetch buffer 105 of a memory 104. In response to an access request from the OS 100 to the HDD 106, if data is stored in the prefetch buffer 105, the data is read from the prefetch buffer 105 to notify to the OS 100.

Description

  The present invention relates to an information processing apparatus that uses a virtualization technology to improve IO performance when an older generation S / W (software) is installed in the latest H / W (hardware).

Conventionally, when an old generation S / W is installed in the latest H / W, a method of using a virtualization technology (hypervisor) as a method of maintaining compatibility without modifying the S / W is known. Known (Patent Document 1).
By emulating the H / W configuration in which the old generation S / W can operate with the hypervisor and showing it to the old generation H / W, the virtual visor provided by the hypervisor can be provided without modifying the old generation S / W. It becomes possible to operate on H / W.

JP 2010-204962 A (pages 13-14, FIG. 3)

When the old generation S / W is operated on the hypervisor, H / W emulation by the hypervisor is required. In addition to the operation time of the old generation S / W, the processing time of the hypervisor is added. Compared to the original H / W performance, the IO performance was reduced.
Also, although H / W can operate at high speed, the old generation S / W does not have access suitable for it, so the processing of the old generation S / W becomes a bottleneck and the H / W performance cannot be fully utilized. There was a case where IO performance deteriorated.

  The present invention has been made to solve the above-described problems. When an older generation S / W is installed in the latest H / W, the IO performance can be improved without forming a virtual H / W. It aims at obtaining the information processing apparatus which improves.

  The information processing apparatus according to the present invention includes a hypervisor that operates on hardware including a CPU, a memory, and a hard disk device, and an OS that operates on the hypervisor, and the hypervisor operates independently of the OS. Pre-reading means for pre-reading data in a predetermined area of the hard disk device and storing the data in a pre-reading buffer provided on the memory. If the access is to an area, the prefetch buffer is accessed.

  According to the present invention, a hypervisor that operates on hardware including a CPU, a memory, and a hard disk device, and an OS that operates on the hypervisor, the hypervisor operates independently of the OS, and the hard disk device is provided. Pre-reading means for pre-reading data in a predetermined area and storing the data in a pre-reading buffer provided on the memory. The pre-reading means is for a request for access to the hard disk device from the OS to the predetermined area of the hard disk device. In some cases, access to the prefetching buffer is executed, so that the IO performance can be improved without forming a virtual H / W even with an older generation S / W.

It is a block diagram which shows the information processing apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows operation | movement of the information processing apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the structure and operation | movement of the information processing apparatus by Embodiment 2 of this invention. It is a block diagram which shows the information processing apparatus by Embodiment 3 of this invention. It is a flowchart which shows the internal operation | movement of the access frequency management function in the information processing apparatus by Embodiment 3 of this invention. It is a block diagram which shows the information processing apparatus by Embodiment 4 of this invention. It is a block diagram which shows the information processing apparatus by Embodiment 5 of this invention.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is a block diagram showing an information processing apparatus according to Embodiment 1 of the present invention.
In FIG. 1, an S / W configuration is adopted in which a hypervisor 101 is mounted on a CPU 103 that is the latest H / W, and an old generation OS 100 is operated on the hypervisor 101. The OS 100 does not directly access the H / W resources of the memory 104 or the HDD 106 (hard disk device), but accesses it via the hypervisor 101.
The hypervisor 101 has a prefetch function 102 (prefetch means) that accesses the HDD 106 independently of the IO request of the OS 100. A space of the prefetch buffer 105 is allocated to the memory 104 as a dedicated memory space used by the prefetch function 102.

FIG. 2 is an explanatory diagram showing the operation of the information processing apparatus according to Embodiment 1 of the present invention.
In FIG. 2, reference numerals 100 to 106 are the same as those in FIG. a to h show the flow of processing.

Next, the operation of the first embodiment will be described with reference to FIG.
Normally, an IO request from the OS 100 to the HDD 106 accesses the HDD 106 via the hypervisor 101 (a) and notifies the OS 100 of the result (b).
At this time, if the IO request from the OS 100 continues to a continuous area (predetermined area) or concentrates in a certain area, the hypervisor 101 determines that the next IO request from the OS 100 is It is determined that there is a high possibility of access to a peripheral area (predetermined area), and the prefetch function 102 is operated.
The prefetch function 102 accesses the HDD 106 using a free time when there is no IO request from the OS 100 (c), and accumulates data in a peripheral area where access from the OS 100 is concentrated in the prefetch buffer 105. (D).

When there is an IO request (read) from the OS 100 to an area accumulated in the prefetch buffer 105 (e), the prefetch function 102 reads the corresponding data from the prefetch buffer 105 and notifies the OS of the result (f) ).
If the IO request from the OS 100 is a write, only the prefetch buffer 105 is updated (g), and the OS 100 is notified of completion. Thereafter, the prefetch function 102 writes the data saved in the prefetch buffer 105 to the HDD 106 using the IO free time (h).

Thus, a part of the IO request from the OS 100 is completed without accessing the HDD 106, so the OS 100 can operate at high speed without waiting for the IO.
In addition, the prefetch function 102 uses the idle time of the processing of the OS 100 to access the HDD 106 regardless of the IO request of the OS 100, so that the original H / W performance is exhibited and data is stored in the prefetch buffer 105. Can be accumulated.

  According to the first embodiment, since the data in the HDD is pre-read by the hypervisor interposed between the OS and the HDD, even an old generation OS can operate at high speed.

Embodiment 2. FIG.
The second embodiment of the present invention will be described below with reference to the drawings.
FIG. 3 is an explanatory diagram showing the configuration and operation of the information processing apparatus according to Embodiment 2 of the present invention.
In FIG. 3, reference numerals 100, 101, 103, 104, and 106 are the same as those in FIG. In FIG. 3, the hypervisor 101 is equipped with a mirroring function 301 (mirroring means) instead of the prefetch function 102 of FIG. The memory 104 is provided with an HDD buffer 302 (hard disk device buffer). When the size of the OS usage area 303 actually required by the OS 100 in the HDD 106 is smaller than the size of the memory 302, this usage mode can be adopted.
The mirroring function 301 performs a mirroring process that synchronizes so that the content of the HDD buffer 302 is the same as that of the OS use area 303.

Next, the operation of the second embodiment will be described with reference to FIG.
The operation of the mirroring function 301 is basically the same as that of the prefetch function 102 in FIG. The mirroring function 301 accesses the HDD buffer 302 using free time without an IO request from the OS 100 (j), and reads the memory 104 and the HDD 106 so as to keep the contents synchronized with the OS use area 303. Write (k). When there is an IO request from the OS 100 (m), all accesses are made to the HDD buffer 302 (n).

The advantage of the second embodiment is that since all IO requests from the OS 100 are made only to the HDD buffer 302, the IO waiting time of the OS 100 is completely eliminated.
In addition, in the hypervisor 101, the process of determining whether or not the IO target data is accumulated in the prefetch buffer (105 in FIG. 1) becomes unnecessary, and thus the process of the hypervisor 101 is reduced. Therefore, the processing time of the hypervisor 101 occupying the IO request of the OS 100 can be shortened.

  According to the second embodiment, by synchronizing the contents of the OS usage area of the HDD and the HDD buffer of the memory, access to the HDD of the OS is eliminated, thus eliminating the IO waiting time of the OS, and The processing of the visor can be reduced.

Embodiment 3 FIG.
Embodiment 3 of the present invention will be described below with reference to the drawings.
FIG. 4 is a block diagram showing an information processing apparatus according to Embodiment 3 of the present invention.
In FIG. 4, reference numerals 100, 101, 103, 104, and 106 are the same as those in FIG. In FIG. 4, the hypervisor 101 is provided with an access frequency management function 401 (access frequency management means) instead of the prefetch function 102 in FIG. The memory 104 is allocated with a space for a buffer 403 for caching the HDD 106 and an access frequency management table 402 for storing the access frequency for each fixed area of the HDD 106.
The access frequency management function 401 divides the HDD 106 into fixed areas and stores the access frequency from the OS 100 in the access frequency management table 402. The access frequency management function 401 gives priority to areas with a high number of accesses or areas that have recently been accessed. Has a function of storing in the buffer 403.

Next, the operation of the access frequency management function 401 will be described based on the flowchart of FIG.
When there is an IO request from the OS 100 (step 501), the access frequency management table 402 is read (step 502), and it is determined whether the IO target area is an area with high access frequency (step 503). If the frequency is not high, the HDD 106 is directly accessed (step 504), and the result is notified to the OS 100 (step 505). The OS 100 ends the IO processing at this point.
Thereafter, the access frequency management function 401 updates the access frequency management table 402 based on the current IO request (step 506), and if it is determined that the frequency is high as a result of the current IO processing ( Step 507), the corresponding area is added to the buffer 403 (Step 508). If it is not determined in step 507 that the frequency is high, the processing is terminated as it is (step 514).

If it is determined in step 503 that the request is an IO request for a high-frequency area, the buffer 403 is accessed (step 509), and the result is notified to the OS 100 (step 510). The OS 100 ends the IO processing at this point.
After that, the access frequency management function 401 updates the HDD 106 according to the contents of the buffer 403 when the current IO request is a write (step 511) (step 512). Finally, the access frequency management table 402 is updated (step 513), and the process ends (step 514).

In the third embodiment, as in the first embodiment, since a part of the IO request from the OS 100 is completed without accessing the HDD 106, the OS 100 can operate at high speed without IO waiting time.
Unlike the first embodiment, the HDD 106 access not related to the IO request from the OS 100 is not performed, so that the operation of the hypervisor 101 is lighter than that of the first embodiment.

  According to the third embodiment, the buffer for caching the HDD is provided in the memory, and the IO operation for the high-frequency access area of the HDD is made to the buffer, so that the operation of the OS and the hypervisor The operation can be made faster.

Embodiment 4 FIG.
Embodiment 4 of the present invention will be described below with reference to the drawings.
FIG. 6 is a block diagram showing an information processing apparatus according to Embodiment 4 of the present invention.
6, 100 to 104 and 106 are the same as those in FIG. 1, and 401 to 403 are the same as those in FIG.

The fourth embodiment is a combination of the functions of the first embodiment and the third embodiment.
The hypervisor 101 is provided with both functions of a prefetch function 102 (prefetch means) and an access frequency management function 401 (access frequency management means). In the fourth embodiment, the prefetch function 102 refers to the access frequency management table 402 so as to accumulate an area with high access frequency in the buffer 403.
As in the third embodiment, the access frequency management function 401 collects access statistics according to IO requests from the OS 100 and stores them in the access frequency management table 402.
The access frequency management function 401 operates in the same manner as in the third embodiment in response to an IO request from the OS 100, and executes an access to the buffer 403 if the IO request is for a high-frequency area.

  According to the fourth embodiment, this makes it possible to expect the effect of prefetching because areas that are normally accessed frequently are preferentially stored in the buffer.

Embodiment 5 FIG.
The fifth embodiment of the present invention will be described below with reference to the drawings.
FIG. 7 is a block diagram showing an information processing apparatus according to Embodiment 5 of the present invention.
7, 101, 104, and 106 are the same as those in FIG. In FIG. 7, the CPU is a multi-core CPU 705, which has a core 1 (706) and a core 2 (707). Corresponding to this, a plurality of OS1 (701) and OS2 (702) operate on the hypervisor 101.
Corresponding to the core 1 (706) and the core 2 (707), the hypervisor 101 is provided with a prefetch function 1 (703) (prefetch means) and a prefetch function 2 (704) (prefetch means). 104 includes a prefetch buffer 1 (708) and a prefetch buffer 2 (709).
The prefetch functions 1 and 2 and the prefetch buffers 1 and 2 are the same as those in the first embodiment.

In the fifth embodiment, the first embodiment is expanded corresponding to the multi-core CPU 705.
In the asymmetric multiprocessing system in which different OS1 (701) and OS2 (702) are assigned to each core 1 (706) and core 2 (707), the area of the HDD 106 accessed by each OS1, 2 (701, 702) is accessed. Since there is almost no correlation, different prefetch functions 1 (703), prefetch functions 2 (704), prefetch buffers 1 (708), and prefetch corresponding to each OS 1 and 2 (701, 702). A buffer 2 (709) is provided.
The group of OS1 (701), prefetch function 1 (703), core 1 (706), prefetch buffer 1 (708), and OS2 (702), prefetch function 2 (704), core 2 (707) in the fifth embodiment ), Each group of the prefetch buffer 2 (709) operates in the same manner as in the first embodiment.

  According to the fifth embodiment, this allows the hypervisor to support the multi-core CPU without performing special modification according to the number of cores, and to implement the implementation on the OS operating on each core. The same effect as in the form 1 can be expected.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

100 OS
101 Hypervisor 102 Prefetch Function 103 CPU
104 Memory 105 Prefetch Buffer 106 HDD
301 Mirroring Function 302 HDD Buffer 303 OS Usage Area 401 Access Frequency Management Function 402 Access Frequency Management Table 403 Buffer 701 OS1
702 OS2
703 Prefetch function 1
704 Prefetch function 2
705 Multi-core CPU
706 Core 1
707 Core 2
708 Prefetch buffer 1
709 Prefetch buffer 2

Claims (5)

A hypervisor that operates on hardware having a CPU, memory, and hard disk drive;
And an OS operating on this hypervisor,
The hypervisor is
Pre-reading means that operates independently of the OS, pre-reads data in a predetermined area of the hard disk device, and stores the data in a pre-read buffer provided on the memory;
The prefetch means executes an access to the prefetch buffer when a request for access to the hard disk device from the OS is for a predetermined area of the hard disk device. apparatus. A hypervisor that operates on hardware having a CPU, memory, and hard disk drive;
And an OS operating on this hypervisor,
The hypervisor is
Mirroring means for making the OS use area used by the OS of the hard disk device the same as the hard disk device buffer provided in the memory;
The information processing apparatus, wherein the mirroring unit executes an access request from the OS to the hard disk device for the hard disk device buffer. A hypervisor that operates on hardware having a CPU, memory, and hard disk drive;
And an OS operating on this hypervisor,
The hypervisor is
The hard disk device area is divided, and the access frequency from the OS for each area is stored in the access frequency management table provided in the memory, and data in the high access frequency area of the hard disk device is preferentially stored. Having access frequency management means for storing in a buffer provided in the memory,
The access frequency management means executes an access to the buffer when an access request from the OS to the hard disk device is for an area with a high access frequency. A hypervisor that operates on hardware having a CPU, memory, and hard disk drive;
And an OS operating on this hypervisor,
The hypervisor is
An access frequency management means for dividing an area of the hard disk device and storing an access frequency from the OS for each area in an access frequency management table provided in the memory;
Prefetching that operates independently of the OS, prefetches data in the frequently accessed area of the hard disk device with reference to the access frequency management table, and stores the prefetched data in a buffer provided in the memory Means,
The access frequency management means executes an access to the buffer when an access request from the OS to the hard disk device is for an area with a high access frequency. The above hardware is equipped with a multi-core CPU,
The hypervisor has the prefetching means for each core,
2. The information processing apparatus according to claim 1, wherein the memory includes the prefetch buffer for each core.

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