JP2013110347A - Manufacturing method of wiring board with through electrode - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a glass interposer having fine through-electrode holes and high thermal conductivity.
At least a step of forming a metal projection 7 on a metal support substrate 1 and a step of covering the metal support substrate 1 and the metal projection 7 with an insulating layer 5 containing SiO ₂ as a main component. Removing the insulating layer 5 covering the metal protrusion 7 to expose the surface of the metal protrusion 7; providing the first conductor layer 4 on the insulating layer 5 and the exposed metal protrusion 7; And a step of forming a pattern including a metal protrusion on the first conductor layer 4 in this order.
[Selection] Figure 2

Description

  The present invention relates to a wiring board on which a semiconductor element is mounted, and more particularly to a method for manufacturing a wiring board with a through electrode using a glass-based material as a base material.

  Semiconductor devices such as various memories, CMOS, and CPU manufactured by the wafer process have terminals for electrical connection. The pitch of the connection terminals and the pitch of the connection portion on the printed circuit board side to be electrically connected to the semiconductor element differ from each other by several to several tens of times. Therefore, when the semiconductor element and the printed board are to be electrically connected, an intermediary board (semiconductor element mounting board) for pitch conversion called an interposer is used. A semiconductor element is mounted on one surface of the interposer and connected to the printed circuit board on the other surface or the periphery of the substrate.

  As an interposer for mounting semiconductor elements, in addition to conventional organic substrates and organic build-up substrates, in recent years, research has been actively conducted on interposers using silicon or glass as a base material as high-end interposers.

  A silicon interposer using silicon as a base material has a small difference in coefficient of thermal expansion between the chip and the base material, and fine wiring can be formed by adopting a wafer process. Furthermore, by using a technique called TSV (Through-SiliconVia) for forming a through electrode on a silicon substrate, excellent electrical characteristics such as an increase in signal transmission speed are expected.

  However, since silicon is a semiconductor and conductive, it is necessary to interpose an insulating layer between the through wiring and the silicon substrate. In a high-speed circuit, a parasitic element is generated between the silicon and the wiring layer, which degrades the signal waveform. There is a problem of end. Moreover, although the transmission characteristic of the through wiring is improved by using high resistance silicon for the substrate, there is a problem that the cost is increased.

  On the other hand, in a glass interposer using glass as a base material, since the base material itself is an insulating material, there is no concern about the problems described above, and an interposer with excellent electrical characteristics is expected. However, a major drawback of the glass interposer lies in workability, and there is a problem that it is difficult to form fine through-holes for through electrodes, especially compared to silicon interposers. Furthermore, since the thermal conductivity of the substrate is inferior to that of the silicon interposer, ensuring reliability is also an important issue.

Japanese Patent Laid-Open No. 2003-249606 JP 2004-31835 A

Journal of Japan Institute of Electronics Packaging Vol.14, No.5, Aug.2011, P344, Susumu Honda, “Trends in Si / Glass Interposers and Passive Devices” 25th Electronics Packaging Society Spring Lecture Meeting Yutaka Onezawa, “3D mounting, high airtightness, glass wafer with through via“ SCHOTT HermeS ””, 2011 (CD-ROM version)

  The present invention has been made in view of the above problems, and has an object to provide a method for manufacturing a glass interposer having fine through-electrode holes and a high heat dissipation effect.

The invention described in claim 1 for achieving the above object includes at least a step of forming a metal projection on a metal support substrate, and the metal support substrate and the metal projection are composed mainly of SiO ₂ . A step of covering with the insulating layer, a step of removing the insulating layer covering the metal convex portion and exposing the surface of the metal convex portion, and a step of providing a first conductor layer on the insulating layer and the exposed metal convex portion And a step of forming a pattern including a metal protrusion on the first conductor layer in this order.

The invention according to claim 2 is a process of coating the patterned first conductor layer with an insulating layer mainly composed of SiO _{2 following the} step of forming the pattern according to claim 1, and an insulating layer. Removing the first conductor layer surface, providing a second conductor layer, forming a pattern on the metal protrusion of the second conductor layer, and forming the second conductor layer on SiO 2 A step of covering with an insulating layer containing ₂ as a main component, a step of removing the insulating layer to expose the patterned second conductor layer surface, a step of providing a third conductor layer, and a third conductor layer And a step of forming a pattern in this order.

  The invention according to claim 3 is characterized in that the pattern formation of the conductor layer includes the formation of a heat dissipation substrate in addition to the circuit wiring. The method for manufacturing a wiring substrate with a through electrode according to claim 1 or 2 It is what.

  The invention according to claim 4 is characterized in that the insulating layer is formed by using a sol-gel method which is a wet method, and the wiring with a through electrode according to any one of claims 1 to 3 This is a method for manufacturing a substrate.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the metal convex portion and the first, second, and third conductor layers are formed using a plating method. The manufacturing method of the wiring substrate with a through electrode as described in the item.

  The invention according to claim 6 includes a step of forming a pattern including a metal convex portion on the metal support substrate, according to any one of claims 1 to 5. This is a method for manufacturing a wiring board with electrodes.

  The invention according to claim 7 is a method for manufacturing a wiring board with through electrodes, wherein the method for manufacturing a wiring board with through electrodes according to any one of claims 2 to 6 is repeated. Is

According to the first aspect of the invention, unlike the conventional method, the base electrode portion is formed of SiO ₂ which is the main component of glass after the through electrode is formed in advance. For this reason, a fine drilling process becomes unnecessary in a brittle glass substrate, and a wiring substrate with a through electrode having excellent electrical characteristics can be produced at low cost.

  The invention according to claim 2 and claim 7 is a wiring board or a multilayer wiring board by repeating the processing steps of the wiring board, and is capable of mounting a multi-pin semiconductor element and is electrically Does not damage the characteristics. Moreover, since a metal with high thermal conductivity can be taken in as a heat dissipation substrate, a highly reliable interposer can be made.

  The invention according to claim 3 is a method in which metal pieces having high thermal conductivity are dispersed and arranged on or inside the insulating layer as a heat radiating base material. effective. This effect is particularly expected for multilayer wiring boards.

According to the invention described in claim 4, the insulating layer produced by the sol-gel method has a larger number of holes in the interior than glass made by melting and quenching a raw material containing SiO ₂ , which is a normal production method, at a high temperature. It will have a structure. Since the inside of the hole is filled with air, the dielectric constant of the insulating layer is further reduced. As a result, it is possible to manufacture a glass interposer with excellent transmission characteristics that is not affected by parasitic elements.

  The invention according to claim 5 is performed by a chemical method using plating as a method of forming the metal protrusion and the conductor layer. For example, an existing method can be used, such as patterning a resist by photolithography and selectively forming a metal protrusion using plating. By this wet method using plating, a large-scale apparatus is not required and a large amount of processing can be performed at one time, and fine processing that is cheaper and shorter in tact than physical processing using a laser or the like is possible.

  The invention according to claim 7 is that the metal support substrate also needs to be finally patterned and separated as an electrode. When to process, there is room for various choices depending on the single layer or multilayer of the wiring structure.

It is a conceptual diagram of the cross-sectional view which shows the structure of the wiring board with a penetration electrode which concerns on this invention. (A) Without heat dissipation board, (b) With heat dissipation board. It is process drawing of the cross-sectional view explaining the manufacturing method of the wiring board with a penetration electrode which becomes this invention. It is process drawing of a sectional view explaining the manufacturing method of the wiring board with a penetration electrode concerning the present invention, and is the case where it expands when the heat dissipation board is built in.

The present invention employs a process in which a fine through electrode is formed on a base substrate before a base material in which the through electrode is accommodated. Hereinafter, it demonstrates in detail based on drawing.
FIG. 1A shows a cross-sectional structure of the wiring board according to the present invention without a heat radiating board, and FIG. 1B shows a cross-sectional structure with the heat radiating board. FIGS. The manufacturing process diagram of the substrate is shown.

  First, a metal plate to be the support substrate 1 is prepared (FIG. 2A), and a plurality of metal projections 7 are formed thereon (FIG. 2B). Plating is used as a means for forming. After a resist is applied to the support substrate 1, exposure and development are performed using a mask to form an opening in a portion where the convex portion is grown. Thereafter, a portion where the metal is thickly formed in the opening by electroless plating is used as the metal convex portion 7, and then unnecessary resist is removed.

  Hereinafter, in principle, the through electrode 3 indicates a completed metal convex portion 7 in which a wiring pattern is laminated on the metal convex portion 7 or a state in which these are laminated, but there is a case where they are not distinguished. The support substrate 1 is preferably copper in view of conductivity and cost.

Next, the insulating layer 5 is formed on the support substrate 1 provided with the metal protrusions 7 (FIG. 2C). As a forming means, a sol-gel method which is a wet method is used. First, a sol solution of a precursor containing a metal alkoxide is stirred and gelled by a hydrolysis / condensation reaction. The precursor solution is supplied to the entire surface by immersing and pulling up the substrate in this solution. Thereafter, unnecessary components such as a solvent are removed by drying, and the insulating layer 5 is formed on the substrate. At this time, if the gap between the metal protrusions 7 cannot be completely covered with the insulating layer 5, the insulating layer 5 is formed until the required thickness is obtained by repeatedly dipping and drying the substrate (FIG. 2 (c)).

The sol-gel method is a technique in which a sol of a precursor solution containing a metal alkoxide, alcohol, or the like is precipitated through a gel state by hydrolysis / condensation reaction. A typical metal alkoxide used in the sol-gel method is Si (OC ₂ H ₅ ) ₄ (TEOS), and the same SiO ₂ insulating layer as the main component of glass is formed by hydrolysis and condensation reaction of TEOS. It is possible.
In addition, when a dry process such as sputtering or CVD is used as a method for forming the insulating layer, the insulating layer is formed on the concave and side surfaces uniformly because the insulating layer forming speed on the metal convex and concave portions is different. difficult. However, since the sol-gel method uses a solution, a raw material can be easily supplied even in a portion that is difficult to form by a dry process, and a uniform insulating layer can be formed.

  Next, the insulating layer 5 covering the metal protrusion 7 is polished to expose the outermost surface of the metal protrusion 7 from the insulating layer 5 (FIG. 2 (d)). The method for polishing the insulating layer is not limited as long as the outermost surface of the metal protrusion can be exposed, but the polishing surface is preferably horizontal. Examples include physical polishing, chemical polishing, or a combination of both. By forming the conductor layer again on the exposed surface, the conductor layer of the base substrate and the conductor layer formed by plating can be made conductive.

  And the 1st conductor layer 4 is formed on the insulating layer 5 which the top part of the metal convex part 7 exposed (FIG.2 (e)). Plating is used as a means for forming. First, an organic monomolecular layer is formed on the insulating layer 5 using a silane coupling agent to adsorb a metal catalyst. Electroless plating is performed using this catalyst as a growth nucleus to form the conductor layer 4. The metal used for forming the conductor layer is preferably the same material as the metal used for the underlying support substrate 1. This is because the contact resistance is increased and the electrical characteristics are affected by the bonding of different metals.

The conductor layer 4 is formed by plating in the same manner as the metal convex portion 7, so that a cheap and short process is possible. There are various catalysts used for electroless plating, but typical ones include palladium and platinum. Examples of the catalyst providing method include a method in which a finely divided metal catalyst is dispersed in a solution and uniformly applied, or an organic monomolecular layer having an electron donating group is bonded to SiO ₂ which is a main component of an insulating layer, and this electron donating group is bonded. A method of adsorbing the ionized metal catalyst on the top is conceivable. At this time, the metal ion adsorbed on the organic monomolecular layer becomes a metal by performing a reduction treatment, and can be used as a catalyst. The electron donating group of the silane coupling agent may be an amino group or a thiol group, but is not limited thereto.

  Next, a circuit pattern is formed on the formed conductor layer 4. First, a resist is applied to the conductor layer 4, and exposure and development are performed using a mask to pattern the resist. The patterning is performed so that the resist remains on the portion where the top of the metal convex portion 7 exists and the portion used as the heat dissipation substrate 2. Thereafter, unnecessary portions are removed by etching, and finally the resist is removed. At this time, an isolated pattern is formed so that the circuit pattern 6 and the heat dissipation substrate 2 do not conduct.

  Examples of the etching method include, but are not limited to, wet etching using ferric chloride when the conductor layer is copper.

The formation of the circuit pattern 6 on the conductor layer 4 requires that the conductor layer be patterned so as to be in contact with at least the exposed top of the metal protrusion 7. That is, the circuit pattern 6 includes the metal protrusion 7 inside. Further, by forming a circuit pattern 6 (which serves as a connection terminal) having a predetermined area on the metal protrusion 7 exposed from the insulating layer 5, the through electrode 3 that connects the front and back as an interposer at the shortest distance is formed. Is possible. As a result, the wiring length is shortened, and a wiring board having high-speed signal transmission characteristics can be formed.

The pattern formation of the conductor layer 4 is performed simultaneously or separately with the pattern formation 6 of the first conductor layer 4 in the case where the later-described multilayering is not performed. There is a need. In the case of multilayering, it may be turned later.
This completes the wiring board with through electrodes shown in FIG. 1 (a) or FIG. 2 (f), which is the simplest configuration. In FIG. 1A, the pattern formation of the heat dissipation substrate 2 and the support substrate 1 is omitted.

Then, when the above-described procedure is repeated on the substrate on which the pattern has been formed, a wiring substrate with a through electrode (FIG. 1B) having the heat dissipation substrate 2 inside the insulating layer 5 can be obtained.
That is, the patterned first conductor layer is covered with the insulating layer 12 containing SiO ₂ as a main component (FIG. 3G). The expression “coating” here is preferable if the gaps between the patterns can be substantially flush with the insulating layer 12, but in practice, the sol is applied, and after the reaction drying, not only the gaps are buried but also on the conductor. May be covered. In this case, polishing is performed.

Next, the second conductor layer 13 is provided by an electroless plating method (FIG. 3 (h)), and the metal protrusions 14 are formed on the conductor layer 13 (FIG. 3 (i)). Again, the gap between the second conductor layers is filled with the insulating layer 15 mainly composed of SiO ₂ , and then the insulating layer 15 on the surface of the metal convex portion 7 is removed (FIG. 3 (j)).

  Next, a third conductor layer is provided by an electroless plating method (not shown), and finally the base and the conductor layer are processed into the same photolithography to form a predetermined wiring pattern 6. Through this process, a wiring board (FIG. 1B) having the through electrode 3 and incorporating the heat dissipation board 2 into the insulating layer 12 can be manufactured (FIG. 3K). By repeating the above process, a multilayer wiring board can be manufactured.

Examples of the present invention are shown below.
A 100 μm copper plate was used as the support substrate 1, a 50 μm thick resist was formed thereon by spin coating, and exposure and development were performed using a photomask on which a predetermined pattern was drawn. And the opening part in which the resist was not formed was thickened by electroless copper plating by 50 um, and the metal convex part 7 was formed. Thereafter, unnecessary resist was removed using a stripping solution. The protrusions 7 formed at this time had a cylindrical structure with a diameter of 30 μm and a height of 50 μm, and had a pattern in which the distance between adjacent protrusions was 150 μm (FIG. 2B).

An insulating layer 5 was formed on the substrate having the metal protrusions 7 by a sol-gel method. The precursor solution of the sol-gel method was adjusted to pH 2 by adding hydrochloric acid to a mixture of TEOS, ethanol, and water at a molar ratio of 1:10:10, and the substrate was immersed in these solutions. Thereafter, in order to dry the substrate, the substrate was heated to 100 ° C., the residual solvent was removed, and the insulating layer 5 containing SiO ₂ as a main component was formed (FIG. 2C).

  The formed insulating layer 5 was polished using a polishing agent mainly composed of a diamond grindstone, and a copper surface having a diameter of 30 μm was exposed from the insulating layer, although not clearly shown in the figure (FIG. 2 (d)).

  Thereafter, a solution in which a silane coupling agent having an amino group was dissolved in toluene was prepared, and an organic monomolecular film was formed on the insulating layer by immersing the substrate at 60 ° C. for 30 minutes.

Then, the substrate was immersed in a solution containing 0.2 g / l of palladium chloride for 30 minutes to give palladium ions as a catalyst. The substrate to which the catalyst was adhered was immersed in a solution containing 0.15 mol / l dimethylamine borane at 60 ° C. for 1 min to reduce palladium ions. A first conductor layer 4 having a thickness of 50 μm was formed by electroless copper plating using the reduced palladium as a nucleus (FIG. 2 (e)).

  A resist was applied to the conductor layer 4, and exposure and development were performed using a photomask on which a predetermined pattern was drawn. And the part in which the resist was not formed was etched with ferric chloride, and the unnecessary conductor layer was removed. The pattern formed at this time had a columnar structure with a diameter of 30 μm and a height of 50 μm, the distance between the patterns was 150 μm, and alignment was performed so as to contact the convex portion of the lower conductor layer. In addition, an isolated pattern of a conductor layer having a diameter of 100 μm and a height of 50 μm was laid between the cylindrical isolated patterns as the heat dissipation substrate 2 (FIG. 2 (f)).

  The processing steps when the heat dissipation substrate 2 is provided in the middle of the insulating layer 5 were completed by repeatedly forming the insulating layer and the conductor layer described above (FIGS. 3 (g) to (k)). The multilayer wiring board can be manufactured by repeating the steps shown in FIGS.

  Finally, a wiring having a thickness of 25 μm was formed on the uppermost portion and the conductor layer of the support substrate 1 by photolithography (not shown).

  When a coplanar transmission line was formed on the fabricated wiring board and the transmission characteristics were evaluated, it was found that there was almost no transmission loss even in the high frequency band (20 GHz).

<Comparative example>
Comparative examples of the present invention are shown below.
Table 1 shows a comparison with the specifications of the glass wafer with through electrodes described in Non-Patent Document 2.

  By these, the manufacturing method of the wiring board with a penetration electrode with the penetration electrode which was excellent in workability and the electrical property in which the board | substrate which is this invention has the same main component as glass was able to be shown.

  The above-described invention can be used as a method of manufacturing an interposer that can cope with higher functionality and higher speed of electronic equipment in three-dimensional mounting.

1 ... Support substrate (metal)
2 ... Heat dissipation substrate 3 ... Through electrode 4 ... Conductor layer (first conductor layer)
DESCRIPTION OF SYMBOLS 5 ... Insulating layer 6 ... Circuit pattern 7 ... Metal convex part 8 ... Insulating layer 10 ... Through-electrode 12 ... Insulating layer 13 ... Conductor layer (2nd conductor layer)
14 ... Metal convex part 15 ... Insulating layer

Claims (7)

At least, it is covering and forming a metal protrusion on a metal support substrate, a step of coating with an insulating layer to the supporting substrate and the metal protrusions metallic main component is SiO _2, the metallic protrusions insulation Removing the layer to expose the surface of the metal protrusion, providing the first conductor layer on the insulating layer and the exposed metal protrusion, and forming a pattern including the metal protrusion on the first conductor layer. And a process for producing a wiring board with a through electrode. A step of coating the patterned first conductor layer with an insulating layer mainly composed of SiO _{2 following the} step of performing pattern formation according to claim 1, and removing the insulating layer to form a surface of the first conductor layer A step of exposing, a step of providing a second conductor layer, a step of forming a pattern on the metal convex portion of the second conductor layer, and an insulating layer containing SiO ₂ as a main component. A step of covering, a step of removing the insulating layer to expose the patterned second conductor layer surface, a step of providing a third conductor layer, and a step of forming a pattern on the third conductor layer. A method for manufacturing a wiring substrate with a through electrode, comprising the steps in this order.   The method for manufacturing a wiring substrate with a through electrode according to claim 1, wherein the pattern formation of the conductor layer includes heat dissipation substrate formation in addition to circuit wiring.   The said insulating layer is formed using the sol-gel method which is a wet method, The manufacturing method of the wiring board with a penetration electrode of any one of Claims 1-3 characterized by the above-mentioned.   5. The wiring substrate with a through electrode according to claim 1, wherein the metal protrusion and the first, second, and third conductor layers are formed using a plating method. Manufacturing method.   6. The method for manufacturing a wiring substrate with a through electrode according to claim 1, further comprising a step of forming a pattern including a metal protrusion on the metal support substrate.   The manufacturing method of the wiring board with a penetration electrode of any one of Claims 2-6 is repeated, The manufacturing method of the wiring board with a penetration electrode characterized by the above-mentioned.

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