JP2013198063A - Distortion compensation circuit and distortion compensation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a distortion compensation circuit and a distortion compensation method capable of improving the performance of distortion compensation without increasing the cost and power consumption even when the sample frequency is small.
In a distortion compensation circuit provided at an input stage of an amplifier, an input-side oversampling filter 10 multiplies an input signal sampled at a frequency of a DAC 91 by a coefficient based on a filter characteristic to artificially exceed the input signal. Sampled sample points are generated and output at each sample timing. A plurality of DPD processing units 100 to 103 distort the sample points at each sample timing into DPD data, and output side oversampling filters 60 to 63 respectively A DPD result obtained by multiplying the DPD data of the sample timing by a filter coefficient of a specific sample timing and returning to the timing of the DAC 91 is output, and the adders 70 to 73 weight each DPD result and add it by the adder 80. A distortion compensation circuit and a distortion compensation method are provided.
[Selection] Figure 1

Description

  The present invention relates to a distortion compensation circuit and a distortion compensation method in an amplifying apparatus, and more particularly to a distortion compensation circuit and a distortion compensation capable of improving the performance of distortion compensation without increasing cost and power consumption even when the sampling frequency is small. Regarding the method.

[Description of Prior Art]
In an amplifying apparatus used in a wireless communication system, non-linear distortion occurs during amplification, and there is a technique for compensating for this non-linear distortion with a DPD (Digital Pre-Distortion) circuit.

[Conventional DPD circuit: FIG. 6]
A conventional DPD circuit will be described with reference to FIG. FIG. 6 is a block diagram showing a mounting example of a conventional DPD circuit.
As shown in FIG. 6, an amplifying apparatus including a conventional DPD circuit includes a DPD circuit 1 ′, a DAC (Digital-Analogue Converter) 91, an amplifier 92, and an ADC (Analogue-Digital Converter) 93. Yes.

The DPD circuit 1 ′ applies a distortion that is a reverse characteristic of the nonlinear distortion generated by the amplifier 92 to the transmission signal.
The DAC 91 performs digital-analog conversion on the output of the DPD circuit 1 '.
The amplifier 92 amplifies the signal to which the reverse characteristic is added. The amplified signal is output from the antenna and branched and fed back.
The ADC 93 performs analog-digital conversion on the feedback signal.

  The DPD circuit 1 ′ includes a delay circuit 2, an envelope calculation unit 3, an orthogonal demodulation unit 4, an LUT (Look Up Table) coefficient calculation unit 5, a delay circuit 6, an LUT coefficient setting unit 7, Multipliers 8a and 8b are provided.

The delay circuit 2 delays the I component and Q component of the input transmission signal by a predetermined time.
The envelope calculation unit 3 obtains an envelope (√ (I ² + Q ² )) of the transmission signal.
The quadrature demodulator 4 performs quadrature demodulation on the output signal from the ADC 93.
The delay circuit 6 delays the input signal in order to match the timing with the feedback signal.

The LUT coefficient calculation unit 5 compares the orthogonally demodulated feedback signal with the delayed transmission signal, obtains the optimum LUT coefficient by calculation, and updates the LUT of the LUT coefficient setting unit 7.
The LUT coefficient setting unit 7 refers to the updated LUT and outputs a coefficient corresponding to the envelope output from the envelope calculation unit 3.
Multipliers 8a and 8b multiply the delayed I signal / I component of the transmission signal by the coefficient output from LUT coefficient setting unit 7 to give distortion, and output the result from DPD circuit 1 '.
A configuration including the delay circuit 2, the envelope calculation unit 3, the LUT coefficient setting unit 7, and the multipliers 8a and 8b is referred to as a DPD processing unit.

[Amplifier Operation: FIG. 6]
The operation of the amplification device having the above configuration will be briefly described with reference to FIG.
The I component and Q component of the input transmission signal are branched, and one of the branched signals is delayed by the delay circuit 2 and multiplied by a coefficient by the multipliers 8a and 8b. It is added and output to the DAC 91.

  The output of the DPD1 circuit ′ is DA-converted by the DAC 91, input to the amplifier 92 and amplified, and the amplified signal is wirelessly transmitted. The non-linear distortion generated during amplification by the amplifier 92 is canceled out by the distortion added by the DPD circuit 1 ', and an amplified signal without distortion is obtained.

  The output of the amplifier 92 is branched to become a feedback signal, converted into a digital signal by the ADC 93 and input to the DPD circuit 1 ′, and orthogonally demodulated by the orthogonal demodulator 4 to extract the I component and Q component.

  On the other hand, the branched input signal is further branched, one of which is delayed by the delay circuit 6 in order to synchronize with the feedback signal by the LUT coefficient calculation unit 5, and the feedback signal and the input signal by the LUT coefficient calculation unit 5 Based on the difference between them, an operation for obtaining an optimum coefficient is performed, and the coefficient of the LUT is updated.

The other of the branched input signals is obtained as an envelope by the envelope calculation unit 3, and a coefficient corresponding to the envelope is read from the LUT by the LUT coefficient setting unit 7, and multipliers 8 a and 8 b. And an inverse characteristic based on a new coefficient is added to the transmission signal.
In this way, the operation of the amplifying apparatus including the conventional DPD circuit is performed.

[Relationship between sample frequency and distortion: Fig. 7]
Next, the relationship between the sampling frequency (sampling frequency) and the distortion in the amplification device having the above configuration will be described with reference to FIG. 7A and 7B are explanatory diagrams illustrating an example of frequency characteristics of the amplifier output.
When the original signal shown in FIG. 7A is amplified by an amplifier, when a DPD circuit is not used (no DPD), a distortion component is included in the amplifier output.
In the case of (a), since the distortion components are all included in the frequency range that can be acquired at the sampling frequency in DPD (sampling frequency of DAC 91 and ADC 93), when the DPD circuit is used (with DPD) The distortion component can be sufficiently compensated, and the same characteristics as the original signal can be obtained.

On the other hand, as shown in FIG. 7B, when the distortion band of the amplifier reaches a range exceeding the sample frequency, the DPD cannot sufficiently compensate for the distortion, and the distortion remains in the amplifier output even when the DPD is used. End up.
Increasing the sampling frequency of the DPD increases the frequency range that can be compensated, and sufficient distortion compensation can be realized. However, the calculation processing speed must be increased, and the cost and power consumption can be reduced by changing the device configuration and device. It will increase.

[Oversampling: Fig. 8]
Here, an example of predistortion when the sampling frequency is increased and oversampling is performed will be described with reference to FIG.
Here, a case will be described in which if the sampling frequency is quadrupled, distortion can be compensated within the sampling frequency.
FIGS. 8A and 8B are explanatory diagrams showing signal examples of DPD circuit output and ADC output depending on the presence or absence of oversampling, where FIG. 8A shows an example of sampling of the original signal, and FIG.

  8 shows the distortion in the frequency domain shown in FIG. 7 on the time axis. FIG. 8A shows examples of sample data when the original signal is not oversampled and when it is oversampled four times. Yes. With 4 times oversampling, 4 times more sample data is obtained than without oversampling.

When DPD is performed using the sampling data of FIG. 8A, as shown in FIG. 8B, the DPD circuit output without oversampling is compared with the DPD circuit output with 4 times oversampled data. Then, the same DPD result is obtained at the same sample timing (sample point).
However, when the DAC output is compared, the number of sample points is different. Therefore, the output waveform is different between no oversampling and four times oversampling, and distortion with different characteristics is added.

[Difference in amplifier output with and without oversampling: Fig. 9]
Next, an amplifier output when the DAC output of FIG. 8 is amplified by an amplifier will be described with reference to FIG. FIG. 9 is an explanatory diagram illustrating a signal example of the amplifier output when the DAC output of FIG. 8 is amplified by the amplifier.
As shown in FIG. 9, when oversampling is performed four times, an amplifier output (ideal waveform) faithful to the original signal can be obtained, but when there is no oversampling, distortion components remain in the amplifier output. As a result, a waveform different from the original signal is output.

  That is, in the case of 4 times oversampling, the DAC output signal shown in FIG. 8B sufficiently compensates for distortion generated in the amplifier. In the case of no oversampling, FIG. It can be seen that distortion compensation is not sufficient for the DAC output. This indicates that the distortion of the high frequency component cannot be accurately compensated because the distortion band is larger than the sample frequency.

[Differences due to sample timing: Fig. 10]
Next, the difference in distortion compensation depending on the sampling timing will be described with reference to FIG. FIG. 10 is an explanatory diagram showing examples of DPD output, DAC output, and amplifier output at different sample timings.
FIG. 10A shows the DPD circuit output and the DAC output at two types of sampling timings when there is no oversampling, and for comparison, the DPD circuit output and the DAC output when oversampling is performed four times. Is shown.

The DPD output and the DAC output of “no oversampling” in FIG. 10A are the same signals as the DPD output and the DAC output without oversampling shown in FIG. This sampling timing is set to a timing without deviation.
A thick solid line indicates a case where the sample timing is shifted by ½ timing from the timing without deviation. Since the 1/2 timing corresponds to 2 samples of 4 times oversampling, it is indicated as “2 sample deviation”.

  Further, the DPD output and the DAC output in the case of oversampling 4 times are the same signals as the DPD output and the DAC output in the case of 4 times oversampling shown in FIG. It is an added signal.

  As shown in FIG. 10 (a), when there is no oversampling, the waveform is different from the ideal 4-times oversampling DAC output regardless of whether there is any deviation, and there is no deviation. And the waveform is different between two samples. That is, a DPD output and a DAC output signal to which different reverse characteristics are added due to a difference in sampling timing.

Further, as shown in FIG. 10B, even in the amplifier output obtained by amplifying the signal of FIG. 10A, the distortion remains in the case of the deviation of 2 samples compared to the ideal case of 4 times oversampling. Furthermore, it can be seen that there is still a distortion different from the case without deviation.
Thus, in DPD, distortion compensation is performed by giving different reverse characteristics depending on the sampling timing.

[Related technologies]
As techniques relating to distortion compensation, Japanese Patent Laid-Open No. 2002-077685 “Distortion Compensation Device” (Hitachi Kokusai Electric Co., Ltd., Patent Document 1), Japanese Patent Laid-Open No. 2003-092518 “Distortion Compensation Device” (Hitachi International Corporation) Electric, Patent Document 2).

Patent Document 1 describes that in a distortion compensation apparatus, the timing for controlling the distortion generated by the distortion generating means is controlled so that the distortion generated by the amplifier is largely compensated.
Patent Document 2 describes that in a distortion compensation device, an input signal is divided into a plurality of frequency bands, and distortion compensation is performed for each band.

JP 2002-077675 JP 2003-092518 A

  However, in the conventional amplification device using the DPD circuit, when the distortion compensation sample frequency of the DPD circuit determined by the ADC and DAC is smaller than the distortion band of the amplifier, sufficient distortion compensation cannot be performed. In addition, if the device is changed to increase the sampling frequency, there is a problem that cost and power consumption increase.

  In Patent Documents 1 and 2, the input side oversampling filter multiplies the filter coefficient to generate pseudo-oversampled sample points, and DPD data is obtained based on them to obtain the output side oversampling. It is not described that a filter is used to return to the basis of the timing of each DPD data, and weighting is performed.

  The present invention has been made in view of the above circumstances, and provides a distortion compensation circuit and a distortion compensation method capable of improving the performance of distortion compensation without increasing cost and power consumption even when the sampling frequency is small. The purpose is to provide.

  The present invention for solving the problems of the above-described conventional example is a distortion compensation circuit that is provided in an input stage of an amplifier and compensates for distortion generated by the amplifier. The input signal sampled at a specific frequency has a filter characteristic. Based on the input side oversampling filter that multiplies a coefficient of oversampling timing of a frequency higher than a specific frequency to generate pseudo oversampled sample data, and outputs the sample data at each sample timing, A plurality of predistortion units that output the predistortion data by giving the inverse characteristics of distortion generated by the amplifier to each sample data according to the sample data envelope of the sample timing, and corresponding to each predistortion unit. In each predistortion data, based on the filter characteristics, The output oversampling filter that multiplies a constant oversampling timing coefficient to convert it to a specific frequency sample timing, and the output data of each output oversampling filter is weighted, and the result of the weighting operation is synthesized. And a synthesizing unit.

  Further, the present invention is characterized in that, in the distortion compensation circuit, the combining unit performs equal weighting on the output data of all output side oversampling filters and outputs an average value.

  Further, the present invention is characterized in that, in the distortion compensation circuit, the synthesis unit selects and weights output data of a specific output-side oversampling filter.

  The present invention for solving the problems of the above conventional example is a distortion compensation method in a distortion compensation circuit that is provided in an input stage of an amplifier and compensates for distortion generated by the amplifier, wherein the distortion compensation circuit has a specific frequency. Based on the filter characteristics, multiply the oversample timing coefficient of a frequency higher than a specific frequency to generate pseudo oversampled sample data. The predistortion data is generated by giving the inverse characteristics of the distortion generated by the amplifier to the sample data, and each predistortion data is multiplied by a specific oversample timing coefficient based on the filter characteristics, and converted to a sample timing of a specific frequency. The predistortion data whose timing is converted is weighted. It is characterized by combining and outputting Te.

  According to the present invention, a distortion compensation circuit is provided at an input stage of an amplifier and compensates for distortion generated by the amplifier, and an input signal sampled at a specific frequency is higher than the specific frequency based on a filter characteristic. Multiply frequency oversample timing coefficients to generate pseudo-oversampled sample data, and input oversampling filter that outputs the sample data at each sample timing, and the sample data envelope at each sample timing In response, each sample data is provided corresponding to each predistortion unit and multiple predistortion units that output the predistortion data by giving the inverse characteristics of the distortion generated by the amplifier to each sample data. Based on specific oversample timing An output side oversampling filter that multiplies the output coefficients of the specific frequency and converts the output data of each output side oversampling filter, and a synthesis unit that synthesizes the weighted result. Therefore, predistortion data is generated based on a plurality of sample data at different sample timings that are artificially generated by the filter on the input side, and those of the original sampling frequency are generated by the filter on the output side. By synthesizing with appropriate weighting in accordance with the timing, there is an effect that the accuracy of distortion compensation can be improved without increasing cost and power consumption even if the sample frequency is small.

  Further, according to the present invention, since the synthesizer is the distortion compensation circuit in which the synthesizer selects and weights the output data of the specific output-side oversampling filter, the synthesizer is appropriately configured according to the distortion characteristics of the amplifier. By selecting the appropriate output data and performing weighting, it is possible to generate distortion that is closer to the inverse characteristics of the distortion generated by the amplifier and give it to the input signal, and to facilitate adjustment of distortion compensation There is.

  According to the present invention, there is also provided a distortion compensation method in a distortion compensation circuit that is provided at an input stage of an amplifier and compensates for distortion generated by the amplifier, wherein the distortion compensation circuit inputs a signal sampled at a specific frequency. Then, based on the filter characteristics, pseudo oversampled sample data is generated by multiplying the oversample timing coefficient higher than the specific frequency, and the sample data is generated by the amplifier at each sample timing. Predistortion data is generated by giving the inverse characteristics of the distortion to be converted, and each predistortion data is multiplied by a specific oversample timing coefficient based on the filter characteristics, and converted to a sample timing of a specific frequency, and the timing is converted. Distortion output by combining each predistortion data with weighting Since the 償方 method, even sample frequency is reduced, without increasing the cost and power consumption, there is an effect that it is possible to improve the accuracy of distortion compensation.

It is a block diagram which shows the example of mounting of the DPD circuit which concerns on embodiment of this invention. FIG. 6 is an explanatory diagram illustrating an example of coefficients of a 4 × oversampling filter. It is explanatory drawing which shows the oversample data of a DPD output signal. It is explanatory drawing which shows the example of an output signal of this DPD circuit. It is explanatory drawing which shows the example of an output signal of the amplifier 92 using this DPD circuit. It is a block diagram which shows the example of mounting of the conventional DPD circuit. It is explanatory drawing which shows the frequency characteristic example of amplifier output. It is explanatory drawing which shows the signal example of the DPD circuit output by the presence or absence of oversampling, and an ADC output. It is explanatory drawing which shows the signal example of an amplifier output at the time of amplifying the DAC output of FIG. 8 with an amplifier. It is explanatory drawing which shows the example of the DPD output in a different sample timing, DAC output, and an amplifier output.

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
The distortion compensation circuit according to the embodiment of the present invention multiplies an input signal sampled at a DAC sampling frequency by a coefficient based on a filter characteristic, thereby obtaining a pseudo-oversampled sampling point at a higher frequency. An input-side oversampling filter that generates and outputs sample points at each sample timing, a DPD processing unit that is connected in parallel and refers to an LUT that is updated based on a feedback signal, and applies distortion to each sample point; A plurality of output-side oversampling filters that multiply the data output from each DPD processing unit by a specific sample timing coefficient based on the filter coefficient and output the data in accordance with the timing of the original DAC sample frequency, and each output Appropriate weighting of output from side oversampling filter And generating a distortion compensation data based on the pseudo-oversampled sample points at different timings, and returning the timing of each distortion compensation data to the original timing by the output side oversampling filter These are weighted and synthesized, and the accuracy of distortion compensation can be improved without changing the calculation speed of the DPD processing unit and without increasing the cost and power consumption.

[DPD Circuit According to Embodiment: FIG. 1]
A DPD circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a mounting example of a DPD circuit according to an embodiment of the present invention.
As shown in FIG. 10, the DPD circuit according to the embodiment of the present invention (ADCD circuit) uses the fact that distortion compensation is performed by giving different inverse characteristics depending on the difference in sampling timing. And generating the pseudo oversampled signal using the oversampling filter in the DPD circuit without changing the DAC rate, and combining the inverse characteristics obtained at different oversampling timings with appropriate weighting. Thus, more accurate distortion compensation is realized.
In the DPD circuit, a case where the predistortion timing is shifted by using a 4 × oversample filter will be described as an example.

As shown in FIG. 1, the amplifying apparatus as an example of mounting the DPD circuit includes a DPD circuit 1, a DAC 91, an amplifier 92, and an ADC 93.
The DAC 91, the amplifier 92, and the ADC 93 are the same as the conventional one shown in FIG.

A characteristic part of the DPD circuit 1 will be described.
The DPD circuit 1 performs predistortion in parallel on the sample points generated at the different oversampling timings generated by the filter, synthesizes the results, and outputs them to the DAC 91 to increase the speed of the arithmetic processing. Therefore, the accuracy of distortion compensation is improved.
In the present DPD circuit, a DPD result is synthesized at four timings by using a 4 × oversampling filter.

  As shown in FIG. 1, this DPD circuit 1 includes a quadrature demodulator 4, an LUT coefficient calculator 5, and a delay circuit 6 as the same parts as in the prior art. 4 × oversampling filter 10, DPD processing units 100 to 103 similar to the conventional one connected in parallel, and output side 4 × oversampling filters 60 to 63 provided at the output stage of each DPD processing unit 100 to 103. , Multipliers 70 to 73 provided at output stages of the output side 4 × oversampling filters 60 to 63, and an adder 80.

The quadrature demodulation unit 4 performs quadrature demodulation on the feedback signal and outputs an I component and a Q component.
The delay circuit 6 delays the input signal and synchronizes with the feedback signal.
The LUT coefficient calculation unit 5 calculates the LUT coefficient by calculation so as to minimize the distortion based on the difference between the input signal and the feedback signal, and updates the LUT coefficient of the LUT coefficient setting units 40 to 43.

[4-times oversampling filter 10: FIG. 1]
The quadruple oversampling filter 10 multiplies the quadrature-modulated input signal by a specific sample timing coefficient based on the filter characteristics, thereby oversampling at a frequency four times the sample frequency of the DAC 91 and the ADC 93. A signal is generated, and filter processing is performed to output sample points to the DPD processing units 100 to 103 at each sample timing.

Specifically, the 0 sample point coefficient unit 10 a multiplies the input signal by the filter coefficient at timing 0 at the timing 0 of 4 times oversampling, and outputs the sample at timing 0 to the DPD processing unit 100.
The 1-sample point coefficient unit 10 b multiplies the input signal by the filter coefficient of timing 1 at timing 0 of 4 times oversampling, and outputs the sample of timing 1 to the DPD processing unit 101.

The 2-sample point coefficient unit 10 c multiplies the input signal by the filter coefficient of timing 2 at timing 0 of 4 × oversampling, and outputs the sample of timing 2 to the DPD processing unit 102.
The 3-sample point coefficient unit 10d multiplies the input signal by the filter coefficient at timing 3 at timing 0 of 4-times oversampling, and outputs the sample at timing 3 to the DPD processing unit 102.

  That is, in the DPD circuit 1, four sample points having different timings are generated from the input signal sampled at the frequency of the DAC 91 by filter processing using the four-time oversampling filter 10, and the four sample points 100 to 103 are generated. By performing parallel processing in (1), DPD processing is performed at a plurality of timings without increasing the processing speed, and these are appropriately combined to give distortion closer to the inverse characteristics of the amplifier.

[Fourth Oversampling Filter 10 Coefficient: FIG. 2]
Here, an example of the filter coefficient of the 4-times oversampling filter 10 will be described with reference to FIG. FIG. 2 is an explanatory diagram illustrating an example of coefficients of the input side 4 × oversampling filter 10. A similar coefficient is set for the output side oversampling filters 60 to 63.
As shown in FIG. 2, a filter coefficient is set for each sample in the input-side 4-times oversampling filter 10 to determine the filter characteristics.

“0 sample” in FIG. 2 is a filter coefficient (0 sample coefficient) set in the 0 sample point coefficient portion 10a, and “1 sample” is a coefficient (1 sample coefficient) in the 1 sample point coefficient portion 10b. , “2 samples” is a coefficient (2 sample coefficients) of the 2 sample point coefficient portion 10c, and “3 samples” is a coefficient (3 sample coefficients) of the 3 sample point coefficient portion 10d.
The input-side 4-times oversampling filter 10 multiplies the input signal by a predetermined coefficient at each sample timing to generate sample points at pseudo different timings, and outputs the sample points to the corresponding DPD processing units 100 to 103.

[DPD processing units 100 to 103: FIG. 1]
The DPD processing units 100 to 103 are the same as the conventional DPD processing units, and are respectively delay circuits 20 to 23, envelope calculation units 30 to 33, LUT coefficient setting units 40 to 43, multipliers 50a to 53a, 50b to 53b.
The delay circuits 20 to 23 delay the input sample points for a predetermined time.
The envelope calculation units 30 to 33 obtain the envelope of the input sample points.

The LUT coefficient setting units 40 to 43 have a common LUT, read the coefficient corresponding to the envelope from the LUT, and set the coefficients in the multipliers 50a to 53a and 50b to 53b.
The multipliers 50a to 53d multiply the I component of the input signal by the LUT coefficient, and the multipliers 50b to 53b multiply the Q component by the LUT coefficient and output DPD data.
The DPD processing units 100 to 103 correspond to the predistortion unit described in the claims.

[Output-side 4-times oversampling filters 60 to 63: FIG. 1]
The quadruple oversampling filters 60 to 63 perform filter processing in which the outputs (DPD data) of the DPD processing units 100 to 103 are artificially four times oversampled by filter processing and output only samples at specific timings, respectively. This is performed, and the timings of the four DPD data are aligned with the timing of the DAC 91 (the timing at which oversampling is not performed) and output to the multipliers 70 to 73.
The DPD data corresponds to the predistortion data described in the claims.

  Specifically, the output-side 4 × oversampling filter 60 includes only 0 sample coefficients among the 4 × oversampling filter coefficients shown in FIG. 2, and 4 × oversampling the input 0 sample timing DPD data. The sampling 0 sample coefficient is multiplied and output to the multipliers 70a and 70b at the timing of the 0 sample point (specifically, the timing delayed by 4 samples).

The output side 4 × oversampling filter 61 includes only 4 × oversampling 3 sample coefficients, and multiplies the input 1 sample timing DPD data by 4 × oversampling 3 sample coefficients to obtain 0 sample timing. Is output to the multipliers 71a and 71b.
In other words, since the output of the DPD processing unit 101 is pseudo 1 sample timing delayed compared to the output of the DPD processing unit 100, the 3 sample coefficient that is delayed by 3 sample times to match the next 0 sample timing Is multiplied and output as a DPD result.

Similarly, the output-side 4-times oversampling filter 62 has 2-sample coefficients for 4-times oversampling, and multiplies the input 2-sample timing DPD data by 2-sample coefficients to give multipliers 72a, To 72b.
Since the output of the DPD processing unit 102 is artificially delayed by 2 sample timings compared to the output of the DPD processing unit 100, the DPD processing unit 102 multiplies the 2 sample coefficients, which are delayed by 2 sample timings, and performs DPD at 0 sample timing. Output the result.

The output-side 4-times oversampling filter 63 has 1-sample coefficient of 4-times oversampling, multiplies the input 3-sample timing DPD data by 1-sample coefficient, and outputs it to the multipliers 72a and 72b at 0-sample timing. To do.
The output of the DPD processing unit 103 is artificially delayed by 3 sample timings compared to the output of the DPD processing unit 100, and outputs a DPD result by multiplying by 1 sample coefficient which is a timing delayed by 1 sample timing.

  As a result, the output side 4 × oversampling filters 60 to 63 all output four DPD results as sample points at the same timing (0 sample timing) as the original signal, and the input side 4 × oversampling filter. The timing of the data oversampled by 10 is returned to the sample frequency of the DAC 91.

[Synthesis unit: Fig. 1]
The synthesizer has a configuration in which the multipliers 70 to 73 and the adder 80 are combined and weights and synthesizes the DPD results at each sample timing. In the synthesis unit, synthesis is performed so as to be closest to the reverse characteristic of the amplifier 92.
[Multipliers 70 to 73]
Multipliers 70 to 73 weight the DPD results of the I component and Q component obtained at each sample timing, and weight coefficients ω0 to ω3 set by the control unit (not shown) for each DPD result. Multiply

For example, when all four sample points (sample point 0 to sample point 3) are averaged uniformly, ω0 to ω3 are all 0.25.
When weighting equally using only the sample point 0 and the sample point 2, the weighting coefficients are ω0 = ω2 = 0.5 and ω1 = ω3 = 0.
The value of the weighting factor can be arbitrarily set from a control unit (not shown) according to the characteristics of the amplifier to be compensated, and is set to be closest to the inverse characteristics of the amplifier.

[Addition unit 80]
The adder 80 includes an I component adder 81 and a Q component adder 82, adds four DPD results weighted for the I component and the Q component, respectively, and outputs the result to the DAC 91.
In this example, the synthesis method is addition. However, the present invention is not limited to this, and any calculation may be performed depending on the distortion characteristics of the amplifier. For example, calculation using a difference or product of each DPD result is performed. You may synthesize.
Furthermore, it is possible to synthesize another LUT by performing an operation corresponding to each DPD result or performing a filter operation.
Thus, by performing appropriate weighting, the distortion compensation signal can be easily adjusted so as to achieve optimum distortion compensation without changing the circuit configuration.

[Operation of Amplifier with DPD Circuit: FIG. 1]
Next, the operation of the amplifying apparatus including the DPD circuit will be described with reference to FIG. It should be noted that the same operation as in the conventional part is the same.
The I component and Q component of the input transmission signal are branched into two, one of the branched signals is input to the input-side quadruple oversampling filter 10 and the other signal is input to the delay circuit 6. Delayed.

  The input signal input to the input-side 4 × oversampling filter 10 is multiplied by the filter coefficient at each of the 0 sample timing to 3 sample timing in the 0 sample point coefficient unit 10a to 3 sample point coefficient unit 10d, Input to corresponding DPD processing units 100 to 103.

  In the DPD processing units 100 to 103, similarly to the conventional DPD processing unit, the LUT coefficient is multiplied to add the inverse characteristic of the amplifier 92, and the DPD data is output to the output side quadruple oversampling filters 60 to 63.

The output side 4 × oversampling 60 to 63 outputs the DPD results returned to the timing of the original signal all at once by multiplying each DPD data by the coefficient of the specific timing of 4 × oversampling.
Each DPD result is multiplied by a predetermined weighting factor in multipliers 70 to 73, and an adder 80 combines DPD results weighted for each of the I component and Q component, and gives the inverse characteristic of amplifier 92. DPD output.

  The DPD output is converted into an analog signal by the DAC 91 and amplified by the amplifier 92. At that time, the distortion generated in the amplifier 92 is canceled by the distortion added by the DPD circuit 1, and an amplified signal without distortion is obtained.

The output of the amplifier 92 is branched to become a feedback signal, converted into a digital signal by the ADC 93, orthogonally demodulated by the orthogonal demodulator 4, and the LUT coefficient of each DPD processor is obtained by the LUT coefficient calculator 5 to obtain the LUT. Is updated.
In this way, the operation of the amplifying device including the DPD circuit is performed.

[Example of oversampled data of DPD output signal: FIG. 3]
Next, an example of overover sample data of the DPD output signal will be described with reference to FIG. FIG. 3 is an explanatory diagram showing oversampled data of the DPD output signal.
In FIG. 3, DPD data without oversampling, data obtained by oversampling the sample four times, data DPD data shifted by two samples without oversampling, and data obtained by oversampling the sample four times. The operation of the output side 4 × oversampling filters 60 to 64 of the DPD circuit 1 is schematically shown.

As shown in FIG. 3, when DPD data in the case of no oversampling is assumed to be 0 sample timing, DPD data at 0 sample timing is the same as 2 sample timing data obtained by oversampling DPD data shifted by 2 samples by 4 times. It's time.
That is, the points surrounded by the common ellipse in FIG. 3 are DPD results of the same sample point (0 sample points).

  In this DPD circuit, a plurality of DPD results obtained at pseudo different sampling timings as described above are used, the timing is adjusted by an output side 4 × oversampling filter, and further weighted appropriately to synthesize the amplifier. It is assumed that a distortion closer to the inverse characteristic of the above can be generated and highly accurate distortion compensation can be performed.

[Output signal example of this DPD circuit: FIG. 4]
Next, an example of the output signal of the DPD circuit 1 will be described with reference to FIG. FIG. 4 is an explanatory diagram showing an example of an output signal of the present DPD circuit.
In FIG. 4, not only the output of the DPD circuit 1 but also for comparison, DPD data without oversampling shown in FIG. 10A and its DAC output, DPD data shifted by 2 samples without oversampling and its The DAC output, and as an ideal example, the DAC output in the case where the oversampling is performed four times are shown superimposed.

  As can be seen from FIG. 4, the output data of this DPD circuit 1 and its DAC output have an ideal waveform (broken line) as compared with the conventional case where there is no oversampling or a simple two-sample deviation. It is a close shape, and it can be seen that distortion according to the characteristics of the amplifier is given.

[Example of amplifier output signal using this DPD circuit: FIG. 5]
Next, an example of an output signal of the amplifier 92 using the DPD circuit 1 will be described with reference to FIG. FIG. 5 is an explanatory diagram illustrating an example of an output signal of the amplifier 92 using the DPD circuit.
FIG. 5 shows an output signal obtained by amplifying each DAC output shown in FIG. 4 by the amplifier 92. Compared to the conventional case where there is no oversampling or a simple two-sample deviation, the ideal 4 is output. An amplifier output close to the double oversampled waveform is obtained. That is, it can be seen that the nonlinear distortion generated in the amplifier 92 is sufficiently compensated by using this DPD circuit.

[Effect of the embodiment]
According to the distortion compensation circuit and the distortion compensation method according to the embodiment of the present invention, the input side 4 × oversampling filter 10 uses the input signal sampled at the sampling frequency of the DAC 91 to generate 0 to 3 sample timings based on the filter characteristics. Is multiplied by the filter coefficient to generate sample points that are pseudo-oversampled 4 times and output to the DPD processing units 100 to 103 corresponding to the respective sample timings. The sample point data is distorted into DPD data, and the output-side oversampling filters 60 to 63 add the DPD results obtained by multiplying the DPD data at each sample timing by the filter coefficient at a specific sample timing and returning to the DAC 91 timing. 70 to 73, and adder 7 ˜73 is a distortion compensation circuit and a distortion compensation method in which each DPD result is appropriately weighted and added by the adder 80, so even if the sample frequency of the DAC 91 is small, combining distortion compensation based on different timings, By weighting and synthesizing distortion compensation at each timing, it is possible to give distortion closer to the distortion characteristics of the amplifier 92 to the transmission signal, and even if the sample frequency is small, the accuracy can be improved without increasing cost and power consumption. There is an effect that high distortion compensation can be performed.

In the embodiment, the case where pseudo-oversampling is performed four times has been described. However, the present invention is not limited to this.
For example, when performing N-times oversampling that is set according to the distortion characteristics of the amplifier, the N-side oversampling filter on the input side, N DPD processing units, and N-times overrun on the output side The configuration includes a sampling filter.

  Then, the input signal is multiplied by a coefficient of 0 sample timing to (N−1) sample timing by the input side N-times oversampling filter to output N sample points, and the N DPD processing units perform parallel DPD. The same effect can be obtained by performing processing, matching the timing of each DPD result with N output-side N-times oversampling filters, and combining them with appropriate weighting in the combining unit.

  The present invention is suitable for a distortion compensation circuit and a distortion compensation method capable of improving the performance of distortion compensation without increasing cost and power consumption even when the sampling frequency is small.

  1, 1 '... DPD circuit, 2, 6, 20, 21, 22, 23 ... delay circuit, 3, 30, 31, 32, 33 ... envelope calculation unit, 4 ... orthogonal demodulation 5, LUT coefficient calculation unit 7, 40, 41, 42, 43 ... LUT coefficient setting unit 8, 50, 51, 52, 53 ... multiplier, 60 ... output side over Sampling filter, 10 ... input side oversampling filter, 70, 71, 72, 73 ... multiplier, 80 ... adder, 81 ... I component adder, 82 ... Q component adder 91 ... DAC, 92 ... Amplifier, 93 ... ADC, 100 to 103 ... DPD processing unit

Claims (4)

A distortion compensation circuit that is provided at an input stage of an amplifier and compensates for distortion generated by the amplifier;
Based on the filter characteristics, the input signal sampled at a specific frequency is multiplied by a coefficient of an oversample timing of a frequency higher than the specific frequency to generate pseudo oversampled sample data. An input-side oversampling filter that outputs at each sample timing;
A plurality of predistortion units that output predistortion data by giving inverse characteristics of distortion generated by the amplifier to each sample data according to an envelope of sample data at each sample timing,
An output-side overload is provided corresponding to each predistortion unit, and multiplies each predistortion data by a specific oversample timing coefficient based on the filter characteristics to convert the predistortion data into a sample timing of the specific frequency. A sampling filter;
A distortion compensation circuit comprising: a weighting operation for output data of each output-side oversampling filter; and a combining unit that combines the results of the weighting operation.   2. The distortion compensation circuit according to claim 1, wherein the synthesizer performs equal weighting on the output data of all output side oversampling filters and outputs an average value.   2. The distortion compensation circuit according to claim 1, wherein the synthesizer performs weighting by selecting output data of a specific output-side oversampling filter. A distortion compensation method in a distortion compensation circuit that is provided at an input stage of an amplifier and compensates for distortion generated by the amplifier,
The distortion compensation circuit receives a signal sampled at a specific frequency, and is pseudo-oversampled by multiplying a coefficient of an oversample timing of a frequency higher than the specific frequency based on a filter characteristic. Sample data is generated, and for each sample timing, predistortion data is generated by giving the sample data an inverse characteristic of distortion generated by the amplifier, and specific pre-sampling timing based on the filter characteristic for each predistortion data The distortion compensation method is characterized in that the coefficient is multiplied to be converted into the sample timing of the specific frequency, and each predistortion data having the converted timing is subjected to weighting operation and synthesized and output.

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