JP2013191263A - Semiconductor memory device and method of driving the same - Google Patents

Abstract

A semiconductor memory device capable of reading data even while data is being written is provided.
A semiconductor memory device includes a plurality of memory banks including a plurality of nonvolatile memory cells. A plurality of buffers are provided corresponding to each of the plurality of memory banks, and temporarily store data in the memory banks at the time of data writing or data reading. The controller controls the memory bank and the buffer, and generates a buffer state signal indicating whether or not data in the memory bank has been read into the buffer. When reading data from the first memory bank that was the target of data writing or data reading, the controller reads data from the buffer corresponding to the first memory bank based on the buffer state signal.
[Selection] Figure 6

Description

  Embodiments described herein relate generally to a semiconductor memory device and a driving method thereof.

  A nonvolatile memory such as an MRAM (Magnetic Random Access Memory) takes time to write data. For this reason, the nonvolatile memory cannot read data from the memory bank during data writing, and has to read data from the memory bank after the write operation is completed.

JP 2008-159178 A

  Provided is a semiconductor memory device capable of accelerating the start of data reading during data writing.

  The semiconductor memory device according to the present embodiment includes a plurality of memory banks including a plurality of nonvolatile memory cells. A plurality of buffers are provided corresponding to each of the plurality of memory banks, and temporarily store data in the memory banks at the time of data writing or data reading. The controller controls the memory bank and the buffer, and generates a buffer state signal indicating whether or not data in the memory bank has been read into the buffer. When reading data from the first memory bank that was the target of data writing or data reading, the controller reads data from the buffer corresponding to the first memory bank based on the buffer state signal.

1 is a block diagram showing a configuration of an MRAM according to a first embodiment. 3 is an explanatory diagram showing a configuration of a single memory cell MC. FIG. The conceptual diagram which shows an example of a structure of several memory bank BK. FIG. 4C is a block diagram showing the data write operation to the memory bank BK0L, a block diagram showing the operation of the command / address receiver CAR and the data buffer DQB, and FIG. 4C shows a mode register MR showing the operation state of the memory. Block Diagram. The circuit diagram which shows the structure of the buffer state circuit BSC provided in the main controller MCNT. FIG. 3 is a timing diagram showing a data write operation of the MRAM according to the first embodiment. The flowchart which shows the data write-in operation | movement of MRAM according to 1st Embodiment. FIG. 10 is a timing chart showing an operation when a write command for page <7> of the same memory bank is issued during a write operation of page <0> of a certain memory bank.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention. The following embodiments describe MRAM, but can be applied to other nonvolatile memories (for example, FeRAM).

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the MRAM according to the first embodiment. The MRAM according to the present embodiment includes a memory bank BK, a command / address receiver CAR, a command controller COMCNT, a data buffer DQB, and an input / output unit I / O.

  The memory bank BK includes, for example, a memory cell array MCA including a plurality of memory cells MC that are two-dimensionally arranged in a matrix. Each memory cell MC is connected to a bit line pair (for example, bit line BL1 and bit line BL2 as shown in FIG. 1) and a word line WL. That is, one end of the memory cell MC is connected to one bit line BL1 of the bit line pair, and the other end is connected to the other bit line BL2 of the bit line pair. The bit line pair BL1, BL2 extends in the column direction. The word line WL extends in the row direction orthogonal to the column direction.

  The memory bank BK further includes a sense amplifier SA, a write driver WD, a column decoder CD, a row decoder RD, a main controller MCNT, and a write read page buffer WRB (hereinafter also simply referred to as a page buffer WRB). I have.

  For example, the sense amplifier SA is connected to the memory cell MC via the bit line BL1 and has a function of detecting data in the memory cell MC. At this time, the bit line BL2 is connected to the reference voltage (ground) via the write driver WD. The write driver WD is connected to the memory cell MC via, for example, the bit lines BL1 and BL2, and has a function of writing data to the memory cell MC.

  The command / address receiver CAR receives a command, an address, and a clock that determine the operation of the memory bank BK. The command / address receiver RCA receives, for example, a bank address, a column address, a row address, and the like as an address. The command / address receiver RCA receives, for example, an active command ACR, a write command MRW, a read command MRR, a reset command RST, and the like as commands. With these commands, the memory bank BK can execute various operations.

  The command controller CMDC receives commands indicating various operations such as a read operation and a write operation, and controls the main controller MCNT in accordance with those commands.

  The main controller MCNT transfers the data received from the DQ buffer DQB to the write driver WD so as to write to the memory bank according to the address, or transfers the data read from the memory bank to the DQ buffer DQB according to the address. Control the entire BK. The main controller MCNT includes ECC (Error Correction Code).

  The column decoder CD is configured to select a bit line pair of a certain column according to the column address. The row decoder RD selects the word line WL according to the row address.

  The page buffer WRB temporarily stores write data input via the input / output unit I / O and the data buffer DQB, or temporarily stores read data from the memory cell MC.

  The data buffer DQB outputs read data to the outside via the input / output unit I / O or transfers the write data taken from the outside via the input / output unit I / O to the inside. Hold temporarily.

  In FIG. 1, one memory bank BK is shown. However, normally, a plurality of memory banks BK are two-dimensionally arranged in a matrix.

  FIG. 2 is an explanatory diagram showing a configuration of a single memory cell MC. Each memory cell MC includes a magnetic tunnel junction element (MTJ (Magnetic Tunnel Junction) element) and a cell transistor CT. The MTJ element and the cell transistor CT are connected in series between the bit line BL1 and the bit line BL2. In the memory cell MC, the cell transistor CT is disposed on the bit line BL2 side, and the MTJ element is disposed on the bit line BL1 side. The gate of the cell transistor CT is connected to the word line WL.

    An MTJ element using the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers and a nonmagnetic layer (insulating thin film) sandwiched between them, and exhibits magnetoresistance due to the spin-polarized tunnel effect. Stores digital data with changes. The MTJ element can take a low resistance state and a high resistance state depending on the magnetization arrangement of the two ferromagnetic layers. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”. For example, the MTJ element is configured by sequentially laminating a fixed layer P, a tunnel barrier layer B, and a recording layer Fr as shown in FIG. The fixed layer P and the recording layer Fr are made of a ferromagnetic material, and the tunnel barrier layer B is made of an insulating film. The fixed layer P is a layer whose magnetization direction is fixed, and the recording layer Fr has a variable magnetization direction, and stores data according to the magnetization direction.

    When a current equal to or greater than the reversal threshold current is passed in the direction of the arrow A1 during writing, the recording layer Fr is in an anti-parallel state with respect to the magnetization direction of the fixed layer P, and is in a high resistance state (data “1”). When a current equal to or greater than the inversion threshold current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the fixed layer P and the recording layer Fr are in a parallel state and a low resistance state (data “0”). Thus, the TMJ element can write different data depending on the direction of current.

  FIG. 3 is a conceptual diagram showing an example of the configuration of the plurality of memory banks BK. The memory banks BK having the same address are included on the left side and the right side in FIG. 3, and two memory banks BK having the same address can be accessed simultaneously. For example, in the memory bank BK0L on the left side and the memory bank BK0L on the right side, the bank address BK0, the bank address BK1, and the column address AC5 are all “0”.

  Similarly, when the bank address BK0, the bank address BL1, and the column address AC5 are “0”, “1”, and “0”, respectively, the memory bank BK2L on the left side and the memory bank BK2L on the right side are selected. The

  Thus, by designating the bank address BK0, the bank address BL1, and the column address AC5, one from each of the plurality of memory banks BK0L to BK3U on the left side and the plurality of memory banks BK0L to BK3U on the right side. The memory bank BK can be selected simultaneously. That is, the left memory bank BK0L and the right memory bank BK0L having the same address can be accessed simultaneously. The selected memory bank BK is subjected to a data read operation or a data write operation.

  Each of the memory banks BK0L to BK3U includes a page buffer WRB, and can temporarily store read data and / or write data. For example, each of the memory banks BK0L to BK3U has 16 pages (32 bits / page) in each column. That is, the page buffer WRB of each of the memory banks BK0L to BK3U can store 512-bit data. Therefore, the page buffer WRB of each of the memory banks BK0L to BK3U has a capacity capable of temporarily storing data of all pages of a certain column of the corresponding memory bank.

  As shown in FIG. 4A, each of the memory banks BK0L to BK3U is divided into an UPPER array and a LOWER array, and each of the UPPER array and the LOWER array stores 8 pages of data.

  Each of the memory banks BK0L to BK3U includes a sense amplifier SA and a write driver WD corresponding to the UPPER array and the LOWER array, respectively. The sense amplifier SA can read data in the UPPER array or the LOWER array via the multiplexer, or the write driver WD can write data to the UPPER array or the LOWER array via the multiplexer.

  FIG. 4A is a block diagram showing a data write operation to the memory bank BK0L. FIG. 4B is a block diagram showing operations of the command / address receiver CAR and the data buffer DQB. FIG. 4C is a block diagram showing the mode register MR indicating the operation state of the memory. 4A to 4C show the configuration and operation in the same chip.

  The command / address receiver CAR receives a clock enable signal CKE, clock signals CK_t and CK_c, a command signal and an address signal CA <9: 0>, and a chip selection signal CS_n from the outside. The clock enable signal CKE is used to enable or disable the clock signals CK_t and CK_c in the command / address receiver CAR. The chip selection signal CS_n is a signal that is temporarily activated when a chip is selected. The command / address receiver CAR generates a clock signal CLK, an address signal ADDRs, a read command READ_CMD, and a write command WRITE_CMD in accordance with these signals CK_t, CK_c, CA <9: 0>, CS_n, as shown in FIG. The data is transferred to BK0L and the mode register MR shown in FIG.

  The mode register MR shown in FIG. 4C holds the state according to the state of the read command READ_CMD or the write command WRITE_CMD. For example, the mode register MR is a latch circuit, and when the read command READ_CMD is active (during data read operation), the latch unit corresponding to the read command is started, and when the write command WRITE_CMD is active (during data write operation) ) To start the latch unit corresponding to the write command. Note that one mode register MR may be provided in the chip to hold the state of the memory chip. It can be seen that the MRAM is executing a data write operation or a data read operation depending on the state of the mode register MR.

  FIG. 4A is a block diagram of the left memory bank among the memory banks BK0L selected by the address ADDRs. The other memory banks BL1L to BL3U have the same configuration as the memory bank BK0L.

  The memory bank BL0L receives the address ADDRs, the read command READ_CMD, the write command WRITE_CMD, and the read / write data RWD_L <63: 0>. In the data write operation, the write command WRITE_CMD is activated and the read command READ_CMD is inactivated. In the data read operation, the read command READ_CMD is activated and the write command WRITE_CMD is inactivated. After the write command WRITE_CMD is activated, read / write data RWD_L <63: 0> (here, write data) is received. For example, when the memory bank BK0L has a capacity of 8 pages (512 bits), the read / write data RWD_L <63: 0> is data for 2 pages (64 bits).

  The memory cell array in the memory bank BL0L is further divided into a LOWER array and an UPPER array, and each of the LOWER array and the UPPER array includes, for example, 8 pages. In this case, each of the LOWER array and the UPPER array of the memory bank BL0L stores 256-bit data.

  In the main controller MCNT, the record switch signal RDSW <7: 0> is a signal activated when reading from the page buffer WRB to the outside of the memory chip. For example, when the record switch signal RDSW <i> is activated, the data of page <i> (data for two pages) out of the eight pages of the LOWER array and the UPPER array is transferred from the page buffer WRB to the memory chip. Is read out to the outside. Note that i is an integer from 0 to 7.

  The page buffer read signal PBR_LTC <7: 0> is a signal that is activated when data is read from the memory cell array MCA to the page buffer WRB. When the page buffer read signal PBR_LTC <i> is activated, the data of page <i> among the eight pages on the UPPER side and the LOWER side is read from the memory cell array MCA to the page buffer WRB.

  The page buffer write signal PBW_LTC <7: 0> is a signal that is activated when data is written from the page buffer WRB to the memory cell array MCA. When the page buffer write signal PBW_LTC <i> is activated, the data of page <i> among the eight pages on the UPPER side and the LOWER side is written from the page buffer WRB to the memory cell array MCA.

  In the same memory bank BK0L, the page on the LOWER side and the page on the UPPER side have corresponding page buffers. Therefore, the read operation from the memory cell array MCA to the page buffer WRB can be executed simultaneously in the LOWER array and the UPPER array. is there. In addition, a write operation from the page buffer WRB to the memory cell array MCA can be performed simultaneously in the LOWER array and the UPPER array. Therefore, the page buffer read signal PBR_LTC <7: 0> is common in the LOWER array and the UPPER array in the memory bank BK0L, and the page buffer read signal PBW_LTC <7: 0> is also in the LOWER array and UPPER in the memory bank BK0L. Common in the array.

  On the other hand, when data is read from the page buffer WRB to the outside of the memory chip or data is written from the outside of the memory chip to the page buffer WRB, the record switch signal RDSW <7: 0> is activated.

  FIG. 5 is a circuit diagram showing a configuration of a buffer state circuit BSC provided in the main controller MCNT. The buffer state circuit BSC is provided in the main controller MCNT of each memory bank, and is provided corresponding to each page.

  The buffer state circuit BSC includes NOR gates G100 and G101 and a latch circuit LCT (i).

  The buffer state circuit BSC receives the page buffer read signal PBR_LTC (i) for the corresponding page, the page buffer write signal PBW_LTC (i) for the corresponding page, the chip ready signal CHRDY, and the precharge signal PRECH.

  The NOR gate G100 performs a NOR operation on the page buffer read signal PBR_LTC (i) and the page buffer write signal PBW_LTC (i), and outputs the result to the latch circuit LCT (i).

  The NOR gate G101 performs a NOR operation on the chip ready signal CHRDY and the precharge signal PRECH, and outputs the result to the latch circuit LCT (i).

  The latch circuit LCT (i) is driven by the output of the NOR gate G101, and latches the output of the NOR gate G100 as the buffer state signal READY (i).

  The buffer state circuit BSC can maintain the state of the buffer state signal READY (i) by the logic of the data latched in the latch circuit LCT (i). The buffer state signal READY (i) indicates whether or not data has been read to the page buffer WRB.

  The chip ready signal CHRDY is a signal that becomes logic high when the power source of the MRAM is turned on, and is always logic high while the MRAM is activated. The chip ready signal CHRDY is set for each memory chip. The precharge signal PRECH is a signal that is activated to a logic high when the MRAM is in a precharge state (standby state) and inactivated to a logic low during a data read operation or a data write operation. The precharge signal PRECH is set for each memory bank.

  At the time of data reading or data writing, the chip ready signal CHRDY is logic high and the precharge signal PRECH is logic low. Therefore, the latch circuit LCT (i) can effectively latch the rising edges of the page buffer read signal PBR_LTC (i) and the page buffer write signal PBW_LTC (i). When the page buffer read signal PBR_LTC (i) or the page buffer write signal PBW_LTC (i) rises to logic high, the latch circuit LCT (i) latches the buffer state signal READY (i) to logic high.

At the time of data reading or data writing, the buffer state signal READY (i) is activated to logic high, so that the main controller MCNT determines that data has already been read from the memory cell array MCA to the page buffer WRB. be able to. In this case, when reading data from page (i), the main controller MCNT can read page (i) data from the page buffer WRB without accessing the memory cell array MCA.

  On the other hand, when the buffer state signal READY (i) is in an inactive state, the main controller MCNT can determine that data is not read from the page buffer WRB. In this case, the main controller MCNT reads data from the memory cell array MCA by accessing the memory cell array MCA.

  In the precharge period, the precharge signal PRECH rises to logic high, and both the page buffer read signal PBR_LTC (i) and the page buffer write signal PBW_LTC (i) are logic low. Therefore, the latch circuit LCT (i) is reset and the buffer state signal READY (i) is inactivated to a logic low.

  In general, in an MRAM, a data mask unit (ECC unit) for prohibiting data writing is different from a data writing unit. For example, the MRAM includes an ECC every 64 bits and performs data masking in units of 32 bits. In this case, the sense amplifier SA needs to once read data of a certain page, which is a unit of data writing, to the page buffer WRB. At the time of reading to the page buffer WRB, the data is corrected using the ECC, and then the page buffer WRB stores the data. After the data other than the data mask is updated with the write data on the page buffer WRB, the write driver WD writes from the page buffer WRB to the memory cell array MCA. Conventionally, the sense amplifier SA once reads only the page to which data is to be written into the page buffer WRB. On the other hand, in the present embodiment, in order to enable reading from the page buffer WRB, data for all pages (for example, 512 bits) in the memory bank BK0L is transferred to the page buffer WRB regardless of the page to be written. Read to. Hereinafter, the data write operation of the MRAM according to the present embodiment will be described in more detail with reference to FIG.

  FIG. 6 is a timing diagram showing a data write operation of the MRAM according to the first embodiment. FIG. 7 is a flowchart showing a data write operation of the MRAM according to the first embodiment. FIG. 6 shows the data write operation of the MRAM and the time when the read command READ can be input. The following description will be made assuming that a certain column in the memory bank BK0L is selected. For convenience of illustration, the page buffer read signal RBR_LTC <i> and the page buffer write signal RBW_LTC <i> are shown together. In FIG. 6, the page buffer read signal RBR_LTC <i> becomes logic high in the pulse. The time is indicated as “PBR” and the time when the page buffer write signal RBW_LTC <i> becomes logic high is indicated as “PBW”.

  As shown in FIG. 7, first, the MRAM receives an active command and a write command (S10, S20). When an active command is received, a bank address and a row address are received, and when a write command is received, a bank address and a column address are received.

  Here, the data write target bank is the memory bank BK0L, and the data write target page is the page <0> of the memory bank BK0L. In the following, only the operation of the left memory bank BK0L in FIG. 3 has been described, but as described above, the same operation is performed for the right memory bank BK0L in FIG. Further, by changing the addresses BK0 and AC5, other memory banks can operate in the same manner.

  The MRAM according to the present embodiment operates according to the clock signals CK_t and CK_c. When the write command WRITE is input at a time before T0 shown in FIG. 6 (S20 in FIG. 7), the page buffer read signal PBR_LTC <0> is then activated at T3. By the activation of the page buffer read signal PBR_LTC <0>, the data of the page <0> in the memory bank BK0L to which data is to be written is read to the page buffer WRB (S30 in FIG. 7). At this time, each page <0> of the LOWER array and the UPPER array shown in FIG. 4A is simultaneously read to the corresponding page buffer WRB. That is, in the memory bank BK0L, data for two pages is simultaneously read to the page buffer WRB.

  By reading the data of page <0> to be written to the page buffer WRB, the data in the page buffer WRB can be updated with the write data. A period from the reception of the write command WRITE to the reading of the page <0> data to be written to the page buffer WRB (T4) is called a write delay time WLT (Write Latency).

  After the elapse of the write delay time WLT, the write data DQs is taken from the outside at T5 (S40 in FIG. 7). Write data DQs is input based on clock signals DQS_c and DQS_t. Then, in the write recovery period tWTR, the write data DQs is transferred to the page buffer WRB. When the page buffer write PBW_LTC <0> is activated at T11 after the elapse of the write recovery period tWTR, the write data DQs is overwritten on the page <0> in the page buffer WRB to be written. Thereby, the data of the page <0> in the page buffer WRB is updated with new write data (S50 in FIG. 7).

  On the other hand, at T5, the page buffer read signal PBR_LTC <1> is activated. As a result, the data of page <1> in memory bank BK0L is read to page buffer WRB. Subsequently, at T7 to T20, the page buffer read signals PBR_LTC <2> to PBR_LTC <7> are sequentially activated. As a result, the data of the pages <2> to <7> in the memory bank BK0L are read out to the page buffer WRB. That is, from T3 to T20, the data of all pages <0> to <7> in the memory bank BK0L are read to the page buffer WRB. The memory bank BK0L stores 8 pages of data (total of 16 pages (512 bits)) in each of the LOWER array and the UPPER array. Since data is simultaneously read from each of the LOWER array and UPPER array of the memory bank BK0L from T3 to T20, the page buffer WRB corresponding to the memory bank BK0L holds the data of all pages of the memory bank BK0L.

  In T11 to T12, when the page buffer write signal PBW_LTC <0> is activated, the page buffer read signals PBR_LTC <1> to <7> cannot be activated. This is because the columns in the same memory bank are selectively connected to the sense amplifier SA or the write driver WD via the multiplexer. If the sense amplifier SA and the write driver WD are provided for each column in the same memory bank, the page buffer read signal PBR_LTC <4> can be raised at T11 to T12. In this case, the page buffer read signals PBR_LTC <0> to <7> can rise continuously in a period from T3 to T18. At T3 to T20, each time the page buffer read signals PBR_LTC <0> to PBR_LTC <7> are activated, the buffer state circuit BSC corresponding to each page <0> to <7> of the memory bank BK0L (see FIG. 5). ) Sequentially activates the buffer state signals READY (0) to READY (7) to logic high. Therefore, after T20, the data of all pages in the memory bank BK0L can be read from the page buffer WRB.

  Thereafter, the write driver WD writes the data in the page buffer WRB to the memory bank BK0L (S60 in FIG. 7).

  In the present embodiment, the read command READ can be received after the write delay time WLT has elapsed (after T4) (S70 in FIG. 7). The address ADDs corresponding to the read command READ may specify the memory bank BK0L. In this case, the main controller MCNT accesses the page buffer WRB according to the states of the buffer state signals READY (0) to READY (7) of the memory bank BK0L, and outputs read data from the page buffer WRB to the outside (FIG. 7). S80, S90). The time from the input of the read command READ to the output of read data is called a read delay time RLT (Read Latency).

  As described above, the MRAM according to the present embodiment reads data from the page buffer WRB without reading data from the memory cell array MCA of the memory bank BK0L when the memory bank BK0L to be written is accessed. As a result, the read command READ can be issued after the write latency WLT has elapsed (after T4). After the read delay time RLT has elapsed, the MRAM outputs data from the page buffer WRB.

  As a comparative example, when read access is made to the memory bank BK0L to be written and the read data is read from the memory cell array MCA, the read command READ is issued after the elapse of the write recovery period tWTR (after T10). Need to be issued. This is because if the read command READ is issued before the write recovery period tWTR elapses, read data from the memory cell array MCA may collide with the write data on the data bus. As described above, the MRAM according to the present embodiment can issue the read command READ at a point earlier than the comparative example after issuing the write command WRITE. That is, the MARM according to the present embodiment can accelerate the start of data reading during data writing.

  Further, the MRAM according to the present embodiment reads the read data from the page buffer WRB (S100 in FIG. 7) when the read access is made to the memory bank BK0L to be written (S80 (NO) in FIG. 7). Therefore, the access frequency to the memory cell array MCA of the memory bank BK0L decreases. That is, the frequency of reading data directly from the memory cell array MCA is reduced. As a result, data disturbance to the memory cell array MCA in the memory bank BK0L can be suppressed.

  In the present embodiment, a read command to the same memory bank input during data writing is based on the state of a flag (for example, the write command WRITE in FIG. 4) indicating that data is being written to the same memory bank. Differentiated from read commands. When a read command is issued while the write command WRITE as the flag is set (when a read command is issued to the same memory bank during data writing), the MRAM is designated. The address data is output from the page buffer WRB to the outside via DQ. At this time, all read data has been read out to the page buffer first, and is output from the page buffer WRB.

  In this embodiment, a read command during writing is handled as a command different from a normal read command in the MRAM, and data is output from the page buffer WRB without accessing the memory cell array MCA. The read command during writing is in a standby state during the write latency WLT period.

  When a read command READ is input to a non-selected memory bank that is not a data write target, the flag (write command WRITE) is not set, so that it is treated as a normal read command and needs to be executed after reading data from the memory cell array MCA. There is.

  In the above embodiment, the memory bank BK0L and the page <0> are the write target memory bank and the write target page. However, needless to say, other memory banks BK1L to BK3U and pages <1> to <7> may be set as write targets. When page <1> is a write target, page buffer read signal PBR_LCT <1> is first activated at T3 in FIG. 6, and thereafter, page buffer read signals PBR_LCT <0>, PBR_LCT <2> ˜ PBR_LCT <7> may be activated in order.

  When the read command READ is issued to a memory bank other than the write target, the MRAM may read data from the memory cell array MCA as usual. However, in the memory bank where the read operation has been executed, data has already been read to the page buffer WRB. In this case, as described with reference to FIG. 5, the buffer state signal READY (i) is in an active state until the precharge signal PRECH is activated. Therefore, when data is read again from the memory bank on which the read operation has been executed, the MRAM reads data from the page buffer WRB. That is, the MRAM can read data from the page buffer WRB not only when the read command READ is issued after the write command WRITE but also when the read command READ is issued after the read command READ. Reading from the page buffer WRB is possible until the precharge signal PRECH is activated and the precharge period starts.

  FIG. 8 is a timing chart showing an operation when a write command for page <7> of the same memory bank is issued during the write operation of page <0> of a certain memory bank. In this case, before reading to the page buffer WRB based on the first write command WRITE1 is completed in all pages <0> to <7>, a write command WRITE2 to page <7> is issued at T10. . In this case, after the reading of the page <3> immediately before the issue of the write command WRITE2 is executed, the reading after the page <4> is interrupted.

  Then, the page buffer read signal PBR_LTC <7> corresponding to the page <7> to be written rises. Thereafter, without reading the pages <0> to <3> already written in the page buffer WRB, the pages <4> to <6> are read after the skip period tSKP has elapsed. The skip period tSKP may be the same period as the periods T2 to T10 for reading the pages <0> to <3> to the page buffer WRB.

  As a result, the MRAM according to the present embodiment allows the page <which has already been read to the page buffer WRB even if the next write command WRITE2 is issued to the same memory bank during the data read period by the first write command WRITE1. Only the remaining pages <4> to <6> can be read to the page buffer WRB without reading the data 0> to <3> again to the page buffer WRB. Thereby, read disturbance can be suppressed.

  In FIG. 8, if a sense amplifier SA and a write driver WD are provided for each column in the same memory bank, the page buffer read signal PBR_LTC <4> is raised at T11 to T12. be able to. In this case, the page buffer read signals PBR_LTC <5> and <6> rise continuously in the period of Tn to Tn + 3 after the activation of the page buffer read signal PBR_LTC <7>.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

BK ... Memory bank, CAR ... Command / address receiver, COMCNT ... Command controller, DQB ... Data buffer, I / O ... Input / output unit, MCA ... Memory cell array, SA ... Sense amplifier, WD ... write driver, CD ... column decoder, RD ... row decoder, MCNT ... main controller, WRB ... page buffer, BSC ... buffer state circuit

Claims (9)

A plurality of memory banks including a plurality of nonvolatile memory cells;
A plurality of buffers provided corresponding to each of the plurality of memory banks, and temporarily storing data of the memory banks at the time of data writing or data reading;
A controller for controlling the memory bank and the buffer, and generating a buffer state signal indicating whether or not data of the memory bank is read to the buffer,
Each of the memory banks is divided into a plurality of pages that are data write units,
The controller includes a page buffer read signal that is activated when data is read from a certain page of the memory bank to the buffer, and a page that is activated when data is written from the buffer to a page of the memory bank. When any one of the buffer write signal is activated, a buffer state unit that activates the buffer state signal is provided for each page.
When reading data from the first memory bank that was the target of data writing or data reading, the controller reads data from the buffer corresponding to the first memory bank based on the buffer state signal. A semiconductor memory device. A plurality of memory banks including a plurality of nonvolatile memory cells;
A plurality of buffers provided corresponding to each of the plurality of memory banks, and temporarily storing data of the memory banks at the time of data writing or data reading;
A controller for controlling the memory bank and the buffer, and generating a buffer state signal indicating whether or not data of the memory bank is read to the buffer,
When reading data from the first memory bank that was the target of data writing or data reading, the controller reads data from the buffer corresponding to the first memory bank based on the buffer state signal. A semiconductor memory device. Each of the memory banks is divided into a plurality of pages that are data write units,
The controller includes a page buffer read signal that is activated when data is read from a certain page of the memory bank to the buffer, and a page that is activated when data is written from the buffer to a page of the memory bank. 3. The semiconductor memory device according to claim 2, further comprising a buffer state unit for activating the buffer state signal for each of the pages when any one of the buffer write signals is activated. The buffer state unit includes a latch unit that latches the buffer state signal in an activated state when either the page buffer read signal or the page buffer write signal is activated,
The semiconductor memory device according to claim 3, wherein the latch unit holds the activation state of the buffer state signal until the data write operation or the data read operation is completed. The buffer temporarily stores data of all pages in the corresponding memory bank at the time of data writing or data reading,
5. The controller according to claim 3, wherein when reading data from the first memory bank, the controller reads data of an arbitrary page from the buffer corresponding to the first memory bank. The semiconductor memory device described. Semiconductor memory including a plurality of memory banks including a plurality of nonvolatile memory cells, a plurality of buffers provided corresponding to each of the plurality of memory banks, and a controller for controlling the memory banks and the buffers An apparatus control method comprising:
Temporarily storing the data of the first memory bank that is the target of data writing or data reading at the time of data writing or data reading in the buffer corresponding to the first memory bank;
A method of driving a semiconductor memory device, comprising: when reading data from the first memory bank, the controller reads data from the buffer corresponding to the first memory bank. Each of the memory banks is divided into a plurality of pages that are data write units,
The controller includes, for each page, a buffer state unit that generates a buffer state signal indicating whether or not data in the memory bank has been read into the buffer.
The buffer state unit is activated when a page buffer read signal activated when reading data from a certain page of the memory bank to the buffer and when writing data from the buffer to a certain page of the memory bank. 7. The page buffer write signal is received, and the buffer state signal is activated when one of the page buffer read signal and the page buffer write signal is activated. Driving method of the semiconductor memory device.   The buffer state unit latches the buffer state signal in an activated state when either the page buffer read signal or the page buffer write signal is activated, and the data write operation or the data read operation ends. 8. The method of driving a semiconductor memory device according to claim 7, wherein the activation state of the buffer state signal is held until. The buffer temporarily stores data of all pages in the corresponding memory bank at the time of data writing or data reading,
9. The controller according to claim 7 or 8, wherein when reading data from the first memory bank, the controller reads data of an arbitrary page from the buffer corresponding to the first memory bank. A driving method of the semiconductor memory device described.

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