JP2013187344A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

Provided is a semiconductor device having a high critical di / dt, which is less affected by an external potential and suppresses an avalanche current in the vicinity of a main junction.
A plurality of pn junctions of a plurality of guard rings 8 are connected to each other, and a pn junction in this region is separated from a pn junction in a main junction region 5 in an active portion. As a result, current concentration at the end of the active part is reduced, so that the critical di / dt is improved.
[Selection] Figure 1

Description

  The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a breakdown voltage holding structure of a semiconductor device.

  IGBTs (insulated gate bipolar transistors), MOSFETs, diodes, and the like used as high-power switching elements are required to have a high breakdown voltage of several hundred volts or more. These elements have a withstand voltage secured by a withstand voltage holding structure provided around the active part which is a main current path.

FIG. 5 shows a cross-sectional view of a prior art pressure holding structure. In this figure, 1 is a diode which is a semiconductor device, 8 is a p-type guard ring, 5 is a p-type main junction region, 4 is an n ⁻ layer, 9 is an n ⁺ layer, 13 is a silicon oxide film, 11 Is an anode electrode, and 12 is a cathode electrode. Here, the main junction region 5 and the guard ring 8 are formed by diffusing p-type impurities on the surface of the n-type Si wafer. The guard rings 8 are separated from each other, and the pn junctions of the guard rings are separated from each other. When a reverse bias voltage is applied to this diode, the depletion layer starts to spread from the main junction region 5 toward the n ⁻ layer 4. The layer can be expanded to relieve the electric field.

  In the breakdown voltage holding structure of FIG. 5, the pn junctions of the guard ring 8 are separated from each other. However, as described in Patent Documents 1-4, the reduction of the breakdown voltage holding structure part, the influence of external charges, or the main In order to suppress the avalanche current in the vicinity of the junction region, a withstand voltage holding structure has been proposed in which the pn junction of the guard ring in the inner periphery is connected including the main junction region. An example of such a breakdown voltage holding structure is shown in FIG. In this example, the pn junction regions of the guard ring 8 from the inner periphery to the second one are in contact with each other including the pn junction of the main junction region 5.

  In the breakdown voltage holding structure as shown in FIG. 6, since the interval between the guard rings 8 can be narrowed, the width of the breakdown voltage holding structure portion 3 can be reduced. Further, since the impurity concentration at the oxide film interface is high, the semiconductor device is hardly affected by external charges, and the durability of the semiconductor device against disturbance is improved. Furthermore, since the avalanche current in the region where the pn junctions of the plurality of guard rings 8 are connected to each other is suppressed, the concentration of the avalanche current at the end of the main junction region can be suppressed.

JP 2003-197898 A JP 2009-38356 A JP-A-1-270346 JP-A-2-186675

  However, in the conventional withstand voltage holding structure, since the pn junctions of the main junction region 5 and the guard ring 8 are connected, current tends to concentrate at the active portion end of the element during switching, and the element is destroyed. There is a fear of For example, in the diode, carriers are easily injected into the breakdown voltage holding structure 3 when a current is passed in the forward direction. The carriers injected into the breakdown voltage holding structure 3 flow in the direction returning to the active portion 2 because a voltage is applied in the reverse direction when the diode is recovered. At this time, if the current change (di / dt) at the time of recovery increases, current concentration occurs at the end of the active portion and the element may be destroyed.

  Generally, the value of di / dt (hereinafter referred to as “critical di / dt”) at the time of failure is required to be large. When the critical di / dt is small, in order to protect the element from destruction, the element is used while suppressing the switching speed by inserting an inductance in the main circuit. However, when the switching speed is lowered, it becomes difficult to use in applications that require high-speed operation. Further, since the turn-on time of the switching element becomes long, the turn-on loss increases, and there arises a problem that the switching frequency is limited and the cost of the element cooling device is increased. For this reason, improving the critical di / dt is an important issue in terms of high-speed operation and loss reduction.

  The present invention has been made in consideration of the above-described problems, and has an object to provide a withstand voltage holding structure capable of increasing the critical di / dt.

  In order to solve the above problems, a semiconductor device according to the present invention includes a first region in which a plurality of pn junctions of a plurality of guard rings are connected to each other, and a pn junction and a first junction of a main junction region in an active portion. 1 region is isolated from the pn junction.

  More specifically, the semiconductor device according to the present invention includes a first conductivity type first semiconductor region, and a second conductivity type main junction region provided in an active portion adjacent to the first semiconductor region and through which a main current flows. And a plurality of second conductivity type guard rings adjacent to the first semiconductor region. The semiconductor device further includes a first region where a plurality of pn junctions of the plurality of guard rings are connected to each other, the pn junction between the first semiconductor region and the main junction region, and the first semiconductor The pn junction between the region and the first region is isolated.

  Here, the first conductivity type and the second conductivity type are p-type or n-type, and are opposite to each other. The guard ring in the present invention is synonymous with so-called FLR (Field Limiting Ring).

  The present invention can be applied to various semiconductor devices such as diodes, IGBTs, MOSFETs, and junction bipolar transistors.

  According to the present invention, the pn junction of the main junction region in the active portion and the pn junction of the first region where the plurality of pn junctions of the plurality of guard rings are connected to each other are separated. Since the current concentration at the end of the part is reduced, the critical di / dt is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. Sectional drawing of the principal part of the diode which is 2nd Example of this invention. Sectional drawing of the principal part of IGBT which is 3rd Example of this invention. Sectional drawing of the principal part of power MOSFET which is 4th Example of this invention. An example of the pressure | voltage resistant holding structure by a prior art. An example of the pressure | voltage resistant holding structure by a prior art.

  First, the pressure | voltage resistant holding structure which implemented this invention is demonstrated, referring FIGS. 1-4. Details of the element structure shown in each drawing will be described later as examples.

  By separating the pn junction of the main junction region 5 that is a p-type semiconductor region and the pn junction of the guard ring 8 that is a similar p-type semiconductor region at the inner periphery, when a voltage is applied in the forward direction, The inflow of carriers into the pressure withstand structure portion 3 is suppressed. For this reason, since the amount of carriers returning to the active part 2 at the time of recovery can be reduced, current concentration at the end part of the active part is relaxed, and the critical di / dt can be improved.

  In order to separate the pn junctions of the main junction region 5 and the guard ring 8 from each other, the main junction region and the innermost guard ring are separated from each other, or at least a plurality of contacts are in contact with the innermost guard ring. The guard ring may be separated. In any configuration, a region where the pn junctions of the plurality of guard rings on the outer peripheral portion are connected to each other is provided from the position of the separated guard ring. Since the surface of this region has a high impurity concentration by connecting a plurality of guard rings, it is hardly affected by external charges. Thereby, an avalanche current can be suppressed.

  When the pn junctions of a plurality of guard rings are connected to each other, when a voltage is applied in the opposite direction, the voltage difference between the guard rings becomes small, and the overall breakdown voltage tends to decrease. For this reason, the number of guard rings 8 connected to each other can affect the breakdown voltage. In addition, as described above, it is effective to provide a region where a plurality of guard rings 8 are connected to each other in a region where the effect of suppressing the generation of avalanche current due to the connection of a plurality of guard rings can be effectively utilized. For example, if an avalanche current is generated near the main junction region 5, current concentration may occur at the end of the main junction region 5, and the element may be destroyed. Therefore, it is effective to provide a region where a plurality of guard rings are connected to each other in a region close to the main junction region 5. In consideration of these points, the pn junctions of a plurality of guard rings are connected to each other in an inner peripheral region of ½ or less of the total number of guard rings and in an inner peripheral region of １ ／ or less in order to further improve the breakdown voltage. It is preferable to provide a connected region.

  Regarding the position where the main junction region 5 and the pn junction of the guard ring 8 are separated, as described above, the region where the plurality of guard rings are connected to each other is ½ or less, preferably １ ／ or less of the total number of guard rings. Since it is preferable to provide in the inner peripheral side region, it is preferable to set the inner peripheral side as much as possible. For this reason, it is preferable to separate the pn junction between the main junction region 5 and the first guard ring 8, or between the first and second guard rings 8, or both.

  A field plate 14 made of a conductor may be electrically connected to the guard ring 8. The field plate 14 can further reduce the influence of external charges. In the present embodiment, the guard ring 8 and the field plate 14 are connected via a slit-like contact hole opened in the silicon oxide film 13 and a contact hole opened in the corner portion around the entire circumference of the guard ring. A guard ring 8 is provided for each guard ring. That is, the field plate is provided for each guard ring even when the plurality of guard rings 8 are connected to each other. Thereby, the breakdown voltage can be improved.

  A method of forming a region composed of a plurality of guard rings 8 in which pn junctions are connected to each other will be described below.

  After forming an oxide film on the surface of the n-type Si wafer, a resist pattern is formed by a photo process. Next, after etching the oxide film using this resist pattern as a mask, p-type dopant is implanted by ion implantation. In this case, a group III element (for example, boron B) is implanted into the n-type Si wafer. Next, after removing the resist, a p-type dopant is diffused by heat treatment to form the guard ring 8.

  In the above process, when forming a plurality of guard rings in which pn junctions are connected to each other, the width of the resist pattern is set to be twice or less the diffusion length of the dopant. Further, by performing the step of forming the guard ring 8 simultaneously with the step of forming the main junction region 5 of the active portion 2, the breakdown voltage holding structure can be formed without increasing the number of steps.

Further, as shown in FIG. 2, a plurality of guard ring pn junctions may be connected by a p ⁻ layer 7 as a region having a lower impurity concentration than the guard ring provided between the guard rings. The method for forming this withstand voltage holding structure is as follows.

After forming an oxide film on the Si wafer surface, a resist pattern is formed in a photo process. Next, after etching the oxide film using this resist pattern as a mask, p-type dopant is implanted by ion implantation. Next, after removing the resist, another resist pattern is formed in a photo process, the oxide film is etched, and a p-type dopant is implanted. At this time, the dopant is implanted at a dose corresponding to the impurity concentration of the p ⁻ layer 7. Next, after removing the resist, the dopant is diffused by heat treatment to form the guard ring 8 and the p ⁻ layer 7. By performing these steps simultaneously with the formation of the main junction region and the like of the active portion, the breakdown voltage holding structure can be formed without increasing the number of steps.

  The embodiments of the present invention shown in FIGS. 1 to 4 will be described below. In the drawings, the same or equivalent components are denoted by the same reference numerals.

  FIG. 1 is a sectional view of an essential part of a diode according to a first embodiment of the present invention.

On the surface of the active portion 2 through which the main current flows in the n-type semiconductor substrate, the main junction region 5 which is a p-type semiconductor region having a higher impurity concentration than the n-type semiconductor substrate, and p which is also a p-type semiconductor region having a high impurity concentration. ^A p ⁻ layer 7 which is a p-type semiconductor region having a lower impurity concentration than the ⁺ region 6, the main junction region 5, and the p ⁺ region 6 is provided. Here, the pn junction of the main junction region 5 and the pn junction of the p ⁺ region 6 are connected by the p ⁻ layer 7. An n ⁺ layer 9 that is an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor substrate is provided on the back surface of the n-type semiconductor substrate. An anode electrode 11 and a cathode electrode 12 made of a conductor film such as a metal film are provided on the front and back surfaces of the n-type semiconductor substrate, respectively. Anode electrode 11 is electrically connected to p ⁺ region 6 and p ⁻ layer 7, and cathode electrode 12 is electrically connected to n ⁺ layer 9. Further, a silicon oxide film 13 is provided between the anode electrode 11 and the main junction region 5 at the end of the surface of the active portion 2.

A breakdown voltage holding structure 3 is provided around the active part 2 of the semiconductor substrate. In the breakdown voltage holding structure 3, 20 guard rings 8 are provided. The pn junction of the first guard ring 8 from the active part 2 side is in contact with the pn junction of the main junction region 5. The pn junctions of the first and second guard rings 8 are separated from each other without contact. Further, a region where the pn junctions of the second to sixth guard rings 8 are connected to each other is provided. Note that an n ⁺ layer 10, which is a channel stopper and is an n-type semiconductor region having a higher impurity concentration than the semiconductor substrate, is provided on the outermost peripheral portion of the breakdown voltage holding structure portion 3. A metal electrode 15 acting as a field plate is also electrically connected to the n ⁺ layer 10.

The guard ring 8 in this embodiment is formed by forming a resist mask pattern and removing the oxide film by etching, then implanting boron B, which is a group III element, and diffusing by heat treatment. These steps can be performed simultaneously with the step of forming the main junction region 5 and the p ⁺ region 6 in the active portion 2. The region where the second to sixth guard rings 8 are connected can be formed by setting the resist mask width between these guard rings to be not more than twice the diffusion length.

  Each guard ring 8 is electrically connected to a field plate 14 made of a metal film. As for the field plate 14 provided in the region composed of the second to sixth guard rings to which the pn junction is connected, the field plates connected to the guard rings are separated from each other. By separating the field plate 14 in this way, a voltage difference is generated between the guard rings, and the breakdown voltage of the entire diode can be improved.

  In the breakdown voltage holding structure of this embodiment, the impurity concentration at the oxide film interface in the region inside the sixth line is high, so that it is not easily affected by the external potential. Thereby, generation | occurrence | production of the avalanche current of this area | region can be suppressed, and the influence on the main junction area | region 5 can be reduced. Further, since the pn junctions of the first and second guard rings are separated, carrier injection into the breakdown voltage holding structure portion 3 can be suppressed when a voltage is applied in the forward direction. For this reason, the diode of this embodiment improves the critical di / dt at the time of recovery and can be applied to high-speed operation. Therefore, the IGBT module including the arm circuit in which the diode of the present embodiment is connected in antiparallel to the IGBT can be applied to high-speed switching.

  FIG. 2 is a cross-sectional view of a main part of a diode according to a second embodiment of the present invention. Hereinafter, differences from the first embodiment will be mainly described.

In the present embodiment, 20 guard rings 8 are formed, and the pn junction of the first guard ring from the side close to the active portion 2 is separated from the pn junction of the main junction region 5 in the active portion 2. The pn junctions of the guard rings are also separated from each other. Further, a p ⁻ layer 7 having a lower impurity concentration than the guard ring 8 is provided between the second to sixth guard rings. That is, a region is provided in which the pn junctions of the second to sixth guard rings 8 are connected to each other through the pn junction of the p ⁻ layer 7.

When forming the guard ring in this embodiment, a resist mask pattern is formed and the oxide film is etched away, and then boron B which is a group III element is ion-implanted. For the p ⁻ layer 7 having a low impurity concentration, boron B is ion-implanted after forming a resist mask pattern and etching the oxide film. Thereafter, boron is diffused and formed by heat treatment. These steps can be performed simultaneously with the step of forming the main junction region 5, the p ⁺ region 6 and the p ⁻ layer 7 of the active portion 2.

  In the breakdown voltage holding structure of this embodiment, the impurity concentration at the oxide film interface in the region inside the sixth guard ring 8 is high, so that it is difficult to be affected by the external potential in this region. In addition, generation of an avalanche current in this region can be suppressed, and the influence on the main junction region 5 can be reduced. Further, the pn junction of the main junction region 5 and the pn junction of the first guard ring are separated, and the pn junctions of the first and second guard rings are separated. For this reason, when the forward voltage of a diode is applied, the injection | pouring of the carrier to the pressure | voltage resistant holding | maintenance structure part 3 can be suppressed. For this reason, according to the present embodiment, the critical di / dt at the time of recovery is improved, so that the diode can be applied to high-speed operation. Therefore, as in the first embodiment, the IGBT module to which the diode according to this embodiment is applied can be applied to high-speed switching.

  FIG. 3 is a cross-sectional view of an essential part of an IGBT according to a third embodiment of the present invention.

A p layer 30, a floating p layer 17 and a main junction region 5, which are p type semiconductor regions, are provided on the surface of the active portion 2 of the n type semiconductor substrate. In addition, a gate electrode 20 having a trench structure is provided. An n ⁺ region 16 is provided in the vicinity of the gate electrode. On the back surface of the semiconductor substrate, an n ⁺ buffer layer 18 that is an n-type semiconductor region having a higher impurity concentration than the semiconductor substrate and a p collector layer 19 that is a p-type semiconductor region having a higher impurity concentration than the n ⁺ buffer layer 18 are provided. Is provided. An emitter electrode 21 and a collector electrode 22 made of a conductor film such as a metal film are provided on the front surface and the back surface of the semiconductor substrate, respectively. The emitter electrode 21 is electrically connected to the p layer 30 and the n ⁺ region 16 and the main junction region 5. The collector electrode 22 is electrically connected to the p collector layer 19.

  Twenty guard rings are provided in the breakdown voltage holding structure portion 3 around the active portion 2. The pn junction of the first guard ring 8 from the active portion 2 side and the pn junction of the main junction region 5 are separated from each other. The pn junctions of the first to third guard rings 8 are connected, the pn junctions of the third and fourth guard rings 8 are separated from each other, and the pn junctions of the fourth to sixth guard rings 8 are connected to each other. An area is provided.

  In the breakdown voltage holding structure of this embodiment, the impurity concentration at the oxide film interface in the region inside the sixth guard ring 8 is high, so that it is difficult to be affected by the external potential in this region. Therefore, generation of an avalanche current in this region can be suppressed, and the influence on the main junction region 5 can be reduced. Further, since the pn junction of the first guard ring and the pn junction of the main junction region are separated, current concentration at the end of the active portion during switching can be prevented. Therefore, according to the present embodiment, the IGBT can be applied to high-speed operation, and the IGBT module to which the IGBT is further applied can be applied to high-speed switching.

  FIG. 4 is a cross-sectional view of a main part of a power MOSFET according to a fourth embodiment of the present invention.

  On the surface of the active portion 2 of the n-type semiconductor substrate, an n-source region 23 which is an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor substrate, and a p-type main junction region having a higher impurity concentration than the n-type semiconductor substrate. A p-well 24 is provided. A gate electrode 20 is provided on the gate oxide film 25. Further, a source electrode 26 made of a conductor film such as a metal film is electrically connected to the n source region 23 and the p well 24.

  In the breakdown voltage holding structure portion 3 around the active portion 2, five guard rings 8 are provided. The pn junction of the first guard ring 8 from the active part 2 side is connected to the pn junction of the p well 24 in the active part 2. The pn junctions of the first and second guard rings are separated from each other. Furthermore, the pn junction of the second guard ring and the pn junctions of all the guard rings 8 outside the second guard ring are connected to each other.

  The guard ring in this embodiment is formed by forming a resist mask pattern and etching away the oxide film, and then implanting boron B, which is a group III element, and diffusing boron by heat treatment. These steps can be performed simultaneously with the step of forming the p-well 24 in the active portion 2. The guard ring 8 in which the pn junctions are connected to each other is formed by setting the resist mask width between these guard rings to be not more than twice the diffusion length.

  As in the first to third embodiments, each guard ring 8 is connected to a field plate 14 made of a conductor film such as a metal film. The field plates 14 provided on the guard ring to which the pn junction is connected are also separated from each other. By separating the field plate 14, a voltage difference is generated between the guard rings, and the breakdown voltage of the entire device can be improved.

  In the breakdown voltage holding structure of this embodiment, since most pn junctions of the guard ring are connected, the impurity concentration at the interface between the semiconductor substrate and the oxide film is high, so that it is not easily affected by external charges. For this reason, the breakdown voltage hardly changes and the reliability of the semiconductor element is improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Active part 3 Pressure | voltage resistant holding | maintenance structure part 4 n < ^- > layer 5 main junction area | region 6 p ⁺ area ^| region 7 p ^{< - >} layer 8 guard ring 9,10 n ⁺ layer 11 anode electrode 12 cathode electrode 13 silicon oxide film 14 field plate 15 Metal electrode 16 n ⁺ region 17 floating p layer 18 n ⁺ buffer layer 19 p collector layer 20 gate electrode 21 emitter electrode 22 collector electrode 23 n source region 24 p well 25 gate oxide film 26 source electrode 30 p layer

Claims (9)

A first semiconductor region of a first conductivity type;
A main junction region of a second conductivity type adjacent to the first semiconductor region and provided in an active portion through which a main current flows;
A plurality of guard rings of the second conductivity type adjacent to the first semiconductor region;
In a semiconductor device comprising:
A first region in which a plurality of pn junctions of the plurality of guard rings are connected to each other;
A semiconductor device, wherein a pn junction between the first semiconductor region and the main junction region is separated from a pn junction between the first semiconductor region and the first region. The semiconductor device according to claim 1,
A second region that is part of the plurality of guard rings and is located between the main junction region and the first region;
A semiconductor device, wherein a pn junction between the first semiconductor region and the first region is separated from a pn junction between the first semiconductor region and the second region. The semiconductor device according to claim 2,
A pn junction between the first semiconductor region and the main junction region is connected to a pn junction between the first semiconductor region and the second region. The semiconductor device according to claim 2,
A semiconductor device, wherein a pn junction between the first semiconductor region and the main junction region is separated from a pn junction between the first semiconductor region and the second region.   5. The semiconductor device according to claim 1, wherein pn junctions are connected by overlapping of guard rings in the first region. 6.   5. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor region having a lower impurity concentration than the guard ring is formed between the guard rings in the first region. 6. A semiconductor device, wherein a pn junction is connected.   7. The semiconductor device according to claim 1, wherein the first region is located in an inner peripheral portion of ½ or less of the total number of guard rings.   8. The semiconductor device according to claim 1, wherein a plurality of field plates made of a conductive layer are electrically connected to the plurality of guard rings.   9. The semiconductor device according to claim 8, wherein the plurality of field plates are separated from each other.