JP2013182600A - Design method for semiconductor integrated circuit, design device for semiconductor integrated circuit, circuit design program, and computer readable recording medium - Google Patents

Abstract

In a semiconductor design apparatus for designing a semiconductor integrated circuit using a standard cell, a signal path timing violation in the semiconductor integrated circuit is solved by using a desired cell having an appropriate driving capability and an appropriate occupied area. Is possible.
In a semiconductor design apparatus 100, a cell placement / wiring unit 112 for placing the standard cells and wiring between the standard cells so as to constitute the semiconductor integrated circuit based on circuit design data, and the semiconductor integration Of the signal paths in the circuit, a timing analysis unit 113 that detects a violation path in which a timing violation has occurred, and at least one standard cell included in the violation path as a replacement target cell, the same logic as each replacement target cell And an additional cell creation unit 115 that creates one or more additional standard cells having different driving capabilities from the replacement target cell for each replacement target cell.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit design method, a semiconductor integrated circuit design apparatus, a circuit design program, and a computer-readable recording medium, and in particular, performs a basic logical operation as a unit for designing a semiconductor integrated circuit. A semiconductor integrated circuit design method and design apparatus for designing a semiconductor integrated circuit by combining various standard cells (standard cells) that are logic circuits based on circuit design data, and such a semiconductor integrated circuit design method is performed by a computer. The present invention relates to a circuit design program and a computer-readable recording medium on which such a circuit design program is recorded.

  In a conventional method of designing a semiconductor integrated circuit using various design tools, various standard cells (arrangements (layouts) of semiconductor regions and wirings that are designed in advance so as to have various basic logical operation functions as logic circuits) Hereinafter, it is also referred to simply as a cell), and the arrangement of the prepared cells and the wiring between the cells (cell arrangement wiring) are automatically performed by a computer so that a semiconductor integrated circuit indicated by the circuit design data can be obtained. Thus, a semiconductor integrated circuit is designed.

  In such a semiconductor integrated circuit design method, in order for the designed semiconductor integrated circuit to operate correctly, a signal path (hereinafter also referred to as a signal path) between the sequential circuit of the preceding stage and the subsequent stage that perform the synchronized operation is timing. Because it is necessary to satisfy the constraints, timing analysis is performed on the semiconductor integrated circuit once designed by cell placement and routing, and if a timing violation is found, the cell or The layout has been improved to correct the wiring layout.

  FIG. 13 is a diagram for explaining such a conventional method for designing a semiconductor integrated circuit, and shows a flow of a general design process.

  Note that the processing of each step shown in FIG. 13 is performed by various design tools constructed by software in the computer.

  First, logic synthesis is performed by the logic synthesis tool to convert circuit design data indicating the arithmetic function of the semiconductor integrated circuit to be designed into circuit information (net list) representing the logic circuit (step S1).

  In other words, in this logic synthesis, there is a process of converting circuit design data described in a hardware description language into a netlist indicating the connection relationship of components (logic gates, power supplies, etc.) in a logic circuit that realizes an arithmetic function. This is done by a logic synthesis tool.

  Here, the netlist is data equivalent to a circuit diagram showing the connection relationship of combinational circuits and sequential circuits stored as standard cells in a cell library (existing cell library) Lrc registered in advance. The combinational circuit is a logic circuit whose output is determined only by the current input, and is a logic gate that performs basic logic operations such as an AND gate and an OR gate, for example. The sequential circuit has an output determined by an input signal and a past internal state held therein, and is, for example, a flip-flop.

  Next, cell placement and routing is performed by the placement and routing tool based on the net list (step S2).

  In this cell placement and routing, placement and routing of cells is performed by a placement and routing tool according to circuit information (net list). That is, using the cells of the existing cell library Lrc, the arrangement of cells such as combinational circuits and sequential circuits, and the connections between the arranged cells are the configurations of the semiconductor region and the wiring layer that constitute the semiconductor integrated circuit to be designed. This is done to get the layout of the element.

  Next, timing analysis is performed on the semiconductor integrated circuit having the layout obtained by the cell arrangement and wiring by the timing analysis tool (step S3).

  In this timing analysis, actual load data is determined based on the specification information (attribute information) of various cells stored in the existing cell library Lrc from layout data indicating the arrangement of cells and the arrangement of wiring between cells in the semiconductor integrated circuit. (Parasitic components such as parasitic resistance and parasitic capacitance in elements and wiring) are obtained, and based on this actual load data, delay information is extracted by the timing analysis tool, and the timing at which the signal reaches each flip-flop in the semiconductor integrated circuit Is calculated.

  Here, the delay time is a delay time in a signal path between the flip-flops at the front and rear stages. Further, the timing analysis tool performs timing verification to determine whether or not the delay time between the preceding and succeeding flip-flops satisfies the timing constraint based on the timing calculation result (step S4), and the obtained semiconductor integrated If the timing constraint is satisfied in the cell and wiring layout in the circuit, the timing verification is finished. If the timing violation occurs, the timing improvement tool can improve the timing using the cells of the existing cell library Lrc. Performed (step S5).

  In other words, in this timing improvement, the placement and routing are optimized to improve the layout so that the timing violation is eliminated. Specifically, for the optimization of the placement and routing, the cell in the designed layout is replaced with a cell having a large driving capability in order to optimize the delay, and the current cell is moved so as to shorten the wiring length. Cell movement and cell insertion for newly inserting a cell in the timing violation path are performed so that the delay time in the timing violation path is optimized.

  Then, the timing analysis is performed again by the timing analysis tool based on the layout data changed by the optimization.

  The timing analysis (step S3), the timing verification (step S4), and the timing improvement (step S5) are performed for all signal paths in a semiconductor integrated circuit obtained by cell placement and wiring, that is, cell placement and wiring between cells. Repeated so that timing violations converge. Repeating attempts to eliminate this timing violation causes an increase in the design period of the semiconductor integrated circuit.

  14 and 15 are diagrams showing a specific example of timing improvement in the conventional method of designing a semiconductor integrated circuit described in FIG.

  For example, as shown in FIG. 14, it is assumed that a setup timing violation has occurred in the signal path Dpx from the flip-flop FF1 to the flip-flop FF2 as a result of the timing analysis (step S3). This setup timing violation is a timing violation in which signal transmission from one flip-flop FF1 to the next flip-flop FF2 is not in time for the specified time.

  In this case, in the timing improvement (step S5), processing for changing the layout designed by automatic placement and routing is performed so that the time (data path delay time) for transmitting data from the flip-flop FF1 to the flip-flop FF2 is reduced.

  Specifically, as the process of changing the layout, the used cells Uax and Ubx, which are standard cells used in the signal path Dpx, are changed from the existing cells A1 to A3 in the existing cell library Lrc so that the timing constraint is satisfied. The cell library Lrc is prepared for a process of replacing the cells A1 and B1 having the same delay time among B1 to B3 with the same function, a process of bringing the cells closer so as to shorten the inter-cell wiring, or a part Wpx of the clock path Cps. A process of delaying the clock signal by inserting the delay cell Csx is performed.

  Further, as shown in FIG. 15, it is assumed that a hold timing violation has occurred in the signal path Dpy from the flip-flop FF3 to the flip-flop FF4. This hold timing violation is a timing violation in which signal transmission from one flip-flop FF3 to the next flip-flop FF4 is too early than a specified time.

  In this case, in the timing improvement (step S5), a process for changing the layout once designed by the cell placement and routing is performed so that the time (data path delay time) for transmitting data from the flip-flop FF3 to the flip-flop FF4 is increased. .

  Specifically, as the process of changing the layout, the used cells Uay and Uby, which are standard cells used in the signal path Dpy, are changed from the existing cells A1 to A3 in the existing cell library Lrc so that the timing constraint is satisfied. A process of replacing the cells A3 and B3 having the same delay with the longest delay among B1 to B3, a process of detouring the wiring so as to lengthen the inter-cell wiring, or moving away the adjacent cells, or a part Wpy of the signal path Dpy In addition, a process of delaying the data signal by inserting a delay cell Csy prepared in the cell library Lrc is performed.

  If the layout is changed so that signal paths with timing violations meet the timing constraints, the layout may be unexpectedly complicated, for example, cell congestion, enormous wiring bypass, and enormous cell insertion. In other words, the congestion of cells and wiring increases, causing a wiring short circuit, or the timing violation path remains in a state where the timing constraint is not satisfied.

  In this case, a large design reversion in the design process, such as redesigning the semiconductor integrated circuit back to the hardware description language, is required, which increases the design period.

  By the way, Patent Documents 1 and 2 disclose a method for designing a semiconductor integrated circuit using standard cells in which a measure for reducing the design period is taken.

  For example, in Patent Document 1, in a semiconductor integrated circuit correction device, correction is performed by looking at the entire circuit, such as correcting timing violation points common to more signal paths in order to shorten the design period. In the above, there is disclosed an apparatus that effectively reduces the total number of timing violations and reduces the number of signal paths that are targets of timing improvement thereafter.

  FIG. 16 is a diagram for explaining the semiconductor integrated circuit correction device disclosed in Patent Document 1. FIG. 16A shows a plurality of cells between a pair of front-stage and rear-stage flip-flops (sequential circuits). 16 (b) shows a state where one of the cells in the signal path shown in FIG. 16 (a) is replaced with a cell having a short delay time, and FIG. A signal path in which only a cell having a minimum delay value is interposed between a pair of front-stage and rear-stage flip-flops is shown.

  In the semiconductor integrated circuit correction device disclosed in Patent Document 1, for example, as shown in FIG. 16A, when the signal path Pa between the flip-flops 20a and 20b causes a timing violation, the timing violation is detected. Replacing a cell (here, cell [1] 22) which is a timing violation location common to more signal paths among a plurality of cells 21a, 22, 23a and 24a on the signal path Pa that is awake By replacing the cell [1] 22 with a modified cell [1] 22a having a small delay value shown in FIG. 16B, the setup timing violation can be improved.

  However, in the correction method disclosed in Patent Document 1, regarding the setup timing violation, the cell [1] 22 which is a timing violation portion common to more signal paths is added to the cell having the minimum delay value in the existing cell library. Is used, or as shown in FIG. 16C, the path signal Pa causing the timing violation is the cell 21a having the minimum delay value that realizes the individual logic function among the cells of the existing cell library. , 22a, 23a, and 24a, the existing cell library has a cell having the same function whose delay is smaller than the delay value of the cell used in the signal path for correcting the violation part. Without replacing the cell.

  The hold timing violation is the same as the case of the setup timing violation. If the timing violation path Pa is composed only of the cells with the maximum delay value among the cells of the existing cell library, the existing cell library Since there is no cell having a delay larger than the maximum delay value for correcting the violation part from the cells having the maximum delay value, the cells cannot be exchanged.

  As described above, the correction method disclosed in Patent Document 1 is insufficient as a measure for improving the timing violation so that the semiconductor integrated circuit having the designed layout satisfies the timing constraint.

  Further, in Patent Document 2, in the method of designing a semiconductor device, in order to shorten the design period, an existing cell library includes a plurality of cells having the same function and having the same occupation area and terminal layout as cells having different driving capabilities. A device that has been prepared and that does not require re-placement and wiring after cell replacement is disclosed.

  For example, FIG. 17 is a diagram for explaining cells prepared in advance in an existing cell library, and FIGS. 17A to 17C each have different driving capabilities, occupied areas and terminal arrangements and shapes. Shows the same cells Cef1a, Cef1b, and Cef1c, and FIG. 17D has higher driving ability than the cells Cef1a to Cef1c shown in FIG. 17A to FIG. A cell Cef1x is shown.

  FIG. 18 is a diagram for explaining a cell having a function different from that of the cell shown in FIG. 17 as a cell prepared in advance in the existing cell library. FIGS. FIG. 18 (d) and FIG. 18 (e) show the cell Cef2a shown in FIGS. 18 (a) to 18 (c). FIG. 18 (d) and FIG. 18 (e) show the cells Cef2a, Cef2b, and Cef2c having the same occupation area and terminal arrangement and shape. The cells Cef2x and Cef2y, which have lower driving capability than the Cef2c, and have different occupation areas and terminal arrangements or shapes, are shown.

  In the design method disclosed in Patent Document 2, for example, as a registered cell, as shown in FIGS. 17A to 17C, the same arithmetic function (for example, a first stage composed of a two-stage CMOS inverter is used. Buffer circuit), a plurality of cells Cef1a, Cef1b, and Cef1c having the same circuit occupation area (vertical and horizontal layout dimensions), the same terminal arrangement, the same terminal shape, and different drive capacities in the existing cell library Prepare.

  Then, the cell at the timing violation, for example, the reference cell Cef1a shown in FIG. 17A is replaced with a cell Cef1b shown in FIG.

  In this case, the cell Cef1a at the location where the timing is violated and the cell Cef1b to be replaced with the cell Cef1b only have different driving capabilities, and the circuit occupation area (vertical and horizontal layout dimensions), terminal arrangement and terminal shape are the same, so the cell is replaced. After that, there is no need to perform placement and routing again, and the processing process for improving the timing violation is simplified.

  It should be noted that the timing violation can be similarly improved when the cell Cef2a shown in FIG. 18A, which has a circuit configuration different from that of the cell Cef1a shown in FIG.

  That is, for example, as a registered cell, as shown in FIG. 18A to FIG. 18C, it has the same arithmetic function (for example, a two-stage CMOS inverter having a different configuration from the first buffer circuit). A second buffer circuit), a plurality of cells Cef2a, Cef2b, and Cef2c having circuit occupying areas (vertical and horizontal layout dimensions), terminal arrangements and terminal shapes, and having different drive capacities are stored in an existing cell library. deep.

  Then, the cell of the path whose timing has been violated, for example, the reference cell Cef2a shown in FIG. 18A is replaced with a cell Cef2b shown in FIG. 18B, which differs from the reference cell Cef2a only in driving capability.

  In this case, the cell Cef2a at the location where the timing is violated and the cell Cef2b to be replaced with the cell Cef2b only have different driving capabilities, and the circuit occupation area (vertical and horizontal layout dimensions), terminal arrangement, and terminal shape are the same. After that, there is no need to perform placement and routing again, and the processing process for improving the timing violation is simplified.

  However, in the method disclosed in Patent Document 2, cells having the same function prepared in the existing cell library have the same circuit occupation area, terminal arrangement, and terminal shape. A cell Cef1x having a larger driving capability with a changed circuit occupation area and terminal shape as shown in FIG. 6 cannot be prepared, which may be insufficient for improving timing violation.

  Furthermore, as shown in FIGS. 18D and 18E, the reference cell Cef2a is replaced with the reference cell Cef2a by using cells Cef2x and Cef2y in which the layout of the circuit occupation region is changed, thereby reducing the circuit occupation region. Even if it is possible, the design method disclosed in Patent Document 2 has a restriction that the layout of the basic cell and the circuit occupation area is the same for the alternative cell to be replaced with the basic cell. The cell area does not change by the replacement, and therefore, even if the cell is replaced with one having a small driving capability, the advantage of area reduction cannot be obtained.

JP 2005-84795 A JP 2010-27644 A

  As described above, in the conventional method of designing a semiconductor integrated circuit described with reference to FIG. 13, if there is a timing violation path as a result of timing analysis, the cells in the timing violation path are replaced with the cells in the existing cell library. The timing violation is improved by moving the cell for changing the wiring, or delaying the clock signal or the data signal by inserting the cell into the clock path or the data path. Unexpected cell crowding, enormous wiring detours, or many cell insertion points may occur, the degree of congestion of placement cells and wiring increases, wiring shorts occur, and timing constraints are not satisfied I'm sorry. As a result, there is a problem that a large design retrofit is required in the design process, such as returning to the hardware description language and changing the layout design, leading to an increase in the design period.

  Further, in the design method of the semiconductor integrated circuit disclosed in Patent Document 1, regarding the setup timing violation, when there is no cell having a smaller delay than the cell at the violation location in the existing cell library, and for the hold timing violation, the violation location If there is no cell in the existing cell library that has a larger delay than the cell, the cell cannot be exchanged.

  As described above, the method disclosed in Patent Document 1 has a problem that it may be insufficient as a measure for improving the timing violation so that the semiconductor integrated circuit having the designed layout satisfies the timing constraint.

  Furthermore, the semiconductor integrated circuit design method disclosed in Patent Document 2 uses a cell having the same layout as the used cell and the circuit occupying region as the cell to be replaced with the cell used in the signal path. The cell area does not change due to the replacement of the cell. For example, there is a problem that the merit of area reduction cannot be obtained even if the cell of the signal path is replaced with a cell having a smaller driving capability.

  The present invention has been made to solve the above-described problems. When designing a semiconductor integrated circuit using a standard cell, a timing violation in a signal path is detected with an appropriate driving capability and an appropriate occupied area. This makes it possible to eliminate the timing violation while avoiding an unnecessarily large area occupied by the cell. As a result, the semiconductor integrated circuit A semiconductor integrated circuit design method and design apparatus capable of further shortening the design period of the semiconductor integrated circuit, a circuit design program for performing such a semiconductor integrated circuit design method by a computer, and such a circuit design program are stored. An object is to obtain a computer-readable recording medium.

  A semiconductor integrated circuit design method according to the present invention provides a storage device in which a plurality of types of standard cells are stored in advance as a unit of circuit design, and combines the standard cells included in the storage device with an information processing device. A step of arranging the standard cells and wiring between the standard cells so as to constitute the semiconductor integrated circuit based on circuit design data, and among signal paths in the semiconductor integrated circuit Detecting a violation path in which a timing violation has occurred, using at least one standard cell included in the violation path as a replacement target cell, performing an operation of the same logic as each replacement target cell, and the replacement target Creating one or more additional standard cells, each having a driving capability different from that of each cell, for each replacement target cell; Is intended to include a step of replacing with the additional standard cells so that the path to eliminate the ring violations, the objects can be achieved.

  According to the present invention, in the above-described semiconductor integrated circuit design method, the signal path in the semiconductor integrated circuit has first and second logic circuits as the first and second logic circuits, respectively. It is preferable that the logic circuit for transmitting a signal to the second sequential circuit is configured by one or more combinational circuits.

  In the method of designing a semiconductor integrated circuit according to the present invention, in the step of detecting the violation path, a timing violation in the violation path is caused by a signal transmission from the first sequential circuit to the second sequential circuit for a specified time. It is preferable to determine whether it is a setup timing violation that is not in time, or whether a signal transmission from the first sequential circuit to the second sequential circuit is a hold timing violation that is too early than a specified time.

  In the design method of the semiconductor integrated circuit according to the present invention, in the step of detecting the violation path, it is determined whether a timing violation in the violation path is the setup timing violation or the hold timing violation. It is preferable to detect the degree of timing violation as a time difference between the time required for signal transmission and the specified time.

  According to the present invention, in the above-described semiconductor integrated circuit design method, as the violation path, a violation path in which a signal transmission from the first sequential circuit to the second sequential circuit is not in time for a specified time has occurred. Is detected, the step of creating the additional standard cell may create one or more additional standard cells having a driving capability higher than that of the replacement target cell for each replacement target cell in the violation path. preferable.

  According to the present invention, in the method of designing a semiconductor integrated circuit, in the step of replacing the replacement target cell with the additional standard cell, a delay time is selected from the plurality of additional standard cells created for each replacement target cell. Is preferably replaced with the smallest additional standard cell.

  According to the present invention, in the above-described semiconductor integrated circuit design method, as the violation path, a violation path in which a signal transmission from the first sequential circuit to the second sequential circuit is too early is a hold timing violation. Is detected, the step of creating the additional standard cell may create one or more additional standard cells having a driving capability lower than that of the replacement target cell for each replacement target cell in the violation path. preferable.

  According to the present invention, in the method of designing a semiconductor integrated circuit, in the step of replacing the replacement target cell with the additional standard cell, a delay time is selected from the plurality of additional standard cells created for each replacement target cell. Is preferably replaced with the largest additional standard cell.

  According to the present invention, in the method for designing a semiconductor integrated circuit, the sequential circuit is preferably a flip-flop circuit.

  According to the present invention, in the method for designing a semiconductor integrated circuit, the step of generating the additional standard cell includes a new cell library including the generated additional standard cell, the default standard cell being created in the storage device. It is preferable to include the step of creating in the storage device in addition to the existing cell library.

  According to the present invention, in the semiconductor integrated circuit design method, the storage device stores the new cell library created when designing one semiconductor integrated circuit so that it can be used in the next semiconductor integrated circuit design. In the step of replacing the replacement target cell with the additional standard cell, the replacement cell is included in the existing cell library and the new cell library created in the previous design of the semiconductor integrated circuit, which are stored in the storage device. Preferably, the replacement target cell is replaced with a standard cell selected from existing standard cells and additional standard cells.

  According to the present invention, in the method of designing a semiconductor integrated circuit, in the step of creating the additional standard cell, the additional standard cell has a driving capability different from that of the replacement target cell and is occupied by the replacement target cell. It is preferable to create one or more additional standard cells having different values for each replacement target cell.

  According to the present invention, in the semiconductor integrated circuit design method, in the step of detecting the violation path, the signal path in the semiconductor integrated circuit obtained by performing the placement of the standard cells and the wiring between the standard cells is a timing violation. It is preferable to determine whether or not the violation path has occurred in all signal paths in the semiconductor integrated circuit.

  In the design method of the semiconductor integrated circuit according to the present invention, the step of creating the additional standard cell is a step of extracting arrangement information indicating arrangement of the constituent members corresponding to all types of standard cells in the violation path. The arrangement of one or more additional standard cells that perform the same logical operation as that of each standard cell and have a driving capability different from that of the standard cell for all types of standard cells based on the respective arrangement information Preferably creating information.

  A semiconductor integrated circuit design apparatus according to the present invention includes a storage device that stores a plurality of types of standard cells in advance as a circuit design unit, and a semiconductor integrated circuit is designed by combining the standard cells included in the storage device. An apparatus for designing an integrated circuit, comprising: a cell placement / wiring unit for placing the standard cells and wiring between the standard cells so as to configure the semiconductor integrated circuit based on circuit design data; Of the signal paths, a violation path detection unit for detecting a violation path in which a timing violation has occurred, and at least one standard cell included in the violation path as a replacement target cell, the same logical operation as each replacement target cell And an additional cell creation unit that creates, for each replacement target cell, one or more additional standard cells having a driving capability different from that of the replacement target cell, and Violation path is one that includes a cell replacement section replacing in the additional standard cells so that the path to eliminate the timing violation, the objects can be achieved.

  The circuit design program according to the present invention is a circuit design program for performing each step in the above-described method for designing a semiconductor integrated circuit according to the present invention by a computer, thereby achieving the above object.

  A computer-readable recording medium according to the present invention is a computer-readable recording medium in which the above-described circuit design program according to the present invention is recorded, whereby the above object is achieved.

  Next, the operation will be described.

  In the present invention, in a method for preparing a semiconductor device in which a plurality of types of standard cells are stored in advance as a unit of circuit design and combining the standard cells included in the storage device with a computer, Of the signal path in the semiconductor integrated circuit obtained by arranging the standard cells and wiring between the standard cells based on the standard cell, and detecting a violation path in which the timing violation has occurred, and then, the standard cells included in the violation path As an additional cell to be replaced with, the same logical operation as the standard cell of the violation route is performed, and one or more additional standard cells having different driving ability from the standard cell of the violation route are created. Using an additional standard cell other than the cell, it is possible to remove the timing violation of the violation route where the timing violation has occurred. Since the choices of the cell to be used for timing improve this way violation path spreads, it is possible to perform timing improved violations path more easily.

  According to the present invention, when detecting a violation path, is the timing violation in the violation path a setup timing violation in which signal transmission from the first sequential circuit to the second sequential circuit is not in time for the specified time? Since it is determined whether the signal transmission from the first sequential circuit to the second sequential circuit is a hold timing violation that is too early than the specified time, the driving that is determined to be effective in improving the timing violation path from the result of the timing analysis Only those having the capability can be created as additional standard cells. By using such additional standard cells, the timing violation path can be effectively improved.

  Further, in the present invention, when detecting the violation route, it is determined whether the timing violation in the violation route is the setup timing violation or the hold timing violation, and the degree of the determined timing violation is determined as follows: Since it is detected as a time difference between the time required for signal transmission and the specified time, the target value of the driving capacity of the additional cell to be created is set in consideration of the degree of timing violation, and the driving capacity of the additional cell is set to the target value. By setting the drive capacity in steps within a certain range centered on the, it is possible to obtain a cell that can eliminate the timing violation as an additional cell to improve the timing violation path, while the driving capacity is large. The adverse effect of being too small or too small can be avoided.

  In the present invention, the new cell library created when designing one semiconductor integrated circuit is stored in the storage device so that it can be used in the next semiconductor integrated circuit design. Each time an integrated circuit is developed, the number of new cell libraries increases to 1, 2, 3, etc., and the number of cell options for further timing adjustment increases, making it easier to improve timing and improving timing. The design period can be shortened by effectively reducing the number of paths.

  As described above, according to the present invention, when designing a semiconductor integrated circuit by performing an arrangement of standard cells and wiring between the standard cells based on circuit design data by an arithmetic processing unit such as a computer, Among the signal paths in the semiconductor integrated circuit obtained by arrangement and wiring between the standard cells, a violation path in which a timing violation has occurred is detected, and then the violation path is used as an additional cell to be replaced with the standard cell included in the violation path. Since one or more additional standard cells that perform the same logic operation as the standard cell and have a different driving capability from the standard cell of this violation path are created, when designing a semiconductor integrated circuit using the standard cell, , Timing violations in the signal path can be eliminated using the desired cell with the appropriate drive capability and the appropriate occupation area, Effect which can be occupied area of Le to easily eliminate timing violations while avoiding becoming unnecessarily large is obtained.

  As a result, a semiconductor integrated circuit design method and design apparatus capable of further shortening the design period of the semiconductor integrated circuit, a circuit design program for performing such a semiconductor integrated circuit design method by a computer, and the like A computer-readable recording medium storing a circuit design program can be realized.

FIG. 1 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, and shows a configuration of a standard cell. FIG. 3 is a diagram for explaining a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention, and shows a process in a design method by the design apparatus in a flowchart. 4A and 4B are diagrams for explaining a design method by the semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention. FIGS. 4A and 4B show logic symbols and circuit diagrams of used cells. 4 (c) shows the layout of the used cells, and FIGS. 4 (d) to 4 (f) show the layouts of three additional cells. FIG. 5 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, and specifically shows processing for improving a setup timing violation in this design method. FIG. 6 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, and specifically shows a process for improving a hold timing violation in this design method. FIG. 7 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention, in which a setup timing violation (FIG. 7A) and a setup timing violation are avoided (FIG. 7B). )). FIG. 8 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention, in which the hold timing violation (FIG. 8A) and the hold timing violation are avoided (FIG. 8B )). FIG. 9 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 2 of the present invention. FIG. 10 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 3 of the present invention. FIG. 11 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 4 of the present invention. FIG. 12 is a diagram for explaining a design method by the semiconductor integrated circuit design apparatus according to the fourth embodiment of the present invention, and shows a process in this design method in a flowchart. FIG. 13 is a diagram for explaining a conventional method for designing a semiconductor integrated circuit, and shows a process in this design method in a flowchart. FIG. 14 is a diagram for explaining a conventional method for designing a semiconductor integrated circuit, and specifically shows processing for improving a setup timing violation in this design method. FIG. 15 is a diagram for explaining a conventional method for designing a semiconductor integrated circuit, and specifically shows processing for improving a hold timing violation in this design method. FIG. 16 is a diagram for explaining a circuit correction method in the semiconductor integrated circuit design method disclosed in Patent Document 1. A timing violation path (FIG. 16A) and a path with improved timing violation (FIG. 16B). ), And a timing violation path (FIG. 16C) configured by only cells having the minimum delay time in the cell library. FIG. 17 is a diagram for explaining a timing violation improving method in the semiconductor integrated circuit design method disclosed in Patent Document 2. FIGS. 17A to 17C are registered in the cell library in advance. A logic cell having the first function is shown, and FIG. 17D shows a logic cell having the same function having a large driving capability that is not registered in the cell library. FIG. 18 is a diagram for explaining a timing violation improving method in the semiconductor integrated circuit design method disclosed in Patent Document 2. FIGS. 18A to 18C are registered in the cell library in advance. A logic cell having the second function is shown. FIGS. 18D and 18E show logic cells having the same function and having a small occupied area which are not registered in the cell library.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention.

  A semiconductor integrated circuit design apparatus (hereinafter also referred to as a semiconductor design apparatus) 100 according to Embodiment 1 includes a processor (CPU) 110 that performs various arithmetic processes, data used for arithmetic processes, and data obtained as a result of the arithmetic processes. It is realized by a computer system having a storage device 120 including a RAM, a hard disk, and the like, and an input device and an output device (not shown).

  The semiconductor design device 100 stores circuit information of various unit circuits (standard cells) having different functions as a unit of circuit design and attribute information of the unit circuits as cell information in the storage device 120. A semiconductor integrated circuit is designed by combining standard cells in which cell information is stored in the storage device 120 based on circuit design data. Hereinafter, the standard cell is also simply referred to as a cell.

  That is, the semiconductor design apparatus 100 connects circuit design data described in a hardware description language or the like to circuit information of a logic circuit indicated by the circuit design data (that is, connection of components (such as logic gates and power supplies) in the logic circuit). A logic synthesis unit 111 that converts the data into a netlist indicating a relationship, and a placement and routing unit 112 that performs cell placement and wiring between cells based on the netlist so that a semiconductor integrated circuit is configured. .

  The semiconductor design apparatus 100 also detects a violation path (timing violation path) that does not satisfy the timing constraint among signal paths (hereinafter also referred to as signal paths) in the semiconductor integrated circuit (violation path detection section). ) 113, a used cell extracting unit 114 that extracts all types of cells used in the timing violation path, and the same logical operation as that of the extracted cell, and one or more different in driving ability from the extracted cell The additional cell generation unit 115 that generates the additional standard cell (hereinafter referred to as an additional cell) and the cell used for the timing violation path in the additional cell so that the timing violation path becomes a path satisfying the timing constraint. A replacement timing improvement unit 116 is provided.

  In the following description, for simplification of description, cell arrangement and wiring between cells are also referred to as cell arrangement wiring, and further, a cell used for a signal path is also referred to as a used cell.

  Here, the timing analysis unit 113 refers to the cell information stored in the storage device 120 based on the arrangement information (layout data) obtained by the cell arrangement and wiring, and executes the actual signal path in the semiconductor integrated circuit. The delay time in the signal path is obtained from the actual load extraction unit 113a for obtaining the load data (parasitic resistance and parasitic capacitance), the obtained actual load data, and the cell information stored in the storage device 120, and the signal path is timed. And a timing verification unit 113b that performs verification on all signal paths in the semiconductor integrated circuit to verify whether or not the constraint is satisfied.

  The storage device 120 includes a net list storage unit 122 that stores the net list generated by the logic synthesis unit 111, and a layout that stores layout data indicating the layout of the semiconductor integrated circuit obtained by cell placement and routing in the placement and routing unit 112. The data storage unit 123 and the actual load data storage unit 124 that stores the actual load data extracted by the actual load extraction unit 113b based on the layout data. The storage device 120 is created by the existing cell library 121 that stores circuit information and attribute information of a standard cell having a predetermined logical operation function as cell information as a registered cell, and an additional cell creation unit 115. And a new cell library 125 for storing circuit information and attribute information of the added cells as cell information of the added cells.

  Furthermore, the processor 110 includes a control unit 130 that controls the units 111 to 116 that constitute the processor 110 and that exchanges data between the units and the storage device 120.

  Here, each part 111-116 which performs each process is constructed | assembled as a tool with the software in the processor 110. FIG. The new cell library 125 is a cell library that is simply added to the existing cell library 121, and can also be used in the timing analysis unit and the timing improvement unit of a general-purpose design support system that runs on a computer system.

  Here, a program for constructing a tool for executing the processing of each unit is a circuit design program, which is stored in a computer-readable recording medium such as a ROM, a RAM, or a hard disk. By reading out the circuit design program from the recording medium, the units 111 to 116 for executing the processes are constructed as tools in the processor.

  FIG. 2 is a diagram for specifically explaining cell information stored in the cell library, taking an inverter cell as an example.

  Cell information Ce1, Ce1a, and Ce1b shown in FIG. 2 are information related to three inverter cells X1, X1a, and X1b having different driving capabilities, and (cell name), (logic symbol), (circuit diagram), and (layout), respectively. ) And (attribute).

  For example, the cell information Ce1 includes cell name [cell X1] data Nx1, logic symbol data Sx1, circuit diagram data Cx1, layout data Lx1, cell attribute data Px1, and the like. Similarly, the cell information Ce1a includes cell name [cell X1a] data Nx1a, logical symbol data Sx1a, circuit diagram data Cx1a, layout data Lx1a, attribute data Px1a, and the like. ] Data Nx1b, logic symbol data Sx1b, circuit diagram data Cx1b, layout data Lx1b, attribute data Px1b, and the like.

  Here, the layout data is information indicating an arrangement pattern of diffusion regions, gate electrodes, wirings, and contact holes in the CMOS circuit constituting the inverter.

  That is, FIG. 2 shows a layout configuration example of a CMOS inverter circuit including the PMOS transistor MP1 and the NMOS transistor MN1. The gates of the PMOS transistor MP1 and the NMOS transistor MN1 serve as the input terminal IN, and the drains of the PMOS transistor MP1 and the NMOS transistor MN1 serve as the output terminal OUT. The cell X1 has a reference cell layout Lx1, and the cells X1a and X1b each have a driving capability (delay time) changed by changing the gate width (W) with respect to the cell layout of the cell X1. Has a layout.

  Here, all these three cells have the same circuit occupation area (vertical and horizontal layout dimensions), and the arrangement and shape of the input terminal IN and the output terminal OUT formed by the first metal wiring layer M1 are also the same. ing. In the cell X1a, the size of the P-type semiconductor region DFP constituting the PMOS transistor MP1 and the size of the N-type semiconductor region DFN constituting the NMOS transistor MN1 are smaller than those of the cell X1. In the cell X1b, the size of the P-type semiconductor region DFP constituting the PMOS transistor MP1 and the size of the N-type semiconductor region DFN constituting the NMOS transistor MN1 are larger than those of the cell X1. In FIG. 2, PO is a polysilicon layer constituting the gate of the transistor, and CT is a contact layer. Further, the attribute data Px1, Px1a, Px1b includes information indicating the delay time, driving capability, parasitic resistance of the input terminal and output terminal, parasitic capacitance, etc. in each of the inverter cells Ce1, Ce1a, Ce1b.

  Next, the operation will be described.

  FIG. 3 is a diagram for explaining a method of designing a semiconductor integrated circuit according to the first embodiment, and shows a flow of design processing performed by the design apparatus.

  First, logic synthesis (step S1) and placement and routing (step S2) are performed using the existing cell library 121, as in the conventional method of designing a semiconductor integrated circuit.

  That is, in the logic synthesis (step S1), the logic synthesis unit 111 performs a process of converting circuit design data described in a hardware description language (HDL) or the like into a netlist. Here, the netlist is a logic circuit that realizes a circuit function described in a hardware description language (HDL) or the like, and connects a combinational circuit or a sequential circuit that is a cell stored in the existing cell library 121. Circuit information indicating the logic circuit obtained in this way.

  In the subsequent placement and routing (step S2), the placement and routing unit 112 performs cell placement and routing using cells of the existing cell library 121 according to the connection relationship indicated by the netlist. That is, based on cell information stored in the existing cell library 121, cells such as combinational circuits and sequential circuits are arranged, and wiring between the arranged cells is performed. The layout data indicating the layout is stored in the layout data storage unit 123.

  In the first timing analysis after this placement and routing, each signal path in the semiconductor integrated circuit (logic circuit) in which the timing analysis unit 113 uses only the cell information of the existing cell library 121 to determine the layout of the cells and wirings. Perform timing analysis for.

  In other words, the timing analysis unit 113 uses only the existing cell library 121 to extract delay information that is attribute information of individual types of cells on the signal path between the preceding and succeeding sequential circuits (flip-flops) (steps). S3) Whether the signal path satisfies the timing constraint, that is, the signal delay time between the preceding flip-flop that is the starting point of the signal path and the succeeding flip-flop that is the ending point of the signal path satisfies the timing constraint. It is determined whether it is a thing (step S4).

  More specifically, in this timing analysis, the actual load extraction unit 113a is stored as cell information in the existing cell library 121 based on layout data indicating the arrangement of cells and the arrangement of wiring between cells in the semiconductor integrated circuit. The actual load data (parasitic components such as parasitic resistance and parasitic capacitance in the elements and wiring) is obtained by referring to the specification information of the various cells, and the timing verification unit 113b uses the actual load data for each signal path. The delay information is extracted, and the timing at which the signal reaches each flip-flop is calculated.

  As a result, when the timing violation has not occurred, the timing verification is finished. On the other hand, when the timing violation has occurred, the used cell extraction unit 114 extracts the cell information related to the used cell on the timing violation path ( Step S11).

  For example, as shown in FIG. 5 or FIG. 6, when the signal path Dpx or Dpy in the semiconductor integrated circuit causes a timing violation, the used cell extraction unit 114 starts from one flip-flop (previous flip-flop) FF1 to the next stage. Cell information relating to all cells (used cells) on the signal path Dpx to the first flip-flop (second-stage flip-flop) FF2 is extracted from the existing cell library 121.

  Next, the additional cell creation unit 115 performs a process of creating a new additional cell having a driving capability different from that of the used cell (step S12).

  In the process of newly creating an additional cell having a different driving capability, circuit information indicating the created additional cell and its attribute information are stored in the new cell library 125 as cell information of the additional cell.

  Specifically, for the used cell from which the cell information is extracted in the previous step (step S11), an additional cell having the same function and a small driving capability, or an additional cell having the same function and a large driving capability, etc. As shown in FIG. 6, a large number of additional cells having propagation delay times different from the used cells are newly created, and circuit information and attribute information thereof are stored in the new cell library 125 as cell information of the additional cells.

  Such additional cells having different driving capabilities from the used cells are created for all types of used cells used on the timing violation path.

  In the next timing improvement (step S5), the timing in each timing violation path is optimized.

  Specifically, the timing improvement unit 116 uses the new cell library 125 in which cell information of an additional cell having a different driving capability from the cells of the existing cell library is used, and uses the cells on the timing violation path, Cell replacement processing that replaces additional cells with the same function and different delay time, or wiring change processing that changes the layout of wiring placed between used cells, so that this timing violation path satisfies timing constraints Do. Thereby, the arrangement of the cells and the wiring between the cells are optimized, and the delay time in the signal path is optimized.

  Next, the timing analysis process (step S3) is performed again. At this time, the timing analysis unit 103 uses both the existing cell library 121 and the newly added new cell library 125 to extract delay information of each signal path, and determines whether each signal path satisfies the timing constraint. To do. If each signal path satisfies the timing constraint, the design of the semiconductor integrated circuit to be designed is completed, and the design apparatus 100 proceeds to the next design stage.

  On the other hand, if there is a signal path that does not satisfy the timing constraint, cell information of the used cell on the timing violation path is extracted (step S11), and the same function as the used cell from which the cell information is extracted has a different driving capability. The newly added cell is newly created and the cell information is added to the new cell library (step S12), the timing improvement process is performed using the created additional cell (step S5), and then the timing analysis process (step S3) is performed again. )I do.

  By adding a new cell library as described above, the number of cell choices when performing timing adjustment is increased, and timing violations that cannot be improved only by a cell library registered in advance can be removed.

  The process of newly creating an additional cell having a driving capability different from that of the used cell (step S12) is performed after extracting the cell information of the used cell on the timing violation path when there is a timing violation path. Although it may be performed by using cell information of a cell stored in the cell library or a new cell library that has already been created, as described below with reference to FIGS. 5 and 6, on the timing violation path, Even if the used cell is replaced with an existing cell whose cell information is stored in an existing cell library or a new cell library that has already been created, an additional cell with a different driving capability from the above used cell is added only if the timing violation is not resolved. You may make it perform the process (step S12) created.

  In addition, when there is a timing violation path, the characteristics (driving capacity or cell occupied area) to be replaced with the cell used in the timing violation path in the existing cell library or the existing cell in which the cell information is already stored in the newly created cell library ), There is always a process of newly creating an additional cell having a driving capability different from that of the used cell (step S12).

  Hereinafter, an example of cell creation processing and timing improvement processing performed by the design apparatus according to the first embodiment will be specifically described.

  First, a specific example of the cell creation process will be described.

  FIG. 4 is a diagram for explaining a process of performing an operation with the same logic as the NAND cell and creating an additional cell having a different driving capability from the NAND cell as the existing cell whose cell information is stored in the existing cell library 121. It is.

  For example, when the used cell extraction unit 114 extracts the NAND cell C1 whose cell information is stored in the existing cell library 121 as one of the used cells in the timing violation path, the additional cell creation unit 115 Cell information (cell name data (not shown), logic symbol data Sc1 (FIG. 4 (a)), circuit diagram data Cc1 (FIG. 4 (b)), layout data Lc1 of the NAND cell C1 stored in 121. Based on (FIG. 4C), attribute data (not shown), etc., the same logic operation as this NAND cell C1 is performed, and cell information of an additional cell having a different driving capability is newly created. The cell information of this additional cell is stored in the new cell library 125.

  FIGS. 4D to 4F respectively show layouts Lc1a, Lc1b, and Lc1c of the additional cells when the first to third additional cells that differ only in driving capability from the existing cell C1, for example, are created. Show.

  4 (a) to 4 (f), MP1a and MP1b are PMOS transistors constituting the NAND cell C1, MN1a and MN1b are NMOS transistors constituting the NAND cell C1, and IN1 and IN2 are this An input terminal OUT of the NAND cell is an output terminal thereof, and these terminals are constituted by the first metal layer M1. Further, DFP is a P-type semiconductor region constituting the PMOS transistors MP1a and MP1b, DFN is an N-type semiconductor region constituting the NMOS transistors MN1a and MN1b, PO is a polysilicon layer constituting the gate electrode of the transistor, CT is a contact layer.

  In the layout Lc1a of the first additional cell, the dimension in the gate width W direction of the P-type semiconductor region PFN and the N-type semiconductor region DFN is smaller than the layout Lc1 of the existing cell C1.

  Also, in the layout Lc1b of the second additional cell, only the dimension in the gate width W direction of the N-type semiconductor region DFN is smaller than the layout Lc1 of the existing cell C1, and in the layout Lc1c of the third additional cell, Compared to the layout Lc1 of the existing cell C1, only the dimension in the gate width W direction of the P-type semiconductor region DFP is made smaller, and the first to third additional cells have a driving capability changed from that of the existing cell C1. It has become.

  The additional cell creation unit 115 creates such additional cell layouts Lc1a to Lc1c based on the layout Lc1 of the existing cell C1.

  Then, based on the layout information of the changed additional cell, the attribute information of the additional cell is created as a change of the attribute information such as the driving capability and delay time of the existing cell, and the cell name is created as the cell information of the created additional cell. The layout data and attribute information are stored in the new cell library 125 together with the data and the circuit diagram data.

  Further, in FIG. 4, as the additional cell layouts Lc1a to Lc1c, the existing cell occupation area (that is, vertical and horizontal sizes) and the additional cell occupation area (that is, vertical and horizontal sizes) are the same. In the present invention, there is no restriction that the additional cell layouts Lc1a to Lc1c must be created so that the area occupied by the additional cells is the same as that of the existing cells. In other words, the layout may be different from that of the existing cell, in which the vertical and horizontal sizes) correspond to the driving ability.

  Next, a specific example of timing improvement will be described.

  First, the setup timing violation and its improvement will be described.

  As a result of the timing analysis, it is assumed that a setup timing violation has occurred in the signal path Dpx from the flip-flop FF1 to the flip-flop FF2, as shown in FIG.

  The setup timing violation is an error in which the flip-flop cannot latch the correct data because the subsequent flip-flop cannot secure enough time to hold the data before the clock signal changes, and FIG. It is explanatory drawing of a setup timing violation.

  Here, the cycle of the clock CK is 10 ns, for example. The output Q of the front-stage flip-flop FF1 shown in FIG. 5 changes with a delay of 1 ns from the falling edge of the clock CK. The signal delay between the two flip-flops is the sum of the delay values of the cells between them, for example 8.5 ns. Here, the setup time of the rear-stage flip-flop FF2 (a period during which the data D does not change, which is necessary before the falling of the clock for latching the data D) is 1 ns. In this case, as shown in FIG. 7A, an error occurs if the data D changes within 1 ns before the fall of the clock CK. For example, if the input data D of the flip-flop F22 changes 0.5 ns before the falling edge of the clock CK, a setup timing violation occurs.

  Therefore, a setup timing violation can be avoided by shortening the signal delay time between these two flip-flops.

  FIG. 7B is a diagram for explaining that the setup timing violation shown in FIG. It can be seen that by reducing the signal delay time of 8.5 ns by 1 ns to 7.5 ns, a margin of 0.5 ns can be made with respect to the setup time.

  Therefore, in the timing improvement shown in FIG. 3 (step S5), the cells used in the timing violation path Dpx are first used by using the cells of the existing cell library 121 so that the time for data transmission from the flip-flop FF1 to the flip-flop FF2 is reduced. Is replaced with the cell with the smallest delay.

  More specifically, when a timing violation path is detected in the first timing analysis, as shown in FIG. 5, from the used cell (delay time 0.10 ns) Uax in the timing violation path Dpx to the cell (delay time 0.09 ns). ) Replacement to A1 and replacement from the used cell (delay time 0.14 ns) Ubx to the cell (delay time 0.12 ns) B1 in the timing violation path Dpx. Note that this cell replacement is performed before an additional cell is created.

  If it is determined in the second timing analysis that the violation is not improved even by this replacement, the used cells on the timing violation path Dpx are extracted, and the same function as that of the cell Uax is used, and the driving capability is different. Additional cells NA1 to NA5 are newly created, subdivided additional cells NB1 to NB6 having the same function and different driving capability as the cell Ubx are newly created, and each cell information is stored in the new cell library 125. To store.

  Next, using the additional cells NA1 to NA5 and NB1 to NB6 whose cell information is included in the new cell library 125, the cells in the timing violation path Dpx are replaced with the cells with the smallest delay.

  Specifically, the cell (delay time 0.09 ns) A1 is replaced with the cell (delay time 0.08 ns) NA1, and the cell (delay time 0.12 ns) B1 is replaced with the additional cell (delay time 0.10 ns) NB1. Replace. By adding the new cell library 125 in this way, options for timing adjustment are increased, and timing violations that cannot be improved only by the existing cell library 121 registered in advance can be removed.

  Next, the hold timing violation and its improvement will be briefly described.

  As a result of the timing analysis, it is assumed that a hold timing violation has occurred in the signal path Dpy from the flip-flop FF3 to the flip-flop FF4 as shown in FIG.

  The hold timing violation is an error in which sufficient time for correctly latching data after the change of the clock signal cannot be secured, and FIG. 8 is an explanatory diagram of this error.

  Here, the cycle of the clock CK is 10 ns. In addition, the hold time (a period during which the data D does not change that is required after the falling timing of the clock for latching the data D) is 1.5 ns. In this case, if the data D changes within 1.5 ns from the falling edge of the clock CK, a hold timing violation occurs. For example, in FIG. 8A, since the data D changes at 0.5 ns from the falling edge of the clock CK, a hold timing violation occurs.

  Therefore, a hold timing violation can be avoided by increasing the signal delay between these two flip-flops.

  FIG. 8B is a diagram for explaining that the hold timing violation shown in FIG. By delaying the signal delay time 8.5 ns by 2 ns and making it 10.5 ns, a margin of 1 ns can be made with respect to the hold time.

  Therefore, in the timing improvement shown in FIG. 3 (step S5), the cells used in the timing violation path Dpy are first used by using the cells of the existing cell library 121 so that the time for data transmission from the flip-flop FF3 to the flip-flop FF4 is increased. To the cell with the longest delay.

  Specifically, when a timing violation path is detected in the first timing analysis, the used cell (delay time: 0.10 nm) Uay in the timing violation path Dpy is replaced with the cell (delay time: 0.13 nm) A3. In addition, the used cell (delay time: 0.14 nm) Uby in the timing violation path Dpy is replaced with the cell (delay time: 0.15 nm) B3.

  If it is determined in the second timing analysis that the violation is not improved even by this replacement, the used cells on the timing violation path Dpy are extracted, and the same function as the cell Uay has the same function but the driving capability is subdivided. Additional cells NA1 to NA5 are newly created, subdivided additional cells NB1 to NB6 having the same function and different driving capability as the cell Ubx are newly created, and each cell information is stored in the new cell library 125. To store.

  Next, using the additional cell whose cell information is included in the new cell library 125, the cell in the timing violation path Dpy is replaced with the cell having the longest delay.

  Specifically, the cell (delay time: 0.13 nm) A3 is replaced with the additional cell (delay time: 0.15 nm) NA5, and the cell (delay time: 0.15 nm) B3 is replaced with the cell (delay time: 0.18 nm). ) Replace with NB6.

  By adding the new cell library 125 in this way, the choices for timing adjustment increase, and timing violations that could not be improved only by the cell library registered in advance can be removed.

  Therefore, in the first embodiment, the ease of timing improvement is improved, and the design period can be shortened by reducing the number of paths that require timing improvement. Further, there is a case where the cell insertion shown in FIG. 14 and FIG.

In the semiconductor integrated circuit design apparatus 100 according to the first embodiment as described above, based on the circuit design data, the placement and routing unit 112 that places standard cells and performs wiring between the standard cells so as to constitute the semiconductor integrated circuit. A timing analysis unit 113 for detecting a violation path in which a timing violation occurs in the signal path in the semiconductor integrated circuit, and at least one standard cell included in the violation path as a replacement target cell, An additional cell creation unit 115 that performs one or more additional standard cells that perform the same logical operation as that of the target cell and that has a driving capability different from that of the replacement target cell; If a timing violation path is included in a semiconductor integrated circuit obtained by performing placement and routing using, what is a cell in an existing cell library? Since an additional cell of the same function with a different dynamic capability is newly created, it becomes possible to remove the timing violation of the violation route where the timing violation has occurred by using an additional standard cell other than the standard cell prepared in advance. Since there are more choices of cells used to improve the timing of violation paths, the timing improvement for timing violation paths can be made easier, and the design period of semiconductor integrated circuits can be shortened by reducing the number of paths that require timing improvements. It becomes possible.
(Embodiment 2)
FIG. 9 is a diagram for explaining a semiconductor integrated circuit design apparatus according to Embodiment 2 of the present invention.

  A semiconductor integrated circuit design apparatus (hereinafter referred to as a semiconductor design apparatus) 200 according to the second embodiment replaces the additional cell creation unit 115 in the semiconductor integrated circuit design apparatus 100 of the first embodiment with the timing violation being a setup timing. If it is a violation, an additional cell having a driving capability larger than that of the cell used in the timing violation path is created. If the timing violation is a hold timing violation, the additional cell having a driving capability smaller than that of the cell used in the timing violation path is created. Is provided with an additional cell creation unit 215 for creating

  Therefore, the semiconductor design apparatus 200 according to the second embodiment includes a timing analysis unit 213 that replaces the timing analysis unit 113 according to the first embodiment, and the timing analysis unit 213 is the same as the timing analysis unit 113 according to the first embodiment. The load extraction unit 113a and the timing verification unit 113b are included, and the additional cell creation unit 215 is notified as to whether the timing violation is a setup timing violation or a hold timing violation as a result of the timing analysis.

  Other configurations of the semiconductor design apparatus 200 of the second embodiment are the same as those of the semiconductor design apparatus 100 of the first embodiment.

  In the semiconductor design apparatus 200 according to the second embodiment having such a configuration, in addition to the effects of the first embodiment, only an additional cell having a driving capability that is determined to be effective in improving the timing violation path from the result of the timing analysis. The timing violation path can be effectively improved.

In the second embodiment, when a setup timing violation path is detected, an additional cell having a higher driving capability than that of the standard cell is created to perform the same logical operation as that of the standard cell of the timing violation path. When a path is detected, an operation is performed in which the same logic as that of the standard cell of the violation path is generated, and an additional cell having a lower driving ability than the standard cell is shown. , The standard cell in the setup timing violation path is replaced with an additional cell with the smallest delay time (that is, the additional cell with the maximum driving capacity), and the standard cell in the hold timing violation path is replaced with an additional cell with the largest delay time (that is, An additional cell having the minimum driving capability may be replaced.
(Embodiment 3)
FIG. 10 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 3 of the present invention.

  A semiconductor integrated circuit design apparatus (hereinafter referred to as a semiconductor design apparatus) 300 according to the third embodiment replaces the timing analysis unit 213 in the semiconductor design apparatus 200 according to the second embodiment and holds whether or not the timing violation is a setup timing violation. The timing analysis unit 313 is configured to determine whether or not it is a timing violation and to detect the degree of each timing violation.

  That is, the timing analysis unit 313 of the semiconductor design apparatus 300 according to the third embodiment replaces the timing verification unit 113b in the timing analysis unit 113 according to the first embodiment with a setup timing violation or hold timing violation during the timing analysis. The timing for detecting the time difference between the signal transmission time obtained by the timing verification in the timing violation path and the normal time (specified time) required for the original signal transmission based on the timing constraint in the timing violation path The verification unit 313b has a timing analysis result, and notifies the additional cell creation unit 315 of the timing violation as the time difference and whether the timing violation is a setup timing violation or a hold timing violation. It has a configuration that.

  In addition, the semiconductor design apparatus 300 according to the third embodiment is replaced with the additional cell creation section 215 in the semiconductor design apparatus 200 according to the second embodiment, and an additional cell creation section that sets the drive capability of the created additional cell based on the time difference. 315 is provided.

  That is, when the timing violation is a setup timing violation, the additional cell creation unit 315 creates an additional cell having a driving capability larger than the used cell in the timing violation path, and the timing violation is a hold timing violation. In the timing violation path, an additional cell having a smaller driving capability than the cell used in the timing violation path is created, and when creating the additional cell, the target value of the driving capability of the additional cell to be created is taken into consideration. A value is set so that the timing violation can be resolved without excess or deficiency, and the drive capacity of the additional cell is set by changing stepwise within a certain range centered on the target value.

  In the semiconductor design apparatus 300 of the third embodiment having such a configuration, in addition to the effects of the first embodiment, the target value of the driving capability of the additional cell to be created is set in consideration of the timing violation, and this target Since the drive capacity of the additional cell is set by converting the drive capacity in steps within a certain range centered on the value, an additional cell that can eliminate the timing violation can be obtained as an additional cell for improving the timing violation path. On the other hand, it is possible to avoid a problem that a bad effect caused by the driving capability being too large or too small.

For example, when an additional cell having a larger driving capability than that of the used cell is created for the used cell in the setup timing violation path, the used cell is replaced with this additional cell if the driving capability of the additional cell is too large. This causes a harmful effect that the occupied area of the cell becomes unnecessarily large. However, as in the third embodiment, the target value of the driving capability of the additional cell to be created is set in consideration of the degree of timing violation. An additional cell that occupies an unnecessarily large area as an additional cell to eliminate the setup timing violation by setting the drive capacity of the additional cell by changing the drive capacity stepwise within a certain range centered on the target value Can be avoided.
(Embodiment 4)
FIG. 11 is a block diagram illustrating a semiconductor integrated circuit design apparatus according to Embodiment 4 of the present invention.

  A semiconductor integrated circuit design device (hereinafter referred to as a semiconductor design device) 400 according to the fourth embodiment includes a storage device 420 and a control unit 430 in place of the storage device 120 and the control unit 130 in the semiconductor design device 100 of the first embodiment. The control unit 430 stores the new cell library created when designing one semiconductor integrated circuit in the storage device 420 so that it can be used in the next semiconductor integrated circuit design. is there.

  Further, in the semiconductor design device 400 of the fourth embodiment, the timing improvement unit 416 assigns the used cells in the timing violation path to all the cell libraries included in the storage device 420, for example, three new cell libraries in the storage device 420. If formed, the existing cell library 121 and the new cell library group 425 are replaced with cells selected from all the new cell libraries [I] 425a to [III] 425c.

  In the semiconductor design apparatus 400 having such a configuration, when designing one semiconductor integrated circuit, as in the semiconductor design apparatus 100 of the first embodiment, logic synthesis (step S1), placement and routing (step S2), timing analysis ( Steps S3 and S4) and extraction of used cells on the timing violation path (step S11) are performed.

  In the subsequent additional cell creation (step S12a), an additional cell that replaces the used cell of the timing violation path is created, and the created additional cell is stored in the new cell library 425a. Thereafter, in the timing improvement (step S5), a predetermined cell is selected from a plurality of cells whose cell information is stored in the new cell library [I] 425a and the existing cell library 121, and the used cell is replaced with the selected cell. It is determined again by timing analysis whether there is a timing violation path. Such additional cell creation and subsequent timing analysis are repeated to design a semiconductor integrated circuit free from timing violation.

  At this time, in the semiconductor design apparatus 400 according to the fourth embodiment, the new cell library [I] created when designing one semiconductor integrated circuit can be used in the next semiconductor integrated circuit design. It remains stored at 420.

  Therefore, in the next design of the semiconductor integrated circuit, if a timing violation has occurred in the first timing analysis process after the placement and routing process (step S3), the used cell extraction unit 114 sets the used cell on the timing violation path. Extract cell information. With respect to the used cells from which the cell information has been extracted, the additional cell creation unit 115 newly creates a number of additional cells having different driving capabilities. In the storage device 420, a second new cell library [II] including the newly created additional cell is created. 425b is created.

  Next, the timing improvement unit 116 improves the timing by using the existing cell library 121, the first new cell library 425a previously created and the second new cell library 425b created this time.

  Therefore, in the next design of the semiconductor integrated circuit, in the first timing analysis process after the placement and routing process (step S3), the existing cell library 121 and the new cell library created in the design of the first semiconductor integrated circuit [ I] 425a and the cell of the new cell library [II] 425b created in the design of the second semiconductor integrated circuit can select a cell to be replaced with a cell used for the timing violation path.

  In designing the third semiconductor integrated circuit, the existing cell library 121 and the new cell libraries [I] 425a and [II] 425b created by designing the first and second semiconductor integrated circuits are also included. If there is no suitable cell to replace the used cell, an additional cell is created to create a new cell library [III] 425c.

  As described above, in the semiconductor design apparatus 400 according to the third embodiment, each time a semiconductor integrated circuit is developed, the number of new cell libraries is increased to one, two, three, etc., so that there are options for further timing adjustment. The ease of timing improvement is greatly increased, and the design period can be further shortened by effectively reducing the number of paths that require timing improvement.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a timing in a signal path when designing a semiconductor integrated circuit using a standard cell in the fields of a semiconductor integrated circuit design method, a semiconductor integrated circuit design apparatus, a circuit design program, and a computer-readable recording medium. Violations can be resolved using a desired cell with the right drive capability and the right occupancy area, which makes it easy to eliminate timing violations while avoiding unnecessarily large cell occupancy areas Semiconductor integrated circuit design method and design apparatus capable of further shortening the design period of the semiconductor integrated circuit, and a circuit design program for performing such a semiconductor integrated circuit design method by a computer And a computer-readable recording medium storing such a circuit design program It is possible.

100, 200, 300, 400 Semiconductor design device 111 Logic synthesis unit 112 Placement and wiring unit 113 Timing analysis unit (violation path detection unit)
113a, 213a Actual load extraction unit 113b, 213b, 313b Timing verification unit 114 Used cell extraction unit 115 Additional cell creation unit 116, 416 Timing improvement unit 120, 420 Storage device 121 Existing cell library 122 Netlist storage unit 123 Layout data storage unit 124 Actual load data storage unit 125 New cell library 130, 430 Control unit 425 New cell library group 425a to 425c New cell library [I] to [III]
A1 to A3, B1 to B3 Cell C1, Ce1, Ce1a, Ce1b Cell information Cc1, Cx1, Cx1a, Cx1b Circuit diagram data CK clock Dpx, Dpy Timing violation path FF1 to FF4 Flip-flops Lc1, Lc1a, Lc1b, Lc1c Layout Lx1a, Lx1b Layout data NA1 to NA5, NB1 to NB6 Additional cells Nx1, Nx1a, Nx1b Cell name [cell X1] data Px1, Px1a, Px1b Attribute data Q output Sc1, Sx1, Sx1a, Sx1b Logical symbol data Uax, Uab, Ux , Uby use cell

Claims (17)

A method of designing a semiconductor integrated circuit by preparing a storage device storing a plurality of types of standard cells in advance as a unit of circuit design, and combining the standard cells included in the storage device with an information processing device,
Arranging the standard cells and wiring between the standard cells so as to constitute the semiconductor integrated circuit based on circuit design data; and
Detecting a violation path in which a timing violation occurs among signal paths in the semiconductor integrated circuit;
At least one standard cell included in the violation path is used as a replacement target cell, the same logical operation as each replacement target cell is performed, and one or more additional standard cells having different driving ability from the replacement target cell are replaced. Creating for each target cell;
Replacing the replacement target cell with the additional standard cell so that the violation route becomes a route in which the timing violation is resolved.
A method for designing a semiconductor integrated circuit. The method for designing a semiconductor integrated circuit according to claim 1,
The signal path in the semiconductor integrated circuit is a logic circuit for transmitting signals from the first sequential circuit to the second sequential circuit, with the logic circuits serving as the start and end points being first and second sequential circuits, respectively. A method for designing a semiconductor integrated circuit, comprising one or more combinational circuits. The method of designing a semiconductor integrated circuit according to claim 2,
In the step of detecting the violation route,
The timing violation in the violation path is a setup timing violation in which signal transmission from the first sequential circuit to the second sequential circuit is not in time for a specified time, or the second order from the first sequential circuit. A method for designing a semiconductor integrated circuit, wherein it is determined whether a signal transmission to a circuit is a hold timing violation that is too early than a specified time. The method of designing a semiconductor integrated circuit according to claim 3,
In the step of detecting the violation route,
It is determined whether the timing violation in the violation path is the setup timing violation or the hold timing violation, and the degree of the determined timing violation is detected as a time difference between the time required for signal transmission and the specified time. A method for designing a semiconductor integrated circuit. The method of designing a semiconductor integrated circuit according to claim 2,
When a violation path in which a setup timing violation occurs in which signal transmission from the first sequential circuit to the second sequential circuit is not in time for a specified time is detected as the violation path,
In the step of creating the additional standard cell,
A method for designing a semiconductor integrated circuit, wherein one or more additional standard cells having a driving capability higher than that of the replacement target cell are created for each replacement target cell in the violation path. The method of designing a semiconductor integrated circuit according to claim 5,
In the step of replacing the replacement target cell with the additional standard cell,
A method for designing a semiconductor integrated circuit, wherein the replacement target cell is replaced with an additional standard cell having a minimum delay time among a plurality of additional standard cells created for each replacement target cell. The method of designing a semiconductor integrated circuit according to claim 2,
When a violation path in which a hold timing violation occurs in which signal transmission from the first sequential circuit to the second sequential circuit is earlier than a specified time is detected as the violation path,
In the step of creating the additional standard cell,
A method for designing a semiconductor integrated circuit, wherein at least one additional standard cell having a driving capability lower than that of the replacement target cell is created for each replacement target cell in the violation path. The method for designing a semiconductor integrated circuit according to claim 7,
In the step of replacing the replacement target cell with the additional standard cell,
A method for designing a semiconductor integrated circuit, wherein the replacement target cell is replaced with an additional standard cell having the longest delay time among a plurality of additional standard cells created for each replacement target cell. The method for designing a semiconductor integrated circuit according to any one of claims 2 to 8,
A method for designing a semiconductor integrated circuit, wherein the sequential circuit is a flip-flop circuit. The method for designing a semiconductor integrated circuit according to any one of claims 1 to 9,
The step of generating the additional standard cell includes:
A method for designing a semiconductor integrated circuit, comprising: creating a new cell library including the generated additional standard cells in the storage device in addition to the existing cell library including the predetermined standard cells generated in the storage device. . The method of designing a semiconductor integrated circuit according to claim 10,
The storage device is configured to store a new cell library created when designing one semiconductor integrated circuit so that it can be used in the next semiconductor integrated circuit design,
In the step of replacing the replacement target cell with the additional standard cell,
The standard cell selected from the existing standard cell and the additional standard cell included in the existing cell library and the new cell library created in the design of the previous semiconductor integrated circuit, stored in the storage device, and the replacement target A method of designing a semiconductor integrated circuit that replaces cells. The method for designing a semiconductor integrated circuit according to any one of claims 1 to 11,
In the step of creating the additional standard cell,
Design of a semiconductor integrated circuit in which one or more additional standard cells having different driving capabilities from the replacement target cell and having an occupied area different from the replacement target cell are created for each replacement target cell as the additional standard cell Method. The method of designing a semiconductor integrated circuit according to any one of claims 1 to 12,
In the step of detecting the violation route,
It is determined whether the signal path in the semiconductor integrated circuit obtained by arranging the standard cells and performing wiring between the standard cells is a violation path in which a timing violation has occurred. A method for designing a semiconductor integrated circuit, which is performed in a signal path. The method of designing a semiconductor integrated circuit according to any one of claims 1 to 13,
The step of creating the additional standard cell includes:
Extracting arrangement information corresponding to all types of standard cells in the violation path and indicating the arrangement of the constituent members;
For all the types of standard cells, based on the respective arrangement information, the same logical operation as that of each standard cell is performed, and the arrangement information of one or more additional standard cells having a driving capability different from that of the standard cell is obtained. A method for designing a semiconductor integrated circuit, comprising the steps of: A semiconductor integrated circuit design apparatus that has a storage device that stores a plurality of types of standard cells in advance as a unit of circuit design, and designs a semiconductor integrated circuit by combining the standard cells included in the storage device,
Based on circuit design data, a cell placement / wiring unit for placing the standard cells and wiring between the standard cells so as to constitute the semiconductor integrated circuit,
Of the signal paths in the semiconductor integrated circuit, a violation path detection unit for detecting a violation path in which a timing violation occurs;
At least one standard cell included in the violation path is used as a replacement target cell, the same logical operation as each replacement target cell is performed, and one or more additional standard cells having different driving ability from the replacement target cell are replaced. An additional cell creation section created for each target cell;
A cell replacement unit that replaces the replacement target cell with the additional standard cell so that the violation route becomes a route in which the timing violation is resolved,
Semiconductor integrated circuit design equipment.   The circuit design program for performing each step in the design method of the semiconductor integrated circuit of any one of Claims 1-14 with a computer.   A computer-readable recording medium on which the circuit design program according to claim 16 is recorded.