JP2013172108A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical GaN-based semiconductor device with improved withstand voltage performance and a manufacturing method thereof.
SOLUTION: A regrowth layer 27 in which a channel of a wall surface of an opening 28 is formed, a gate electrode G, an n-type GaN-based drift layer 4 located on both sides of the opening or around the opening. A side opening 38 that reaches the inside, and a source electrode S that is electrically connected to the channel and that is positioned to cover the side opening on or around the opening. The side opening 38 is provided with a connection structure 5 that electrically connects the source electrode S to the p-type GaN-based barrier layer and insulates the source electrode S from the n-type GaN-based drift layer.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a vertical semiconductor device used for switching a large current and having a high withstand voltage performance and a manufacturing method thereof.

A switching element for large current is required to have a high reverse breakdown voltage and a low on-resistance. Field effect transistors (FETs) using Group III nitride semiconductors are excellent in terms of high breakdown voltage, high temperature operation, etc. due to their large band gaps, and in particular, transistors using GaN-based semiconductors are It is attracting attention as a high-power control transistor. In particular, vertical transistors that allow current to flow in the thickness direction have attracted attention because they can increase current density. For example, by providing an opening in a GaN-based semiconductor and providing a regrowth layer including a channel of a two-dimensional electron gas (2DEG) on the wall of the opening, the on-resistance is reduced while increasing the mobility. A vertical GaN-based HFET (Heterostructure Field Effect Transistor) has been proposed (Patent Document 1).
On the other hand, in a HEMT structure GaN-based transistor using a two-dimensional electron gas as a channel, when a large current is handled, a high electric field region is generated in the vicinity of the channel drain when a high drain voltage is applied, and avalanche breakdown occurs due to high energy electrons. . Holes are formed by this avalanche breakdown, but since the GaN-based semiconductor is a wide gap, the rate at which the recombination constant largely disappears is small, and holes are accumulated in the i-GaN buffer layer. As a result, a kink phenomenon that leads to channel increase and runaway is caused. In order to suppress this, a structure for forming a hole extraction electrode via an i-GaN layer or a pGaN layer is disclosed (Patent Document 2). Although this GaN-based transistor is a lateral transistor, it is considered that the same hole accumulation occurs in a vertical GaN-based transistor, and the effectiveness of the hole extraction electrode is presumed.

JP 2006-286542 A US Patent US 6,555,851 B2

In the vertical GaN-based transistor using the two-dimensional electron gas as a channel provided with the opening, the on-off threshold voltage is shifted in the positive direction by the back gate effect of the p-type GaN barrier layer, and at a certain level. Longitudinal pressure resistance is obtained. However, in a vertical GaN-based transistor, when a high drain voltage is applied, the electric field concentrates under the gate provided in the opening, so that the withstand voltage performance is greatly restricted. Overcoming such pressure resistance is a problem peculiar to a vertical transistor having an opening.
Furthermore, the p-type GaN-based barrier layer described in the cited document 1 can obtain a predetermined level of back potential effect, but there is a point of lack of certainty because the potential is not fixed. Further, in an isolated state sandwiched between n-type layers, it does not have a hole extracting function like the p-type layer in the cited document 2.

  It is an object of the present invention to provide a vertical GaN-based semiconductor device with improved withstand voltage performance and a method for manufacturing the same.

  The semiconductor device of the present invention is a vertical transistor formed in a GaN-based laminate. In this semiconductor device, the GaN-based stacked body has an n-type GaN-based drift layer / p-type GaN-based barrier layer / n-type GaN-based cap layer sequentially from the substrate side to the surface, and the surface of the GaN-based stacked body To reach the n-type GaN-based drift layer, a regrowth layer that is positioned along the wall surface of the opening and in which a channel is formed by a two-dimensional electron gas, and a channel that is positioned on the regrowth layer A gate electrode that controls the gate, a side opening that is located on both sides of the opening, or around the opening, reaching from the surface of the GaN-based stacked body into the n-type GaN-based drift layer, and electrically connected to the channel And a source electrode positioned on both sides of the opening or around the opening so as to cover the side opening. The side opening has at least the p-type GaN source electrode. Conductively connected to the system barrier layer, and Insulated -type GaN-based drift layer, wherein the connection structure is provided.

According to said structure, the side part opening which reaches in an n-type GaN-type drift layer is provided in the both sides of the opening part in which a gate electrode is located, or around an opening part. For this reason, the electric field concentration is formed not only in the opening where the gate electrode is located but also in the side openings located on both sides or around the opening. As a result, the electric field concentration at the opening where the gate electrode is located is alleviated, and the relaxation can be shared with the side opening.
Since the channel is a two-dimensional electron gas, layers other than the p-type GaN-based barrier layer in the GaN-based stacked body are formed of n-type or i-type GaN-based semiconductors. In particular, the GaN-based cap layer is formed of a high-concentration n-type GaN-based cap layer because the source electrode is in ohmic contact. Therefore, the p-type GaN-based barrier layer is sandwiched between the surface-side n-type GaN-based semiconductor layer and a relatively low-concentration n-type GaN-based drift layer where electrons drift.
The p-type GaN-based barrier layer in the above configuration (i) improves the pinch-off characteristics by shifting the band in the positive direction, and (ii) improves the longitudinal breakdown voltage performance, although the effect is small compared to the side opening. (Iii) By providing the connection structure, effects such as prevention of kink phenomenon are exhibited. The functions (i) and (ii) can be obtained by the so-called back gate effect without the above connection structure, that is, by being a p-type semiconductor. However, by providing a connection structure in contact with the p-type GaN-based barrier layer, holes generated between the channel and the drain electrode when the drain voltage is increased can be extracted to the source electrode. Can be obtained. That is, the connection structure can draw holes in the p-type GaN-based barrier layer and draw them out to the source electrode. This eliminates the accumulation of holes and prevents the kink phenomenon.
It is essential for the side opening to reach the n-type GaN-based drift layer in order to reduce the electric field concentration by making the distance from the drain electrode the same as the opening under the gate electrode. However, if the connection structure provided in the side opening is conductively connected between the source electrode and the n-type GaN-based drift layer, the channel path by the two-dimensional electron gas becomes meaningless and does not become a transistor. It must be insulated from the GaN-based drift layer.

The connection structure can be a metal layer in contact with the source electrode and the p-type GaN-based barrier layer with an insulator interposed between the n-type GaN-based drift layer.
Thus, the connection structure can be easily formed using an existing method. Contact between the source electrode and the p-type GaN-based barrier layer and the metal layer can easily be ohmic contact.

The connection structure can be a p-type semiconductor layer in contact with the p-type GaN-based barrier layer and the source electrode.
The p-type semiconductor layer forming the connection structure is electrically isolated from the n-type GaN-based drift layer by a pn junction barrier. As a result, a desired circuit configuration can be obtained without forming a complicated structure.

An insulator may be interposed between the p-type semiconductor layer having the connection structure and the n-type GaN-based drift layer.
As a result, since the insulation is performed by the insulator without depending on the barrier of the pn junction, the n-type GaN-based drift layer and the source electrode can be reliably insulated regardless of the size of the potential barrier of the pn junction. .

When the connection structure includes a metal layer, the metal layer may electrically connect the source electrode and the channel.
Usually, the source electrode and the channel are electrically connected by a plurality of paths. A path of (source electrode / connection structure metal layer / n-type GaN-based cap layer / channel) and / or (source electrode / connection structure metal layer / channel) can be provided therein. Accordingly, it can be considered that the source electrode is substantially enlarged, and the on-resistance and the like can be reduced.

A structure in which an insulating film (gate insulating film) is interposed between the regrowth layer including the channel and the gate electrode can be employed.
As a result, a gate leakage current when a positive voltage is applied to the gate can be suppressed, so that a large current operation is possible. Further, since the threshold voltage can be shifted in the positive direction, it is easy to obtain normally-off. Further, at this time, a gate insulating film is interposed between the gate electrode and the drain electrode, so that the electric field concentration can be reduced or the vertical breakdown voltage performance can be improved.

  The method for manufacturing a semiconductor device of the present invention manufactures a vertical transistor made of a GaN-based semiconductor. The method includes a step of forming a GaN-based laminate by sequentially growing an n-type GaN-based drift layer, a p-type GaN-based barrier layer, and an n-type GaN-based cap layer on a GaN-based substrate; A step of providing an opening reaching the n-type GaN drift layer from the surface of the GaN-based laminate, and a step of forming a regrowth layer including a channel by a two-dimensional electron gas along the wall surface of the opening; A step of providing side openings reaching the inside of the n-type GaN-based drift layer from the surface of the GaN-based stacked body on both sides of the opening, or around the openings; and an n-type GaN-based drift layer in the side openings Insulating and forming a connection structure that is conductively connected to at least the p-type GaN-based barrier layer, and electrically connecting to the channel and covering the side opening while being conductively connected to the connection structure, Form source electrode Characterized in that it comprises a degree.

  By using the above-described method, an existing semiconductor device that can relieve electric field concentration on the opening under the gate electrode by the side opening and obtain the effects (i) to (iii) described above using the p-type GaN-based barrier layer is provided. The method can be easily manufactured. Further, since the p-type GaN-based barrier layer is buried under the source electrode, a small device can be obtained.

  According to the present invention, it is possible to obtain a vertical GaN-based semiconductor device or the like with improved breakdown voltage performance.

It is sectional drawing which shows the vertical GaN-type semiconductor device in Embodiment 1 of this invention. FIG. 2 is a partial plan view of a chip including the GaN-based semiconductor device of FIG. 1. 2A and 2B are views showing (a) a state where an epitaxial layered body is formed and (b) a state where a resist pattern for forming an opening is formed in the manufacture of the GaN-based semiconductor device of FIG. 1. The stage which provides an opening part by RIE is shown, (a) is the state which has arrange | positioned the resist pattern, (b) is a figure which shows the state which digs down an opening and expands (retracts) an opening, irradiating ion. . The figure which shows the state which formed the regrowth layer after forming the regrowth layer in the opening part, (a) opening a side part opening, (b) depositing an insulating film, and (c) enlarging a side part opening. It is. (A) It is a figure which expands a side part opening, (b) The resist pattern was removed by the lift-off method, (c) The state which formed the metal layer and source electrode of a connection structure. It is a modification of Embodiment 1, and is a figure which shows one Example of this invention. It is sectional drawing which shows the GaN-type semiconductor device in Embodiment 2 of this invention. It is a modification of Embodiment 2, and is a figure which shows one Example of this invention. It is sectional drawing which shows the GaN-type semiconductor device in Embodiment 3 of this invention.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing a GaN-based FET 10 that is a semiconductor device according to Embodiment 1 of the present invention. The vertical GaN-based FET 10 includes a conductive GaN substrate 1 and an n ⁻ -type GaN-based drift layer 4 / p-type GaN barrier layer 6 / n ⁺ -type GaN-based cap layer 8 epitaxially grown thereon. The n ⁻ -type GaN-based drift layer 4 / p-type GaN-based barrier layer 6 / n ⁺ -type GaN-based cap layer 8 forms a continuously formed GaN-based laminate 15. Depending on the type of the GaN substrate 1, a buffer layer made of an AlGaN layer or a GaN layer may be inserted between the GaN substrate 1 and the n ⁻ -type GaN-based drift layer 4.

  The GaN substrate 1 may be a substrate having a GaN layer that is in ohmic contact with the support base. In the product state as described above, a considerable thickness portion of the GaN substrate or the like is removed, and an epitaxial growth of a GaN-based laminate is performed. Only a thin GaN layer as the underlying film may remain. These GaN substrates, substrates having a GaN layer in ohmic contact with the support base, and underlying GaN layers left thin on the product may be simply referred to as GaN substrates.

The GaN-based laminate 15 is provided with an opening 28 that penetrates the p-type GaN-based barrier layer 6 and reaches the n ⁻ -type GaN-based drift layer 4. An epitaxially grown regrowth layer 27 is formed so as to cover the surface (the surface of the cap layer 8). The regrowth layer 27 includes an i (intrinsic) GaN electron transit layer 22 and an AlGaN electron supply layer 26. An intermediate layer such as AlN may be inserted between the iGaN electron transit layer 22 and the AlGaN electron supply layer 26. The gate electrode G is located on the regrowth layer 27, and the drain electrode D is located on the back surface of the GaN substrate 1. The source electrode S is in ohmic contact with the regrowth layer 27 on the GaN-based stacked body 15. In FIG. 1, the source electrode S is in contact with the regrowth layer 27 and positioned on the regrowth layer 27, but is in contact with the n ⁺ type GaN-based cap layer 8 and positioned on the n ⁺ type cap layer 8. You may make it ohmic-contact with the end surface of the regrowth layer 27. FIG.
Further, as one of the greatest features of the present embodiment, side openings 38 are provided on or around both sides of the opening 28, and the source electrode S and p-type GaN are provided in the side opening 38. A connection structure 5 for conductively connecting the system barrier layer 6 is provided. This connection structure 5 is insulated from the n ⁻ -type GaN-based drift layer 4 by an insulating layer 5 b. The connection structure 5 is formed by the metal layer 5a that conductively connects the source electrode S and the p-type GaN-based barrier layer, and the insulating layer 5b. The metal layer 5a is preferably in ohmic contact with the p-type GaN-based barrier layer 6 and the source electrode S in order to reduce the on-resistance.

In the vertical GaN-based FET 10 of the present embodiment, electrons flow in the thickness direction or the vertical direction from the source electrode S through the electron transit layer 22, through the n ⁻ -type GaN-based drift layer 4 to the drain electrode D. In this electron path, the p-type GaN-based barrier layer 6 is sandwiched between the n ⁻ -type GaN-based drift layer 4 and the n ⁺ -type GaN-based cap layer 8. The p-type GaN-based barrier layer 6 exhibits a back gate effect such as raising the band energy of electrons and improving the breakdown voltage characteristics.

The points in the present embodiment are as follows.
(1) In a switching device intended for a wide-gap compound semiconductor such as a GaN-based semiconductor, the source electrode S on one main surface (the surface of the GaN-based stack) and the GaN-based stack on the source electrode A high voltage of several hundred volts to several hundreds of volts is applied between the drain electrode D facing each other. The source electrode S is fixed to the ground potential, and a high voltage is applied to the drain electrode D. Further, the gate electrode G is held at minus several volts, for example, −5 V when it is turned off for opening and closing the channel. That is, during the off operation, the gate electrode G holds the lowest potential. The distance between the gate electrode G and the drain electrode D is smaller than the distance between the source electrode S and the drain electrode D. During the off operation, the distance between the drain electrode D and the gate electrode G is − A voltage increased by 5V is applied. That is, in a structure where there is no side opening 38 and only the opening 28 is present, the electric field is concentrated on the opening 28 where the gate electrode G is located. In particular, the electric field concentrates on the bottom corner K of the opening 28, and dielectric breakdown tends to occur.
According to the above configuration, the side openings 38 that reach the n-type GaN-based drift layer 6 are provided on both sides of the opening 28 where the gate electrode G is located or around the opening. For this reason, the electric field concentration is formed not only in the opening 28 where the gate electrode is located but also in the side openings 38 located on both sides or around the opening. When the potential difference between the gate electrode G and the drain electrode D is the same, the electric field concentration at the opening 28 where the gate electrode is located is greatly relaxed, and the relaxed part is shared with the side opening 38.
(2) Since the channel is a two-dimensional electron gas, layers other than the p-type GaN-based barrier layer in the GaN-based stack are formed of n-type or i-type GaN-based semiconductors. In particular, the n-type GaN cap layer is a high concentration n ⁺ -type GaN cap layer because the source electrode S is in ohmic contact. Therefore, the p-type GaN-based barrier layer 6 is sandwiched between the n ⁺ -type GaN-based cap layer 8 on the surface layer side and a relatively low concentration n ^- type GaN-based drift layer 4 where electrons drift. become.
The p-type GaN-based barrier layer 6 in the above configuration (i) improves the pinch-off characteristics by shifting the band in the positive direction, and (ii) improves the vertical breakdown voltage performance, although its effect is small compared to the side opening. iii) By providing the connection structure, effects such as prevention of kink phenomenon are exhibited. The functions (i) and (ii) can be obtained by the so-called back gate effect without the connection structure 5 described above, that is, when the barrier layer is the p-type semiconductor 6. However, by providing the connection structure 5 in contact with the p-type GaN-based barrier layer 6, holes generated between the channel and the drain electrode D when the drain voltage is increased can be extracted to the source electrode S. The effect of iii) can be obtained. That is, the connection structure 5 can draw holes in the p-type GaN-based barrier layer 6 and extract them to the source electrode S. Hereinafter, (iii) will be described in detail.
When the connection structure 5 is not provided, even if the p-type GaN-based barrier layer 6 is disposed, when the drain voltage is increased, a high electric field region is formed on the drain side of the channel, and avalanche breakdown occurs due to high energy electrons. Holes are formed. Since the GaN-based semiconductor has a wide band gap, the recombination time constant is long, and holes are accumulated in the GaN-based stacked body 15 or the p-type GaN-based barrier layer 6. The GaN-based semiconductor layer is not grounded with respect to the Fermi level of holes, and accumulation of holes lowers the potential near the channel and increases the electron concentration in the conduction band. As a result, runaway such as increase of drain current is caused in the drain current-drain voltage saturation region.
By providing the connection structure 5 that conductively connects the p-type GaN-based barrier layer 6 and the source electrode S, even if avalanche breakdown occurs and a large number of holes are formed, the connection structure 5 can be extracted to the source electrode S. Therefore, the accumulation of holes is eliminated and the kink phenomenon is prevented.
(3) It is essential for the side opening 5 to reach the n-type GaN drift layer 6 in order to reduce the electric field concentration by making the distance from the drain electrode D equal to the opening 28 under the gate electrode. It is. However, if the connection structure 5 provided in the side opening 38 is conductively connected to the source electrode S and the n-type GaN-based drift layer 4, the channel path by the two-dimensional electron gas becomes meaningless and does not become a transistor. The structure 5 and the n-type GaN-based drift layer 4 must be insulated.

The p-type GaN-based barrier layer 6 may be a p-type GaN layer or a p-type AlGaN layer. When the p-type AlGaN layer is used, the band can be further lifted in the positive direction, and the pinch-off characteristics can be further improved. The carrier concentration of the p-type GaN-based barrier layer 6 is usually about 5 × 10 ¹⁶ cm ⁻³ , but may be a high-concentration p ⁺ -type GaN-based barrier layer in order to enhance the effect of the back gate. .

  The GaN-based laminate is epitaxially grown on a predetermined crystal plane of GaN, but the underlying GaN may be a GaN substrate or a GaN film on a support base as described above. Furthermore, it is formed on a GaN substrate or the like during the growth of the GaN-based laminate, and in the subsequent process, except for a predetermined thickness portion such as the GaN substrate, only a thin GaN layer base remains in the product state. There may be. The thin underlying GaN layer may be conductive or non-conductive, and the drain electrode can be provided on the front or back surface of the thin GaN layer, depending on the manufacturing process and the structure of the product. When the GaN substrate or the supporting base remains in the product, the supporting base or the substrate may be conductive or non-conductive. In the case of conductivity, the drain electrode can be directly provided on the back surface (lower) or front surface (upper) of the supporting base or substrate. In the case of non-conductivity, a drain electrode can be provided on the non-conductive substrate and on the conductive layer located on the lower layer side in the semiconductor layer.

FIG. 2 is a plan view of the vertical GaN-based FET 10 shown in FIG. According to this plan view, the gate electrode G and the opening 28 in the vertical GaN-based FET 10 are hexagonal and can be arranged densely in a plane. Further, side openings 38 are provided on both sides of or around the opening 28, and the connection structure 5 is formed in the side openings 38. However, the side openings 38 and the connection structure 5 are completely covered by the source electrode S. Thus, the side opening 38 and the connection structure 5 are arranged without providing any additional portion in terms of area. For this reason, it is possible to provide provision for mitigation of electric field concentration or improvement of pressure resistance in the vertical direction and kink phenomenon while maintaining a small size while being densely arranged in a plane.
The gate electrode G of each element is conductively connected by the gate wiring 12 extending from the gate pad 13, and all the channels are controlled in the same manner.

For example, the n ⁻ -type GaN-based drift layer 4 may have a thickness of 1 μm to 25 μm and a carrier concentration of 0.2 × 10 ¹⁶ cm ^{−3 to} 20.0 × 10 ¹⁶ cm ⁻³ . The p-type GaN-based barrier layer 6 may have a thickness of 0.1 μm to 10 μm and a carrier concentration of 0.5 × 10 ¹⁶ cm ⁻³ to 50 × 10 ¹⁶ cm ⁻³ . When emphasizing the function of the back gate effect of the p-type GaN-based barrier layer 6, the carrier concentration can be increased to 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The n ⁺ -type GaN-based cap layer 8 may have a thickness of 0.1 μm to 3 μm and a carrier concentration of 1.0 × 10 ¹⁷ cm ^{−3 to} 30.0 × 10 ¹⁷ cm ⁻³ .

  In the regrowth layer 27, the electron transit layer 22 is preferably about 5 nm to 100 nm in thickness, and the electron supply layer 26 is preferably about 1 nm to 100 nm in thickness. When the thickness of the electron transit layer 22 is less than 5 nm, the interface between the 2DEG and the electron supply layer 26 / the electron transit layer 22 is too close to reduce the mobility of the 2DEG. If the thickness of the electron transit layer 22 exceeds 100 nm, the effect of the p-type GaN layer 6 is reduced and the pinch-off characteristics are deteriorated.

-Manufacturing method-
Next, a method for manufacturing the vertical GaN-based semiconductor device 10 in the present embodiment will be described. In order to be specific, the GaN-based layer is referred to as a GaN layer. First, as shown in FIG. 3A, an n ⁻ -type GaN drift layer 4 / p-type GaN barrier layer 6 / n ⁺ is formed on a substrate 1 or a GaN substrate 1 having a GaN layer in ohmic contact with a support base. A stacked body 15 of the type GaN cap layer 8 is epitaxially grown. For example, MOCVD (metal organic chemical vapor deposition) is used to form these layers. Alternatively, the MBE (molecular beam epitaxial) method may be used instead of the MOCVD method. Thereby, a GaN-based semiconductor layer with good crystallinity can be formed. The film thickness and carrier concentration of each layer are as follows.
n ⁻ type GaN drift layer 4: thickness 5.0 μm, carrier concentration 5.0 × 10 ¹⁵ cm ⁻³
p-type GaN layer 6: thickness 0.5 μm, carrier concentration 5.0 × 10 ¹⁸ cm ⁻³
n ⁺ -type GaN cap layer 8: thickness 0.3 μm, carrier concentration 5.0 × 10 ¹⁷ cm ⁻³

Next, as shown in FIG. 3B, a resist pattern M1 is formed in a predetermined region on the n ⁺ -type GaN cap layer 8 using a normal exposure technique. The resist pattern M1 formed here has a hexagonal plane shape and a trapezoidal (mesa type) cross-sectional shape.
Thereafter, as shown in FIG. 4A, an n ⁺ -type GaN cap layer is formed by RIE (Reactive Ion Etching) using high-density plasma generated by using inductively coupled plasma. 8. Part of the p-type GaN layer 6 and the n ⁻ -type GaN drift layer 4 is etched to form an opening 28. Thereby, the end surfaces of the n ⁺ -type GaN cap layer 8, the p-type GaN layer 6, and the n ⁻ -type GaN drift layer 4 are exposed to the opening 28 to form the wall surface of the opening. At this point, etching damage has occurred on the wall surface of the opening 28 over a depth of several nm (about 1 nm to 20 nm). The wall surface of the opening 28 is an inclined surface of about 10 ° to 90 ° with respect to the substrate surface. However, in the present invention, the widest angle is between 0 ° and 90 ° or less with respect to the substrate surface, regardless of the production method. The same applies to the side openings 38. The angle of the inclined surface with respect to the substrate surface can be controlled by the gas pressure of chlorine gas used in the RIE method and the flow rate ratio with other gases. When RIE ends, organic cleaning is performed, and the resist pattern M1 is removed by ashing or the like.

Subsequently, anisotropic wet etching of the wall surface of the opening is performed using an aqueous solution of TMAH (tetramethylammonium hydroxide) as an etchant (80 ° C., several minutes to several hours). By anisotropic wet etching, etching damage generated on the wall surface of the opening 28 by RIE using high-density plasma is removed. At the same time, the respective m-planes are exposed at part of the end faces of the n ⁺ -type GaN cap layer 8 and the p-type GaN layer 6.
The side surface of the opening 28 includes a plurality of surfaces S ₁ that are substantially perpendicular to the substrate surface, and an inclined surface S ₃ that is formed so as to complement between the surfaces S _1. Inclination angle θ) is mixed. In the vertical FET 10, in the case of the GaN substrate 1 whose main surface is the {0001} plane, the hexagonal GaN layer and the AlGaN layer are epitaxially grown with the {0001} plane (hereinafter referred to as C plane) as the growth plane. Yes. Therefore, the vertical plane S ₁ in the n ⁺ -type GaN cap layer 8 is a {1-100} plane (hereinafter referred to as m plane). Unlike the C plane, the m plane is a nonpolar plane. For this reason, when the GaN electron transit layer 22 and the AlGaN electron supply layer 26 are regrown using the m-plane as the growth surface, polarization charges such as piezoelectric charges are not generated at the heterointerface of the AlGaN 26 / GaN 22. For this reason, the electric field of the direction which reduces the minimum energy of a channel does not arise. As a result, the pinch-off characteristics can be further improved.
The closer the tilt angle of the wall surface of the opening 28 theta is 90 ° shown in FIG. 4 (b) or the like, the proportion of m-plane or surface S ₁ in the wall surface increases. Therefore, in order to further improve the pinch-off characteristics in the vertical FET 10, it is preferable that the inclination angle θ is close to 90 °, for example, 60 ° or more.

The depth of etching damage varies depending on RIE processing conditions. Further, the ratio of the m-plane to the opening boundary surface varies depending on the specifications of the vertical FET 10 to be manufactured. Therefore, in consideration of these conditions, the anisotropic etching may be performed under such etching conditions that etching damage can be removed and predetermined identification can be obtained. Note that the etching solution for performing anisotropic wet etching is not limited to the TMAH aqueous solution. An appropriate etchant may be used depending on the material of the substrate.
4B, the opening 28 has a hexagonal planar shape as shown in FIG.

  Next, the GaN electron transit layer 22 and the AlGaN electron supply layer 26 constituting the regrowth layer 27 are formed on the wall surface of the opening 28 and the GaN-based laminate 15 around the opening 28. An AlN intermediate layer may be inserted between the GaN electron transit layer 22 and the AlGaN electron supply layer 26. In the growth of the regrowth layer 27, first, the GaN electron transit layer 22 to which no impurities are added is formed using MOCVD. The growth temperature in MOCVD is 1020 ° C. When inserting the AlN intermediate layer, the AlN intermediate layer and the AlGaN electron supply layer 26 are formed at a growth temperature of 1080 ° C. As a result, a regrowth layer 27 including the electron transit layer 22, the AlN intermediate layer, and the electron supply layer 26 is formed along the surface of the opening 28. As an example, the thicknesses of the GaN electron transit layer 22, the AlN intermediate layer, and the AlGaN electron supply layer 26 to be formed are 100 nm, 1 nm, and 24 nm, respectively, and the Al composition ratio of the AlGaN electron supply layer 26 is 25%.

  In the formation of the regrowth layer, it is preferable to form the regrowth layer at a temperature lower than the growth temperature of the GaN-based stacked body 15 and at a high V / III ratio in order to avoid a decrease in the growth rate on the wall surface of the opening 28. Furthermore, when the growth temperature is raised in order to form the intermediate layer and the electron supply layer 26 from the formation of the electron transit layer 22, the temperature is preferably raised in a short time in order to reduce damage to the crystal surface. For example, it is preferable to raise the temperature in a time of 20 minutes or less. Note that the MBE method may be used instead of the MOCVD method.

  Thereafter, a resist pattern M2 is formed as shown in FIG. 5A, and the side openings 38a are provided by dry etching using the resist pattern M2 as a mask. Thereafter, as shown in FIG. 5B, an insulating layer 5b is formed on the entire surface. The insulating layer 5b is intended to be provided at the bottom of the side opening 38, but is deposited over the entire surface for the time being. Next, as shown in FIG. 5C, a resist pattern M3 is formed on the insulating film 5b. A resist pattern M3 is also formed on the insulating film 5b at the bottom of the side opening 38. Using this resist pattern M3 as a mask, as shown in FIG. 6A, a side opening 38 having a diameter larger than that of the previous side opening 38a is provided by etching. When forming the large-diameter side opening 38, the insulating layer 5b may be removed together. As shown in FIG. 6A, the large-diameter side opening 38 is preferably set to a depth that slightly enters the p-type GaN barrier layer 6. Thereafter, as shown in FIG. 6B, the resist patterns M2 and M3 are removed, and the insulating film 5b between the mask patterns is lifted off. Thereafter, a resist pattern M4 for forming the metal layer 5a and the source electrode S of the connection structure 5 is formed, and the metal layer 5 and the source electrode S are sequentially formed. The metal layer 5a and the source electrode S are lifted off while removing the resist pattern M4. Thereafter, the gate electrode G and the drain electrode D can be formed.

In forming the metal layer 5a of the connection structure 5, the Ti / Al film is formed up to a predetermined depth position of the side opening 38 provided with the insulating layer 5b at the bottom by the above procedure. Thereafter, a Ti / Al film is formed as the source electrode S so as to close the side opening 38. Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of 800 ° C. for 30 seconds. As a result, an alloy layer is formed at the interface between the Ti / Al film and the GaN stack (p-type GaN barrier layer 6, n ⁺ -type GaN cap layer 8) or regrowth layer 27. As a result, the metal layer 5a and the source electrode S having a good ohmic contact with an ohmic contact resistance of about 0.4 Ωmm can be formed.
The source electrode S may be any metal other than Ti / Al as long as it is in ohmic contact with the regrown layer 27. In addition, before depositing Ti / Al as the source electrode S, it is preferable to remove the AlGaN electron supply layer 26 and the AlN intermediate layer by etching by RIE using a chlorine-based gas. In this case, there is no electron barrier by the intermediate layer, and the resistance in the ohmic contact can be reduced to 0.2 Ωmm. Further, the metal layer 5a may not be the same as the material of the source electrode S.

  In forming the gate electrode G, first, a photoresist having a predetermined opening is formed using a normal exposure technique. Next, a Ni / Au film is formed along the AlGaN electron supply layer 26 formed in the opening 28 by using a vapor deposition method and a lift-off method. In addition to Ni / Au, the gate electrode G may be a metal that forms a Schottky junction with a GaN-based semiconductor such as Pt / Au, Pd / Au, and Mo / Au.

  Thereafter, a wiring layer (not shown) connected to the gate electrode G and the source electrode S is formed, and an insulating film layer (not shown) for protecting the transistor surface is formed. As the insulating film layer, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed so as to cover the entire transistor surface. Further, the insulating film layer of the bonding pad portion (not shown) is removed by using the RIE method. This completes the wafer surface manufacturing process.

  In forming the drain electrode D, first, the wafer surface is protected with a photoresist. A Ti / Al film is formed on the back surface of the substrate 1 having a GaN layer that is in ohmic contact with the support base, by vapor deposition. After removing the photoresist on the wafer surface, heat treatment is performed at a temperature of 850 ° C. for 30 seconds. As a result, the substrate 1 having the GaN layer in ohmic contact with the support base and the metal of the drain electrode D form an alloy, and the substrate 1 and the drain electrode D are in ohmic contact. Thus, the vertical GaN-based FET 10 shown in FIG. 1 is completed.

Although the drain electrode D is formed on the back surface of the GaN substrate 1, the drain electrode D may be formed on the surface of the n ⁻ -type GaN drift layer 4 facing the source electrode S. For example, an n ^- type GaN contact layer may be provided between the n ⁻ -type GaN drift layer 4 and the GaN substrate 1 to form a drain electrode connected to the contact layer from the surface side.

(Modification of Embodiment 1)
FIG. 7 shows a semiconductor device 10 according to a modification of the first embodiment, and is a diagram illustrating an example of the present invention. This modification is characterized in that the structure of the connection structure 5 provided in the side opening 38 is simple. That is, the side openings 38 are grooves having the same width and no step. For this reason, the process of forming the insulating film 5b / metal layer 5a is greatly simplified.
The action of relaxing the electric field concentration at the bottom of the opening 28, particularly the corner K, by the side openings 38, and the extraction of holes due to the conductive connection between the p-type GaN-based barrier layer 6 and the source electrode S by the connection structure 5. The description of the first embodiment applies to the actions and the like.

(Embodiment 2)
FIG. 8 is a cross-sectional view showing a vertical GaN-based FET 10 which is a semiconductor device according to the second embodiment of the present invention. The configurations of the substrate 1, the GaN-based stacked body 15, the opening 28, the regrowth layer 27 including a channel by a two-dimensional electron gas, the side opening 38, and the like are the same as those in the first embodiment. The difference from the first embodiment is that the connection structure 5 is formed of a p ⁺ -type GaN-based layer 5p. This connection structure 5 (5p) is also a feature of the present embodiment.

The p ⁺ -type GaN-based layer 5p can reliably realize low-resistance contact with the p-type GaN-based barrier layer 6 and the source electrode S. On the other hand, the n ⁻ type GaN-based drift layer 4 is electrically separated by a barrier of a pn junction. Therefore, the role of (metal layer 5a / insulating layer 5b) in the first embodiment as an electric circuit can be replaced by the p ⁺ -type GaN-based layer 5p. Thereby, the structure of the connection structure 5 can be simplified. The description of the first embodiment applies to the operation of other parts, for example, the effect of reducing the electric field concentration at the bottom of the opening 28, particularly the corner K, by the side openings 38.

(Modification of Embodiment 2)
FIG. 9 shows a semiconductor device 10 according to a modification of the second embodiment, and is a diagram illustrating an example of the present invention. The present modification is characterized in that the connection structure 5 in the side opening 38 is constituted by (p ⁺ -type GaN-based layer 5p / insulating layer 5b). By interposing the insulating layer 5b between the p ⁺ -type GaN-based layer 5p and the n ⁻ -type GaN-based drift layer 4, the insulation between the two is ensured without worrying about the size of the potential barrier of the pn junction. It becomes possible to take.
The description of the first embodiment applies to the operation of other parts, for example, the effect of reducing the electric field concentration at the bottom of the opening 28, particularly the corner K, by the side openings 38.

(Embodiment 3)
FIG. 10 is a cross-sectional view showing a GaN-based FET 10 that is a semiconductor device according to Embodiment 3 of the present invention. The difference between the semiconductor device 10 of the present embodiment and the semiconductor device of the first embodiment shown in FIG. 1 is that the gate insulating film 9 is interposed between the gate electrode G and the regrowth layer 27 including the channel. It is in the point. By disposing the insulating layer 9 under the gate electrode G, a gate leakage current when a positive voltage is applied to the gate electrode G can be suppressed, so that a large current operation is possible. Further, since the threshold voltage can be shifted in the positive direction, it is easy to obtain normally-off. Furthermore, since an insulating film is interposed between the gate electrode and the drain electrode, it is possible to alleviate electric field concentration or improve the vertical withstand voltage performance.

As a manufacturing method, before forming the gate electrode G in the manufacturing method of the first embodiment, the insulating film 9 made of, for example, a silicon oxide film is formed by using a CVD (Chemical Vapor Deposition) method or a sputtering method. It can be formed 10 nm along the inner AlGaN electron supply layer 26. Thereby, the vertical semiconductor device in this embodiment having a MIS-HFET structure can be obtained. As the insulating film 9, a silicon nitride film or an aluminum oxide film may be used in addition to the silicon oxide film.
The description of the first embodiment is applicable to the effects of portions other than the MIS structure, for example, the effect of reducing the electric field concentration at the bottom of the opening 28, particularly the corner K, by the side openings 38.

  The structures of the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  According to the present invention, side openings reaching the drift layer are provided on both sides of or around the opening where the gate / channel is provided, and the connection structure is disposed in the side opening, thereby The electric field concentration generated at the bottom can be relaxed and the pressure resistance can be improved. Furthermore, the connection structure described above electrically connects the source electrode and the p-type barrier layer, whereby holes accumulated in the p-type barrier layer can be extracted to the source electrode. With the above configuration, it is possible to realize durability improvement such as pressure resistance, which has been a concern.

1 GaN substrate, 4 n ⁻ type GaN based drift layer, 5 connection structure, 5a metal layer, 5b insulating layer, 5p p ⁺ type GaN based layer, 6 p type GaN based barrier layer, 8 n ⁺ type GaN based cap layer, 9 Gate Insulating Film, 10 Vertical GaN Semiconductor Device, 12 Gate Wiring, 13 Gate Pad, 15 GaN Stack, 22 GaN Electron Traveling Layer, 26 AlGaN Electron Supply Layer, 27 Regrown Layer, 28 Opening, 28b Opening Bottom part, 38 side opening, S
Source electrode, G gate electrode, D drain electrode, bottom corner of K opening, M1-M4 resist pattern.

Claims (7)

A vertical transistor formed in a GaN-based stack,
The GaN-based laminate has an n-type GaN-based drift layer / p-type GaN-based barrier layer / n-type GaN-based cap layer sequentially from the substrate side to the surface,
An opening reaching the n-type GaN-based drift layer from the surface of the GaN-based stack;
A regrowth layer that is positioned along the wall surface of the opening and in which a channel formed by a two-dimensional electron gas is formed;
A gate electrode positioned over the regrowth layer to control the channel;
Side openings reaching the inside of the n-type GaN-based drift layer from the surface of the GaN-based stacked body on or around the opening,
A source electrode electrically connected to the channel and positioned so as to cover the side opening at both sides of the opening or around the opening;
The side opening is provided with a connection structure in which the source electrode is conductively connected to at least the p-type GaN-based barrier layer and insulated from the n-type GaN-based drift layer. Semiconductor device.   The connection structure is a metal layer in contact with the source electrode and the p-type GaN-based barrier layer with an insulator interposed between the n-type GaN-based drift layer and the p-type GaN-based barrier layer. The semiconductor device described.   The semiconductor device according to claim 1, wherein the connection structure is a p-type semiconductor layer in contact with the p-type GaN-based barrier layer and the source electrode.   The semiconductor device according to claim 3, wherein an insulator is interposed between the p-type semiconductor layer and the n-type GaN-based drift layer.   The semiconductor device according to claim 1, wherein when the connection structure includes a metal layer, the metal layer electrically connects the source electrode and the channel.   6. The semiconductor device according to claim 1, wherein an insulating film is interposed between the regrowth layer including the channel and the gate electrode. A method of manufacturing a vertical transistor using a GaN-based semiconductor,
Forming a GaN-based stacked body by sequentially growing an n-type GaN-based drift layer, a p-type GaN-based barrier layer, and an n-type GaN-based cap layer on a GaN-based substrate;
Providing an opening that reaches from the surface of the GaN-based laminate into the n-type GaN-based drift layer;
Forming a regrowth layer including a channel by a two-dimensional electron gas along the wall surface of the opening; and
Providing side openings reaching both sides of the opening, or around the opening, from the surface of the GaN-based stack to the n-type GaN-based drift layer;
Forming a connection structure in the side opening that is electrically connected to at least the p-type GaN-based barrier layer after being insulated from the n-type GaN-based drift layer;
Forming a source electrode so as to cover the side opening while being electrically connected to the channel and conductively connected to the connection structure.

Images