JP2013168549A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A high breakdown voltage semiconductor device capable of suppressing concentration of an electric field and obtaining a stable breakdown voltage, and a manufacturing method thereof.
A second conductivity type semiconductor region is formed in the vicinity of the surface on one side in the thickness direction of a semiconductor epitaxial layer on a semiconductor substrate. A plurality of junction termination (FLR) regions 15 are formed on the outer peripheral end side of the semiconductor epitaxial layer 12 relative to the second conductivity type semiconductor region 13. The plurality of FLR regions 15 are annularly spaced apart from each other and have a second conductivity type. A second conductivity type electric field relaxation region 16 is formed in contact with each FLR region 15 on the radially inner side and outer side of each FLR region 15. At this time, the concentration of the second conductivity type impurity in the electric field relaxation region 16 is set to 1/10 or less of the concentration of the second conductivity type impurity in the FLR region 15.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a field limiting ring (abbreviation: FLR) region and a manufacturing method thereof.

  As semiconductor devices using a semiconductor substrate, there are power semiconductor devices such as Schottky diodes, pn diodes, and metal-oxide-semiconductor field effect transistors (abbreviated as MOSFETs). In these power semiconductor devices, various termination structures are introduced in order to prevent the electric field from concentrating on the pn junction. One of the termination structures is a field limiting ring (abbreviation: FLR) structure (see, for example, Non-Patent Document 1).

  In the FLR structure, a plurality of annular regions (hereinafter referred to as “FLR regions”) are formed so as to surround a semiconductor region (hereinafter referred to as “main junction region”) that forms a main junction. By using the FLR structure to equalize the electric field distribution at the device termination at the time of voltage blocking, breakdown due to locally high electric field strength at a relatively low voltage is prevented. With this technique, the main junction region can obtain a breakdown voltage of at least the kilovolt (kV) order.

  Further, in order to reduce the electric field strength at the end of the FLR region, it has been proposed to form a region having an impurity concentration lower than that of the FLR region so as to include all or part of the FLR structure ( For example, see Patent Documents 1 and 2).

Japanese Patent No. 3770857 Special table 2011-1151474 gazette

B. Jayant Baliga, “POWER SEMICONDUCTOR DEVICES” (USA), 1st edition, Springer-Verlag, December 30, 2008, p. 120-132

  In a high breakdown voltage semiconductor device having an FLR structure as a termination structure, when a relatively high reverse voltage is applied to the pn junction, a region having a high electric field strength is locally generated at the end of the FLR region. When the electric field strength reaching the substrate surface is high, creeping discharge occurs outside the substrate, and there is a problem that the breakdown voltage of the semiconductor device is significantly reduced.

  As the FLR structure that reduces the electric field strength at the end of the FLR region, there are FLR structures disclosed in Patent Document 1 and Patent Document 2 described above. The FLR structure disclosed in Patent Document 1 is a structure that includes a plurality of FLR regions in a region having an impurity concentration lower than that of the FLR region. The FLR structure disclosed in Patent Document 2 is a structure including a side portion and a bottom portion of the FLR region in a region having an impurity concentration lower than that of the FLR region.

  However, in the FLR structures disclosed in Patent Document 1 and Patent Document 2, in some FLR regions, the impurity concentration is abruptly changed at the lateral end, and the region where the electric field strength is locally high in the portion. Occurs. Therefore, there is a problem that the electric field intensity reaching the substrate surface or the device surface cannot be sufficiently reduced.

  An object of the present invention is to provide a high breakdown voltage semiconductor device that suppresses concentration of an electric field and obtains a stable breakdown voltage, and a manufacturing method thereof.

  A semiconductor device of the present invention includes a semiconductor substrate having a first conductivity type, a semiconductor epitaxial layer having a first conductivity type provided on a surface on one side in the thickness direction of the semiconductor substrate, and the semiconductor epitaxial layer. Of the second conductivity type semiconductor region having the second conductivity type formed in a part of the surface vicinity portion on one side in the thickness direction, and the second conductivity type in the surface vicinity portion on one side in the thickness direction of the semiconductor epitaxial layer. A plurality of junction termination regions having a second conductivity type, which are annularly spaced apart from each other at a portion closer to the outer peripheral end of the semiconductor epitaxial layer than the semiconductor region of the type, and a radial direction of each of the junction termination regions Provided on the inner side and the outer side in contact with the junction termination region and provided on the electric field relaxation region having the second conductivity type, the semiconductor region of the second conductivity type, and the junction termination region. A Mamorumaku, the concentration of the second conductivity type impurity in the electric field relaxation region is characterized in that the joint is in the end region following 1/10 of the concentration of impurities of the second conductivity type.

  The method for manufacturing a semiconductor device of the present invention includes an epitaxial layer forming step of forming a semiconductor epitaxial layer having a first conductivity type on a surface on one side in the thickness direction of a semiconductor substrate having a first conductivity type, and the semiconductor A semiconductor region forming step of forming a second conductivity type semiconductor region having a second conductivity type in a part of the surface vicinity on one side in the thickness direction of the epitaxial layer; and on the surface on one side in the thickness direction of the semiconductor epitaxial layer. And forming an ion implantation mask in which a plurality of annular openings are formed apart from each other on the outer peripheral end side of the semiconductor epitaxial layer with respect to the semiconductor region of the second conductivity type, and then formed. A first implantation step of forming a plurality of junction termination regions by ion-implanting impurities of a second conductivity type via A second implantation for forming an electric field relaxation region by ion implantation of a second conductivity type impurity through the ion implantation mask. And a process.

  According to the semiconductor device of the present invention, in the vicinity of the surface on the one side in the thickness direction of the semiconductor epitaxial layer on the semiconductor substrate, the portion closer to the outer peripheral end of the semiconductor epitaxial layer than the semiconductor region of the second conductivity type is mutually connected. A plurality of junction termination regions are provided that are spaced apart and formed in an annular shape and have the second conductivity type. An electric field relaxation region formed in contact with the junction termination region and having the second conductivity type is provided on the radially inner side and outer side of each junction termination region. Since the concentration of the second conductivity type impurity in the electric field relaxation region is 1/10 or less of the concentration of the second conductivity type impurity in the junction termination region, the slope of the impurity concentration distribution at the lateral end of the junction termination region Becomes gentle and the concentration of the electric field is eased. As a result, the electric field strength inside the semiconductor device when a reverse voltage is applied and the electric field strength reaching the surface of the semiconductor substrate can be reduced, so that creeping discharge outside the semiconductor substrate is suppressed, and the semiconductor device A decrease in breakdown voltage can be prevented. Therefore, it is possible to realize a high breakdown voltage semiconductor device that can suppress concentration of the electric field and obtain a stable breakdown voltage.

  According to the method for manufacturing a semiconductor device of the present invention, the semiconductor epitaxial layer is formed on the surface on one side in the thickness direction of the semiconductor substrate in the epitaxial layer forming step. In the semiconductor region forming step, a semiconductor region of the second conductivity type is formed in a part of the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer. In the first implantation step, a plurality of junction termination regions are formed by ion implantation through an ion implantation mask formed on one surface in the thickness direction of the semiconductor epitaxial layer. In the second implantation step, the ion implantation mask is trimmed and the diameter of the opening is expanded by an enlarged width, and then ion implantation is performed through the ion implantation mask, thereby forming an electric field relaxation region. Thus, in addition to the ion implantation mask used for forming the junction termination region, the radial direction of each junction termination region can be simply and highly accurately in a self-aligned process without using a new ion implantation mask as described above. A semiconductor device having an electric field relaxation region on the inner side and the outer side can be manufactured. For example, by setting the surface density of the ion implantation in the second implantation step to 1/10 or less of the surface density of the ion implantation in the first implantation step, the concentration of the second conductivity type impurity in the electric field relaxation region can be reduced as described above. Thus, a semiconductor device having a concentration of 1/10 or less of the impurity concentration of the second conductivity type in the junction termination region can be manufactured.

1 is a cross-sectional view showing a configuration of a semiconductor device 1 according to a first embodiment of the present invention. It is sectional drawing which shows the state of the stage which the formation of the 2nd conductivity type semiconductor region 13 was complete | finished. 6 is a cross-sectional view showing a state at a stage where the formation of the ohmic contact region 14 is completed. FIG. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the FLR region 15 is completed. It is sectional drawing which shows the state of the stage which the formation of the implantation mask 22 was complete | finished. It is sectional drawing which shows the state of the stage which the formation of the electric field relaxation area | region 16 was complete | finished. It is sectional drawing which shows the state in the stage where formation of the protective film 17 was complete | finished. It is sectional drawing which shows the state in the stage which the formation of the opening part 18 was complete | finished. It is sectional drawing which shows the state of the stage which the formation of the anode electrode 19 was complete | finished. FIG. 4 is a cross-sectional view showing a state at a stage where the formation of the cathode electrode 20 is completed. 5 is a graph showing the relationship between the electric field intensity reaching the substrate surface and the distance from the second conductivity type semiconductor region 13 in two types of termination structures. It is a graph which shows the relationship between the reverse voltage applied to two types of termination structures, and the maximum value of the electric field strength inside a device. It is a figure which shows the simulation result of sectional electric field strength distribution of a FLR area | region edge part. It is a figure which shows the simulation result of sectional electric field strength distribution of a FLR area | region edge part. It is sectional drawing which shows the structure of the semiconductor device 2 which is the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device 3 which is the 3rd Embodiment of this invention.

<First Embodiment>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 1 according to a first embodiment of the present invention. The semiconductor device 1 of the present embodiment is a pn diode. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 11, a semiconductor epitaxial layer 12, a second conductivity type semiconductor region 13, an ohmic contact region 14, an FLR (Field Limiting Ring) region 15, an electric field relaxation region 16, a protective film. 17, an anode electrode 19 and a cathode electrode 20 are provided. The second conductivity type semiconductor region 13 corresponds to a second conductivity type semiconductor region. The FLR region 15 corresponds to a junction termination region.

  The semiconductor epitaxial layer 12 is provided on the surface of one side in the thickness direction of the semiconductor substrate 11. The semiconductor substrate 11 and the semiconductor epitaxial layer 12 have the first conductivity type.

  In the following description, the semiconductor substrate 11, the semiconductor layer provided on the semiconductor substrate 11, and the semiconductor epitaxial layer 12 in this embodiment may be collectively referred to as “substrate”. In this case, the substrate includes each region formed in the semiconductor epitaxial layer 12, that is, the second conductivity type semiconductor region 13, the ohmic contact region 14, the FLR region 15, and the electric field relaxation region 16.

  In FIG. 1, only the outer peripheral edge of the substrate (hereinafter sometimes referred to as “outermost edge”) and its vicinity are illustrated, and the illustration of the inner portion is omitted. In FIG. 1, the right side toward the paper surface corresponds to the outer peripheral edge side of the substrate, and the left side toward the paper surface corresponds to the inner side of the outer peripheral edge of the substrate.

  The FLR region 15 is formed in a portion near the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 on the outer peripheral end side of the semiconductor epitaxial layer 12 relative to the second conductivity type semiconductor region 13. The “surface vicinity portion” includes the surface and a portion in the vicinity thereof. The semiconductor device 1 includes a plurality of FLR regions 15. In the present embodiment, the semiconductor device 1 includes three FLR regions 15.

  The plurality of FLR regions 15 surround the second conductivity type semiconductor region 13 which is a main junction region that forms a main junction. The plurality of FLR regions 15 are provided at predetermined intervals in a direction perpendicular to the thickness direction of the semiconductor substrate 11 (hereinafter sometimes referred to as “lateral direction”) toward the outermost edge of the semiconductor device 1. In FIG. 1, the horizontal direction is the left-right direction toward the page.

  The plurality of FLR regions 15 are provided so that the length, which is a dimension in the horizontal direction, decreases toward the outermost edge of the semiconductor device 1. The plurality of FLR regions 15 have the same injection surface density. “Implanted surface density” is the surface density of impurities during ion implantation.

  The second conductivity type semiconductor region 13 is a part of the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer 12, specifically, a region in the vicinity of the surface in a region inside the substrate with respect to the FLR region 15 in the lateral direction. Is formed. The second conductivity type semiconductor region 13 is provided at a distance from the FLR region 15 and the electric field relaxation region 16 provided at the innermost side of the substrate in the lateral direction. The second conductivity type semiconductor region 13 is formed from the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 to the central portion in the thickness direction. The second conductivity type semiconductor region 13 has the second conductivity type.

  The ohmic contact region 14 is formed in a part of the surface vicinity portion on one side in the thickness direction of the second conductivity type semiconductor region 13, specifically, in a portion inside the outer peripheral edge of the second conductivity type semiconductor region 13. . The ohmic contact region 14 is formed shallower than the second conductivity type semiconductor region 13. For example, the ohmic contact region 14 is formed from the surface on one side in the thickness direction of the second conductivity type semiconductor region 13 to a depth of about 2/5 (2/5) the depth of the second conductivity type semiconductor region 13. The The ohmic contact region 14 has the second conductivity type. The impurity concentration of the ohmic contact region 14 is higher than the impurity concentration of the second conductivity type semiconductor region 13.

  Among the plurality of FLR regions 15, the FLR region (hereinafter sometimes referred to as “internal FLR region”) 15 provided on the innermost side of the substrate in the lateral direction is spaced apart from the second conductive semiconductor region 13 in the lateral direction. Opened. Specifically, the inner FLR region 15 is provided so as to be separated from the second conductive semiconductor region 13 and to surround the second conductive semiconductor region 13 when viewed from one side in the thickness direction of the substrate. . The other FLR region 15 is provided so as to be separated from the inner FLR region 15 and to surround the inner FLR region 15 when viewed from one side in the thickness direction of the substrate.

  In the present embodiment, the semiconductor substrate 11 has a rectangular planar shape when viewed from one side in the thickness direction. The second conductivity type semiconductor region 13 is formed along the outer peripheral end of the semiconductor substrate 11 in a ring shape, specifically, a substantially rectangular ring shape when viewed from one side in the thickness direction. Each FLR region 15 is formed in an annular shape, specifically a substantially rectangular annular shape, as viewed from one side in the thickness direction. Each FLR region 15 has the second conductivity type.

  In the lateral direction, an electric field relaxation region 16 is formed in contact with each FLR region 15 on the inner side and outer side of each FLR region 15, that is, on the inner side and outer side in the radial direction of the FLR region 15. The semiconductor device 1 includes a plurality of electric field relaxation regions 16.

  Each electric field relaxation region 16 is formed deeper than the FLR region 15. For example, each electric field relaxation region 16 has a half (1/2) of the thickness of the semiconductor epitaxial layer 12 from the surface on one side of the thickness direction of the semiconductor epitaxial layer 12 which is the surface on one side in the thickness direction of the FLR region 15. ) Formed to a depth of about. Each electric field relaxation region 16 has the first conductivity type.

  The protective film 17 is provided on the surface of one side in the thickness direction of the semiconductor epitaxial layer 12. The protective film 17 is provided at least on the second conductivity type semiconductor region 13 and the FLR region 15. The protective film 17 has an opening 18 at a position corresponding to the region where the ohmic contact region 14 is formed. The opening 18 is formed with an opening that opens to one side in the thickness direction of the substrate.

  The anode electrode 19 is provided in the opening of the opening 18 of the protective film 17. The anode electrode 19 is in contact with the ohmic contact region 14 in the opening of the opening 18 of the protective film 17. The anode electrode 19 is electrically connected to the second conductivity type semiconductor region 13 through the ohmic contact region 14.

  The cathode electrode 20 is provided on the surface on the other side in the thickness direction of the semiconductor substrate 11. As shown in FIG. 1, the cathode electrode 20 is provided to face the anode electrode 19.

  In the present embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. Therefore, the semiconductor substrate 11 and the semiconductor epitaxial layer 12 have n-type conductivity, and the second conductivity-type semiconductor region 13, the ohmic contact region 14, the FLR region 15 and the electric field relaxation region 16 have p-type conductivity. .

  Next, a method for manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described. 2 to 10 are views for explaining a method of manufacturing the semiconductor device 1 according to the first embodiment of the present invention. 2 to 10, similarly to FIG. 1, only the outer peripheral edge of the substrate and the vicinity thereof are illustrated, and the illustration of the inner portion is omitted.

  FIG. 2 is a cross-sectional view showing a state in which the formation of the second conductivity type semiconductor region 13 is completed. First, in the epitaxial layer forming step, an epitaxial growth process using a predetermined dopant is performed on the surface on one side in the thickness direction of the semiconductor substrate 11 having the first conductivity type. As a result, as shown in FIG. 2, the semiconductor epitaxial layer 12 having the first conductivity type is formed on the surface of the semiconductor substrate 11 on one side in the thickness direction. In this embodiment, a first conductivity type impurity, specifically, an n-type impurity is used as the predetermined dopant. For example, nitrogen (N), phosphorus (P), or the like is used as the n-type impurity.

  Next, in the semiconductor region formation step, a region (hereinafter referred to as “semiconductor region formation scheduled region”) that is predetermined as a region for forming the second conductivity type semiconductor region 13 in the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer 12. A process of implanting ions of a predetermined dopant (hereinafter also referred to as “ion implantation process”). In the present embodiment, an ion implantation process is performed so that ions are implanted from the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 to the vicinity of the central portion in the thickness direction of the semiconductor epitaxial layer 12 in the semiconductor region formation scheduled region. . As a result, as shown in FIG. 2, the second conductivity type having the second conductivity type is formed in a part of the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer 12, more specifically, in the region where the semiconductor region is to be formed. A semiconductor region 13 is formed.

  The ion implantation process in the semiconductor region forming step may be performed with a single implantation energy, or may be performed while changing the implantation energy stepwise, for example, stepwise changing from high energy to low energy. Here, “implantation energy” refers to acceleration energy of ion implantation. As the predetermined dopant used in the ion implantation process in the semiconductor region forming step, an impurity of the second conductivity type, specifically, a p-type impurity is used in this embodiment. For example, aluminum (Al) or boron (B) is used as the p-type impurity.

  FIG. 3 is a cross-sectional view showing a state in which the formation of the ohmic contact region 14 is completed. After forming the second conductivity type semiconductor region 13, in the ohmic region formation step, the region in which the second conductivity type semiconductor region 13 of the semiconductor epitaxial layer 12 is formed is previously defined as a region for forming the ohmic contact region 14. An ion implantation process is performed on the determined region. As a result, as shown in FIG. 3, an ohmic contact region 14 having a higher impurity concentration than the second conductivity type semiconductor region 13 and having the second conductivity type is formed in the second conductivity type semiconductor region 13.

  The ion implantation process in the ohmic region forming step may be performed with a single implantation energy, or may be performed while changing the implantation energy stepwise, for example, stepwise changing from high energy to low energy. As the predetermined dopant used in the ion implantation process in the ohmic region forming step, an impurity of the second conductivity type, specifically, a p-type impurity is used in this embodiment. For example, aluminum (Al) or boron (B) is used as the p-type impurity.

  FIG. 4 is a cross-sectional view showing a state in which the formation of the FLR region 15 has been completed. After the ohmic contact region 14 is formed, an ion implantation mask (hereinafter simply referred to as “implantation mask”) may be formed in a predetermined region near the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 in the first implantation step. ) 21 to perform the ion implantation process. As a result, as shown in FIG. 4, a plurality of FLR regions 15 are formed so as to surround the second conductivity type semiconductor region 13. As the implantation mask 21, for example, a photoengraving photoresist or an oxide film is used.

  Specifically, the first injection step is performed as follows. First, in the mask formation stage, an implantation mask 21 is formed on the surface on one side in the thickness direction of the semiconductor epitaxial layer 12. In the implantation mask 21, a plurality of openings are formed apart from each other on the outer peripheral end side of the semiconductor epitaxial layer 12 relative to the second conductivity type semiconductor region 13. In this embodiment, three openings are formed. The width, which is the dimension in the lateral direction of each opening, is selected so that the opening closer to the outermost edge of the semiconductor device 1 becomes smaller. Each opening is formed in an annular shape so as to surround the second conductivity type semiconductor region 13.

  Next, in the implantation step, an ion implantation process is performed in which a predetermined dopant is ion-implanted through the implantation mask 21 formed in the mask formation step. As the predetermined dopant, a second conductivity type impurity, specifically, a p-type impurity is used in this embodiment. For example, aluminum (Al) or boron (B) is used as the p-type impurity. As described above, the first implantation step is performed, and a plurality of FLR regions 15 are formed.

  The plurality of FLR regions 15 are formed to be spaced apart in the lateral direction toward the outermost edge. That is, the second conductivity type semiconductor epitaxial layer 12 exists between the FLR regions 15. Here, each FLR region 15 has the same implantation surface density.

  The ion implantation process in the first implantation step for forming the FLR region 15 described above may be performed with a single implantation energy, or, for example, stepwise from high energy to low energy while changing the implantation energy stepwise. You may go while changing.

  In the ion implantation process, ions are implanted deeper as the implantation energy increases. Therefore, when ion implantation is performed with a single implantation energy, an impurity concentration distribution having an impurity concentration peak at a deeper position from the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 is realized as the implantation energy increases. .

  FIG. 5 is a cross-sectional view showing a state in which the formation of the implantation mask 22 has been completed. After the FLR region 15 is formed, the implantation mask 21 is trimmed. That is, the excess portion of the implantation mask 21 is removed. Trimming is performed, for example, by an ashing process using oxygen plasma. By the trimming, the implantation mask 22 is formed by reducing the dimension in the lateral direction of each part constituting the implantation mask 21 (hereinafter referred to as “width”) by a predetermined reduction width. Reducing the width of each part of the implantation mask 21 by a predetermined reduction width corresponds to increasing the width of the opening of the implantation mask 21 by a predetermined expansion width. The reduced width of each part of the implantation mask 21 (hereinafter sometimes referred to as “mask reduced width”) corresponds to the enlarged width of the opening of the implantation mask 21.

  The intervals between the portions of the implantation mask 22 after trimming are larger than the intervals between the portions of the implantation mask 21 before trimming. In other words, the interval between the openings of the implantation mask 22 after trimming is smaller than the interval between the openings of the implantation mask 21 before trimming. The reduced width of each part of the implantation mask 21, in other words, the enlarged width of the opening of the implantation mask 21 is the width of the side portion of the electric field relaxation region 16 formed in a later step, and therefore should be 0.1 μm or more. Is desirable.

  FIG. 6 is a cross-sectional view showing a state in which the formation of the electric field relaxation region 16 has been completed. After the implantation mask 22 is formed, an ion implantation process is performed on a region in the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 where the implantation mask 22 is not formed. As a result, as shown in FIG. 6, a plurality of electric field relaxation regions 16 are formed so as to include each FLR region 15.

  The ion implantation process in this step for forming the electric field relaxation region 16 may be performed with a single implantation energy, or while stepping the implantation energy, for example, stepping from high energy to low energy. You may go.

  In the ion implantation process, ions are implanted deeper as the implantation energy increases. Therefore, in the present embodiment, the ion implantation process is performed with an energy larger than the ion implantation energy for forming the FLR region 15. That is, the acceleration energy of the ion implantation in the second implantation step, which is the ion implantation energy for forming the electric field relaxation region 16, is the acceleration of the ion implantation in the first implantation step, which is the ion implantation energy for forming the FLR region 15. Greater than energy. By doing so, the electric field relaxation region 16 can be formed so as to be in contact with the bottom of the FLR region 15.

  The horizontal dimension of the portion of the electric field relaxation region 16 in contact with the side of the FLR region 15 (hereinafter referred to as “side width”) is preferably 0.1 μm or more. The dimension (hereinafter sometimes referred to as “depth”) in the depth direction, which is the direction along the thickness direction of the semiconductor substrate 11, of the portion of the electric field relaxation region 16 in contact with the bottom of the FLR region 15 is 0.1 μm or more. Is desirable.

  After each of the aforementioned ion implantation processes, an activation annealing process is performed. Thereby, each impurity ion-implanted in each process described above can be electrically activated. Further, the crystallinity of the ion implantation region can be recovered together by the activation annealing treatment.

FIG. 7 is a cross-sectional view showing a state in which the formation of the protective film 17 has been completed. After the electric field relaxation region 16 is formed, a protective film 17 is formed on the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 as shown in FIG. The protective film 17 is realized by an insulating film made of an insulating material such as SiO ₂ or polyimide.

  FIG. 8 is a cross-sectional view showing a state in which the formation of the opening 18 has been completed. After the protective film 17 is formed, an opening 18 is formed in the protective film 17 as shown in FIG. As shown in FIG. 8, the opening 18 is formed such that the ohmic contact region 14 is exposed from the bottom of the opening 18.

  FIG. 9 is a cross-sectional view showing a state in which the formation of the anode electrode 19 has been completed. After the opening 18 is formed, an anode electrode 19 is formed as shown in FIG. 9 so as to be electrically connected to the ohmic contact region 14 exposed from the bottom of the opening 18.

  FIG. 10 is a cross-sectional view showing a state in which the formation of the cathode electrode 20 has been completed. After the anode electrode 19 is formed, the cathode electrode 20 is formed on the surface on the other side in the thickness direction of the semiconductor substrate 11 as shown in FIG.

  Through the above steps, the semiconductor device 1 according to the first embodiment of the present invention shown in FIG. 1 is obtained. In the present embodiment, the semiconductor device 1 having a structure in which the electric field relaxation region 16 is in contact with the side portion and the bottom portion of each FLR region 15 can be obtained.

  The semiconductor device 1 having such a configuration can reduce the electric field intensity reaching the substrate surface or the device surface when a relatively high reverse voltage is applied to the pn junction, as described above. Electric field strength can also be reduced. Therefore, according to the method for manufacturing a semiconductor device of the present embodiment, it is possible to provide a high breakdown voltage semiconductor device 1 that can improve reliability and obtain a stable breakdown voltage.

  Such an effect of the semiconductor device 1 of the present embodiment has been confirmed by the simulation results shown below. The simulation will be described in detail below. In the following simulation studied by the inventors of the present application, assuming that a semiconductor device having a withstand voltage of 3300 V, specifically, a pn diode is manufactured as the semiconductor device 1, each element is set to the following values.

The implantation surface density of the second conductivity type semiconductor region 13 and the FLR region 15 is 5 × 10 ¹⁴ cm ^−2, and the implantation energy of the second conductivity type semiconductor region 13 and the FLR region 15 is 500 keV. Further, the injection surface density of the electric field relaxation region 16 is 1 × 10 ¹³ cm ^−2, and the injection energy of the electric field relaxation region 16 is 700 keV. Since the electric field relaxation region 16 has a larger implantation energy than the FLR region 15, the electric field relaxation region 16 is formed in contact with at least the bottom of the FLR region 15.

  In this simulation, it is assumed that the termination structure is an FLR structure formed by 20 FLR regions 15. Here, for comparison, it is assumed that two types of termination structures, specifically, two types of FLR structures are formed.

  In the first type of FLR structure, the mask reduction width for forming the electric field relaxation region 16 is 0 μm, and the electric field relaxation region 16 is formed so as to contact only the bottom of the FLR region 15. That is, in the first type of FLR structure, the electric field relaxation region 16 is formed using an implantation mask for forming the FLR region 15 without reducing it.

  The second type of FLR structure has a mask reduction width for forming the electric field relaxation region 16 of 0.1 μm, and is formed so that the electric field relaxation region 16 is in contact with the side portion and the bottom portion of the FLR region 15. is there. Therefore, with respect to the impurity concentration of the second conductivity type in the lateral direction, the slope of the concentration distribution is more gentle in the second type FLR structure than in the first type FLR structure.

  In the following description, the first type of FLR structure may be referred to as “comparative FLR structure A” and the second type of FLR structure may be referred to as “present FLR structure B”. These may be collectively referred to as “FLR structures A and B”. In these two types of FLR structures A and B, the surface on one side in the thickness direction of the semiconductor epitaxial layer 12 may be referred to as “substrate surface S0”. It is assumed that a reverse voltage of 3300 V is applied to the pn diode that is the semiconductor device 1 in which these two types of FLR structures A and B are formed.

  FIG. 11 is a graph showing the relationship between the electric field intensity reaching the substrate surface and the distance from the second conductivity type semiconductor region 13 in two types of termination structures. In FIG. 11, the horizontal axis indicates the distance [μm] from the second conductivity type semiconductor region 13, and the vertical axis indicates the electric field strength [MV / cm]. The direction of the horizontal axis in FIG. 11 corresponds to the horizontal direction of the substrate, that is, the left-right direction toward the paper surface of FIG. FIG. 11 shows the electric field reaching the substrate surface S0 as a function of the distance from the second conductivity type semiconductor region 13 for the two types of FLR structures A and B.

  The maximum value of the electric field intensity reaching the substrate surface S0 is 2. when the mask reduction width for forming the electric field relaxation region 16 is 0 μm as in the comparative FLR structure A which is the first type of FLR structure. 7 MV / cm. On the other hand, as in the present FLR structure B which is the second type of FLR structure, the mask reduction width for forming the electric field relaxation region 16 is formed to be 0.1 μm, and the second conductivity type impurity in the lateral direction is formed. It was found that the maximum value of the electric field intensity reaching the substrate surface S0 is 1.6 MV / cm when the concentration distribution has a gentler slope than the first type FLR structure A. .

  From the above results, the following can be understood. In the present embodiment, the electric field relaxation region 16 having an impurity concentration equal to or less than one-tenth (1/10) the impurity concentration of the FLR region 15 is placed inside and outside of the FLR region 15 in the lateral direction. Forms in contact with. In this case, by setting the mask reduction width in trimming to 0.1 μm or more and providing the electric field relaxation region 16 on the side of the FLR region 15 to 0.1 μm or more, the concentration distribution in the lateral direction to the extent that ions are scattered can be obtained. Compared to the inclination, a gentle concentration distribution inclination is realized.

  As a result, when a high reverse voltage is applied to the pn junction, the degree of concentration of the electric field is relaxed, and the electric field intensity reaching the substrate surface is reduced. Therefore, creeping discharge outside the substrate can be suppressed, and the breakdown voltage of the semiconductor device can be prevented from being lowered. Therefore, it is possible to realize a high breakdown voltage semiconductor device that can suppress the concentration of the electric field and obtain a stable breakdown voltage.

  FIG. 12 is a graph showing the relationship between the reverse voltage applied to the two types of termination structures and the maximum value of the electric field strength inside the device. In FIG. 12, the horizontal axis represents the reverse voltage [V], and the vertical axis represents the maximum electric field strength [MV / cm].

In FIG. 12, after the FLR region 15 is formed with an implantation surface density of 5 × 10 ¹⁴ cm ⁻² and an implantation energy of 500 keV, the implantation mask is trimmed with a reduction width of 0.1 μm, and the implantation surface density is 1 ×. 10 ¹³ cm ⁻² , implantation energy is set to 700 keV, and the maximum value of the electric field strength inside the device for each structure when the electric field relaxation region 16 is formed (D) and when the electric field relaxation region 16 is not formed (C). And the reverse voltage. In the following description, the FLR structure when the electric field relaxation region 16 is formed may be referred to as “FLR structure D”, and the FLR structure when the electric field relaxation region 16 is not formed may be referred to as “FLR structure C”. Further, these may be collectively referred to as “FLR structures C and D”.

  13 and 14 are diagrams showing simulation results of the cross-sectional electric field intensity distribution at the end of the FLR region. 13 and 14, the horizontal axis indicates the distance X [μm] from the second conductivity type semiconductor region 13, and the vertical axis indicates the distance Y [μm] from the substrate surface S0. The horizontal axis directions in FIGS. 13 and 14 correspond to the horizontal direction of the substrate, that is, the left-right direction toward the paper surface of FIG. In FIG. 13 and FIG. 14, the electric field strength distribution is shown for the two types of FLR structures C and D described above. FIG. 13 shows a simulation result of the FLR structure C, and FIG. 14 shows a simulation result of the FLR structure D.

  From the simulation results shown in FIG. 13, when the electric field relaxation region 16 is not formed (C), the maximum value P1 of the electric field strength inside the device when a reverse voltage of 3300 V is applied is 3.8 MV / cm. I understood.

  Further, from the simulation results shown in FIG. 14, when the electric field relaxation region is formed (D), the maximum value P2 of the electric field strength inside the device when a reverse voltage of 3300 V is applied is 3.0 MV / cm. I understood. From this, it can be seen that the formation of the electric field relaxation region 16 can also reduce the electric field strength inside the device and improve the reliability.

In the present embodiment, when the semiconductor device 1 including the FLR region 15 and the electric field relaxation region 16 having the above-described configuration is manufactured, in order to form the FLR region 15 and the electric field relaxation region 16, Ion implantation treatment. In the ion implantation process for forming the FLR region 15, it is desirable to perform the ion implantation process so that the implantation surface density is 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . The implantation surface density is equal to the integral of the impurity concentration over the thickness of the impurity region. When the impurity concentration is constant, the implantation surface density is equal to the product of the impurity concentration and the thickness of the impurity region.

Here, the depth of the FLR region 15, that is, the thickness which is a dimension in the thickness direction is about 0.2 μm to 2.0 μm. Further, the FLR region 15 is composed of about 2 to 100, and has a uniform implantation width / interval arrangement, a non-uniform implantation width / interval arrangement, and / or a uniform implantation width / interval. They are arranged in a uniform injection width / interval combination. Further, in the ion implantation process for forming the electric field relaxation region 16, it is desirable to perform the ion implantation process so that the implantation surface density is 1 × 10 ¹² cm ^{−2 to} 5 × 10 ¹³ cm ^−2. .

  Here, the depth, that is, the thickness of the electric field relaxation region 16 is about 0.4 μm to 3.0 μm. The implantation mask reduction width for forming the electric field relaxation region 16 is desirably 0.1 μm or more. Moreover, it is desirable that the electric field relaxation region 16 is in contact with the side portion and the bottom portion of the FLR region 15. The width of the side portion of the electric field relaxation region 16 that is in contact with the side portion of the FLR region 15 is preferably 0.1 μm or more. The depth of the electric field relaxation region 16 in contact with the bottom of the FLR region 15, that is, the dimension in the depth direction is preferably 0.1 μm or more. Thereby, the effect of the present invention is sufficiently exhibited.

<Second Embodiment>
FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device 2 according to the second embodiment of the present invention. Since the semiconductor device 2 according to the present embodiment is similar in configuration to the semiconductor device 1 according to the first embodiment described above, different parts from the semiconductor device 1 will be described, and parts corresponding to the semiconductor device 1 will be described. The same reference numerals are assigned and common description is omitted. Also in the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type, as in the first embodiment.

  The semiconductor device 2 of the present embodiment is a pn diode, like the semiconductor device 1 of the first embodiment described above. Similar to the semiconductor device 1 of the first embodiment described above, the semiconductor device 2 of the present embodiment has a semiconductor substrate 11, a semiconductor epitaxial layer 12, a second conductivity type semiconductor region 13, an ohmic contact region 14, and an FLR region. 25, an electric field relaxation region 26, a protective film 17, an anode electrode 19, and a cathode electrode 20.

  In the semiconductor device 1 of the first embodiment described above, as shown in FIG. 1 described above, a plurality of FLR regions 15 and electric field relaxation regions 16 are formed up to the substrate surface. On the other hand, in the semiconductor device 2 of the present embodiment, as shown in FIG. 15, a plurality of FLR regions 25 and electric field relaxation regions 26 are formed apart from the substrate surface. That is, the first conductivity type semiconductor epitaxial layer 12 is interposed between the substrate surface and the FLR region 25 and the electric field relaxation region 26. In other words, the first conductivity type semiconductor epitaxial layer 12 is present on the surface side of the semiconductor epitaxial layer 12 relative to the FLR region 25 and the electric field relaxation region 26. The first conductivity type semiconductor epitaxial layer 12 corresponds to a first conductivity type semiconductor region.

  In the semiconductor device 2 of the present embodiment, when the FLR region 25 and the electric field relaxation region 26 are formed by the ion implantation process, the semiconductor epitaxial layer 12 remains so as to remain on the FLR region 25 and the electric field relaxation region 26. Manufactured by adjusting the injection energy.

  The distance from the substrate surface to the FLR region 25 and the electric field relaxation region 26 is preferably 0.1 μm or more. As a result, the FLR region 25 and the electric field relaxation region 26 can have a position where the impurity concentration is maximized in the depth direction at a position separated by 0.1 μm or more from the surface of the semiconductor epitaxial layer 12. At this time, the plurality of FLR regions 25 are formed so as to have the same impurity concentration at the same depth from the surface of the semiconductor epitaxial layer 12.

  Also in the semiconductor device 2 of the present embodiment, the same effect as that described in the first embodiment can be obtained. That is, even when a relatively high reverse voltage is applied to the pn junction, the electric field strength reaching the substrate surface can be reduced and the electric field strength inside the device can also be reduced. Therefore, it is possible to provide a high breakdown voltage semiconductor device that can obtain a stable breakdown voltage.

<Third Embodiment>
FIG. 16 is a cross-sectional view showing a configuration of the semiconductor device 3 according to the third embodiment of the present invention. Since the semiconductor device 3 of the present embodiment is similar in configuration to the semiconductor device 2 of the second embodiment described above, only the parts different from the semiconductor device 2 will be described, and the parts corresponding to the semiconductor device 2 will be described. The same reference numerals are assigned and common description is omitted. Also in the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type, as in the first embodiment.

  The semiconductor device 3 according to the present embodiment is a pn diode, like the semiconductor device 2 according to the second embodiment described above. Similar to the semiconductor device 2 of the second embodiment, the semiconductor device 3 of the present embodiment has a semiconductor substrate 11, a semiconductor epitaxial layer 12, a second conductivity type semiconductor region 13, an ohmic contact region 14, and an FLR region. 35, an electric field relaxation region 36, a protective film 17, an anode electrode 19, and a cathode electrode 20.

  In the semiconductor device 2 of the second embodiment described above, the first conductivity type semiconductor epitaxial layer 12 is interposed on the plurality of FLR regions 25 as shown in FIG. On the other hand, in the semiconductor device 3 of the present embodiment, as shown in FIG. 16, the electric field relaxation region 36 is formed so as to be in contact with the upper portions of the plurality of FLR regions 35. The first conductivity type semiconductor epitaxial layer 12 is interposed therebetween.

  In the semiconductor device 3 of the present embodiment, when the FLR region 35 and the electric field relaxation region 36 are formed by ion implantation, the semiconductor epitaxial layer 12 is further left on the FLR region 35 and the electric field relaxation region 36. It is manufactured by adjusting the ion implantation energy so that the electric field relaxation region 36 is in contact with the upper part of the FLR region 35.

  Also in the semiconductor device 3 of the present embodiment, the same effect as that described in the first embodiment can be obtained. That is, even when a relatively high reverse voltage is applied to the pn junction, the electric field strength reaching the substrate surface can be reduced and the electric field strength inside the device can also be reduced. Therefore, it is possible to provide a high breakdown voltage semiconductor device that can obtain a stable breakdown voltage.

  In the first to third embodiments described above, the case where the semiconductor device is a pn diode has been described. However, as a termination structure, a Schottky diode, a MOSFET, and an insulated gate bipolar having an FLR region and an electric field relaxation region. Also in a transistor (Insulated Gate Bipolar Transistor; abbreviation: IGBT), etc., the structure of each of the above-described embodiments, that is, an electric field relaxation region having a predetermined width from the lateral end of the FLR region and having an impurity concentration lower than that of the FLR region. A structure in which is formed can be applied.

  In addition, the effect of precise impurity concentration control as in the present invention is particularly large for a material that hardly causes thermal diffusion of impurities such as SiC (silicon carbide, silicon carbide) as a semiconductor. That is, as in the first to third embodiments, the semiconductor substrate 11, the semiconductor epitaxial layer 12, the second conductivity type semiconductor region 13, the ohmic contact region 14, the FLR region 15, and the electric field, which are parts composed of semiconductors. The effect is particularly great when relaxation region 16 is made of silicon carbide.

  In the first to third embodiments described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type, The conductivity type may be n-type. In this case, the semiconductor substrate 11, the semiconductor epitaxial layer 12, and the electric field relaxation regions 16, 26, and 36 have p-type conductivity, and the second conductivity type semiconductor region 13, the ohmic contact region 14, and the FLR regions 15, 25, 35 has n-type conductivity.

  In the present invention, the constituent elements of the embodiments can be appropriately modified or omitted within the scope of the invention.

  1, 2, 3 Semiconductor device, 11 Semiconductor substrate, 12 Semiconductor epitaxial layer, 13 Second conductivity type semiconductor region, 14 Ohmic contact region, 15, 25, 35 FLR region, 16, 26, 36 Electric field relaxation region, 17 Protective film , 18 opening, 19 anode electrode, 20 cathode electrode.

Claims (10)

A semiconductor substrate having a first conductivity type;
A semiconductor epitaxial layer provided on the surface of one side in the thickness direction of the semiconductor substrate and having a first conductivity type;
A second conductivity type semiconductor region having a second conductivity type, formed in a part of the surface vicinity of one side in the thickness direction of the semiconductor epitaxial layer;
Of the vicinity of the surface on one side in the thickness direction of the semiconductor epitaxial layer, formed in an annular shape spaced apart from each other at a portion closer to the outer peripheral end of the semiconductor epitaxial layer than the semiconductor region of the second conductivity type, A plurality of junction termination regions having a conductivity type;
An electric field relaxation region formed in contact with the junction termination region on the radially inner side and outer side of each junction termination region and having the second conductivity type,
A protective film provided on the semiconductor region of the second conductivity type and on the junction termination region,
The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the electric field relaxation region is 1/10 or less of the concentration of the second conductivity type impurity in the junction termination region.   2. The semiconductor device according to claim 1, wherein the electric field relaxation region has a dimension in a lateral direction perpendicular to a thickness direction of the semiconductor substrate of 0.1 μm or more. The electric field relaxation region is formed inside the semiconductor epitaxial layer and in contact with a bottom portion that is an end portion of the junction termination region in the thickness direction of the semiconductor substrate,
3. The semiconductor device according to claim 2, wherein a dimension in a depth direction along a thickness direction of the semiconductor substrate of a portion in contact with the bottom portion of the electric field relaxation region is 0.1 μm or more.   The plurality of junction termination regions have the same impurity concentration at the same depth from the surface of the semiconductor epitaxial layer, and the position where the impurity concentration is maximum in the depth direction is the position of the semiconductor epitaxial layer. The semiconductor device according to claim 1, wherein the semiconductor device is present at a position separated by 0.1 μm or more from the surface.   2. The semiconductor device according to claim 1, further comprising a first conductivity type semiconductor region having a first conductivity type on a surface side of the semiconductor epitaxial layer with respect to each junction termination region.   The semiconductor device according to claim 1, wherein the semiconductor substrate, the semiconductor epitaxial layer, the semiconductor region, the junction termination region, and the electric field relaxation region are made of silicon carbide. An epitaxial layer forming step of forming a semiconductor epitaxial layer having the first conductivity type on the surface on one side in the thickness direction of the semiconductor substrate having the first conductivity type;
A semiconductor region forming step of forming a second conductivity type semiconductor region having a second conductivity type in a part of the surface vicinity of one side in the thickness direction of the semiconductor epitaxial layer;
Ion implantation in which a plurality of annular openings are formed on the surface of one side in the thickness direction of the semiconductor epitaxial layer, spaced apart from each other on the outer peripheral end side of the semiconductor epitaxial layer with respect to the semiconductor region of the second conductivity type. A first implantation step of forming a plurality of junction termination regions by ion-implanting a second conductivity type impurity through the formed ion implantation mask after forming the mask;
By trimming the ion implantation mask, the width of each opening is increased by a predetermined expansion width, and then ion implantation of a second conductivity type impurity is performed through the ion implantation mask to thereby form an electric field relaxation region. A method of manufacturing a semiconductor device, comprising: a second implantation step to be formed.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the surface density of the ion implantation in the second implantation step is 1/10 or less of the surface density of the ion implantation in the first implantation step.   The method of manufacturing a semiconductor device according to claim 7, wherein the expansion width is 0.1 μm or more.   8. The method of manufacturing a semiconductor device according to claim 7, wherein acceleration energy of ion implantation in the second implantation step is larger than acceleration energy of ion implantation in the first implantation step.