JP2013168454A - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

There is provided a semiconductor memory device capable of reducing an initial break voltage and suppressing variations between elements.
A substrate, a first interlayer insulating film formed on the substrate, and at least a part of the surface of the first interlayer insulating film are exposed upward from the surface of the first interlayer insulating film. The first wiring 51 formed as described above, the first electrode 11 formed across the boundary between the surface of the first interlayer insulating film 1 and the surface of the first wiring 51, and the second transition metal oxide. The configured low oxygen deficiency layer 22 and the high oxygen deficiency layer 21 configured using the first transition metal oxide having a larger oxygen deficiency than the second transition metal oxide are stacked in this order or in reverse order. And the second electrode 12 formed on the resistance change element 70, and the boundary between the surface of the first interlayer insulating film 1 and the exposed surface of the first wiring 51 is A step 1a is formed, and the low oxygen deficiency layer 22 is formed along the shape of the boundary. Having a stepped portion 22a at.
[Selection] Figure 1B

Description

  The present invention relates to a resistance change type semiconductor memory device (nonvolatile semiconductor memory device) whose resistance value reversibly changes by application of a voltage pulse.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile memory represented by a flash memory is rapidly expanding. Further, research and development of a variable resistance nonvolatile memory element using a so-called variable resistance element is progressing as a next-generation new nonvolatile memory that replaces the flash memory. Here, the resistance change element refers to an element having a property that the resistance value reversibly changes when a voltage pulse (electrical signal) is applied. By assigning information to each resistance value of the variable resistance element, information can be stored in a nonvolatile manner.

  As an example of the variable resistance element, a semiconductor memory element is disclosed in which transition metal oxides having different oxygen contents are stacked and used for the variable resistance layer (see, for example, Patent Document 1). In this semiconductor memory element, two tantalum oxide layers having different oxygen contents are stacked and used as a resistance change layer. By applying a voltage pulse between the upper and lower electrodes of the resistance change element having the resistance change layer having such a laminated structure, at the interface between the resistance change layer having a high oxygen content and the electrode in contact with the resistance change layer, It is disclosed to selectively generate an oxidation / reduction reaction to stabilize a resistance change.

International Publication No. 2008/149484

  Here, the “oxygen content” is indicated by the ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide. On the other hand, the “oxygen deficiency” refers to the ratio of oxygen deficiency with respect to the amount of oxygen constituting the oxide having the stoichiometric composition in each transition metal oxide. .

  In order to immediately function the layer formed by stacking two tantalum oxide layers having different oxygen contents described above as a resistance change layer, in general, the initial break voltage is once after the manufacturing. It is necessary to perform an initial break operation for applying. When an initial break voltage is applied, a part of the tantalum oxide layer having a high oxygen content and a high resistance value is locally short-circuited (a conductive path or filament is formed at the initial break). Thus, a transition is made to a state in which a resistance change occurs in the conductive path or filament. The voltage value of the initial break voltage is generally larger than the voltage value of the voltage pulse applied to change the resistance state of the resistance change layer during the normal operation of the semiconductor memory device.

  The conventional resistance change element described above has a problem that the initial break voltage increases and the initial break voltage varies from one resistance change element to another. Therefore, it is required to achieve both reduction in the initial break voltage applied to the resistance variable element and suppression of variations in the initial break voltage.

  Therefore, the present invention reduces the initial break voltage applied to the nonvolatile memory element used for the resistance change layer by laminating transition metal oxide layers having different degrees of oxygen deficiency, and reduces variations thereof. Objective.

  In order to solve the above problems, a semiconductor memory device according to the present invention includes a substrate, an interlayer insulating film formed on the substrate, and at least part of a surface of the interlayer insulating film on the interlayer insulating film. A wiring formed in a state exposed from the upper surface of the film, a lower electrode formed across the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring, and an oxygen-deficient second transition metal oxide. A low oxygen deficiency layer configured using a high oxygen deficiency layer configured using a first transition metal oxide having a greater oxygen deficiency than the second transition metal oxide on the lower electrode. A variable resistance layer formed by stacking and an upper electrode formed on the variable resistance layer, and a step is formed at a boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring. The low oxygen deficiency layer of the variable resistance layer is formed in the boundary shape. By being formed along, it has a stepped portion in cross section.

  In the semiconductor memory device according to the present invention, a step is formed at the boundary between the exposed surface of the wiring and the surface of the interlayer insulating film, and the resistance change is configured by the lower electrode, the upper electrode, and the resistance change layer across the boundary. By stacking the elements, a step portion in a cross-sectional view is formed in the low oxygen deficiency layer constituting the resistance change layer. The stepped portion forms a locally thinned or bent portion in the low oxygen deficiency layer, so that the initial break voltage can be lowered. Furthermore, in the present invention, since the shape of the stepped portion of the low oxygen deficiency layer can be created relatively stably, variation between elements can be reduced.

FIG. 1A is a plan view showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a configuration example of the semiconductor memory device according to Embodiment 1 of the present invention. FIG. 2A is a cross-sectional view showing a step of forming the first interlayer insulating film and the first wiring in the method for manufacturing the semiconductor memory device in the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing a step of selectively patterning the first interlayer insulating film in the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention. FIG. 2C is a cross-sectional view illustrating a process of forming the first electrode film, the high oxygen deficiency film, the low oxygen deficiency film, and the second electrode film in the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention. It is. FIG. 2D is a cross-sectional view showing the step of forming the variable resistance element in the method for manufacturing the semiconductor memory device in the first embodiment of the present invention. FIG. 2E is a cross-sectional view showing a step of forming a second interlayer insulating film in the first embodiment. FIG. 2F is a cross-sectional view showing a step of forming a contact plug in the first embodiment. FIG. 2G is a cross-sectional view showing a step of forming the second wiring in the first embodiment. FIG. 3A is a schematic block diagram showing another example of the positional relationship between the first wiring and the resistance change element in Modification 1 of Embodiment 1 of the semiconductor memory device according to the invention. FIG. 3B is a schematic block diagram showing another example of the positional relationship between the first wiring and the resistance change element in Modification 2 of Embodiment 1 of the semiconductor memory device according to the invention. FIG. 3C is a schematic block diagram showing another example of the positional relationship between the first wiring and the resistance change element in Modification 3 of Embodiment 1 of the semiconductor memory device according to the invention. FIG. 4A is a plan view showing a configuration example of the semiconductor memory device according to the second embodiment of the present invention. FIG. 4B is a cross-sectional view showing a configuration example of the semiconductor memory device in the second embodiment of the present invention. FIG. 5A is a plan view showing a configuration example of the semiconductor memory device according to the third embodiment of the present invention. FIG. 5B is a cross-sectional view showing a configuration example of the semiconductor memory device according to Embodiment 3 of the present invention. FIG. 6A is a cross-sectional view showing a step of forming the first interlayer insulating film and the first wiring in the method for manufacturing the semiconductor memory device in the third embodiment of the present invention. FIG. 6B is a cross-sectional view showing a step of forming a third interlayer insulating film in the method for manufacturing the semiconductor memory device in the third embodiment of the present invention. FIG. 6C is a cross-sectional view showing a step of selectively patterning the TEOS film in the method of manufacturing a semiconductor memory device according to the third embodiment of the present invention. FIG. It is a top view which shows the process of selectively patterning a TEOS film | membrane among the manufacturing methods of the semiconductor memory device in Embodiment 3 of invention. 6D is a cross-sectional view showing a step of forming the first electrode film, the high oxygen deficiency film, the low oxygen deficiency film, and the second electrode film in the method for manufacturing the semiconductor memory device according to the third embodiment of the present invention. It is. FIG. 6E is a cross-sectional view showing the step of forming the resistance change element in the method for manufacturing the semiconductor memory device in the third embodiment of the present invention. FIG. 7A is a plan view showing a configuration example of a semiconductor memory device according to a modification of the third embodiment of the present invention. FIG. 7B is a cross-sectional view showing a configuration example of the semiconductor memory device according to the modification of the third embodiment of the present invention. FIG. 8A is a cross-sectional view showing a step of selectively patterning the TEOS film in the method for manufacturing a semiconductor memory device according to the modification of the third embodiment of the present invention, and FIG. These are top view which shows the process of selectively patterning a TEOS film | membrane among the manufacturing methods of the semiconductor memory device in the modification of Embodiment 3 of this invention. FIG. 9 is a cross-sectional view showing a configuration example of a conventional first semiconductor memory device. FIG. 10 is a cross-sectional view showing a configuration example of a second conventional semiconductor memory device. FIG. 11A is a cross-sectional view of the conventional first and second semiconductor memory devices based on SEM images. FIG. 11B is a cross-sectional view of the conventional first and second semiconductor memory devices based on SEM images. FIG. 12 is a graph showing variations in initial break voltages of the conventional first and second semiconductor memory devices.

(Explanation of terms, etc.)
In the embodiment of the present invention, the “step portion” indicates a bent shape in a sectional view. “Linear part” indicates a linear shape in plan view, and “curved part” indicates a non-linear shape in plan view, and includes shapes such as corners and arcs.

  In addition, “rectangle”, “square”, and the like in the description of the shapes of elements constituting the semiconductor memory device include not only general rectangles and squares but also shapes including rounded corners in a normal manufacturing process. .

  “Oxygen content” is indicated by the ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide. The “oxygen deficiency” refers to the ratio of oxygen deficiency with respect to the amount of oxygen constituting the oxide having the stoichiometric composition in each transition metal oxide.

  “Oxygen-deficient transition metal oxide” means that the oxygen content (atomic ratio: the ratio of the number of oxygen atoms to the total number of atoms) is higher than that of a transition metal oxide having a stoichiometric composition. Less transition metal oxide.

The “transition metal oxide having a stoichiometric composition” refers to a transition metal oxide having an oxygen deficiency of 0%. For example, in the case of tantalum oxide, it refers to Ta ₂ O ₅ which is an insulator. Note that the transition metal oxide has conductivity by adopting an oxygen-deficient type.

More specifically, when the transition metal is tantalum (Ta), the stoichiometric composition of the transition metal oxide is Ta ₂ O ₅ , and can be expressed as TaO _2.5 . The degree of oxygen deficiency of TaO _2.5 is 0 [%]. For example, the oxygen deficiency of an oxygen deficient tantalum oxide having a composition of TaO _1.5 is oxygen deficiency = (2.5−1.5) /2.5=40 [%]. On the other hand, as described above, the oxygen content is represented by the ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide. The oxygen content of Ta ₂ O ₅ is the ratio of the number of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 [atm%]. Therefore, the oxygen-deficient tantalum oxide has an oxygen content larger than 0 and smaller than 71.4 [atm%].

(Background of the invention)
Hereinafter, before explaining the details of the present invention, new findings obtained by the inventors through experiments will be described.

  9 and 10 are cross-sectional views schematically showing an example of a conventional resistance change type semiconductor memory device.

  As shown in FIG. 9, a resistance change type semiconductor memory device 1000 including a conventional resistance change element includes a first wiring 1101 formed on a substrate 1100 and a first wiring covering the first wiring 1101. An interlayer insulating layer 1102 and a first contact hole 1103 penetrating through the first interlayer insulating layer 1102 and reaching the first wiring 1101 are embedded and electrically connected to the first wiring 1101. 1 contact plug 1104.

  Further, the semiconductor memory device 1000 is formed on the lower electrode 1105 and the lower electrode 1105 formed on the first interlayer insulating layer 1102 so as to cover the entire exposed surface of the first contact plug 1104. A resistance change element having a resistance change layer 1106 and an upper electrode 1107 formed on the resistance change layer 1106 is provided.

  Further, the semiconductor memory device 1000 includes a second interlayer insulating layer 1108 formed so as to cover the variable resistance element, and a second contact hole that reaches the upper electrode 1107 through the second interlayer insulating layer 1108. A second contact plug 1110 embedded in 1109 and electrically connected to the upper electrode 1107 and a second wiring 1111 electrically connected to the second contact plug 1110 are provided.

  More specifically, the resistance change layer 1106 includes a first resistance change layer 1106a (high oxygen deficiency layer) formed using an oxygen-deficient first transition metal oxide, and oxygen from the first transition metal oxide. It has a laminated structure with the second resistance change layer 1106b (low oxygen deficiency layer) made of the second transition metal oxide with a low deficiency.

  When a voltage pulse is applied to the variable resistance element having such a structure, most of the voltage is applied to the second variable resistance layer 1106b having a low oxygen deficiency and a higher resistance value. Further, in the vicinity of the interface between the second resistance change layer 1106b and the upper electrode 1107, there is also abundant oxygen that can contribute to the reaction. Therefore, an oxidation / reduction reaction occurs selectively at the interface between the upper electrode 1107 and the second resistance change layer 1106b, and the resistance change can be realized stably.

  In order to make the above-described laminated structure of two transition metal oxides having different degrees of oxygen deficiency function as a resistance change layer, it is necessary to perform an initial break operation of applying an initial break voltage once in the initial stage after manufacturing. When the initial break voltage is applied, a part of the second transition metal oxide having a small oxygen deficiency and a high resistance value among the two transition metal oxides is locally short-circuited (initial break), and the resistance change is caused. Transition to the resulting state. The voltage value of the initial break voltage is generally larger than the voltage value of the voltage pulse applied to change the resistance state of the resistance change layer during the normal operation of the semiconductor memory device.

  Here, in the semiconductor memory device 1000 shown in FIG. 9, the upper surface of the first contact plug 1104 and the upper surface of the first interlayer insulating layer 1102 are not continuous, and recesses (5 to 50 [nm]) are formed in the discontinuous portions. ) Has occurred. Therefore, gentle recesses are also generated on the surfaces of the lower electrode 1105, the first variable resistance layer 1106a, the second variable resistance layer 1106b, and the upper electrode 1107 formed on the first contact plug 1104. . The recess has a problem that the resistance change characteristic varies between elements and the initial break voltage varies.

  On the other hand, as shown in FIG. 10, there is a semiconductor memory device 1001 in which the surface of the lower electrode 1105 is flattened to eliminate the recess and suppress the variation in the initial break voltage. More specifically, in the semiconductor memory device 1001 illustrated in FIG. 10, the lower electrode 1105 is formed so as to enter the recessed portion generated above the first contact plug 1104, so that the surface of the lower electrode 1105 is flat. It has become. As a result, the thickness of the lower electrode 1105 on the first contact plug 1104 is thicker than that of the first interlayer insulating layer 1102.

  The resistance change type semiconductor memory device 1001 shown in FIG. 10 has excellent surface flatness, so that variations in the shape and film thickness of the resistance change layer 1106 can be suppressed, and variations in resistance change characteristics can be reduced. . In particular, the variation in film thickness of the second resistance change layer 1106b, which is a thin film with a small oxygen deficiency and high resistance, is suppressed, and the initial break operation is stabilized, thereby greatly reducing the variation for each bit. A semiconductor memory device (nonvolatile memory) having a capacity can be realized.

  However, in the semiconductor memory device 1001 shown in FIG. 10, the problem that the initial break voltage varies can be solved, but the problem that the initial break voltage becomes large occurs.

  In the following, new knowledge on the subject will be described with reference to FIGS. 11 and 12, which is intended to assist in understanding embodiments of the present invention described later. Therefore, the present invention is not limited to these drawings and the description thereof.

  FIG. 11A is a cross-sectional view of the first conventional semiconductor memory device 1000 shown in FIG. 9, which was actually made as a prototype and imaged with a scanning electron microscope (SEM). FIG. 11B is a cross-sectional view of the semiconductor memory device 1001 of the second conventional example shown in FIG.

  In this experiment, in both the semiconductor memory device 1000 and the semiconductor memory device 1001, the first contact plug 1104 is formed using tungsten as a material.

  The lower electrode 1105 includes three layers, a tantalum nitride layer using tantalum nitride as a material, a titanium nitride aluminum layer using titanium nitride aluminum as a material, and a titanium nitride layer using titanium nitride as a material from the upper surface. (Laminated structure).

The first variable resistance layer 1106a of the variable resistance layer 1106 was formed of tantalum oxide (TaO _x ) as an example of an oxygen-deficient (oxygen deficient) first transition metal oxide. The second resistance change layer 1106b is formed of Ta ₂ O ₅ (actually sufficiently high resistance but may be slightly deficient in oxygen) as an example of the second transition metal oxide.

  The upper electrode 1107 was formed using iridium as the upper electrode material.

  The second contact plug 1110 was formed using tungsten as a material.

  As shown in FIG. 11A, in the semiconductor memory device 1000, a recess is generated on the first contact plug 1104, which affects the shape of the lower electrode 1105, and about 40 [nm] on the surface of the lower electrode 1105. The dent has occurred. Similarly, the recess of the lower electrode 1105 affects the resistance change layer 1106 formed thereon, and the resistance change layer 1106 has a recess at the center. Thereby, the film thickness of the central portion of the resistance change layer 1106 is slightly thinner than other portions. In particular, when a voltage is applied between the upper electrode 1107 and the lower electrode 1105, the second resistance change layer 1106b to which a voltage is effectively applied is as thin as a few [nm], so that its shape In addition, the film thickness variation has affected the variation in resistance change characteristics.

  On the other hand, as shown in FIG. 11B, in the semiconductor memory device 1001, the surface of the lower electrode 1105 is formed to be flat. For this reason, the surfaces of the first variable resistance layer 1106a and the second variable resistance layer 1106b formed on the lower electrode 1105 are also flat, and the film thickness variation is extremely small.

  FIG. 12 is a graph showing initial break voltages of the semiconductor memory device 1000 and the semiconductor memory device 1001 described above. More specifically, this graph shows a result of evaluating an initial break voltage required when a variable resistance element and a load resistance 5 k [Ω] are connected in series. The vertical axis of the graph indicates the initial break voltage [V], “1” on the horizontal axis of the graph indicates the semiconductor memory device 1000, and “2” indicates the semiconductor memory device 1001.

  As can be seen from FIG. 12, the semiconductor memory device 1000 has an initial break voltage of 2 to 6 [V] (average value of about 5 [V]), and the semiconductor memory device 1001 has an initial break voltage of 5.5. To 6.5 [V] (average value of about 6 [V]). That is, the semiconductor memory device 1000 has a large variation compared to the semiconductor memory device 1001. This suggests that the thickness of the second resistance change layer 1106b varies in the direction of thinning or local short-circuiting due to the occurrence of recesses and variations in the amount of recesses (0 to 50 [nm]). doing.

  On the other hand, in the semiconductor memory device 1001, variations in the initial break voltage are suppressed compared to the semiconductor memory device 1000. However, the average value of the semiconductor memory device 1000 is about 5 [V], whereas the average value of the semiconductor memory device 1001 is as high as about 6 [V]. This is because the variation in the film thickness is suppressed and the variation in the initial break voltage is suppressed because the structure in which the film thickness of the second resistance change layer 1106b is hardly affected even if the recess amount varies. is there. However, on the other hand, it is considered that the initial break voltage is high because there are no locally thinned parts or bent parts, that is, there are no easy-to-break parts.

  The present invention has been conceived and completed based on the above findings. Embodiments of the present invention will be described below.

(Outline of Semiconductor Memory Device and Manufacturing Method According to the Present Invention)
The semiconductor memory device according to the present invention is formed on the substrate, the interlayer insulating film formed on the substrate, and on the interlayer insulating film in a state where at least a part of the surface is exposed from the upper surface of the interlayer insulating film. A low oxygen deficiency degree formed using the formed wiring, the lower electrode formed across the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring, and the oxygen-deficient second transition metal oxide A variable resistance layer formed by laminating a layer and a high oxygen deficiency layer composed of a first transition metal oxide having a greater oxygen deficiency than the second transition metal oxide on the lower electrode And an upper electrode formed on the variable resistance layer, a step is formed at a boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring, and the low oxygen content of the variable resistance layer The deficiency layer is formed along the shape of the boundary, Having a step portion in a plane view.

  With this configuration, it is possible to reduce the initial break voltage by forming a stepped portion that easily breaks in the low oxygen deficiency layer. Further, since the shape of the step portion is formed at the boundary between the interlayer insulating film and the wiring, it is easy to control intentionally, and the shape of the step portion of the low oxygen deficiency layer can be stabilized. . By stabilizing the shape of the stepped portion, variations in the initial break voltage can be suppressed. As described above, in the semiconductor memory device according to the present invention, both the reduction of the initial break voltage and the suppression of the variation can be achieved.

  Furthermore, since the semiconductor memory device according to the present invention forms a step portion in the low oxygen deficiency layer using the boundary between the interlayer insulating film and the wiring, a special process for forming the step portion is required. However, an increase in manufacturing cost can be effectively suppressed.

  Since it is possible to achieve both a reduction in the initial break voltage and suppression of variations, the resistance change type semiconductor memory device (memory) can be further miniaturized and increased in capacity.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the high oxygen deficiency layer of the resistance change layer is formed on the lower electrode, and the low oxygen deficiency layer of the resistance change layer includes: It is formed on the high oxygen deficiency layer.

  With this configuration, the shape of the resistance change element can be stabilized because the element shape of the resistance change element can be easily etched during manufacturing. It is advantageous for miniaturization because of easy etching.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the low oxygen deficiency layer of the resistance change layer is formed on the lower electrode, and the high oxygen deficiency layer of the resistance change layer includes: It is formed on the low oxygen deficiency.

  With this configuration, since the low oxygen deficiency layer is formed at a position close to the lower electrode, the step portion of the low oxygen deficiency layer is closer to the step formed at the boundary between the interlayer insulating film and the wiring. Will be formed. That is, since the curvature of the corner portion in the step portion is smaller, the electric field is easily concentrated, and the initial break voltage can be lowered. Furthermore, since the variation in the curvature of the corner portion in the step portion is reduced, the variation in the initial break voltage can be more effectively suppressed. In addition, it becomes easier to form the step portion so as to be located at the center of the low oxygen deficiency layer.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the lower electrode is formed across a part of the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the entire exposed surface of the wiring is formed above the upper surface of the interlayer insulating film.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the exposed surface of the wiring is formed so as to be lower than the upper surface of the interlayer insulating film, and the interlayer insulating film includes: The wiring is formed so as to cover a part of the upper surface of the wiring.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the stepped portion in the cross-sectional view of the low oxygen deficiency layer has a linear shape in a plan view.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the stepped portion in a cross-sectional view of the low oxygen deficiency layer has a curved portion in a plan view.

  If configured in this manner, the electric field tends to concentrate at the curved portion in plan view, so that the initial break voltage can be further reduced.

  More preferably, in one embodiment of the semiconductor memory device according to the present invention, the first transition metal oxide and the second transition metal oxide are made of a material containing tantalum, hafnium, or zirconium.

  By selecting the material in this way, the resistance change phenomenon can be expressed more stably.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the second transition metal oxide is made of an insulator.

  By selecting the material in this manner, the resistance change phenomenon can be expressed more stably.

  More preferably, in one aspect of the semiconductor memory device according to the present invention, the electrode formed in contact with the low oxygen deficiency layer among the lower electrode and the upper electrode is platinum, palladium, iridium, or these It is comprised with the material containing the mixture of these.

  By selecting the material in this manner, the resistance change phenomenon can be limitedly expressed in the vicinity of the low oxygen deficiency layer.

  The method for manufacturing a semiconductor memory device according to the present invention includes a first step of forming an interlayer insulating film on a semiconductor substrate, and exposing at least a part of the surface from the surface of the interlayer insulating film on the interlayer insulating film, And forming a lower electrode film in a state of straddling the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring, in a second step of forming the wiring so as to have a step at the boundary with the interlayer insulating film. A third step, a low oxygen deficiency film composed of an oxygen deficient second transition metal oxide on the lower electrode film, and a first transition having a greater oxygen deficiency than the second transition metal oxide A fourth step of forming a resistance change film by laminating a high oxygen deficiency film made of metal oxide in this order or the reverse order; and a fifth step of forming an upper electrode film on the resistance change film. And the lower electrode film, the resistance change film and the upper electrode film And a sixth step of processing into a shape including a step portion of the low degree of oxygen deficiency film formed along the stepped.

  Thus, in the first step and the second step, a step is formed at the boundary between the wiring and the interlayer insulating film, and the third step to the fifth step for forming the resistance change element using the step are performed. Since it performs, a level | step-difference part can be formed in a low oxygen deficiency layer, without requiring a special process. That is, since it is not always necessary to add a very expensive photomask, an increase in cost during manufacturing can be prevented. Further, since the step portion is formed in the low oxygen deficiency layer, the initial break voltage can be lowered. Furthermore, since the step portion is formed in the low oxygen deficiency layer using the step, it becomes easy to intentionally control the shape of the step portion. Since the shape of the stepped portion can be stabilized, variation in the initial break voltage between the resistance change elements can also be suppressed. From the above, it is possible to provide a method for manufacturing a semiconductor memory device that can achieve both a reduction in the initial break voltage and suppression of variations thereof.

  More preferably, in one aspect of the method for manufacturing a semiconductor memory device according to the present invention, the fourth step includes a step of forming the high oxygen deficiency film on the lower electrode film, and a step on the high oxygen deficiency film. Forming the low oxygen deficiency film.

  More preferably, in one aspect of the method for manufacturing a semiconductor memory device according to the present invention, the fourth step includes a step of forming the low oxygen deficiency film on the lower electrode film, and a step on the low oxygen deficiency film. Forming the high oxygen deficiency film.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. The invention is specified by the claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present invention are not necessarily required to achieve the object of the present invention, but are more preferable. It will be described as constituting a form.

(Embodiment 1)
The semiconductor memory device according to the first embodiment of the present invention and the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. 1A, 1B, and 2A to 2G.

(Configuration of Semiconductor Memory Device According to First Embodiment)
First, the configuration of the semiconductor memory device according to the first embodiment will be described. Here, FIG. 1A is a schematic plan view (top view) of the semiconductor memory device 90 according to the first embodiment of the present invention. 1B is a cross-sectional view of the semiconductor memory device 90 corresponding to the XX ′ cross section of FIG. 1A. Note that FIGS. 1A and 1B are diagrams different from the shape-dimension ratio of an actually configured semiconductor memory device for explanation.

  As shown in FIGS. 1A and 1B, the semiconductor memory device 90 includes a substrate S, a first interlayer insulating film 1 disposed on the substrate S, and a first layer formed on the first interlayer insulating film 1. The resistance change element 70 formed across the boundary between the wiring 51, the first interlayer insulating film 1 and the first wiring 51, and electrically connected to the first wiring 51, and the first wiring 51 and the resistance change element 70 Formed on the second interlayer insulating film 2, the plug 40 that penetrates the second interlayer insulating film 2 and is electrically connected to the resistance change element 70, and the second interlayer insulating film 2. A second wiring 52 electrically connected to the plug 40 is provided. In the first embodiment, the semiconductor memory device according to the present invention includes the first interlayer insulating film 1, the first wiring 51, and the resistance change element 70. That is, the substrate S, the plug 40, the second interlayer insulating film 2, and the second wiring 52 are not essential components of the present invention, but will be described as constituting a more preferable form.

More specifically, in the first embodiment, the first interlayer insulating film 1 is composed of a material mainly composed of silicon oxide (SiO ₂ ), particularly a plasma TEOS film. Note that the material of the first interlayer insulating film 1 is not limited to silicon oxide (SiO ₂ ). The material of the first interlayer insulating film 1 is preferably an insulating material that can reduce parasitic capacitance between wirings, such as a fluorine-containing oxide (for example, FSG) or a low-k material.

  The first wiring 51 of the first embodiment is formed in a prismatic shape having a linear shape (rectangular shape) in plan view and a rectangular shape in sectional view. More specifically, in the first embodiment, the first wiring 51 is formed so as to be partially buried inside the first interlayer insulating film 1, and the height of the surface (upper surface) is The height of the surface of the first interlayer insulating film 1 does not coincide with the surface of the first interlayer insulating film 1, and is protruded from the surface of the first interlayer insulating film 1. Thereby, a step 1 a of 5 to 100 [nm] is formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1. Here, the exposed surface of the first wiring 51 indicates a surface of the surface of the first wiring 51 that is not in contact with the first interlayer insulating film 1.

  The size of the step 1a is appropriately set according to the semiconductor process to be used and the thickness and number of layers formed between the first wiring 51 and the low oxygen deficiency layer 22. In the first embodiment, the first wiring 51 will be described on the assumption that it is copper (Cu), but aluminum (Al) or an aluminum alloy (Al—Cu alloy, Ti—Al—N alloy, etc.) is used. It may be composed of a wiring material such as. In the first embodiment, the case where the first wiring 51 is formed so as to be partially buried inside the first interlayer insulating film 1 has been described. However, the present invention is not limited to this. Alternatively, the first interlayer insulating film 1 may be formed on the upper portion without having a portion buried therein.

  The resistance change element 70 according to the first embodiment includes a first electrode 11 (corresponding to a lower electrode in the first embodiment), a high oxygen deficiency layer 21, a low oxygen deficiency layer 22, and a second electrode 12 (this embodiment). (Corresponding to the upper electrode in the first embodiment) is laminated in this order (laminated structure). The resistance change element 70 has a square shape with a side of 200 to 500 [nm] in a plan view, and is formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1 described above. It is formed across the step 1a.

  In the first embodiment, the case where the shape of the resistance change element 70 in plan view is a square will be described, but the present invention is not limited to this. The shape of the resistance change element 70 in a plan view is arbitrary, such as a square having a rounded corner, a rectangle, a rectangle having a rounded corner, an ellipse, or a hexagon.

  More specifically, the first electrode 11 is formed across the step 1a formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1, and according to the step 1a. It has a stepped part with a shape.

  In FIG. 1A and FIG. 1B, the shape of the exposed surface of the first wiring 51 in a plan view is a linear shape. The resistance change element 70 is arranged so that the linear shape of the first wiring 51 is included in a plan view and the step portion 22a of the low oxygen deficiency layer 22 includes a portion reflecting the linear shape. ing. That is, the step portion 22a in the cross-sectional view of the low oxygen deficiency layer 22 has a linear shape in the plan view.

  The first electrode 11 has a film thickness of 5 to 100 [nm] and is composed of a first electrode material having a standard electrode potential lower than that of a second electrode material constituting the second electrode 12 described later. In the first embodiment, the first electrode material is assumed to be tantalum nitride (TaN). In the first embodiment, the first electrode material is assumed to be tantalum nitride, but is not limited to tantalum nitride. The first electrode material is preferably a metal containing at least one selected from, for example, copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), and nitrides thereof.

The high oxygen deficiency layer 21 is formed on the first electrode 11 and has a stepped portion corresponding to the shape of the stepped portion of the first electrode 11. The high oxygen deficiency layer 21 has a film thickness of 20 to 100 [nm], and is a tantalum oxide (TaO _x , where x is an oxygen (O) atom when the number of tantalum (Ta) atoms is 1. It is composed of an oxygen-deficient first transition metal oxide whose main component is a number, preferably 0 <x <2.5.

The low oxygen deficiency layer 22 is formed on the high oxygen deficiency layer 21 and has a step portion 22 a corresponding to the shape of the step portion of the high oxygen deficiency layer 21. That is, the step portion 22 a of the low oxygen deficiency layer 22 has a shape corresponding to the step 1 a formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1. The low oxygen deficiency layer 22 preferably has a thickness of 1 to 10 [nm] in order to facilitate an initial break. The low oxygen deficiency layer 22 is mainly composed of tantalum oxide (TaO _y , y is the number of oxygen (O) atoms when the number of tantalum (Ta) atoms is 1, preferably x <y). The oxygen-deficient second transition metal oxide.

Here, the oxygen content of the first transition metal oxide forming the high oxygen deficiency layer 21 is lower than the oxygen content of the second transition metal oxide forming the low oxygen deficiency layer 22. In order to realize a stable operation as a variable resistance element, it is more preferable that TaO _x satisfies 0.8 ≦ x ≦ 1.9 and TaO _y satisfies 2.1 ≦ y. Ta ₂ O ₅ may be used as the low oxygen deficiency layer 22. Ta ₂ O ₅ is an insulator.

  The second electrode 12 has a thickness of 5 to 100 [nm] and is made of a material having a higher standard electrode potential than the metal constituting the high oxygen deficiency layer 21 and the low oxygen deficiency layer 22. As the electrode material of the second electrode 12, for example, a noble metal such as platinum (Pt), iridium (Ir), palladium (Pd) is preferably used, but a mixture thereof may be used. In the present embodiment, the second electrode 12 has a stepped portion having a shape corresponding to the stepped portion 22a of the low oxygen deficiency layer 22, but the surface may be flattened.

  The first electrode 11, the second electrode 12, the high oxygen deficiency layer 21, and the low oxygen deficiency layer 22 satisfy the above standard electrode potential relationship, whereby the high oxygen deficiency layer 21 in the vicinity of the second electrode 12. In addition, the resistance change phenomenon can be selectively expressed in the low oxygen deficiency layer 22.

In the first embodiment, the second interlayer insulating film 2 is made of a material composed mainly of silicon oxide (SiO ₂ ), particularly a plasma TEOS film. The material of the second interlayer insulating film 2 is not limited to silicon oxide (SiO ₂ ), as with the first interlayer insulating film 1, but is a fluorine-containing oxide (for example, FSG) or a low-k material. For example, an insulating material that can reduce the parasitic capacitance between the wirings is preferable.

  The plug 40 is formed in a cylindrical shape with a diameter of 50 to 300 [nm], and is made of a plug material such as a metal whose main component is tungsten (W). More specifically, in the first embodiment, the plug 40 is in contact with the second interlayer insulating film 2 and has two layers of a TiN / Ti layer functioning as an adhesion layer and a diffusion barrier, and a main component film made of tungsten. It consists of

  In the first embodiment, the second wiring 52 is described on the assumption that it is copper (Cu), but aluminum (Al) or an aluminum alloy (Al—Cu alloy, Ti—Al—N alloy or the like) is used. It may be composed of a wiring material such as.

  According to such a configuration, the step portion 22 a having a shape corresponding to the step 1 a formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1 is formed in the low oxygen deficiency layer 22. Therefore, the initial break can be made even at a low voltage starting from the stepped portion 22a. Further, the shape of the stepped portion 22a is a shape corresponding to the stepped portion 1a formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1, and therefore is formed with intentional control. It becomes possible to do. Thereby, the shape of the stepped portion 22a of the low oxygen deficiency layer 22 can be stabilized, and variations in the initial break voltage between elements can be suppressed. As described above, it is possible to achieve both the reduction of the initial break voltage and the suppression of the variation between the elements, and the miniaturization and the capacity increase of the memory can be realized.

(Method for Manufacturing Semiconductor Memory Device According to Embodiment 1)
Next, a method for manufacturing the semiconductor memory device 90 according to the first embodiment will be described. 2A to 2G are schematic cross-sectional views illustrating a method for manufacturing the semiconductor memory device 90 shown in FIG.

  First, as shown in FIG. 2A, a first interlayer insulating film 1 and a first wiring 51 are formed on a substrate S on which transistors, lower layer wirings, and the like are formed.

  Specifically, in the first embodiment, first, a silicon oxide film having a thickness of 500 to 1000 [nm] is formed on a substrate S by a CVD method (Chemical Vapor Deposition) using TEOS (tetraethyl orthosilicate) as a raw material. To form a first interlayer insulating film 1 (first step).

  Subsequently, using copper (Cu) as a wiring material, the first wiring 51 is embedded and formed in the first interlayer insulating film 1 by a general Cu damascene method (second step). Here, the Cu film thickness was 200 [nm], and the wiring width was about 0.5 [μm].

Next, as shown in FIG. 2B, the surface of the first interlayer insulating film 1 is selectively etched so that the surface of the first wiring 51 protrudes from the surface of the first interlayer insulating film 1 in a convex shape. Form. As a result, a step 1 a of 5 to 100 [nm] is formed at the boundary between the exposed surface of the first wiring 51 and the surface of the first interlayer insulating film 1. A general dry etching method was used for the selective etching of the surface of the first interlayer insulating film 1. As the etching gas, a fluorine-based gas (CHF ₃ , CF _4, or the like) can be used.

  In the first embodiment, the first wiring 51 is embedded by the Cu damascene method and etching. However, the present invention is not limited to this. For example, the first wiring 51 may be formed by depositing a wiring material by a sputtering method and performing patterning using a desired mask and dry etching without forming the buried wiring.

  Next, as shown in FIG. 2C, the first electrode film 11 ′, the high oxygen deficiency film 21 ′, the low oxygen deficiency film 22 ′, and the second electrode film 12 ′ are arranged in this order so as to cover the entire wafer surface. Deposit.

  More specifically, for example, tantalum nitride (TaN) is deposited by sputtering so as to cover the entire wafer plane and to have a thickness of 5 to 100 [nm], preferably 30 [nm]. Then, the first electrode film 11 ′ is formed (third step). Note that although the sputtering method has been described here as the method for depositing the first electrode material layer 105M, a CVD method or an ALD method (Atomic Layer Deposition) may be used.

  Subsequently, a high oxygen deficiency film 21 'and a low oxygen deficiency film 22' are formed in this order by sputtering (fourth step). Here, the second transition metal oxide that is the material of the low oxygen deficiency film 22 ′ and the first transition metal oxide that is the material of the high oxygen deficiency film 21 ′ are oxygen deficient tantalum oxide. Will be described.

  Here, the high oxygen deficiency film 21 ′ is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an argon and oxygen gas atmosphere. The oxygen content is 50 to 65 [atm%], the resistivity is 2 to 50 m [Ωcm], and the film thickness is 50 [nm].

Further, a low oxygen deficiency film 22 ′ was formed by a reactive sputtering method in which a tantalum target was sputtered in an oxygen gas atmosphere. The oxygen content is 67 to 71 [atm%], the resistivity is 10 ⁷ m [Ωcm] or more, and the film thickness is 6 [nm]. Here, although formed by reactive sputtering, a reactive sputtering method of sputtering a tantalum oxide target in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.

  Subsequently, iridium (Ir) as a second electrode material is deposited by 50 [nm] by sputtering to form a second electrode film 12 '(fifth step). Note that the standard electrode potential of iridium (Ir) as the second electrode material is larger than the standard electrode potential of tantalum nitride (TaN) as the first electrode material.

  Next, as shown in FIG. 2D, the first electrode film 11 ′, the high oxygen deficiency film 21 ′, the low oxygen deficiency film 22 ′, and the second electrode film 12 ′ are stepped into the low oxygen deficiency layer 22. The first electrode 11, the high oxygen deficiency layer 21, the low oxygen deficiency layer 22 and the second electrode 12 are formed by masking and etching using an exposure process so that 22a is included (sixth step) ). Thereby, the resistance change element 70 is formed. In the first embodiment, the variable resistance element 70 is formed such that the size and shape in plan view are 0.5 [μm] × 0.5 [μm] square.

  Further, the position of the resistance change element 70 in plan view is that the film thickness of the first electrode film 11 ′ shown in FIG. 2C is T1, the film thickness of the high oxygen deficiency film 21 ′ is T2, and the film thickness of the low oxygen deficiency film 22 ′. When the film thickness is T3, the position of the surface of the step portion 22a in contact with the second electrode 12 in a plan view is approximately (T1 + T2 + T3) from the step 1a on the lateral side (in FIG. 2C, the surface of the first interlayer insulating film 1 and the first surface Of the exposed surface of one wiring 51, the surface is located on the lower side, here the first interlayer insulating film 1 side). Further, in lithography in a general technical level, it is necessary to consider a positional deviation of about ± 50 [nm] when forming a resist mask. Therefore, in order to form the resistance change element 70 so that the low oxygen deficiency layer 22 includes the step portion 22a, the step 1a and the step 1a of the resistance change element 70 from the step 1a to the first interlayer insulating film 1 side in plan view The dimension d1 between the end portion in the direction toward the head needs to be larger than (T1 + T2 + T3 + 50) [nm]. Further, in plan view, the dimension d2 between the step 1a and the end of the resistance change element 70 in the direction from the step 1a toward the first wiring 51 side comprehensively improves process accuracy such as lithography accuracy and etching accuracy. In consideration, the first electrode 11 and the first wiring 51 need only be dimensioned to be electrically connected. In the first embodiment, as shown in FIGS. 1A and 1B, the dimension d1 and the dimension d2 are set so that the center of the resistance change element 70 in a plan view is close to or overlaps the step 1a.

  Next, as shown in FIG. 2E, an insulating layer is formed so as to cover the exposed surfaces of the resistance change element 70 and the first wiring 51, and then the surface of the insulating layer is flattened to obtain the second interlayer insulation. A film 2 is formed. More specifically, a silicon oxide film is deposited on the resistance change element 70 and the first wiring 51 by a CVD method to a thickness of 500 to 1000 [nm] using TEOS as a raw material, and a chemical mechanical polishing method (CMP method) is performed. To flatten the surface.

  Next, as shown in FIG. 2F, the second interlayer insulating film 2 is patterned using a desired mask to form a contact hole 40a that penetrates the second interlayer insulating film 2 and reaches the second electrode 12. The contact hole 40a is formed in a cylindrical shape having a diameter of 50 to 300 [nm].

  Next, the contact plug 40 is formed in the contact hole 40a. Specifically, first, a TiN / Ti layer is formed in a thickness of 5 to 30 [nm] by sputtering in the contact hole 40a and on the second interlayer insulating film 2, and the TiN / Ti layer is formed on the TiN / Ti layer. In addition, tungsten as a main component is formed to a thickness of 200 to 400 [nm] by CVD. Further, the entire surface of the wafer is planarized and polished by using the CMP method, and unnecessary tungsten and TiN / Ti layers on the second interlayer insulating film 2 are removed. Thereby, the plug 40 is formed inside the contact hole 40a.

  Next, as shown in FIG. 2G, the second wiring 52 is formed, which is formed by using a general Cu damascene process in the same manner as the first wiring 51 shown in FIG. 2A.

  By adopting such a manufacturing method, the shape of the step formed by the first wiring 51 and the first interlayer insulating film 1 is reflected in the low oxygen deficiency layer 22 so that the shape of the stepped portion 22a is stably formed. It becomes possible. Further, the step 1a at the boundary between the first wiring 51 and the first interlayer insulating film 1 can be formed by, for example, selective etching, so that it is not always necessary to add a very expensive photomask, and additional man-hours are also increased. Since the amount is small, it is possible to prevent an increase in cost during manufacturing. Furthermore, according to the manufacturing method described above, by forming the step portion 22a in the low oxygen deficiency layer 22, the initial break voltage can be reduced and the step portion 22a can be formed in a stable shape. Can be suppressed. Thereby, miniaturization and large capacity of the memory can be realized.

(Modification of the first embodiment)
Next, a modified example of the semiconductor memory device 90 will be described with reference to FIGS. 3A to 3C.

  In the first embodiment described above, the first wiring 51 is formed in a linear shape (rectangular shape) in plan view, and the resistance change element 70 is connected to one of the long sides of the first wiring 51 and the first interlayer. The case where it is formed so as to straddle part of the boundary with the insulating film 1 has been described. However, in the following modification, the shape of the first wiring 51 and the position of the first wiring 51 and the resistance change element 70 are described. A case where the relationship is different will be described.

  Here, FIGS. 3A to 3C are diagrams schematically illustrating another example of the positional relationship between the shape of the first wiring 51 and the resistance change element 70 in plan view.

  FIG. 3A shows a case where the first wiring 51 is divided for each unit cell and the shape of the exposed surface in a plan view is a rectangular shape. The resistance change element 70 includes a portion in which one of the corners and the center of the first wiring 51 coincides or is close to each other in a plan view, and the step 22a of the low oxygen deficiency layer 22 reflects the shape of the corner. It is arranged to be.

  FIG. 3B shows a case where the shape of the exposed surface in the plan view of the first wiring 51 is a linear shape, and a rectangular recess is formed in a part of the linear shape. The resistance change element 70 includes the corners of the recesses of the first wiring 51 in plan view, and the step portion 22a of the low oxygen deficiency layer 22 includes a portion reflecting the shape of the corners. Has been placed.

  FIG. 3C shows a case where the shape of the exposed surface in the plan view of the first wiring 51 is a linear shape, and a rectangular convex portion is formed on a part of the linear shape. The variable resistance element 70 includes a corner of the convex portion of the first wiring 51 in a plan view, and includes a portion reflecting the shape of the corner in the step portion 22 a of the low oxygen deficiency layer 22. Have been placed.

  In any of FIGS. 3A to 3C described above, the step 1a has a corner in a plan view, and the step portion 22a of the low oxygen deficiency layer 22 reflects the shape of the corner (the low oxygen deficiency layer 22). Corners) are formed. That is, the step portion 22a in the cross-sectional view of the low oxygen deficiency layer 22 has a curved portion in the plan view.

  Since the electric field tends to concentrate at the corners of the low oxygen deficiency layer 22, the initial break voltage can be lowered.

(Embodiment 2)
A semiconductor memory device according to the second embodiment of the present invention and a method for manufacturing the semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. 4A and 4B.

  The semiconductor memory device 91 of the second embodiment is different from the semiconductor memory device 90 of the first embodiment in that the first electrode 111, the high oxygen deficiency layer 121, and the low oxygen deficiency constituting the resistance change element 170 are different. The layer 122 and the second electrode 112 are stacked in the reverse order from the resistance change element 70 of the semiconductor memory device 90 of the first embodiment.

(Configuration of Semiconductor Memory Device According to Second Embodiment)
First, the configuration of the semiconductor memory device 91 according to the second embodiment will be described. Here, FIG. 4A is a schematic plan view (top view) of the semiconductor memory device 91 according to the second embodiment of the present invention. 4B is a cross-sectional view of the semiconductor memory device 91 corresponding to the XX ′ cross section of FIG. 4A. 4A and 4B, the same components as those in FIGS. 2A to 2G are denoted by the same reference numerals, and description thereof is omitted. The same applies to other embodiments described below.

  As shown in FIGS. 4A and 4B, the semiconductor memory device 91 includes a substrate S, a first interlayer insulating film 1 disposed on the substrate S, and a first layer formed on the first interlayer insulating film 1. The resistance change element 70 formed across the boundary between the wiring 51, the surface of the first interlayer insulating film 1 and the exposed surface of the first wiring 51, and electrically connected to the first wiring 51, and the first wiring 51 And the second interlayer insulating film 2 formed so as to cover the resistance change element 70, the plug 40 penetrating the second interlayer insulating film 2 and electrically connected to the resistance change element 70, and the second interlayer insulating film 2 A second wiring 52 formed on and electrically connected to the plug 40 is provided. In the second embodiment, the semiconductor memory device according to the present invention includes the first interlayer insulating film 1, the first wiring 51, and the resistance change element 70 as in the first embodiment. That is, the substrate S, the plug 40, the second interlayer insulating film 2, and the second wiring 52 are not essential components of the present invention, but will be described as constituting a more preferable form.

  The shapes, materials, arrangements, and the like of the first interlayer insulating film 1, the first wiring 51, the step 1a, the second interlayer insulating film 2, the plug 40, and the second wiring 52 are the same as those in the first embodiment.

  The resistance change element 170 in the second embodiment includes a second electrode 112 (corresponding to a lower electrode in the second embodiment), a low oxygen deficiency layer 122, a high oxygen deficiency layer 121, and a first electrode 111 (in this embodiment). In the second embodiment, the upper electrode) is stacked in this order. Like the resistance change element 70 of the first embodiment, the resistance change element 170 has a shape in a plan view of 200 to 500 [nm □], and the exposed surface of the first wiring 51 and the first interlayer insulating film 1 It is formed across the step 1a formed at the boundary with the surface.

  In addition, the second electrode 112, the low oxygen deficiency layer 122, the high oxygen deficiency layer 121, and the first electrode 111 according to the second embodiment are stacked at the position of the step portion formed under the influence of the step 1a. Although different depending on the order, the film thickness and material are the same as those of the second electrode 12, the low oxygen deficiency layer 22, the high oxygen deficiency layer 21, and the first electrode 11 of the first embodiment.

  In the semiconductor memory device 91, the step 122 a of the low oxygen deficiency layer 122 is formed near the step 1 a through only the second electrode 112. Therefore, the step 122a of the low oxygen deficiency layer 122 can be formed in a state that accurately reflects the shape of the step 1a. Further, the distance between the step 1a and the step 122a can be shortened, and the control of the formation position of the step 122a during manufacturing becomes easier.

(Method for Manufacturing Semiconductor Memory Device According to Second Embodiment)
Next, a method for manufacturing the semiconductor memory device 91 according to the second embodiment will be described. Detailed description of the same parts as those in the first embodiment will be omitted as appropriate.

  Specifically, first, a first step of forming the first interlayer insulating film 1 and a second step of embedding and forming the first wiring 51 in the first interlayer insulating film 1 are performed. The first step and the second step are the same as the first step and the second step in the first embodiment.

  Subsequently, a second electrode film, a low oxygen deficiency film, a high oxygen deficiency film, and a first electrode film are deposited in this order so as to cover the entire wafer surface.

  More specifically, iridium (Ir) as the second electrode material is deposited by 50 [nm] by sputtering to form a second electrode film (third step). Subsequently, a low oxygen deficiency film and a high oxygen deficiency film are formed in this order by sputtering (fourth step). The setting of the sputtering apparatus is the same as in the first embodiment, but the stacking order of the low oxygen deficiency film and the high oxygen deficiency film is reversed, so the oxygen partial pressure ratio is changed from 7 [%] to 1 [ %]. Furthermore, by sputtering, for example, tantalum nitride (TaN) is deposited to a thickness of 5 to 100 [nm] so as to cover the entire wafer plane to form a first electrode film (fifth). Process).

  Subsequently, the second electrode film, the low oxygen deficiency film, the high oxygen deficiency film, and the first electrode film are etched using an exposure process so that the low oxygen deficiency layer 122 includes the stepped portion 122a. Thus, the first electrode 111, the high oxygen deficiency layer 121, the low oxygen deficiency layer 122, and the second electrode 112 are formed, and the resistance change element 170 is formed (sixth step). In the second embodiment, similarly to the first embodiment, the variable resistance element 170 is formed such that the size and shape in plan view are 0.5 [μm] × 0.5 [μm] square. did.

  The position of the resistance change element 170 in plan view is the position of the surface in contact with the second electrode 112 of the stepped portion 22a in plan view, where T4 is the thickness of the second electrode film and T3 is the thickness of the low oxygen deficiency film. Is a position away from the step 1a to the first interlayer insulating film 1 side by approximately (T4 + T3). Further, in consideration of lithography misregistration in a general technical level, in order to form the resistance change element 170 so as to include the stepped portion 122a in the low oxygen deficiency layer 122, in the plan view, the step 1a and the resistance The dimension d3 between the step 1a of the change element 170 and the end portion in the direction toward the first interlayer insulating film 1 side needs to be larger than (T4 + T3 + 50) [nm]. In plan view, the dimension d4 between the step 1a and the end portion of the variable resistance element 170 in the direction from the step 1a toward the first wiring 51 side comprehensively improves process accuracy such as lithography accuracy and etching accuracy. In consideration, the second electrode 112 and the first wiring 51 need only be dimensioned to be electrically connected. In the first embodiment, as shown in FIGS. 4A and 4B, the dimension d3 and the dimension d4 are set so that the center of the resistance change element 170 in plan view is close to or overlaps the step 1a. Note that the shape of the variable resistance element 170 in the present embodiment in plan view is not limited to a square.

  Subsequently, a step of forming the second interlayer insulating film 2, a step of forming the contact plug 40, and a step of forming the second wiring 52 are executed. These steps are the same as those in the first embodiment.

  In the second embodiment described above, similarly to the modification of the first embodiment, when the shape of the exposed surface in the plan view of the first wiring 51 is a shape having corners, the position including the corner is included. If the variable resistance element 170 is disposed in the first break voltage, the initial break voltage can be further lowered.

(Embodiment 3)
A semiconductor memory device according to the second embodiment of the present invention and a method for manufacturing the semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. 5A, 5B, and 6A to 6E.

  The semiconductor memory device 92 according to the third embodiment is different from the semiconductor memory device 90 according to the first embodiment and the semiconductor memory device 91 according to the second embodiment in the configuration of the first wiring 51 and the first interlayer insulating film 1. Is a different point. More specifically, in the semiconductor memory device 90 of the first embodiment and the semiconductor memory device 91 of the second embodiment, the surface of the first wiring 51 is formed to be higher than the surface of the first interlayer insulating film 1. However, in the third embodiment, the surface of the first wiring 51 is formed to be lower than the surface of the first interlayer insulating film 1.

(Configuration of Semiconductor Memory Device According to Third Embodiment)
First, the configuration of the semiconductor memory device 92 according to the third embodiment will be described. Here, FIG. 5A is a schematic plan view of the semiconductor memory device 92 according to the third embodiment of the present invention. 5B is a cross-sectional view of the semiconductor memory device 92 corresponding to the XX ′ cross section of FIG. 5A.

  As shown in FIGS. 5A and 5B, the semiconductor memory device 92 includes a substrate S, a first interlayer insulating film 1 disposed on the substrate S, and a surface height higher than that of the first interlayer insulating film 1. The first wiring 51 formed so as to be low, and a resistor formed across the boundary between the surface of the first interlayer insulating film 1 and the exposed surface of the first wiring 51 and electrically connected to the first wiring 51 The change element 270, the second interlayer insulating film 2 formed so as to cover the first wiring 51 and the resistance change element 270, and the plug that penetrates the second interlayer insulating film 2 and is electrically connected to the resistance change element 270. 40 and a second wiring 52 formed on the second interlayer insulating film 2 and electrically connected to the plug 40.

  In the third embodiment, the semiconductor memory device according to the present invention includes the first interlayer insulating film 1, the first wiring 51, and the resistance change element 270, as in the first and second embodiments. . That is, the substrate S, the plug 40, the second interlayer insulating film 2, and the second wiring 52 are not essential components of the present invention, but will be described as constituting a more preferable form.

  The shape, material, arrangement, and the like of the second interlayer insulating film 2, the plug 40, and the second wiring 52 are the same as those in the first and second embodiments. In the third embodiment, the structure (stacking order), film thickness, material, arrangement, and the like of the resistance change element 270 are assumed to be the same as those of the resistance change element 70 of the first embodiment. However, it may be the same as the resistance change element 170 of the second embodiment.

  The first interlayer insulating film 1 of the third embodiment is composed of two layers, a third interlayer insulating film 3 and a fourth interlayer insulating film 4. The surface of the third interlayer insulating film 3 has the same height as the surface of the first wiring 51 embedded in the third interlayer insulating film 3. The fourth interlayer insulating film 4 is formed on the third interlayer insulating film 3 and the first wiring 51, and an opening is provided so as to expose a part of the surface of the first wiring 51. That is, as shown in FIG. 5B, a part of the first wiring 51 is covered with the fourth interlayer insulating film 4. Here, the exposed surface of the first wiring 51 indicates a surface of the surface of the first wiring 51 that is not in contact with the third interlayer insulating film 3 and the fourth interlayer insulating film 4.

In the third embodiment, the third interlayer insulating film 3 and the fourth interlayer insulating film 4 are formed of silicon oxide (SiO ₂ ) as in the first interlayer insulating film 1 of the first and second embodiments. In particular, the material is composed mainly of a plasma TEOS film. Note that the material of the third interlayer insulating film 3 and the fourth interlayer insulating film 4 is not limited to silicon oxide (SiO ₂ ), as in the first and second embodiments. The material of the third interlayer insulating film 3 and the fourth interlayer insulating film 4 is preferably an insulating material that can reduce the parasitic capacitance between wirings, such as a fluorine-containing oxide (for example, FSG) or a low-k material.

  According to such a configuration, since the stepped portion 222a of the low oxygen deficiency layer 222 in the cross-sectional view is formed on the first wiring 51 in the plan view, the configuration shown in the first and second embodiments. The area of the region where the resistance change element 270 and the first wiring 51 are in contact with each other in plan view can be increased. As a result, the area of the resistance change element 270 that overlaps the first wiring 51 in plan view can be reduced, and a large capacity can be realized.

(Method for Manufacturing Semiconductor Memory Device According to Embodiment 3)
Next, a method for manufacturing the semiconductor memory device 92 according to the third embodiment will be described. Detailed description of the same parts as those in the first embodiment will be omitted as appropriate. Here, FIGS. 6A, 6B, and 6C (a) and FIGS. 6D to 6E are schematic cross-sectional views showing a method of manufacturing the semiconductor memory device 92 shown in FIGS. 5A and 5B. Moreover, (b) of FIG. 6C is a plan view (top view) corresponding to (a) of FIG. 6C. The manufacturing method of the principal part of the semiconductor memory device 92 of the third embodiment will be described using these. Note that the process of FIG. 6A is the same as that of FIG. Moreover, since the process after FIG.6 (e) is the same as that of FIG.2 (e)-FIG.2 (g), description is abbreviate | omitted.

  First, as shown in FIG. 6A, a third interlayer insulating film 3 is formed on a substrate S by depositing a silicon oxide film to a thickness of 500 to 1000 [nm] using TEOS as a raw material by a CVD method. (Part of the first step).

  Subsequently, the first wiring 51 is embedded and formed in the third interlayer insulating film 3 by a general Cu damascene method using copper (Cu) as a wiring material (second step). Here, as in the first and second embodiments, the Cu film thickness was 200 [nm] and the wiring width was about 0.5 [μm].

  Subsequently, as shown in FIG. 6B, the TEOS film 4 ′ constituting the fourth interlayer insulating film 4 is formed in a thickness of 5 to 100 by CVD so as to cover the surfaces of the third interlayer insulating film 3 and the first wiring 51. Deposit to a thickness of [nm].

Subsequently, as shown in (a) of FIG. 6C, masking is performed using an exposure process, and the TEOS film 4 ′ is etched, thereby forming a wiring upper recess 61 on the first wiring 51. As a result, a step 4 a is formed at the boundary between the surface of the fourth interlayer insulating film 4 and the exposed surface of the first wiring 51. A general dry etching method was used for etching the TEOS film 4 ′. As the etching gas, a fluorine-based gas (CHF ₃ , CF _4, or the like) can be used.

  Here, as shown in FIG. 6C (b), the etching region has a groove shape along the extending direction (longitudinal direction) of the first wiring 51. In the third embodiment, the groove width of the etching region is 450 [nm]. The groove width of the etching region is preferably set appropriately in consideration of the process, the width of the first wiring 51, the size of the resistance change element 270, and the like.

  Next, as shown in FIG. 6D, the first electrode film 211 ′, the high oxygen deficiency film 221 ′, the low oxygen deficiency film 222 ′, and the second electrode film 212 ′ are arranged in this order so as to cover the entire wafer surface. Deposit. In the third embodiment, the third step of forming the first electrode film 211 ′, the fourth step of forming the high oxygen deficiency film 221 ′ and the low oxygen deficiency film 222 ′, and the second electrode film 212 ′. The fifth step of forming is the same as the third to fifth steps of the first embodiment.

  In the third embodiment, it is assumed that the resistance change element 270 is the same as the resistance change element 70 in the first embodiment, but the resistance change element 170 in the second embodiment is used as the resistance change element 270. Is used, the third to fifth steps of the second embodiment are executed in place of the step of FIG. 6D described above.

  Next, as shown in FIG. 6E, the first electrode film 211 ′, the high oxygen deficiency film 221 ′, the low oxygen deficiency film 222 ′, and the second electrode film 212 ′ are stepped into the low oxygen deficiency layer 222. The first electrode 211, the high oxygen deficiency layer 221, the low oxygen deficiency layer 222, and the second electrode 212 are formed by masking and etching using an exposure process so that 222 a is included (sixth step) ). Thereby, the resistance change element 270 is formed. At this time, the resistance change element 270 is formed so as to include the step portion 222 a of the low oxygen deficiency layer 222. In the third embodiment, as in the first and second embodiments, the resistance change element 270 has a square size and shape of 0.5 [μm] × 0.5 [μm] in plan view. It formed so that it might become.

  Further, the position of the resistance change element 270 in plan view is that the film thickness of the first electrode film 211 ′ shown in FIG. 6D is T1, the film thickness of the high oxygen deficiency film 221 ′ is T2, and the film thickness of the low oxygen deficiency film 222 ′. When the film thickness is T3, the position of the surface in contact with the second electrode 212 of the stepped portion 222a in plan view is a position separated from the step 4a by about (T1 + T2 + T3) to the first wiring 51 side. In consideration of lithography misregistration in a general technical level, in order to form the resistance change element 270 so as to include the stepped portion 222a in the low oxygen deficiency layer 222, in the plan view, the step 4a and the resistance The dimension d5 between the step 4a of the change element 270 and the end portion in the direction toward the first wiring 51 needs to be larger than (T1 + T2 + T3 + 50) [nm]. Further, in plan view, the dimension d6 between the step 4a and the end of the resistance change element 270 in the direction from the step 4a toward the first interlayer insulating film 1 side is a total of process accuracy such as lithography accuracy and etching accuracy. In consideration, the first electrode 211 and the first wiring 51 need only be dimensioned to be electrically connected. In the third embodiment, as shown in FIGS. 5A and 5B, the dimension d5 and the dimension d6 are set so that the center of the resistance change element 270 in plan view is close to or overlaps the step 4a. Note that the shape of the variable resistance element 270 according to the third embodiment in plan view is not limited to a square. For example, a square with rounded corners, a rectangle, a rectangle with rounded corners, an ellipse, a hexagon, and the like are arbitrary.

  Subsequent to the sixth step shown in FIG. 6E, a step of forming the second interlayer insulating film 2, a step of forming the contact plug 40, and a step of forming the second wiring 52 are executed. These steps are the same as those in the first embodiment.

(Modification of Embodiment 3)
Next, a modification of the semiconductor memory device 92 will be described with reference to FIGS. 7A and 7B.

  In the third embodiment described above, the case where the wiring depression 61 has a linear shape has been described. However, the shape of the wiring depression 61 is not limited to this.

  Here, FIG. 7A is a schematic plan view of a semiconductor memory device 93 according to a modification of the third embodiment. FIG. 7B is a schematic cross-sectional view of the semiconductor memory device 93 corresponding to the X-X ′ cross section of FIG. 7A.

  As shown in FIGS. 7A and 7B, the shape of the wiring upper depression 61 in the modification of the third embodiment is a square.

  According to such a configuration, the step 4a has a corner in plan view. That is, in the stepped portion 222a of the low oxygen deficiency layer 222, a portion reflecting the corner shape of the stepped portion 4a is formed. Thereby, since the electric field tends to concentrate at the corners of the low oxygen deficiency layer 222, the initial break voltage can be further reduced as compared with the configurations of FIGS. 5A and 5B.

(Manufacturing Method of Semiconductor Memory Device According to Modification of Third Embodiment)
Next, a method for manufacturing the semiconductor memory device 93 according to the modification of the third embodiment will be described with reference to FIG. In the modification of the third embodiment, the steps other than the step of forming the wiring upper recess 61 are the same as the manufacturing steps in the third embodiment. The description of the same steps as those in Embodiment 3 is omitted.

  Here, FIG. 8A is a schematic cross-sectional view showing a method of manufacturing the semiconductor memory device 93 shown in FIG. FIG. 8B is a plan view (top view) corresponding to FIG.

  As shown in FIG. 8B, the etching region for the TEOS film 4 ′ has a square shape in plan view, and the position in plan view is arranged at a position where the surface of the first wiring 51 is exposed. ing. The dimension of the etching region in plan view was a quadrangular shape with a side of 400 [nm]. Note that the etching region does not have to be entirely on the first wiring 51 in plan view. Also in this case, the resistance change element 270 is located on the boundary between the surface of the fourth interlayer insulating film 4 (first interlayer insulating film 1) and the exposed surface of the first wiring 51 in the boundary of the etching region. To be formed.

  Further, the shape of the etching region in plan view is not limited to a square. The shape of the etching region in plan view may be a square with rounded corners, a rectangle, a rectangle with rounded corners, an ellipse, a polygon, or the like. Note that the step 4a has a shape including a corner in plan view, and a portion reflecting the shape of the corner of the step 4a is formed in the step 222a of the low oxygen deficiency layer 222. Similar to the configuration of the third embodiment, the initial break voltage can be further reduced as compared with the configurations of FIGS. 5A and 5B.

(Modification of Embodiments 1 to 3)
In the first to third embodiments, the tantalum oxide is used as the second transition metal oxide constituting the low oxygen deficiency layer and the first transition metal oxide constituting the high oxygen deficiency layer. As described above, other transition metal oxides such as hafnium oxide and zirconium oxide may be used.

When hafnium oxide is used, assuming that the composition of the second transition metal oxide is HfO _y and the composition of the first transition metal oxide is HfO _x , 0.9 ≦ x ≦ 1.6, 1.8 <y It is preferable to satisfy <2.0.

  In this case, the high oxygen deficiency layer using hafnium oxide can be generated, for example, by a reactive sputtering method using an Hf target and sputtering in argon gas and oxygen gas. As in the case of the tantalum oxide described above, the oxygen content of the high oxygen deficiency layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

  The low oxygen deficiency layer using hafnium oxide can be formed, for example, by exposing the surface of the high oxygen deficiency layer to a plasma of argon gas and oxygen gas. The film thickness of the low oxygen deficiency layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. The thickness of the low oxygen deficiency layer is preferably 3 [nm] or more and 4 [nm] or less.

When zirconium oxide is used, assuming that the composition of the second transition metal oxide is ZrO _y and the composition of the first transition metal oxide is ZrO _x , 0.9 ≦ x ≦ 1.4, 1.9 It is preferable to satisfy <y <2.0.

  In this case, the high oxygen deficiency layer using zirconium oxide can be generated by, for example, a reactive sputtering method using a Zr target and sputtering in argon gas and oxygen gas. As in the case of the tantalum oxide described above, the oxygen content of the high oxygen deficiency layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

  The low oxygen deficiency layer using zirconium oxide can be formed, for example, by exposing the surface of the high oxygen deficiency layer to plasma of argon gas and oxygen gas. The film thickness of the low oxygen deficiency layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. The thickness of the low oxygen deficiency layer is preferably 1 [nm] or more and 5 [nm] or less.

  Note that the above-described hafnium oxide layer and zirconium oxide layer can be formed by using a CVD method or an ALD (Atomic Layer Deposition) method instead of sputtering.

  Furthermore, the high oxygen deficiency layer and the low oxygen deficiency layer only need to contain an oxide layer such as tantalum, hafnium, zirconium, etc. as the main resistance change layer that exhibits resistance change. Other elements may be included. It is also possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, if nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the reactivity of resistance change can be improved.

Therefore, in the resistance change element using the oxygen-deficient transition metal oxide M for the resistance change layer, the resistance change layer includes the oxygen-deficient first transition metal oxide having a composition represented by MO _x. In the case of a configuration having an oxygen deficiency layer and a low oxygen deficiency layer containing an oxygen-deficient second transition metal oxide having a composition represented by MO _y (x <y), high oxygen The deficiency layer and the low oxygen deficiency layer do not prevent inclusion of a predetermined impurity (for example, an additive for adjusting the resistance value) in addition to the corresponding transition metal oxide.

  In addition, when a resistive film is formed by sputtering, an unintended trace element may be mixed into the resistive film due to residual gas or outgassing from the vacuum vessel wall. Naturally, it is also included in the scope of the present invention when mixed into the film.

  Moreover, you may use a different transition metal for the 1st transition metal which comprises a 1st transition metal oxide, and the 2nd transition metal which comprises a 2nd transition metal oxide. In this case, the second transition metal oxide preferably has a lower degree of oxygen deficiency than the first transition metal oxide, that is, has a higher resistance.

  By adopting such a configuration, the voltage applied between the first electrode and the second electrode is distributed more in the second transition metal oxide layer, and as a result, the second transition metal oxidation is performed. The oxidation-reduction reaction generated in the physical layer can be more easily caused.

  When different materials are used for the first transition metal and the second transition metal, the standard electrode potential of the second transition metal is preferably smaller than the standard electrode potential of the first transition metal. This is because the resistance change phenomenon is considered to occur when a redox reaction occurs in a small filament (conductive path) formed in the second transition metal oxide layer having a high resistance, and the resistance value changes.

For example, a stable resistance change operation can be obtained by using an oxygen-deficient tantalum oxide for the first transition metal oxide and titanium oxide (TiO ₂ ) for the second transition metal oxide. Titanium (standard electrode potential = −1.63 [eV]) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 [eV]).

  The standard electrode potential represents a characteristic that the greater the value, the less likely it is to oxidize. By disposing a metal oxide having a standard electrode potential smaller than that of the first transition metal oxide in the second transition metal oxide, a redox reaction is more likely to occur in the second transition metal oxide layer.

  The resistance change phenomenon in the variable resistance film of the laminated structure of each material described above is caused by the oxidation-reduction reaction occurring in the minute filament formed in the second transition metal oxide layer having high resistance, and the resistance value changes. And is thought to occur.

  That is, when a positive voltage is applied to the second electrode on the second transition metal oxide layer side with respect to the first electrode, oxygen ions in the resistance change layer are attracted to the second transition metal oxide layer side. Thus, it is considered that an oxidation reaction occurs in the microfilament formed in the second transition metal oxide layer and the resistance of the microfilament increases.

  Conversely, when a negative voltage is applied to the second electrode on the second transition metal oxide layer side with respect to the first electrode, oxygen ions in the second transition metal oxide layer are converted into the first transition metal oxide. It is considered that the reductive reaction occurs in the microfilament formed in the second transition metal oxide layer by being pushed to the layer side, and the resistance of the microfilament is reduced.

  The second electrode connected to the second transition metal oxide layer having a smaller oxygen deficiency includes, for example, a second transition metal constituting the second transition metal oxide, such as platinum (Pt), iridium (Ir), and the like. The first electrode is made of a material having a higher standard electrode potential than the material constituting the first electrode. With such a configuration, a redox reaction occurs selectively in the filament in the second transition metal oxide layer near the interface between the second electrode and the second transition metal oxide layer, and a stable resistance change phenomenon Is obtained.

  The semiconductor memory device and the manufacturing method thereof according to the present invention have been described based on the embodiments. However, the present invention is not limited to such embodiments. A variable resistance nonvolatile element realized by making various modifications conceived by those skilled in the art without departing from the gist of the present invention, or by arbitrarily combining the components in the embodiment, and a method for manufacturing the variable resistance nonvolatile element are also included in the present invention. include.

  The present invention provides a resistance change type semiconductor memory device and a method for manufacturing the same, and can realize a semiconductor memory device that can lower an initial break voltage and reduce inter-element variation. The present invention is useful in various electronic equipment fields using a conductive semiconductor memory device.

S substrate 1 first interlayer insulating film 1a, 4a step 2 second interlayer insulating film 3 third interlayer insulating film 4 fourth interlayer insulating film 4 ′ TEOS films 11, 111, 211 first electrodes 11 ′, 211 ′ first electrode Membrane 12, 112, 212 Second electrode 12 ', 212' Second electrode membrane 21, 121, 221 High oxygen deficiency layer 21 ', 221' High oxygen deficiency film 22, 122, 222 Low oxygen deficiency layer 22 ' , 222 ′ Low oxygen deficiency films 22 a, 122 a, 222 a Stepped portion 40 Plug 40 a Contact hole 51 First wiring 52 Second wiring 61 Upper depressions 70, 170, 270 Resistance change elements 90, 91, 92, 93 Semiconductor memory device

Claims (14)

A substrate,
An interlayer insulating film formed on the substrate;
A wiring formed on the interlayer insulating film in a state where at least a part of the surface is exposed from the upper surface of the interlayer insulating film;
A lower electrode formed across the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring;
A low oxygen deficiency layer configured using an oxygen-deficient second transition metal oxide, and a high oxygen configured using a first transition metal oxide having a greater oxygen deficiency than the second transition metal oxide A variable resistance layer configured by laminating a deficiency layer on the lower electrode;
An upper electrode formed on the variable resistance layer,
A step is formed at the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring,
The low oxygen deficiency layer of the resistance change layer is formed along the shape of the boundary, thereby having a step portion in a cross-sectional view. The high oxygen deficiency layer of the resistance change layer is formed on the lower electrode,
The semiconductor memory device according to claim 1, wherein the low oxygen deficiency layer of the resistance change layer is formed on the high oxygen deficiency layer. The low oxygen deficiency layer of the resistance change layer is formed on the lower electrode;
The semiconductor memory device according to claim 1, wherein the high oxygen deficiency layer of the resistance change layer is formed on the low oxygen deficiency layer. The semiconductor memory device according to claim 1, wherein the lower electrode is formed across a part of the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring. The semiconductor memory device according to claim 1, wherein the entire exposed surface of the wiring is formed to be above the upper surface of the interlayer insulating film. The exposed surface of the wiring is formed to be lower than the upper surface of the interlayer insulating film; and
The semiconductor memory device according to claim 1, wherein the interlayer insulating film is formed so as to cover a part of the upper surface of the wiring. The semiconductor memory device according to claim 1, wherein the stepped portion in a cross-sectional view of the low oxygen deficiency layer has a linear shape in a plan view. The semiconductor memory device according to claim 1, wherein the step portion in the cross-sectional view of the low oxygen deficiency layer has a curved portion in a plan view. The semiconductor memory device according to claim 1, wherein the first transition metal oxide and the second transition metal oxide are made of a material containing tantalum, hafnium, or zirconium. The semiconductor memory device according to claim 9, wherein the second transition metal oxide is made of an insulator. The electrode formed in contact with the low oxygen deficiency layer among the lower electrode and the upper electrode is composed of a material containing platinum, palladium, iridium, or a mixture thereof. 2. A semiconductor memory device according to claim 1. A first step of forming an interlayer insulating film on the semiconductor substrate;
A second step of forming a wiring on the interlayer insulating film so that at least a part of the surface is exposed from the surface of the interlayer insulating film and having a step at a boundary with the interlayer insulating film;
A third step of forming a lower electrode film across the boundary between the upper surface of the interlayer insulating film and the exposed surface of the wiring;
On the lower electrode film, a low oxygen deficiency film composed of an oxygen-deficient second transition metal oxide and a first transition metal oxide having a greater oxygen deficiency than the second transition metal oxide are formed. A fourth step of stacking the high oxygen deficiency films in this order or in the reverse order to form a resistance change film;
A fifth step of forming an upper electrode film on the variable resistance film;
A sixth step of processing the lower electrode film, the resistance change film, and the upper electrode film into a shape including a step portion of the low oxygen deficiency film formed along the step. Method. The fourth step includes a step of forming the high oxygen deficiency film on the lower electrode film and a step of forming the low oxygen deficiency film on the high oxygen deficiency film. Manufacturing method of the semiconductor memory device of FIG. The fourth step includes: forming the low oxygen deficiency film on the lower electrode film; and forming the high oxygen deficiency film on the low oxygen deficiency film. Manufacturing method of the semiconductor memory device of FIG.