JP2013165159A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method and a semiconductor device capable of stably forming a buried wiring having a fine pattern without using a high-precision lithography technique or the like.
A step of forming a plurality of fin portions by forming a first groove 1D in a silicon substrate 1 and a film of a conductive material containing impurities on a wall surface of the first groove 1D are formed. Forming a bit line 6 underneath, forming a lower diffusion layer 5 by heat-treating the bit line 6 to diffuse impurities under the plurality of fins, and forming a second groove in the fins Thus, a step of forming the pillar portion 1C, a step of forming a word line by forming a conductive material containing impurities on the side surface of the second groove, and an upper diffusion by injecting impurities into the upper surface 1c of the pillar portion 1C Forming the layer 14.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device obtained thereby.

  In general, in the field of a semiconductor device such as a DRAM (Dynamic Random Access Memory) or a PRAM (Parameter Random Access Memory), higher integration is being promoted due to higher functions of devices in which the semiconductor device is used.

  However, in the conventional semiconductor layer device, as the degree of integration increases, the area occupied by semiconductor elements in a plane decreases, and for example, the size of the area where a transistor is formed, that is, the active area gradually decreases. There is a problem that. Specifically, as the size of the active region is reduced, the channel length of a normal planar transistor is reduced, so that a so-called short channel effect occurs. For this reason, a semiconductor device in which a three-dimensional transistor such as a vertical transistor is formed instead of a conventional planar transistor and a manufacturing method thereof are proposed in order to increase the channel length and width in a limited region. (See, for example, Patent Documents 1 and 2). Specifically, a silicon substrate is formed in a pillar shape, an upper impurity diffusion layer is formed at the top, a channel region surrounded by a gate electrode is formed at the center, and a lower impurity diffusion layer is formed on the substrate side, thereby forming a so-called MOS transistor. It has been proposed to manufacture a semiconductor device.

  In such a vertical transistor, a method of forming a buried bit line using an ion implantation method has been adopted, and a method of forming a buried bit line as a silicide layer has also been proposed. (For example, see Patent Document 3).

Japanese Patent Application Laid-Open No. 07-273221 JP-T-2002-541667 JP 2007-329480 A

  When manufacturing a semiconductor device by a method as described in Patent Documents 1 to 3, for example, in a process of forming a bit line conductive film pattern on a side surface of a fin portion formed on a silicon substrate, a conventionally known lithography technique is used. Used. However, when a fine bit line conductive film pattern is formed, if a general lithography technique is used, problems such as misalignment may occur, and the manufacturing yield may be reduced. In order to prevent such problems, it is necessary to use a high-precision lithography process in forming a fine pattern. In this case, however, the manufacturing equipment becomes expensive and the process time becomes long, resulting in an increase in cost. It was a factor.

  In addition, when forming a bit line conductive film pattern by a conventional method, first, after forming a conductive material on the side surface of the fin portion, a method of adjusting the pattern height by a conventionally known etching method is adopted. . However, in such a method, the dimension in the height direction of the bit line conductive film pattern is affected by the error of the etching amount, so that a stable height cannot be obtained and it is difficult to form a fine pattern. There is.

  Further, when forming a lower diffusion layer by a conventional method and further forming a bit line conductive film pattern, first, after doping the impurity on the side surface of the fin portion to form the lower diffusion layer, as described above, the lower diffusion layer is formed. A method of forming a conductive material on the surface of the layer and performing an etching process is employed. However, such a conventional method has a problem that it is difficult to reduce the number of steps and improve productivity, and it is difficult to reduce production cost. Furthermore, if the bit line conductive film pattern formed on the surface of the lower diffusion layer is fine, the resistance of the bit line increases, which may affect the device characteristics.

  In order to solve the above problems, the present inventors have conducted intensive research, and in the process of manufacturing a semiconductor device having a three-dimensional structure, first, a bit line conductive film pattern is formed as a buried wiring on the side surface of the fin portion of the semiconductor substrate. In this case, by adopting a method of forming a bit line conductive film pattern under a sidewall-like insulating film mask formed on the side surface, a bit line having a fine pattern can be formed without using a high-precision lithography technique or the like. We focused on the point that it can be formed stably. Further, the bit line conductive film is made of a conductive material containing impurities, and further subjected to heat treatment, whereby the impurities contained in the bit line conductive film can be diffused into the fin portion of the semiconductor substrate, so that the lower part can be manufactured with high productivity. The present inventors have found that a diffusion layer can be formed and completed the present invention.

  That is, the method for manufacturing a semiconductor device of the present invention includes a step of forming a plurality of fin portions by removing at least a part of a silicon substrate to form a first groove, and impurities on a wall surface of the first groove. Forming a buried wiring under the plurality of fin portions by depositing a conductive material containing the conductive material; and applying heat treatment to the buried wiring to remove impurities contained in the buried wiring of the plurality of fin portions. A step of forming a lower diffusion layer by diffusing in the lower part and a second groove having a bottom surface at a position higher than the embedded wiring in the fin part, thereby dividing the fin part into a plurality of parts. Forming a pillar portion; forming a gate wiring including a gate electrode by depositing a conductive material containing an impurity on a side surface of the second groove; and impregnating an upper surface of the pillar portion. Characterized in that it comprises a step of forming an upper diffusion layer by implanting.

  In the method for manufacturing a semiconductor device of the present invention, a mask insulating film and a first resist mask are sequentially formed on a silicon substrate, and then the silicon substrate and the mask insulating film are etched using the first resist mask. Forming a plurality of fin portions by forming a first groove in the extending direction of the embedded wiring planned line, and then removing the first resist mask; and forming the first groove with an insulating material Then, the upper part of the insulating material is removed by etching to form a first insulating film at the bottom of the first groove, and then the upper surface of the first insulating film, the side surface of the first groove, and the mask After forming a thin film made of an insulating material so as to cover the insulating film, the upper surface of the first insulating film and the thin film on the mask insulating film are etched back, so that an upper portion of the side surface of the first groove is formed. Forming a second insulating film provided in a sidewall shape, and then etching and removing the first insulating film filled in the lower portion of the first groove, and the first groove contains impurities. After filling the conductive material, a part of the conductive material is removed by etching to expose the bottom surface of the first groove, and the conductive material is placed at a position lower than the second insulating film on the side surface of the first groove. By leaving the embedded wiring, a buried wiring forming step for forming a buried wiring under the plurality of fin portions, and by performing a heat treatment on the buried wiring, impurities contained in the buried wiring are formed under the plurality of fin portions. By diffusing, a lower diffusion step of forming a lower diffusion layer in a region of the silicon substrate in contact with the embedded wiring, and the fin portion crosses the embedded wiring. A pillar part that etches in the extending direction of the wiring line and forms a plurality of pillar parts by dividing the fin part into a plurality of parts by forming a second groove whose bottom surface is located higher than the buried wiring. Forming a thin film made of a conductive material containing impurities on the side surface and bottom surface of the second groove, and then etching away the thin film formed on the bottom surface; and further, forming the thin film on the side surface Etching the upper portion of the thin film to form a gate wiring including a gate electrode on the side surface of the second groove; and etching the mask insulating film to expose the upper surface of the pillar portion; An upper diffusion step of forming an upper diffusion layer by injecting impurities into the upper surface.

  According to the method for manufacturing a semiconductor device having such a configuration, it is possible to form a buried wiring that is a bit line having a fine pattern while preventing misalignment or the like without using a high-precision lithography technique or the like. In addition, the height of the embedded wiring on the side surface of the fin portion can be formed while being limited by the height of the lower end of the first insulating film formed on the side surface of the first groove. It can be formed at a stable height without receiving.

  In addition, by using a conductive material containing impurities for the embedded wiring and adopting a method of diffusing impurities contained in the fins of the semiconductor substrate, the process can be simplified and productivity is improved. Manufacturing costs can be reduced.

  According to the method for manufacturing a semiconductor device of the present invention, by adopting the above method, the embedded wiring which is a bit line having a fine pattern can be prevented from misalignment without using a high-precision lithography technique or the like. Since it can be formed, a semiconductor device can be manufactured with high productivity and high yield. In addition, the height of the embedded wiring on the side surface of the fin portion can be formed while being limited by the height of the lower end of the second insulating film formed on the side surface of the first groove. It becomes possible to form with stable height without receiving.

  In addition, by using a conductive material containing impurities for the embedded wiring and diffusing the impurities included in the embedded wiring into the fin portion of the semiconductor substrate, the process can be simplified and productivity is improved. At the same time, the manufacturing cost can be reduced. Further, when the lower diffusion layer is shared as the lower source / drain region in the vertical type MOS transistor, the lower source / drain region forming step can be omitted, so that the effect of further improving productivity can be obtained.

  Further, according to the semiconductor device of the present invention, the lower diffusion layer is formed by diffusing impurities contained in the conductive material forming the buried wiring, and is formed in close contact with the buried wiring at the lower portion of the pillar portion. Therefore, it can be used as a bit line in the same manner as the embedded wiring. As a result, the resistance of the bit line can be reduced. In particular, the resistance of the bit line can be remarkably reduced even when the embedded wiring that is the bit line is configured with a fine pattern. It becomes possible to realize element characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS It is a cross-sectional schematic diagram which shows the manufacturing method and semiconductor device of the semiconductor device which are 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross-section A- shown in (a) A 'and (c) are cross sections BB'. 1A and 1B are schematic cross-sectional views illustrating a semiconductor device manufacturing method and a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view CC ′ shown in FIG. D ′. BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a). . It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIG. 15A is a process diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention, in which FIG. 14A is a cross-section CC ′ illustrated in FIG. 14A and FIG. 14C is a cross-section DD ′. . BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIGS. 17A to 17C are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention, in which FIG. 16A is a cross-section CC ′ illustrated in FIG. 16A and FIG. . BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIGS. 19A to 19C are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention, in which FIG. 18A is a section CC ′ illustrated in FIG. 18A and FIG. 18C is a section DD ′; . BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIGS. 21A and 21B are process diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention, in which FIG. 20A is a section CC ′ and FIG. 20C is a section DD ′ illustrated in FIG. . FIG. 22 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view illustrating the stacked body in the process illustrated in FIGS. 20 and 21, and the X direction illustrated in FIG. The current direction and the Y direction are the bit line extending directions. BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIGS. 24A and 24B are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention, in which FIG. 23A is a cross-section CC ′ illustrated in FIG. 23A and FIG. 23C is a cross-section DD ′; . BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIG. 26 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention, in which (a) is a section CC ′ shown in FIG. 25A and (c) is a section DD ′. . BRIEF DESCRIPTION OF THE DRAWINGS It is process drawing which shows the manufacturing method of the semiconductor device which is 1st Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a), ( c) is a cross-section BB ′. FIG. 28A is a process diagram illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention, where FIG. 27A is a cross-section CC ′ illustrated in FIG. 27A, and FIG. 27C is a cross-section DD ′. . FIG. 3 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and is a perspective view illustrating the stacked body illustrated in FIGS. 1 and 2, in which an X direction is a word line extending direction; , Y direction is a bit line extending direction. It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention, (a) is the top view seen from the upper surface side, (b) is the cross section AA 'shown in (a). . It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which is 2nd Embodiment of this invention.

  A semiconductor device manufacturing method and a semiconductor device according to embodiments of the present invention will be described below with reference to the drawings as appropriate. The drawings referred to in the following description are for explaining the semiconductor device manufacturing method and the semiconductor device of the present embodiment, and the size, thickness, dimensions, etc. of each part shown are the dimensions of the actual semiconductor device. The relationship is different.

[First Embodiment]
FIGS. 1A to 1C and FIGS. 2A and 2B are cross-sectional views schematically showing a semiconductor device A according to a first embodiment to which the present invention is applied. 29 is a perspective view showing the stacked body (semiconductor device A) shown in FIGS. 1 and 2, in which the X direction is the bit line extending direction and the Y direction is the word line extending direction. is there. 3 to 28 are process diagrams schematically showing each process of the manufacturing method of the semiconductor device of this embodiment.

"Configuration of semiconductor devices"
First, the configuration of the semiconductor device of this embodiment will be described below.
As shown in FIGS. 1A to 1C and FIGS. 2A and 2B, the semiconductor device A of this embodiment includes at least a plurality of columnar pillars erected on the base portion 1B. A bit line (buried wiring) 6 made of a conductive material including impurities, and a silicon substrate (substrate, semiconductor substrate) 1 including the portion 1C and the side surface 1a of the base portion 1B; The lower diffusion layer 5 formed in the base portion 1B and formed by diffusing impurities contained in the conductive material forming the bit line 6, and the side surface 1b side of the pillar portion 1C above the bit line 6, Formed on the gate electrode 10A, which is provided through the gate insulating film 8 and made of a conductive material containing impurities, forms part of the word line (gate wiring) 10 and the upper surface 1c of the pillar portion 1C, and the impurities are diffused. An upper diffusion layer 14 and a schematic configuration It is. As described above, the semiconductor device A according to this embodiment includes the upper diffusion layer 14, the word line 10, the bit line 6, the lower diffusion layer 5, and the like, so that a so-called vertical structure is formed on the silicon substrate 1. The MOS transistor is configured.

A silicon substrate (substrate) 1 includes a base portion 1A having a flat surface, a base portion 1B provided on the base portion 1A, and a plurality of columnar pillar portions 1C provided on the base portion B. In this embodiment, it is made of a silicon single crystal.
The base part 1B is formed as a base of the columnar pillar part 1C on the base part 1A. Further, in the lowermost part between each of the base parts 1B, a digging part 1F is formed to divide the lower diffusion layer 5 into the side surface 1a of each base part 1B, which will be described in detail in the manufacturing method described later. ing.
The pillar portion 1C is a columnar portion made of silicon, and the upper surface 1c can be, for example, elliptical. The height of the upper surface 1c is substantially uniform.
As the silicon substrate 1, a substrate in which a base portion and a pillar portion made of a silicon layer are formed on a base portion may be used.

  In the present embodiment, the bit line (embedded wiring) 6 is made of a conductive material containing at least impurities, is formed in a thin film shape so as to cover the side surface 1a of the base portion 1B, and extends in the bit line extending direction. Provided. Further, as shown in FIG. 1B, the bit line 6 is disposed at a position lower than the buried insulating film (second insulating film) 4 formed on the side surface 1b of the pillar portion 1C.

  The bit line 6 is made of a conductive material containing an impurity having a conductivity type opposite to that of the silicon substrate 1, and for example, a material doped with phosphorus or the like as an impurity is used. In this embodiment, only the example in which the bit line 6 is made of a conductive material containing an impurity is described. However, the present invention is not limited to this. For example, a configuration made of a silicide layer containing an impurity can be adopted. And can be adopted as appropriate.

  The buried insulating film (second insulating film) 4 is provided as a sidewall covering the side surface 1b of the pillar portion 1C in the bit line extending direction. In the example shown in FIG. 1B and the like, the side surface 1b of the pillar portion 1C is provided. Are formed at a position higher than the bit line 6. As the buried insulating film 4 used in the present embodiment, for example, a silicon nitride film or the like can be used and can be formed by a CVD method or the like.

As described above, the lower diffusion layer 5 is a region formed by diffusing impurities contained in the bit line 6 that is a buried wiring, such as phosphorus, into the base portion 1B forming the silicon substrate 1 by heat treatment. The lower diffusion layer 5 shown in FIG. 1B or the like is formed on the side surface 1a of the base 1B so that the dimension in the height direction is larger than that of the bit line 6.
The lower diffusion layer 5 is disposed at a position lower than the upper diffusion layer 14 described later, and is a region in which impurities such as phosphorus are diffused so as to have a concentration of about 2.5E ¹⁵ atoms / cm ² , for example. It is.

The word line (gate wiring including a gate electrode) 10 is provided so as to cover the side surface 1b of the pillar portion 1C at least above the bit line 6 with the gate insulating film 8 interposed therebetween. The electrode 10A is included.
As a material of the word line 10, for example, a doped silicon film containing impurities can be used, and the word line 10 can be formed by a CVD method. However, the material of the word line 10 is not limited to this. For example, as the word line 10, a high melting point metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film may be used as a single layer, or a laminated film thereof may be used. It is possible to select appropriately including the material.
Note that the film thickness of the word line 10 is preferably set to a thickness that does not fill the second groove 1E formed between each of the plurality of pillar portions 1C as described in a manufacturing method described later. .

  As in the example shown in FIG. 2A and the like, the gate insulating film 8 is provided so as to cover the side surface 1b of the pillar portion 1C in the gate line extending direction. As the gate insulating film 8 used in the present embodiment, for example, a silicon oxide film or the like can be used, and can be formed by, for example, a thermal oxidation method or the like.

The upper diffusion layer 14 is composed of an impurity diffusion region into which an impurity (dopant) is ion-implanted, and is provided on the upper surface 1 c of the pillar portion 1 C of the silicon substrate 1. As an impurity diffused in the upper diffusion layer 14, for example, N-type arsenic (As) is used and is introduced into the substrate by a conventionally known ion implantation method. Further, the upper diffusion layer 14 of the present embodiment can be configured such that arsenic is implanted so as to have a concentration of about 2.5E ¹⁵ atoms / cm ² , for example.

The first interlayer insulating film (interlayer insulating film) 7 covers at least a part of the side surfaces of the base portion 1B and the pillar portion 1C via the buried insulating film 4, and the position of the side surface 1a of the base portion 1B. The bit line 6 is formed so as to cover the lower diffusion layer 5 formed in a large number.
Further, as shown in FIGS. 2A and 2B, the second interlayer insulating film (interlayer insulating film) 11 covers the side surface 1b of the pillar portion 1C via the word line 10 and the gate insulating film 8 described above. At the same time, it is formed so as to cover the side surfaces of the upper diffusion layer 14 and a contact conductive film 12 described later.

  Furthermore, in the semiconductor device A of the present embodiment, as illustrated in FIG. 1B and the like, a third interlayer insulating film 15 disposed on the first interlayer insulating film 7 and covering the side surface of the capacitor structure described later is provided. Further, a fourth interlayer insulating film 16 is provided on the capacitor structure.

  The material used for each of the above-described interlayer insulating films 7, 11, 15, and 16 is not particularly limited. For example, a conventionally known material such as a silicon nitride film or a silicon oxide film can be used without any limitation. .

  The contact conductive film 12 is a layer that is connected to the entire upper surface of the upper diffusion layer 14, and the material thereof is not particularly limited. For example, an impurity-doped silicon film can be used. It is not limited. For example, as the contact conductive film 12, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film may be used as a single layer, or a laminated film of these may be used.

  The capacitor 13 is provided on the above-described contact conductive film 12, and a conventionally known capacitor structure can be employed without any limitation. As illustrated in FIG. 1B, the capacitor 13 provided in the semiconductor device A of this embodiment includes a contact conductive film 12, a capacitor lower electrode 13b belonging to the back, and a capacitor insulating film 13a formed thereon. And the capacitor upper electrode 13c.

As a material of the capacitor insulating film 13a, a conventionally known capacitor material may be employed. For example, a zirconium oxide film or the like can be used.
The capacitor lower electrode 13b is a connection electrode with the contact conductive film 12 formed so as to cover the side surface and the bottom surface of the capacitor insulating film 13a, and may be made of a conventionally known conductive material such as a titanium nitride film. it can.
The capacitor upper electrode 13c is formed so as to cover the upper portion of the capacitor insulating film 13a while filling the concave portion of the capacitor insulating film 13a. As the material of the capacitor upper electrode 13c, similarly to the capacitor lower electrode 13b, for example, a conventionally known conductive material such as a titanium nitride film can be used.

  Furthermore, in the semiconductor device A of the present embodiment, the fourth interlayer insulating film 16 made of an insulating material is stacked on the capacitor upper electrode 13c. Further, the semiconductor device A is provided with a peripheral contact (not shown) connected to the word line 10 (gate electrode 10A), the lower diffusion layer 5 and the like so as to penetrate each interlayer insulating film 16, 15, 11 and the like. .

  The semiconductor device A shown in FIGS. 1A to 1C and FIGS. 2A and 2B is connected to the peripheral contact (not shown) and includes a base layer 17a and a main wiring layer 17b. Peripheral wiring 17 is provided. Although not shown in detail, in the semiconductor device of this embodiment, a configuration further including an upper interlayer film, a via hole, various wirings, a passivation film, and the like can be employed as necessary.

  As described above, the semiconductor device A of this embodiment includes the upper diffusion layer 14, the word line 10, the bit line 6, and the lower diffusion layer 5 on the silicon substrate 1, and is further connected to the upper diffusion layer 14. The capacitor 13 is provided, and a vertical structure MOS transistor is formed. In other words, in the semiconductor device A, the lower diffusion layer 5 is used as the lower source / drain region to form a MOS transistor.

  In the semiconductor device A of the present embodiment, the lower diffusion layer 5 is formed by diffusing impurities contained in the conductive material forming the bit line 6, and is formed in close contact with the bit line 6 in the base portion 1B. Therefore, it can be used together with the bit line 6 for bit wiring. As a result, the resistance of the bit line 6 can be reduced. In particular, even when the bit line 6 is configured with a fine pattern, the bit line 6 and the lower diffusion layer 5 are used in combination. The resistance at 6 can be significantly reduced.

"Manufacturing method of semiconductor device"
Next, a method for manufacturing the semiconductor device A of this embodiment will be described below with reference to FIGS. 2 to 29 (also refer to FIG. 1).
In the manufacturing method of the semiconductor device A according to the present embodiment, the step of forming the plurality of fin portions 1G by removing at least a part of the silicon substrate 1 to form the first groove 1D, and the wall surface of the first groove 1D A conductive material containing impurities is deposited on the plurality of fin portions 1G to form bit lines (embedded wirings), and the bit lines 6 are subjected to heat treatment to be included in the bit lines 6. By diffusing impurities under the plurality of fin portions 1G, a step of forming the lower diffusion layer 5 and a second groove 1E having a bottom surface at a position higher than the bit line 6 are formed in the fin portion 1G. The word line (gate wiring including the gate electrode 10A) 10 is formed by dividing the fin part 1G into a plurality of parts to form the pillar part 1C and by depositing a conductive material containing impurities on the side surface of the second groove 1E. Forming, and forming an upper diffusion layer 14 by implanting impurities into the upper surface 1c of the pillar portion 1C, a method comprising a.

In addition, the manufacturing method of the present embodiment can be more specifically a method in which the following steps (1) to (7) are sequentially provided.
(1) A mask insulating film 2 and a first resist mask are sequentially formed on the silicon substrate 1, and then the silicon substrate 1 and the mask insulating film 2 are etched using the first resist mask, whereby a bit line (embedded wiring) is formed. ) A fin portion forming step of forming the plurality of fin portions 1G by forming the first groove 1D in the extending direction of the planned line and then removing the first resist mask.
(2) After embedding the first trench 1D with an insulating material, the first insulating film 31 is formed on the bottom of the first trench 1D by etching away the upper portion of the insulating material, and then the first insulating film 31 After forming a thin film made of an insulating material so as to cover the upper surface, the side surface of the first groove 1D and the mask insulating film 2, the upper surface of the first insulating film 31 and the thin film on the mask insulating film 2 are etched back, An insulating film forming step of forming a second insulating film 32 provided in a sidewall shape on an upper portion of the side surface of the first groove 1D, and then etching away the first insulating film 31 filled in the lower portion of the first groove 1D;
(3) After the first groove 1D is filled with a conductive material containing impurities, a part of this conductive material is removed by etching to expose the bottom surface of the first groove 1D, and the second insulation on the side surface of the first groove 1D. A buried wiring forming step of forming bit lines (buried wiring) 6 below the plurality of fin portions 1G by leaving the conductive material at a position lower than the film 32.
(4) By performing heat treatment on the bit line 6, the impurities contained in the bit line 6 are diffused below the plurality of fin portions 1 G, thereby forming the lower diffusion layer 5 in a region in contact with the bit line 6 of the silicon substrate 1. Lower diffusion process to be formed.
(5) Etching the fin portion 1G in the extending direction of the planned line of the gate wiring (word line 10) intersecting the bit line 6 to form the second groove 1E having a bottom surface at a position higher than the bit line 6. The pillar part formation process which divides | segments the fin part 1G into plurality and forms the several pillar part 1C by these.
(6) After forming a thin film made of a conductive material containing impurities on the side surface and bottom surface of the second groove 1E, the thin film formed on the bottom surface of the second groove 1E is removed by etching. A word line (gate wiring) forming step of forming the word line 10 which is a gate wiring including the gate electrode 10A on the side surface of the second groove 1E by etching away the upper part of the thin film formed on the side surface.
(7) An upper diffusion step of forming the upper diffusion layer 14 by etching away the mask insulating film 2 to expose the upper surface 1c of the pillar portion 1C and implanting impurities into the upper surface 1c.
Hereinafter, each step will be described in detail.

<(1) Fin part formation process>
In the fin portion forming step, the mask insulating film 2 is formed on the silicon substrate 1 as described above. Thereafter, a first resist mask is further formed on the mask insulating film 2, and then the silicon substrate 1 and the mask insulating film 2 are etched using the first resist mask, whereby the bit line (buried wiring) planned line is formed. A plurality of fin portions 1G are formed by forming the first groove 1D in the extending direction.

  Specifically, as shown in FIGS. 3A and 3B, first, a silicon substrate 1 made of P-type silicon single crystal is prepared, and a mask insulating film 2 is formed on the silicon substrate 1. At this time, for example, a silicon nitride film is used as the mask insulating film 2 and the material, and the film thickness is approximately 200 nm and is formed by a conventionally known film forming method.

  Next, although not shown, a first resist mask is formed on the mask insulating film 2. At this time, as the first resist mask, a resist material used in this field is usually used, and a film can be formed by a conventionally known film forming method.

  Next, as shown in FIGS. 4A and 4B, the mask insulating film 2 and the silicon substrate 1 are sequentially etched using a first resist mask (not shown) as a mask, thereby forming a first groove 1D. The first grooves 1D have a pattern extending in the X direction (see FIG. 29) in the bit line direction, and a plurality of the first grooves 1D are arranged in the Y direction. A plurality of fin portions 1G made of the silicon substrate 1 are formed between the first grooves 1D adjacent to each other, and a mask insulating film 2 is laminated on the upper surface of the fin portions 1G. Similar to the first groove 1D, the fin portion 1G has a pattern extending in the X direction in the bit line direction, and a plurality of fin portions 1G are arranged in parallel in the Y direction.

  Here, when the groove width of the first groove 1D is w2, the pattern of the first groove 1D is, for example, using the minimum processing dimension F of the process, the groove width w2 = F, the interval F, and the pitch 2F in the Y direction. In this case, the minimum processing dimension F of the process is preferably about 50 nm. The depth of the first groove 1D is preferably about 500 nm, for example, combined with the mask insulating film 2.

  In the fin portion forming step, the first resist mask (not shown) is removed by an etching method.

<(2) Insulating film forming step>
Next, in the insulating film forming step, the first groove 1D is filled with an insulating material, and then the upper portion is etched away to form the first insulating film 31 at the bottom of the first groove 1D. After forming a thin film of an insulating material so as to cover the upper surface of the film 31, the side surface of the first groove 1D, and the mask insulating film 2, the upper surface of the first insulating film 31 and the thin film on the mask insulating film 2 are etched back, A second insulating film 32 provided in a sidewall shape is formed on the upper part of the side surface of the first groove 1D, and then the first insulating film 31 filled in the lower part of the first groove 1D is removed by etching.

  Specifically, first, an insulating material is embedded from the inside of the first trench 1 </ b> D to the mask insulating film 2. Next, the upper surface of the mask insulating film 2 is exposed by etching the buried insulating material. Then, by continuing the etching further, the etching amount is adjusted so that the insulating material remains at the bottom in the first groove 1D, whereby the first insulation as shown in FIGS. 5A and 5B is obtained. A film 31 is formed. In the example shown in FIG. 5B, for convenience of explanation, the height of the first insulating film 31 from the bottom surface of the first groove 1D is represented as d3.

  The material for the first insulating film 31 is not particularly limited. For example, the first insulating film 31 is formed using a silicon oxide film by a conventionally known method such as a CVD method or a method of forming an SOD film by applying and annealing. be able to. As the etching method, a conventionally known method such as a dry etching method or a wet etching method can be employed.

  The height d3 of the first insulating film 31 after the etching is the height of the bit line (buried wiring) 6 formed in the bit line forming process described later. Further, the height d3 of the first insulating film 31 can be controlled by the etching amount, and for example, d3 = about 100 nm.

  The formation of the first insulating film 31 by etching as described above is performed using an etching method having such a characteristic that the etching rate of the insulating material (first insulating film 31) is higher than that of the silicon substrate 1 and the mask insulating film 2. Do. In order to perform such etching, for example, as described above, the first insulating film 31 is formed of a silicon oxide film, the semiconductor substrate (silicon substrate 1) is a silicon substrate, and the mask insulating film 2 is a silicon nitride film. It is desirable to form. By adopting an etching method in which the silicon substrate 1 and the mask insulating film 2 can secure an etching selectivity with respect to the first insulating film 31, the insulating material (first insulating film 31) can be etched. Further, even the side surfaces of the first groove 1D are etched, so that the surface becomes rough and the width of the first groove 1D is prevented from being increased, and the first insulating film 31 can be embedded and formed with high accuracy. It becomes possible.

  Next, in the insulating film forming step of this embodiment, as shown in FIGS. 6A and 6B, the upper surface of the first insulating film 31, the side surface of the first groove 1D, and the mask insulating film 2 are covered. A thin film made of an insulating material is formed. As a material for such a thin film, it is desirable to use a material that can ensure a selection ratio in an etching process described later. For example, a silicon nitride film or the like is used, and a method such as a CVD method that has excellent step coverage is used. Can be membrane. In this case, the thickness of the thin film made of the insulating material is set to a thickness that does not embed the first groove 1D. For example, the thickness on the side surface of the first groove 1D is preferably set to about 10 nm. Here, in the example shown in FIG. 6B, for convenience of explanation, the thickness of the second insulating film 32 on the side surface of the first groove 1D is represented by t4.

  Next, as shown in FIGS. 7A and 7B, mask insulation is performed by etching back a thin film made of an insulating material formed on the upper surface of the first insulating film 31 and the mask insulating film 2 in the above procedure. The upper surfaces of the film 2 and the first insulating film 31 are exposed. Thereby, the second insulating film 32 provided in a sidewall shape can be formed in the upper part of the side surface of the first groove 1D. At this time, the lateral width of the second insulating film 32 is formed to be approximately the same as the thickness t4 described above.

Next, as shown in FIGS. 8A and 8B, the first insulating film 31 filled in the lower portion of the first groove 1D is selectively removed by etching. As an etching method at this time, for example, wet etching using hydrofluoric acid as a chemical solution can be used.
Through this etching process, a space 33 is formed in the first groove 1D. The space 33 is wide at the top and narrow at the bottom. In the example shown in FIG. 8B, the space portion sandwiched between the second insulating films 32 in the upper portion of the space portion 33 as described above is defined as the space portion 33 a and the width formed below the space portion 33 a. The wide space portion is represented as a space portion 33b, and in particular, a portion of the space portion 33b that is located immediately below the second insulating film 32 is represented as a space portion 33c. Here, when the horizontal width of the space portion 33b shown in FIG. 8B is expressed as w2, the horizontal width of the space portion 33a is approximately expressed by the following expression {w2-2 × t4}.

<(3) Bit line (embedded wiring) formation process>
Next, in the bit line (embedded wiring) forming step, after the first groove 1D is filled with a conductive material containing impurities, a part of this conductive material is removed by etching to expose the bottom surface of the first groove 1D. By leaving the conductive material at a position lower than the second insulating film 32 on the side surface of the first trench 1D, bit lines (buried wiring) 6 are formed below the plurality of fin portions 1G.

  Specifically, as shown in FIGS. 9A and 9B, first, a conductive material is formed so as to cover the surface in the space 33 (see FIG. 8B), and the mask insulating film 2 is formed. A conductive material is deposited over the top. As the conductive material used here, a conductive material containing an impurity having a conductivity type opposite to that of the silicon substrate 1 can be used. For example, a phosphorus-doped silicon film or the like can be used. In addition, as a method for forming a conductive material, a method having excellent step coverage can be used, for example, a CVD method or the like can be used. The conductive material can be formed to a thickness that closes the space 33a shown in FIG. 8B, for example, about 50 nm. At this time, in the space portion 33b in the first groove 1D, a cavity 6a surrounded by a thin film made of a conductive material is formed.

  A thin film made of a conductive material for forming a bit line is formed below the second insulating film 32 along the side surface of the first groove 1D. When the thickness of the conductive material on the side surface of the first groove 1D is equal to or less than t4 which is the thickness of the second insulating film 32, the lateral width of the bit line 6 (see FIG. 10B) to be formed later is It is formed approximately equal to the film thickness of the bit line 6 on the 1D side surface. When the thickness of the conductive material on the side surface of the first groove 1D is larger than t4 which is the thickness of the second insulating film 32, the lateral width of the bit line 6 to be formed later is roughly defined as t4.

  Next, in the bit line formation step, as shown in FIGS. 10A and 10B, the mask insulating film 2 is exposed by performing anisotropic etching on the thin film of the conductive material, Etching the conductive material in the space 33 (see FIG. 8B) exposes the silicon substrate 1 on the bottom surface of the first groove 1D. At this time, a thin film of a conductive material is left in the space 33c (FIG. 8B) under the second insulating film 32. By such a procedure, the bit line 6 can be formed under the second insulating film 32.

  Here, the bit line 6 embedded in the space portion 33c forms a wiring extending in the X direction in the perspective view shown in FIG. A bit line 6 is formed below each of the two side surfaces of the fin portion 1G.

  The height of the bit line 6 to be formed is equivalent to the height d3 of the first insulating film 31 in the above-described insulating film forming step (FIGS. 5A and 5B). That is, in the insulating film formation step shown in FIGS. 5A and 5B, the height d3 of the first insulating film 31 is controlled by etching, whereby the height of the bit line 6 can be controlled. As a result, in the bit line forming step in the present invention, when the bit line 6 is formed by etching the conductive material, the second insulating film 32 formed on the conductive material is used as a mask, so that it depends on the etching amount. Thus, the height of the bit line 6 does not change. Further, since the bit line 6 is formed by etching with the upper end 6a covered with a mask, the bit line 6 has a shape such as a rounded shape when the head of the bit line 6 is hit by etching. There is no deformation.

  Through the etching process as described above, a space 34 extending in the direction perpendicular to the substrate is formed in the first trench 1D, sandwiched between the second insulating film 32 and the bit line 6.

<Digging process>
In the method for manufacturing a semiconductor device of the present invention, in addition to the above steps (1) to (7), the bottom surface of the first groove 1D is etched before or after the lower diffusion step (4) described later. A digging step for forming a digging portion 1F communicating with the first groove 1D may be provided. In the present embodiment, a case where the digging process is provided between the bit line forming process and the lower diffusion process will be described.

  In the digging process of the present embodiment, as shown in FIGS. 11A and 11B, the bottom surface of the first groove 1D exposed in the bit line forming process is etched to further dig the silicon substrate 1, The digging portion 1F is formed. Thereby, as shown in FIG.11 (b), the above-mentioned space part 34 becomes wide only by the part which the digging part 1F was formed.

  Since the etching of the silicon substrate 1 in the digging process is performed using the second insulating film 32 formed on the bit line 6 as a mask, similarly to the bit linear process, the bit line 6 is etched during the etching of the silicon substrate 1. The digging portion 1 </ b> F can be formed while suppressing the occurrence of fluctuations in height, shape deterioration, and the like.

  In the manufacturing method of the present invention, after the impurity contained in the bit line 6 is previously diffused so as to cover the bottom surface from the side surface of the first groove 1D in the lower diffusion process described later, the lower diffusion layer 5 is formed. It is also possible to adopt a method of dividing the lower diffusion layer 5 along each side surface of the first groove 1D by forming the digging portion 11F in the digging step.

<(4) Lower diffusion process>
Next, in the lower diffusion step, the bit line 6 is subjected to heat treatment to diffuse impurities contained in the bit line 6 below the plurality of fin portions 1G, so that the region in contact with the bit line 6 of the silicon substrate 1 is formed. A lower diffusion layer 5 is formed.

  Specifically, as shown in FIGS. 12A and 12B, by heating the bit line 6 and performing a heat treatment, impurities contained in the bit line 6, that is, phosphorus in the example described in this embodiment, are removed. The lower diffusion layer 5 is formed by diffusing the silicon substrate 1 at the portion where the bit line 6 contacts, that is, the lower portion of the fin portion 1G. At this time, as shown in FIG. 12B, the lower diffusion layer 5 is formed in the lower part of each of the two side surfaces of the fin portion 1G. Thus, the lower diffusion layers 5 formed on both side surfaces of the first groove D are electrically separated by the digging portion 1F. Here, the depth of the digging portion 1F is set in advance such that the lower diffusion layers 5 formed on both side surfaces of the first groove 1D can be electrically separated in the digging step described above. .

  The adjacent lower diffusion layer 5 and bit line 6 can be combined to form one bit wiring, and bit wiring is formed on both side surfaces of the fin portion 1G. Such two bit wirings formed on both side surfaces of the fin portion 1G can be short-circuited at the end of the memory cell array and used as one bit wiring.

  The two lower diffusion layers 5 formed on both side surfaces of the fin portion 1G can be formed so as to be joined near the center of the fin portion 1G, and further formed below the plurality of fin portions 1G. It is also possible to form each of the formed lower diffusion layers 5 so as to be connected. When such a configuration is adopted, the structure of the transistor formed through the subsequent process is such that the position above the lower diffusion layer 5 of the silicon substrate 1 is located below the lower diffusion layer 5 and the lower diffusion layer. 5 is a so-called FBC (floating body cell) structure that is electrically separated by 5.

  When the above-described digging step is provided after the lower diffusion step, first, in the lower diffusion step, impurities such as phosphorus contained in the bit line 6 are diffused so as to cover the bottom surface from the side surface of the first groove 1D. To form a lower diffusion layer. Then, in the digging step, by forming the digging portion 1F communicating with the first groove 1D, the lower diffusion layer is divided along each side surface of the first groove 1D, so that both sides of the fin portion 1G are formed. It is also possible to employ a method of forming the lower diffusion layer 5.

<(5) Pillar part formation process>
Next, in the pillar portion forming step, the fin portion 1G is etched in the extending direction of the planned line of the gate wiring (word line 10) intersecting with the bit line 6, and the second position having a position higher than the bit line 6 as the bottom surface is second. By forming the groove 1E, the fin portion 1G is divided into a plurality of pillar portions 1C.

  Specifically, as shown in FIGS. 13A and 13B, first, the space portion 34 (FIG. 12 (FIG. 12 (A)) is formed in advance inside the first groove 1D and the digging portion 1F over the upper surface of the mask insulating film 2. b) etc.) is filled with an insulating material so as to be embedded. As the insulating material at this time, for example, a silicon oxide film or the like can be used. Then, the first interlayer insulating film 7 is formed in the space 34 by removing the insulating material deposited on the mask insulating film 2 using a method such as CMP.

  Next, as shown in FIGS. 14A to 14C and FIGS. 15A and 15B, a resist mask 35 having a linear pattern intersecting with the formation direction of the fin portion 1G is formed. In this embodiment, the line pattern of the resist mask 35 extends in the Y direction (word line extending direction) shown in the perspective view of FIG. 29, and a plurality of line patterns are arranged in parallel in the X direction (bit line extending direction). Arranged. In the present embodiment, the size of the resist mask 35 is a width F, an interval F, and a pitch 2F in the X direction.

Next, the exposed mask insulating film 2, the first interlayer insulating film 7, and the second insulating film 32 are etched using the resist mask 35. When the mask insulating film 2 is removed by etching, the silicon substrate 1 is exposed, and the exposed portion of the silicon substrate 1 is further etched so that the upper portion of the lower diffusion layer 5 is exposed. At this time, the first interlayer insulating film 7 and the second insulating film 32 are formed to have a height substantially equal to the height of the silicon substrate 1 dug down. As a result, a second groove 1E extending through the Y direction (word line extending direction) is formed. That is, a fin-like structure extending in the Y direction is formed between the second grooves 1E adjacent in the X direction (bit line extending direction).
Through the above steps, a plurality of pillar portions 1C having a columnar shape as shown in FIGS. 16A to 16C and FIGS. 17A and 17B can be formed. The pillar portion 1C is a main portion in which a vertical MOS transistor is formed in the semiconductor device A of the present invention.

  Furthermore, in the pillar part forming step provided in the present invention, the silicon substrate 1 is provided on the base part 1A by performing etching according to the above procedure and conditions, and the pillar part 1C is provided thereon. The base portion 1B having the lower diffusion layer 5 formed on the side surface 1d is formed.

  Further, in the pillar portion forming process of the present invention, a groove portion is formed in the mask insulating film 2, the first interlayer insulating film 7 and the second insulating film 32 in communication with the second groove 1E by the etching process described above. A gate trench portion M extending in the Y direction (word line extending direction) is formed. In the present embodiment, the gate groove M may also be referred to as the second groove 1E for convenience.

<(6) Word line (gate wiring) formation process>
Next, in the word line (gate wiring) formation step, a thin film made of a conductive material containing impurities is formed on the side surface and bottom surface of the second groove 1E, and then the thin film formed on the bottom surface of the second groove 1E is etched. Further, by removing the upper portion of the thin film formed on the side surface of the second groove 1E by etching, the word line 10 is a gate wiring including the gate electrode 10A on the side surface of the second groove 1E (gate groove portion M). Form.

  Specifically, as shown in FIGS. 18A to 18C and FIGS. 19A and 19B, the resist mask 35 is first removed. Next, a gate insulating film 8 is formed on the silicon substrate 1 exposed at the side and bottom surfaces of the second trench 1E (gate trench portion M). The material of the gate insulating film 8 is, for example, a silicon oxide film, which is formed by thermally oxidizing the surface layer of the silicon substrate 1 by a thermal oxidation method.

  Next, a conductive material forming a word line is formed so as to cover the side and bottom surfaces of the second trench 1E (gate trench portion M), the mask insulating film 2, the first interlayer insulating film 7, and the gate insulating film 8. As the conductive material at this time, for example, a doped silicon film containing impurities is used, and as the film formation method, for example, a CVD method is used. Note that the conductive material used at this time is not limited to the above materials, and for example, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film is formed as a single layer, or These laminated films may be formed. In addition, the thickness of the conductive material formed at this time is set to a thickness that does not fill the second groove 1E.

  Next, as shown in FIGS. 20A to 20C and FIGS. 21A and 21B, the second groove 1E (gate groove portion M) is obtained by etching back the conductive material using a dry etching technique. ) To form a sidewall-like word line 10 (a gate wiring including the gate electrode 10A). At this time, the height to the upper end of the gate wiring 10 is formed to be approximately the same as that of the pillar portion 1C, for example. As in the illustrated example, the word line 10 (gate electrode 10A) includes the gate insulating film 8 and the first insulating film 8 in the gate groove portion M communicating in the same shape as the second groove 1E in addition to both side surfaces of each pillar portion 1C. The interlayer insulating film 7 and the second insulating film 32 are formed so as to cover the interlayer insulating film 7 and the second insulating film 32. The word lines 10 formed on both side surfaces of the pillar portion 1C and in communication with the side surfaces are short-circuited between the word lines 10 formed on the respective side surfaces at the end of the memory cell array (not shown), thereby forming a common word line ( Gate wiring).

  FIG. 22 shows a perspective view of the laminate as viewed from the α direction shown in FIG. As shown in FIG. 22, a word line 10 (gate electrode 10A) formed extending in the Y direction serves as a gate wiring (word line) and a bit line 6 formed in the X direction and a lower diffusion. The layer 5 functions as a bit line by forming the same wiring adjacent to each other. In the present invention, pillar portions 1C are formed at the respective intersections of the word line 10 and the bit line 6 so that these function as unit memory cells.

<(7) Upper diffusion step to step of forming a contact conductive film>
Next, in the upper diffusion step, the mask insulating film 2 is removed by etching to expose the upper surface 1c of the pillar portion 1C, and an impurity is implanted into the upper surface 1c to form the upper diffusion layer 14. In the present embodiment, after the upper diffusion step, a contact conductive film 12 is formed by depositing a conductive material on the upper diffusion layer 14.

  Specifically, as shown in FIGS. 23A to 23C and FIGS. 24A and 24B, first, the second trench 1E (gate trench portion M) is buried and the upper surface of the mask insulating film 2 is filled. For example, a layer made of a silicon oxide film or the like is formed so as to cover the surface. Next, the silicon oxide film on the mask insulating film 2 is removed by CMP polishing or the like and planarized to form the second interlayer insulating film 11 in the second trench 1E (gate trench portion M).

  Next, as shown in FIGS. 25A to 25C and FIGS. 26A and 26B, the mask insulating film 2 is removed by etching to expose the upper surface 1c of the pillar portion 1C. At this time, for example, the mask insulating film 2 is removed by wet etching using a hot phosphoric acid solution. Further, the exposed upper surface 1c of the pillar portion 1C functions as a part of a contact opening for forming a contact conductive film 12 described later.

  Next, as shown in FIGS. 27A to 27C and FIGS. 28A and 28B, impurities are introduced into the exposed upper surface 1c of the pillar portion 1C. At this time, as an impurity, for example, arsenic (As) which is an N-type impurity can be used and introduced and diffused by an ion implantation method. Then, the upper diffusion layer 14 is formed on the upper surface 1c of the pillar portion 1C by activating the impurity by heat-treating the impurity introduction portion.

Further, in the step of forming the contact conductive film, as shown in FIGS. 27A to 27C and FIGS. 28A and 28B, the upper diffusion layer 14 exposed from between the second interlayer insulating films 11 is formed. A contact conductive film 12 is formed so as to embed (upper surface 1c). At this time, as a material used for the contact conductive film 12, for example, a silicon film doped with impurities can be used. Further, the material of the contact conductive film 12 is not limited to the above materials, and for example, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film is used as a single layer, or these It is also possible to use the laminated film.
Further, after the contact conductive film 12 is formed, the surplus is removed by CMP polishing or the like.

  FIG. 29 is a perspective view of the laminate as viewed from the α direction shown in FIG. As shown in FIG. 29, in the pillar portion 1C, the upper diffusion layer 14 is formed in the upper portion, the lower diffusion layer 5 is formed in the lower portion, and the word line 10 (gate electrode 10A) is formed on both side surfaces. Also, a vertical MOS transistor is formed in which the vertical direction of the silicon substrate 1 is the direction in which the channel current flows.

<Process for forming capacitor>
Next, the manufacturing method according to the present embodiment may further include a capacitor forming step of forming the capacitor 13 on the contact conductive film 12.

  Specifically, first, a third interlayer insulating film 15 is formed by forming an insulating material so as to cover the upper surface of the stacked body shown in FIG. Next, a capacitor opening for exposing the contact conductive film 12 is formed in the third interlayer insulating film 15 (see FIG. 1B).

Next, as shown in FIGS. 1A to 1C and FIGS. 2A and 2B, the capacitor openings of the third interlayer insulating film 15 and the capacitor conductive film 12 are covered so as to cover the capacitor openings. A capacitor lower electrode 13b connected to the contact conductive film plug 12 is formed. At this time, as a material of the capacitor lower electrode 13a, for example, a titanium nitride film or the like can be used.
Next, a capacitor insulating film 13a is formed on the capacitor lower electrode 13b. As a material of the capacitor insulating film 13a, for example, a zirconium oxide film or the like can be used.
Next, a capacitor upper electrode 13c is formed on the capacitor insulating film 13a. As a material of the capacitor upper electrode 17c, for example, a titanium nitride film or the like can be used.
Then, the capacitor upper electrode 13c is patterned into a predetermined shape, thereby forming the capacitor 13 including the capacitor lower electrode 13b, the capacitor insulating film 13a, and the capacitor upper electrode 13c.

<Other forming processes>
In the method for manufacturing the semiconductor device A according to the present embodiment, as shown in FIGS. 1A to 1C and FIGS. 2A and 2B, the capacitor 13 is further formed on the above-described procedure. A method of forming the fourth interlayer insulating film 16 on the capacitor upper electrode 13c can be employed. As the material of the fourth interlayer insulating film 16, a conventionally known insulating material can be used as described above.
Next, in the present embodiment, peripheral contacts (not shown) connected to the word line 10 (gate electrode 10A), the lower diffusion layer 5 and the like are formed so as to penetrate the interlayer insulating films 16, 15, 11 and the like.

Next, in the present embodiment, the peripheral wiring 17 composed of the base layer 17a and the main wiring layer 17b is formed, which is connected to the peripheral contact (not shown) described above. At this time, as the base layer 17a and the main wiring layer 17b, a conventionally known conductive material used in this field can be used, and it is formed by forming a film using a method such as a CVD method and then patterning it. Is possible.
In the present embodiment, a method of forming an upper interlayer film, a via hole, various wirings, a passivation film, and the like can be appropriately employed as necessary.
The semiconductor device A of this embodiment can be manufactured through the above steps.

  The semiconductor device A of the present invention includes a columnar semiconductor (pillar portion 1C) having a square plane, a bit line conductive film pattern (bit line 6) formed in contact with each of two opposing side surfaces of the columnar semiconductor, Lower diffusion layer 5 provided in the columnar semiconductor adjacent to the bit line conductive film pattern, gate electrode 10A (word line 10) provided on the side surface of the columnar semiconductor above the bit line conductive pattern via a gate insulating film, columnar The semiconductor device includes an upper diffusion layer 14 provided on the semiconductor and a storage element (capacitor structure) connected to the upper diffusion layer 14. That is, a vertical type MOS transistor having the lower diffusion layer 5 and the upper diffusion layer 14 as the source / drain and including the gate electrode 10A (word line 10) is formed. The vertical MOS transistor is a switching transistor, the bit line 6 and the lower diffusion layer 5 are combined as a bit wiring, a gate electrode 10A is included in the word line 10, and a memory element including a storage element is also provided. Composed.

  Further, in the method of manufacturing the semiconductor device A according to the present invention, a plurality of grooves are formed in the semiconductor substrate (silicon substrate 1), and semiconductor fins (fin portions 1G) are formed between the adjacent first grooves 1D. A step of embedding the first insulating film 31 in the bottom of the first groove 1D, a step of forming a sidewall-like second insulating film 32 on the side surface of the first groove 1D existing above the upper surface of the first insulating film 31, and The step of removing the first insulating film 31 and the step of forming the bit line 6 in the first groove 1D are performed, and the conductive material forming the bit line 6 is anisotropically etched. A method is employed in which the conductive film pattern of the bit line 6 is left to be formed below. By adopting such a method, the conductive film pattern of the bit line 6 separated from each other is formed on each of the two side surfaces facing each other in the first groove 1D, and each of the two side surfaces of the fin portion 1G is formed. The bit line 6 can be formed.

  In the present invention, when the bit line conductive film pattern is formed on the side surface of the fin portion 1G, the side wall-like second insulating film 32 formed on the side surface of the first groove 1D is used as a mask to conduct the bit line 6 below. A method of forming a film pattern is employed. As a result, a fine bit line pattern can be formed without using a high-precision lithography technique or the like, so that both reduction in production cost and miniaturization of the bit line can be realized. Therefore, it is possible to manufacture a semiconductor device with a good yield without problems such as misalignment that occurs when the lithography technique is used.

Further, since the height of the bit line 6 can be formed depending on the height of the first insulating film 31 embedded in the bottom of the first groove, it is stable without being affected by the etching amount. It can be formed at a height.
Further, the bit line 6 is made of a conductive material containing impurities, the impurities are diffused from the bit line 6 to the fin portion 1G, and the lower diffusion layer 5 is formed in the fin portion 1G. By using it as a bit wiring together with the bit line 6, the resistance of the bit line can be reduced.
Furthermore, by sharing the lower diffusion layer 5 as the lower source / drain region of the vertical MOS transistor, the lower source / drain region process can be reduced, and the productivity can be improved and the manufacturing cost can be reduced. Have.

[Second Embodiment]
The method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 30 to 35 as appropriate. 30 to 35 are process diagrams schematically showing a semiconductor device manufacturing apparatus according to a second embodiment to which the present invention is applied.
In the present embodiment, the same reference numerals are given to the procedures, semiconductor structures, etc. common to the manufacturing method of the semiconductor device A of the first embodiment, and detailed description thereof is omitted.

  As illustrated in FIGS. 30A and 30B, the method for manufacturing a semiconductor device according to the present embodiment first includes a step of filling the first groove 11 </ b> D with an impurity-containing material 61. Next, as shown in FIGS. 31A and 31B, the lower diffusion layer 50 is formed by diffusing impurities contained in the impurity-containing material 61 so as to cover the bottom surface from the side surface of the first groove 11D. A process is provided. Next, as shown in FIGS. 32A and 32B, after removing the impurity-containing material 61 from the first groove 11D, FIGS. 33A and 33B and FIGS. 34A and 34B are used. As shown, the bit line 60 is formed by filling and etching the first groove 11D with a conductive material. In the present embodiment, as shown in FIGS. 35A and 35B, after forming the lower diffusion layer 50 and the bit line 60, the digging portion 11F communicated with the first groove 11D is formed in the digging step. It differs from the said 1st Embodiment by the point which employ | adopts the method of dividing | segmenting the lower diffusion layer 50 along each side surface of 1st groove | channel 11D by forming.

In the method described in the first embodiment, a conductive material containing impurities is used as the material of the bit line, and then a heat treatment is applied to this to diffuse the impurities from the bit line, thereby forming a lower diffusion layer. Adopted. For this reason, a doped silicon film or the like is used as the bit line because it is necessary to use a material containing impurities at a high concentration. However, since materials such as doped silicon films have a relatively high electrical resistance compared to metal materials, the use of such materials for bit lines increases the electrical resistance of the bit lines, resulting in memory cell data. In some cases, there are restrictions on the rewrite time, read time, and the like.
For this reason, in the second embodiment, it is possible to avoid the use of a conductive material containing a large amount of impurities for the material of the bit line, and a method that can widen the selection of the material is adopted.

Further, in the method described in the first embodiment, since the conductive film pattern of the bit line adopts a structure formed on the side wall in the first groove, two bit lines are within the width of the first groove. The conductive film pattern and an isolation region for separating the conductive film patterns of the adjacent bit lines must be formed. For this reason, there is a limitation that the conductive film pattern of the bit line must be formed in the remaining region in which the width of the isolation region is secured within the width of the first groove.
On the other hand, the second embodiment has an effect that the width of the conductive film pattern of the bit line that can be formed in the first groove can be made larger than that of the first embodiment.

Below, the manufacturing method of the semiconductor device of this embodiment is demonstrated.
In the present embodiment, first, after forming the mask insulating film 20 on the surface of the silicon substrate 10 using the same procedure as in the first embodiment, the fin 10G is formed by forming the first groove 10D. Further, a sidewall-like second insulating film 132 is formed inside the first trench 10D. In this embodiment, as shown in FIGS. 30A and 30B, the impurity-containing material 61 is filled so as to fill the first trench 10 </ b> D and cover the mask insulating film 20. At this time, a phosphorus-doped silicon film or the like can be used as the impurity-containing material 61 and can be formed by a conventionally known method.

  Next, as shown in FIGS. 31 (a) and 31 (b), in the lower diffusion step, the impurity-containing material is subjected to heat treatment so that the impurity phosphorus contained in this material is removed from the adjacent silicon substrate 10. The lower diffusion layer 50 is formed by diffusing in the base portion 10B. The lower diffusion layer 50 is formed by diffusing into the silicon substrate 10 from the side surface of the first groove 10D. In the example shown in FIGS. 31A and 31B, the lower diffusion layers 50 of the adjacent first grooves 10D are formed so as not to be joined under the fin portion 10G. . Further, the adjacent lower diffusion layers 50 can be formed so as to be coupled to each other, and in this case, it is possible to configure the FBC (floating body cell) structure as described above.

  Next, as shown in FIGS. 32A and 32B, the impurity-containing material 61 formed so as to fill the first trench 10D and cover the mask insulating film 32 is selectively removed by etching. As an etching method at this time, for example, isotropic etching conditions can be adopted. When silicon is used as the impurity-containing material as in this embodiment, for example, a wet etching method using hydrofluoric acid as a chemical solution. Can be used. In the etching process, the impurity-containing material 61 can be removed by etching and the surface portion of the silicon substrate 10 in contact with the impurity-containing material 61 under the second insulating film 132 can also be etched. In the example shown in FIG. 32B, the length of the etched portion of the silicon substrate 10 at this time is represented as w22 for convenience. When the silicon substrate 10 is etched, the lower diffusion layer 50 is scraped off, but the lower diffusion layer 50 is etched so as to remain with a predetermined thickness. As described above, the impurity-containing material 61 and a part of the silicon substrate 10 are removed by etching, so that the space portion 133c near the bottom of the first groove 10D is enlarged as illustrated.

  Further, the etching process of the above procedure secures a space 133d having a predetermined height from the lower end of the second insulating film 132 to the bottom of the first groove 10D. In the example shown in FIG. 32B, a portion sandwiched between the second insulating films 132 is represented as a space portion 133a, and a portion formed in the first groove 10D is represented as a space portion 133b.

  Next, as shown in FIGS. 33A and 33B, a material forming the bit line (buried wiring) 60 is formed so as to cover the inner surface of the space portion 133c. As a film forming method at this time, a method having excellent coverage is preferable, and a CVD method, an ALD method, or the like can be employed. Further, as the material of the bit line 60, for example, a refractory metal material, a doped silicon film, or the like can be used. Among these, when a refractory metal material is used for the bit line 60, for example, a laminated film of a titanium film and a titanium nitride film, a laminated film of a titanium film, a titanium nitride film, and a tungsten film can be used. By using the refractory metal film described above for the bit line 60, the bit line resistance can be reduced as compared with the case of using a doped silicon film, and the memory cell can be miniaturized, data can be rewritten, and read. Can be speeded up. The film thickness of the bit line 60 is desirably formed so as to close the space 133d, and can be set to a thickness of, for example, about 50 nm.

  Next, as shown in FIGS. 34A and 34B, the bit line 60 is etched to expose the mask insulating film 20. Subsequently, the bit line 60 is etched using anisotropic etching conditions, the upper surface of the bit line 60 is lowered to expose the bottom of the space portion 133c, and the lower diffusion layer 50 on the side surface of the space portion 133c. The bit line 60 is left along.

  By the etching process as described above, the bit line 60 is formed so as to be embedded in the space portion 133d secured so as to face each other in the first groove 10D. The bit line 60 constitutes a wiring extending in the X direction (bit line extending direction). The bit line 60 has a shape in which the bit line 60 is formed on each lower portion of both side surfaces, that is, on each side surface of the base portion 10B, as viewed from the fin portion 10C. These bit lines 60 function as bit lines of memory cells in a vertical structure MOS transistor.

  As described in the first embodiment (see FIGS. 5A and 5B), the height of the bit line 60 in the vertical direction of the substrate is the height of the first groove 10D from the lower end of the second insulating film sidewall 132. It can be adjusted by controlling the height d3 to the upper end. In the etching process for forming the conductive film pattern of the bit line 60, etching is performed using the second insulating film 132 formed on the bit line 60 as a mask, so that the etching amount for forming the bit line conductive pattern is increased. Accordingly, the height of the bit line 60 does not change and can be formed in a stable shape. Thereby, in the bit line formation step, the etching amount can be determined without considering the height variation of the bit line 60. In addition, during the etching, it is possible to suppress various deformations such as the upper end 60a of the bit line 60 being hit by etching and the upper end shape being rounded or formed in an inclined shape.

  The lateral width of the bit line 60 is generally formed by a length that is a combination of the above-described t4 and t22. However, the bit line 60 can be formed wider than the first embodiment by the amount corresponding to t22. By performing the etching of the bit line 60, a space 134 connected to the bottom of the first groove 10D is secured between each of the second insulating films 132 and between each of the bit lines 60.

Next, in the present embodiment, as shown in FIGS. 35A and 35B, following the above steps, the bottom of the first groove 10D in the exposed silicon substrate 10 is etched, and the silicon substrate 10 is formed. Further, a digging step is provided in which the digging portion 10F is formed by digging to separate the lower diffusion layer 50 into both side surfaces of the base groove 10D. At this time, the depth of the dug portion 10F is set to such a depth that the lower diffusion layers 50 formed on the left and right sides of the first groove 10D can be electrically separated. By such a digging process, the space 134 is formed deeper by the amount of the digging portion 10F.
Since the etching of the silicon substrate 10 in the digging process is performed in a state where the second insulating film 132 is formed on the bit line 6, the bit by etching is similar to the etching when forming the bit line 60. Deformation of the upper end 60a of the line 60 can be prevented.

  Thereafter, the semiconductor device can be manufactured by performing the same steps as the pillar portion forming step and thereafter in the first embodiment.

  In this embodiment, in the etching process shown in FIGS. 32A and 32B, an example in which a certain amount of the side surface of the first groove 10D located below the second insulating film 132 is etched is shown. However, the present invention is not limited to this, and conditions under which the silicon substrate 10 is not etched may be employed. In this case, w22 shown in FIG. 32B is substantially zero, and the width that the bit line 60 can be formed is equivalent to the bit line 6 of the first embodiment.

  According to the method for manufacturing a semiconductor device of the present invention as described above, by adopting the above method, the bit line 6 (embedded wiring) having a fine pattern can be formed without using a high-precision lithography technique or the like. Since it can be formed while preventing misalignment and the like, the semiconductor device A can be manufactured with high productivity and high yield. Further, the height of the bit line 6 on the side surface of the fin portion 1G (10G) is formed while being limited by the height of the lower end of the second insulating film 32 (132) formed on the side surface of the first groove 1D (10D). Therefore, it can be formed at a stable height without being affected by the etching amount in the etching process.

  Further, by using a conductive material containing impurities for the bit line 6 and adopting a method of diffusing the impurities contained in the bit line 6 into the fin portion 1G of the silicon substrate 1, the process can be simplified and the production can be performed. As a result, the manufacturing cost can be reduced. Further, when the lower diffusion layer 5 is shared as the lower source / drain region in the vertical type MOS transistor, the lower source / drain region forming step can be omitted, so that the productivity can be further improved. .

  Further, according to the semiconductor device A of the present invention, the lower diffusion layer 5 is formed by diffusing impurities contained in the conductive material forming the bit line 6, and the base portion 1B below the pillar portion 1C. In FIG. 2, the bit line 6 is formed in close contact with the bit line 6 and can be used as a bit wiring. As a result, the resistance of the bit line can be reduced. In particular, even when the bit line 6 is configured with a fine pattern, the resistance of the bit line 6 can be significantly reduced. Can be realized.

  Alternatively, in the present invention, as described in the second embodiment, before the bit line conductive pattern is formed, the first groove 10D is filled with the impurity-containing material 61, and then the impurity-containing material 61 is subjected to heat treatment. It is also possible to adopt a method of forming the bit line 60 after the impurities are diffused into the base portion 10B of the silicon substrate 10 and the lower diffusion layer 50 is formed in advance.

A ... Semiconductor device, 1, 10 ... Silicon substrate, 1A, 11A ... Base part, 1B, 11B ... Base part, 1C, 11C ... Pillar part, 1D, 11D ... First groove, 1E ... Second groove, 1F ... Excavation part, 1G, 10G ... fin part, 1a ... side face (base part), 1b ... side face (pillar part), 1c ... top face (pillar part), 2, 20 ... mask insulating film, 31 ... first insulating film , 32, 132 ... second insulating film, 5, 50 ... lower diffusion layer, 6, 60 ... bit line (buried wiring), 6a, 60a ... upper end (bit line), 61 ... impurity-containing material, 7 ... first interlayer Insulating film (interlayer insulating film), 11 ... second interlayer insulating film (interlayer insulating film), 15 ... third interlayer insulating film (interlayer insulating film), 16 ... fourth interlayer insulating film (interlayer insulating film), 10 ... word Line (gate wiring), 10A ... gate electrode, 12 ... contact, 13 ... capacitor, 1 ... upper diffusion layer,

Claims (13)

Forming a plurality of fin portions by removing at least a portion of the silicon substrate to form a first groove;
Forming a buried wiring under the plurality of fin portions by forming a conductive material containing impurities on the wall surface of the first groove;
Forming a lower diffusion layer by performing heat treatment on the buried wiring to diffuse impurities contained in the buried wiring into the lower portions of the plurality of fin portions;
Forming a pillar portion by dividing the fin portion into a plurality of portions by forming a second groove having a bottom surface at a position higher than the embedded wiring in the fin portion;
Forming a gate wiring including a gate electrode by forming a conductive material including an impurity on a side surface of the second groove;
And a step of forming an upper diffusion layer by implanting impurities into the upper surface of the pillar portion. A mask insulating film and a first resist mask are sequentially formed on the silicon substrate, and then the silicon substrate and the mask insulating film are etched using the first resist mask, whereby a first embedded wiring line is extended in the extending direction. Forming a plurality of fin portions by forming one groove, and then removing the first resist mask;
After the first trench is filled with an insulating material, the upper portion of the insulating material is etched away to form a first insulating film at the bottom of the first trench, and then the upper surface of the first insulating film, the first After forming a thin film made of an insulating material so as to cover the side surface of one groove and the mask insulating film, the upper surface of the first insulating film and the thin film on the mask insulating film are etched back, thereby Forming an insulating film formed in a sidewall shape at the upper part of the side surface, and then etching away the first insulating film filled in the lower part of the first groove;
After the first groove is filled with a conductive material containing impurities, a part of the conductive material is removed by etching, and the bottom surface of the first groove is exposed, while the second insulating film on the side surface of the first groove is exposed. Embedded wiring forming step of forming embedded wiring below the plurality of fin portions by leaving the conductive material at a lower position,
By performing a heat treatment on the buried wiring, an impurity contained in the buried wiring is diffused below the plurality of fin portions, thereby forming a lower diffusion layer in a region of the silicon substrate in contact with the buried wiring. Process,
The fin portion is etched in the extending direction of a gate wiring planned line intersecting the embedded wiring, and a second groove having a bottom surface at a position higher than the embedded wiring is formed, thereby dividing the fin portion into a plurality of portions. And a pillar part forming step of forming a plurality of pillar parts,
After forming a thin film made of a conductive material containing impurities on the side surface and bottom surface of the second groove, the thin film formed on the bottom surface is removed by etching, and the upper portion of the thin film formed on the side surface is further removed. A gate wiring forming step of forming a gate wiring including a gate electrode on a side surface of the second groove by etching away;
An upper diffusion step of forming an upper diffusion layer by exposing the upper surface of the pillar portion by etching away the mask insulating film and implanting impurities into the upper surface. .   Furthermore, before or after the lower diffusion step, a digging step for forming a digging portion communicating with the first groove by etching the bottom surface of the first groove is provided. Item 3. A method for manufacturing a semiconductor device according to Item 2.   In the lower diffusion step, impurities contained in the buried wiring are diffused so as to cover the bottom surface from the side surface of the first groove to form a lower diffusion layer, and then communicated with the first groove in the digging step. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the lower diffusion layer is divided along each side surface of the first groove by forming a digging portion.   The semiconductor device manufacturing method according to claim 2, further comprising a step of forming a contact conductive film by depositing a conductive material on the upper diffusion layer. Method.   After the lower diffusion step, there is provided a step of filling the first groove with an insulating material to form an interlayer insulating film, and further, after the gate wiring forming step, filling the second groove with an insulating material. 6. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming an interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 2, further comprising a capacitor forming step of forming a capacitor on the contact conductive film. Forming a plurality of fin portions by removing at least a portion of the silicon substrate to form a first groove;
Filling the first groove with an impurity-containing material;
Forming a lower diffusion layer by performing a heat treatment on the impurity-containing material to diffuse impurities contained in the impurity-containing material into the lower portions of the plurality of fin portions;
Removing the impurity-containing material from the inside of the first groove, and then forming a conductive material on the wall surface of the first groove, thereby forming embedded wirings below the plurality of fin portions;
Forming a pillar portion by dividing the fin portion into a plurality of portions by forming a second groove having a bottom surface at a position higher than the embedded wiring in the fin portion;
Forming a gate wiring including a gate electrode by forming a conductive material including an impurity on a side surface of the second groove;
And a step of forming an upper diffusion layer by implanting impurities into the upper surface of the pillar portion. At least a silicon substrate including a pillar-shaped pillar portion erected on the base portion;
Embedded wiring made of a conductive material containing impurities, provided so as to cover the side surface of the base portion;
A lower diffusion layer formed in the base portion in contact with the buried wiring and formed by diffusing impurities contained in the conductive material forming the buried wiring;
A gate electrode that is provided on the side surface of the pillar portion above the embedded wiring via a first insulating film, made of a conductive material containing an impurity, and forming a part of the gate wiring;
A semiconductor device comprising: an upper diffusion layer formed on an upper surface of the pillar portion and doped with impurities.   The semiconductor device according to claim 9, wherein the silicon substrate including the pillar portion and the base portion is made of a silicon single crystal.   11. The semiconductor device according to claim 9, wherein the embedded wiring is made of a conductive material containing an impurity having a conductivity type opposite to that of the silicon substrate.   The semiconductor device according to claim 9, further comprising a contact conductive film provided on the upper diffusion layer, and a capacitor provided on the contact conductive film. The buried wiring layer and the lower diffusion layer form a bit line, the gate wiring including the gate electrode forms a word line, and the lower diffusion layer serves as a lower source / drain region. 13. The semiconductor device according to claim 9, wherein a MOS transistor is formed.

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