JP2013161151A - Memory device and method for avoiding data garbling - Google Patents

Abstract

A memory device that can easily avoid data corruption that is a problem with unauthorized access with a small amount of hardware, and a data corruption avoidance method using memory patrol.
A patrol flag 15 is provided in a status 14 of a cache 13 so that the data registered by the patrol request can be recognized. In addition, when a normal function for writing back to the spare memory 36 from the cache 13 is diverted and a normal request is illegally issued to the data registered by the patrol request in the cache 13, before the data is used The data was written back to the spare memory 36. As a result, it is possible to easily identify and process an unauthorized access in which a normal request is issued to the spare memory 36, and to avoid the problem of garbled data.
[Selection] Figure 1

Description

  The present invention relates to a memory device and a method for avoiding data corruption by memory patrol.

  If a normal request such as a read request or a write request issued from the processor is issued to the spare memory, it will be processed as unauthorized access, but the data is registered in the cache by the patrol function. If issued at the same timing, the normal request may be handled normally. If such a case occurs, there is a possibility of garbled data.

  With the patrol function described above, the memory space of the entire main memory is read for a certain period, and when a correctable error is detected by ECC (Error Check and Correct memory), the data is corrected and normal data is written back. It is a function. The data in the memory is stored with a correctable code such as ECC, and the patrol function corrects the data in the memory by periodically accessing the data before it becomes a bit that cannot be corrected. Correct as many bits as possible and restore normal data.

  Here, the unauthorized access of the normal request will be described with reference to the memory device shown in FIG. The memory device 29 shown in FIG. 3 includes a memory patrol issuing unit 31, a request issuing unit 32, a cache 33, a memory control 35, and a spare memory 36. In the cache 33, status 34 information indicating whether or not the requested data is registered is recorded. When a patrol request is issued from the memory patrol issuing unit 31 to the cache 33, the status 34 for the address indicated by the patrol request in the cache 33 is indexed. If the target data is registered in the cache 33, the patrol request processing is completed. If the target data is not registered, data is read from the patrol target spare memory 36 via the memory control 35. Is registered in the cache 33. After a memory patrol operation, when a normal request is issued by mistake from the request issuing unit 32 to the spare memory 36, the normal request hits data registered by the patrol request in the cache 33, and the request is not recognized as an unauthorized access A normal reply is returned to the issuing unit 32 and processed normally.

  The memory control 35 has a function of detecting unauthorized access when a normal request is issued to the spare memory 36. However, it is normal for the memory control 35 to have data registered in the cache 33 by a patrol request. Unauthorized access is not detected because the request is not issued. That is, when the data that was the target of patrol execution is registered in the cache 33, if a normal request is erroneously issued for the same data as the patrol in the spare memory space, the data in the cache 33 is acquired. A normal reply is returned to the request issuing unit 32. As a result, an illegal operation in which a normal request is issued to the spare memory space is overlooked. When this occurs, the request issuing unit 32 may perform processing using data that has not been corrected by the patrol function, which may cause data corruption.

  The memory device 40 shown in FIG. 4 can detect an unauthorized access of a normal request. In the figure, a range register 45 that holds the range of the spare memory space in the cache 43, and an error transmission for returning an error reply from the cache 43 to the request issuing unit 32 when an unauthorized access is detected in the cache 43. Circuit 46. The range register 45 is provided so that an illegal access can be detected in the cache 43 when a normal request is issued by mistake from the request issuing unit 32 to an address within the range of the spare memory space.

  Even if a normal request is erroneously issued from the request issuing unit 32 to the spare memory space by the range register 45 and the error transmission circuit 46, the range register 45 in which the address of the spare memory space provided in the cache 43 is set is hit. Therefore, unauthorized access is detected in the cache 43. When unauthorized access is detected, an error reply is returned to the request issuing unit 42 through the error transmission circuit 46. Data corruption is avoided by detecting an illegal operation in which a normal request is issued to the spare memory space.

  As an example of using a memory patrol method as a method of correcting a soft error, for example, there are methods described in Patent Documents 1 and 2. In the memory patrol method described in Patent Document 1, for example, every 8-byte data is guaranteed with an ECC code of SEC-DED (1-bit error correction / 2-bit error detection). When the memory patrol is activated, a series of operations of reading data from the RAMBLE → checking and correcting the ECC code of the read data → generating a check bit (data guarantee bit) → writing back to the RAM is repeated. In the memory patrol method described in Patent Document 2, when the patrol main control unit starts patrol, the read command generation unit continuously outputs the read commands for the patrol unit while counting up the address counter. This read command is transmitted to the memory unit through the memory control unit, and read data is taken out. The read data is inspected by the ECC circuit, and if there is no correctable error, the patrol process is terminated. If there is a correctable error, the correction command generation unit is activated after the read command is completed. In the correction instruction generation unit, first, the address counter is rewound to the head address in the patrol unit, and then the correction instruction for the patrol unit is executed while counting up.

JP 2009-116398 A JP 2000-010871 A

  Here, the circuit configuration shown in FIG. 4 can avoid the problem of unauthorized access, but the amount of hardware to be added increases and the control of the hardware becomes complicated. There is a problem that data corruption, which is a problem with unauthorized access, cannot be avoided easily by the amount of wear.

  In Patent Documents 1 and 2 described above, there is no description that can solve the above problem.

  An object of the present invention is to provide a memory device and a method for avoiding data corruption by memory patrol that can solve the above-described problems.

  In the memory device of the present invention, a request issuing unit that issues a normal request, a memory patrol issuing unit that issues a patrol request for data for check and correction, a spare memory, and data are registered in a cache. And a cache having a patrol flag for identifying whether the data in the cache is data registered by the patrol request or data registered by the normal request.

  The present invention can easily avoid data corruption that is a problem with unauthorized access with a small amount of hardware.

1 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention. FIG. 1 is a sequence diagram for explaining the operation of the memory device of FIG. A block diagram showing a schematic configuration of a memory device for explaining an unauthorized access of a normal request A block diagram showing a schematic configuration of a memory device capable of detecting unauthorized access of normal requests

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments for carrying out the invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention. In the figure, the same reference numerals are given to the portions common to FIG. 1 described above. The memory device 1 according to the present embodiment includes a memory patrol issuing unit 31, a request issuing unit 32, a cache 13, a memory control 35, and a spare memory 36.

  The memory patrol issuing unit 31 issues a patrol request for data for check and correction purposes. Here, the patrol request issued from the memory patrol issuing unit 31 of the present embodiment is a request for updating data with errors to a normal value. The request issuing unit 32 issues a request such as a normal read or write.

  The cache 13 records a status 14 indicating that data is registered in the cache 13 for each address. Each of the caches 13 indicates whether the data in the cache 13 is registered based on a patrol request issued by the memory patrol issuing unit 31 or registered based on a normal request issued by the request issuing unit 32. A patrol flag 15 for identifying the address is recorded. Further, in the cache 13, when a normal request is issued from the request issuing unit 32 to the data registered by the patrol request issued by the memory patrol issuing unit 31, the data sweeping function (existing The data write-back unit 16 is also provided which writes back the data in the cache 13 (data registered by the patrol request) to the spare memory 36 by using the function normally possessed by the cache. The data write-back unit 16 is a function that has been conventionally provided, although not shown in FIG.

  When the patrol request issued from the memory patrol issuing unit 31 reaches the cache 13, the control unit in the cache 13 indexes the status 14. The control unit in the cache 13 ends the patrol request operation when there is data to be accessed in the cache 13. On the other hand, when there is no data to be accessed in the cache 13, the control unit in the cache 13 issues a read request from the cache 13 to the spare memory 36.

  The memory control 35 has a function of detecting unauthorized access in advance when a normal request is issued to the spare memory 36. However, since the received request is a read request to the spare memory 36 by a patrol request, it is determined that there is no unauthorized access and is processed. Then, the memory control 35 transfers a read request to the spare memory 36 by the patrol request to the spare memory. As a result, when the read data is returned from the spare memory 36, the address indicated by the read data at the time of cache registration of the read data. The patrol flag 15 for is set and registered in the cache 13. Thereby, it becomes possible to identify that the data in the cache 13 is registered by the patrol request. After that, when a normal request is issued from the request issuing unit 32, the corrected data is written back to the spare memory 36, and the operation as the patrol is completed.

  FIG. 2 is a sequence diagram for explaining the operation of the memory device 1 according to the present embodiment. In the figure, first, data read from the spare memory 36 is registered in the cache 13 based on the patrol request 40 issued from the memory patrol issuing unit 31, and based on the patrol request 40. It is assumed that the patrol flag 15 is registered at the same time for the registered data address. A normal request 41 to the space of the spare memory 36 that should not be issued is issued from the request issuing unit 32 due to a processing failure or the like, and hits the data in which the patrol flag 15 is registered in the cache 13 If so, the control unit of the cache 13 temporarily waits for the normal request 41 (42). Then, while the normal request 41 is waiting, the control unit of the cache 13 writes the data to be referred to by the normal request 41 back to the spare memory 36 via the memory control 35 by the forced sweep process (43 ).

  After that, the control unit of the cache 13 executes the waiting normal request 41 and indexes the status of the address of the reference data indicated by the normal request 41, so that the data that the normal request 41 has received is stored in the cache 13. Since it does not exist, it is determined as a miss hit (44). As a result, the control unit of the cache 13 issues a normal request 45 for retrieving data to the spare memory 36 via the memory control 35. Then, since the memory control 35 has a function of recognizing an unauthorized access when a normal request 45 is issued to the spare memory space, the memory control 35 recognizes the normal request 45 as an unauthorized access and returns an error reply 47 to the cache 13. To do. Then, the control unit of the cache 13 returns the error reply 47 to the request issuing unit 32.

  As described above, according to the memory device 1 according to the present embodiment, the status 14 and the patrol flag 15 for each address are recorded in the cache 13 so that the data registered by the patrol request can be recognized. Therefore, it can be avoided that the normal request mistakenly uses the data registered by the patrol request. In addition, when a normal request is diverted to the data registered by the patrol request in the cache 13 by using the normal function of writing back from the cache 13 to the spare memory 36, the normal request is made to wait, The data required in the request is written back to the spare memory 36 before being used. At this time, the cache 13 returns the error reply issued by the function of the memory control 35 to the request issuing unit 32. As a result, an illegal access in which a normal request is issued to the spare memory 36 by the error processing that the memory control 35 has already provided without newly providing a circuit for performing error processing such as returning an error reply in the cache 13. Can be easily identified and error-processed, and the problem of garbled data can be avoided.

  In the memory device 1 according to the present embodiment, a failure of the spare memory 36 may be detected in advance by issuing a patrol request to the spare memory space. By doing so, data corruption due to the failure of the spare memory 36 can be prevented in advance.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1) A request issuing unit that issues a normal request;
A memory patrol issuing unit that issues a patrol request for data for check and correction purposes;
Spare memory,
A status indicating that data is registered in the cache, and a patrol flag for identifying whether the data in the cache is registered by the patrol request or data registered by the normal request Cache,
A memory device.

  (Supplementary Note 2) When a normal request is issued from the request issuing unit to the data registered by the patrol request issued by the memory patrol issuing unit, the data sweep function of the cache is used, The memory device according to appendix 1, further comprising a data write-back unit that writes data registered by the patrol request in the cache to the spare memory.

  (Supplementary note 3) The memory device according to supplementary note 2, wherein the data write-back unit is provided in the cache.

  (Supplementary Note 4) A memory control is provided for performing data control between the cache and the spare memory and returning an error reply to the request issuing unit through the cache when the normal request is recognized as an unauthorized access. The memory device according to any one of appendices 1 to 3.

  (Supplementary Note 5) When data is registered in the cache, it is identified whether the data in the cache is data registered by the memory patrol function or data registered by a normal request, and the data registered by the patrol function On the other hand, when a normal request is issued, a method for avoiding garbled data by writing data registered by the patrol function in the cache to the spare memory using a data sweeping function of the cache.

  (Additional remark 6) The data corruption avoidance method of Additional remark 5 which returns an error reply to the request issuing part which issues a normal request, when the said normal request is unauthorized access.

  (Supplementary note 7) The data corruption avoidance method according to supplementary note 5 or appendix 6, wherein a failure of the spare memory is detected by issuing a patrol request to the spare memory space.

  The present invention can be applied to a semiconductor element capable of data writing / reading such as a RAM (Randum Access Memory).

1 Memory Device 13 Cache 14 Status 15 Patrol Flag 16 Data Write Back Unit 31 Memory Patrol Issuing Unit 32 Request Issuing Unit 35 Memory Control 36 Memory

Claims (7)

A request issuing unit for issuing normal requests;
A memory patrol issuing unit that issues a patrol request for data for check and correction purposes;
Spare memory,
A status indicating that data is registered in the cache, and a patrol flag for identifying whether the data in the cache is registered by the patrol request or data registered by the normal request Cache,
A memory device.   When a normal request is issued from the request issuing unit to the data registered by the patrol request issued by the memory patrol issuing unit, the data in the cache is used by using the data sweep function. The memory device according to claim 1, further comprising a data write-back unit that writes back data registered by a patrol request to the spare memory.   The memory device according to claim 2, wherein the data write-back unit is provided in the cache.   The memory control for performing data control between the cache and the spare memory and returning an error reply to the request issuing unit through the cache when the normal request is recognized as an unauthorized access. The memory device according to claim 3.   When data is registered in the cache, whether the data in the cache is registered by the memory patrol function or the data registered by the normal request, and for the data registered by the patrol function, A method for avoiding garbled data in which when a normal request is issued, data registered by a patrol function in the cache is written back to a spare memory by using a data sweeping function of the cache.   The data corruption avoiding method according to claim 5, wherein when the normal request is unauthorized access, an error reply is returned to a request issuing unit that issues the normal request.   The data corruption avoiding method according to claim 5 or 6, wherein a failure of the spare memory is detected by issuing a patrol request to the spare memory space.

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