JP2013160567A - Capacitive pressure sensor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitive pressure sensor capable of reducing variation in detection accuracy, and capable of achieving cost reduction and miniaturization by disposing a reference pressure chamber inside one semiconductor substrate.SOLUTION: A capacitive pressure sensor 1 includes: a SOI substrate 2 which includes a structure where an insulating layer 203 is sandwiched between a lower semiconductor layer 201 and an upper semiconductor layer 202, and inside which a reference pressure chamber 4 partitioned by digging the lower semiconductor layer 201 is formed; a diaphragm 5 which is formed on the upper semiconductor layer 202, and inside which an annular peripheral through hole 6 partitioning an upper electrode 10 composed of a part of the diaphragm 5 and a plurality of central through holes 7 are formed; a central insulating layer 9 which is disposed in each central through hole 7 and blocks the central through hole 7; and a peripheral insulating layer 8 which is disposed in the peripheral through hole 6 and blocks the peripheral through hole 6, and which electrically separates the upper electrode 10 from a frame part 11 of the SOI substrate 2.

Description

  The present invention relates to a capacitive pressure sensor and a method for manufacturing the same.

In recent years, the use of pressure sensors that enable sensing in the height direction is increasing due to the spread of smartphones and the like. As a pressure sensor, a piezoresistive pressure sensor that detects a change amount of a resistance value of a piezoresistive element as a change amount of pressure has been proposed.
For example, Patent Document 1 uses a base substrate, a cap substrate that forms a recess and is bonded to the base substrate to partition a space between the recess and the base substrate, and a part of the base substrate. A pressure sensor including a membrane formed in a space and an impurity diffusion region functioning as a pressure sensor element formed in the membrane is disclosed. In this pressure sensor, the membrane is displaced according to the applied pressure, and the pressure is detected by measuring a change in the resistance value of the impurity diffusion region accompanying the displacement.

JP 2011-146687 A

However, the piezoresistive element tends to depend on changes in the ambient temperature, and variations in detection accuracy tend to occur in situations where the ambient temperature varies in various ways. Therefore, in a pressure sensor using a piezoresistive element, correction is indispensable when detecting pressure.
Further, a sensor having a three-dimensional structure in which at least two substrates are bonded together like the pressure sensor of Patent Document 1 has a problem that the cost is high and the bulk of the pressure sensor is increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a capacitance type pressure sensor that can reduce variations in detection accuracy by providing a reference pressure chamber inside one semiconductor substrate, and can further reduce the cost and size. Is to provide.
Another object of the present invention is to provide a manufacturing method capable of easily manufacturing a capacitance type pressure sensor that can reduce variations in detection accuracy and can be further reduced in cost and size. is there.

  In order to achieve the above object, a capacitive pressure sensor according to the present invention has a structure in which an insulating layer is sandwiched between a lower semiconductor layer and an upper semiconductor layer, and the lower semiconductor layer is dug into the section. A semiconductor substrate having a reference pressure chamber formed therein, and a diaphragm selectively formed in the upper semiconductor layer of the semiconductor substrate, wherein a space between the surface of the upper semiconductor layer and the reference pressure chamber is formed An annular peripheral through hole that penetrates and defines an upper electrode made of a part of the diaphragm inside, and a plurality of central penetrations that penetrate between the surface of the upper semiconductor layer and the reference pressure chamber in the upper electrode A diaphragm in which a hole is formed, a peripheral insulating layer that is provided in the peripheral through hole, closes the peripheral through hole, and electrically isolates the upper electrode from other parts of the upper semiconductor layer; Each of the above Provided in the through hole, and a central insulating layer for closing the central opening (claim 1).

  According to this configuration, since the upper electrode is electrically separated from the other part of the upper semiconductor layer by the peripheral insulating layer, the upper electrode (upper electrode) and the lower part that face each other with the reference pressure chamber (cavity) interposed therebetween A capacitor structure can be formed by the semiconductor layer (lower electrode). When the diaphragm receives pressure, the diaphragm is deformed according to the pressure difference between the inside and outside of the reference pressure chamber, and the distance between the upper electrode and the lower electrode changes. As a result, the capacitance between the upper electrode and the lower electrode changes. By detecting the amount of change in capacitance, the pressure received by the diaphragm can be detected. As described above, since a piezo element that is easily dependent on a change in ambient temperature is not used as an element for pressure detection, variations in detection accuracy can be reduced even in a situation where the ambient temperature varies in various ways.

Further, since it is not necessary to define the reference pressure chamber by bonding the two semiconductor substrates, the cost can be reduced and the entire pressure sensor can be reduced in size.
In the capacitive pressure sensor of the present invention, it is preferable that a semiconductor portion other than the portion where the central insulating layer is disposed in the upper electrode is selectively exposed on the top surface of the reference pressure chamber. (Claim 2). For example, in a manufactured capacitive pressure sensor, if the surface (lower surface) of the upper electrode on the side of the reference pressure chamber is covered with an insulating film such as silicon oxide, the diaphragm is deformed, for example, and the upper electrode becomes the lower semiconductor layer. There is a possibility that the insulating film is charged when it contacts the (lower electrode). Therefore, in this configuration, in the capacitive pressure sensor after manufacture, the insulating layer is not left on the lower surface of the upper electrode, and the semiconductor portion of the upper electrode is exposed on the top surface of the reference pressure chamber, thereby causing a charging problem. Can be avoided.

  Further, when the central through hole is arranged in a polka dot pattern, the peripheral through hole has a plurality of dots having the same size as each of the dot-shaped central through holes constituting the polka dot pattern, It is preferable that the slits are formed so as to be connected to each other so as to surround the upper electrode. In that case, the slit-shaped peripheral through-hole may have a wavy contour formed by connecting the peripheral surfaces of the plurality of dots when the semiconductor substrate is viewed from the surface side ( Claim 4). Note that the dots may include not only a circle but also a triangle, a quadrangle, and other polygons.

  Further, the semiconductor substrate is preferably an SOI substrate in which the lower semiconductor layer and the upper semiconductor layer are made of silicon and the insulating layer is made of silicon oxide. Since the SOI substrate can be easily procured, the labor required for preparing the semiconductor substrate can be saved. When the semiconductor substrate is an SOI substrate, it is preferable that both the central insulating layer and the surrounding insulating layer are made of silicon oxide.

In addition, it is preferable that the capacitive pressure sensor of the present invention further includes a first wiring connected to the upper electrode and a second wiring connected to the lower semiconductor layer. According to this configuration, it is possible to provide a capacitive pressure sensor having a simple structure in which each of the upper electrode and the lower semiconductor layer of one semiconductor substrate is an electrode.
The reference chamber is preferably a sealed space (claim 8). If the reference pressure chamber is hermetically sealed, a change in pressure in the reference pressure chamber due to a change in ambient temperature can be prevented. As a result, the pressure detection accuracy of the sensor can be improved.

  Further, the manufacturing method of the capacitive pressure sensor of the present invention for achieving the above object has a structure in which an insulating layer made of silicon oxide is sandwiched between a lower semiconductor layer made of silicon and an upper semiconductor layer. An annular peripheral recess for partitioning a closed region on the surface of the upper semiconductor layer and a plurality of central recesses disposed in the closed region on the semiconductor substrate so as to reach the insulating layer from the surface of the upper semiconductor layer A step of selectively forming; a step of forming a protective film made of silicon oxide on each inner surface of the peripheral recess and the central recess; and a bottom surface of the peripheral recess and the central recess in the protective film and the insulating layer A step of selectively removing a portion, and the peripheral recess and the central recess are dug into the lower semiconductor layer by anisotropic etching, and then the isotropic etching is performed to A reference pressure chamber dug into the lower semiconductor layer is formed by connecting the lower part of the surrounding recess and the plurality of central recesses to each other, and at the same time, the reference pressure chamber disposed on the surface side with respect to the reference pressure chamber Forming a diaphragm including an upper electrode formed of the closed region in the upper semiconductor layer; and thermally oxidizing the semiconductor substrate to penetrate between the surface of the upper semiconductor layer and the reference pressure chamber. A peripheral insulating layer made of silicon oxide is formed in the peripheral through hole made of the peripheral recess, which closes the peripheral through hole and electrically isolates the upper electrode from other parts of the upper semiconductor layer. And a step of thermally oxidizing the semiconductor substrate, in the central through hole formed of the central recess penetrating between the surface of the upper semiconductor layer and the reference pressure chamber , And forming a central insulating layer of silicon oxide so as to close the central through-hole (claim 9).

  According to this method, in order to form the reference pressure chamber in the semiconductor substrate, the reference pressure chamber is formed by hollowing a part of the lower semiconductor layer by anisotropic etching and isotropic etching. A peripheral insulating layer and a central insulating layer for sealing the chamber are formed in the peripheral through hole and the central through hole, respectively. That is, in forming the reference pressure chamber, it is only necessary to perform processing such as etching and formation of each insulating layer on the semiconductor substrate. Therefore, it is not necessary to separately prepare a substrate for bonding to the semiconductor substrate or to attach the substrate to the semiconductor substrate.

  And since the pressure sensor manufactured by this method has a reference pressure chamber inside one semiconductor substrate, it is possible to prevent an increase in cost due to the use of another substrate, and there is one reference pressure chamber. Since it is defined by a part of the semiconductor substrate, it is small. Therefore, according to this method, it is possible to easily manufacture a capacitance-type pressure sensor that can reduce variations in detection accuracy and can be further reduced in cost and reduced in size.

  Furthermore, when the lower part of the peripheral concave part and the plurality of central concave parts are connected to each other by isotropic etching, the lower part of the upper semiconductor layer is covered with an insulating layer, so that the upper semiconductor layer can be protected by this insulating layer. it can. As a result, since the upper semiconductor layer is not eroded by the etchant, the diaphragm can be formed with a desired thickness. Therefore, in the completed capacitive pressure sensor, variations in sensitivity can be eliminated, so that detection accuracy can be improved.

The method of manufacturing a capacitive pressure sensor according to the present invention may further include a step of forming the upper semiconductor layer on the insulating layer by epitaxial growth after forming an insulating film on the lower semiconductor layer. Preferred (claim 10). By adjusting the conditions for epitaxial growth, the thickness of the upper semiconductor layer serving as a diaphragm can be easily controlled.
Further, in the method of manufacturing a capacitive pressure sensor according to the present invention, the etching gas is supplied to the peripheral through hole and the central through hole prior to the formation of the peripheral insulating layer and the central insulating layer. Preferably, the method further includes a step of removing the protective film remaining on the inner surface of the peripheral through hole and the central through hole.

  For example, when the protective film is formed by plasma CVD (Chemical Vapor Deposition), the film quality is lower than that of the thermal oxide film. Therefore, in this method, after once cleaning the inner surface of the peripheral through hole and the central through hole by removing the protective film, by thermally oxidizing the semiconductor substrate, in each of the peripheral through hole and the central through hole, A peripheral insulating layer and a central insulating layer made of a thermal oxide film are formed. Thereby, the film quality of a surrounding insulating layer and a center insulating layer can be made favorable. In this case, the step of removing the protective film includes the step of supplying the etching gas obliquely with respect to the peripheral through hole and the central through hole to form the top surface of the reference pressure chamber. Preferably, the method includes a step of selectively removing (Claim 12). Thereby, in the manufactured capacitance type pressure sensor, the semiconductor layer of the upper electrode can be exposed to the top surface of the reference pressure chamber without leaving the insulating layer on the lower surface of the upper electrode.

  Further, in the method of manufacturing a capacitive pressure sensor according to the present invention, the step of forming the peripheral recess and the plurality of central recesses is formed so that the dot-like central recesses are arranged in a polka dot pattern, At the same time, the peripheral recesses are formed by arranging a plurality of recesses made of dots having the same size as each of the center recesses in an annular shape so as to surround the closed region at an interval narrower than the interval between the adjacent center recesses. The step of forming the peripheral insulating layer and the central insulating layer includes filling the central through-hole formed of the dot-shaped central recess with a silicon oxide film by the same thermal oxidation treatment. At the same time, the peripheral through hole made of the dot-shaped peripheral recess is filled with a silicon oxide film, and the silicon oxide film in the adjacent peripheral through hole is filled As mutually connected, preferably includes a step of also sandwiched between the peripheral through holes adjacent portions forming the periphery insulating layer by alteration in the silicon oxide film (claim 13).

  According to this method, since the peripheral insulating layer and the central insulating layer can be formed simultaneously, the manufacturing efficiency can be improved. Moreover, in the previous stage of forming the peripheral insulating layer and the central insulating layer, the peripheral concave portion and the central concave portion are formed so as to be dots of the same size, so the etching rate and the central concave portion for forming the peripheral concave portion are formed. The variation between the etching rate and the etching rate can be reduced.

  In the step of forming the peripheral insulating layer and the central insulating layer, it is preferable to perform a thermal oxidation process in a vacuum.

FIG. 1 is a plan view of a silicon wafer used in the manufacturing process of a pressure sensor according to an embodiment of the present invention. FIG. 2 is a plan view of a pressure sensor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along section line III-III in FIG. FIG. 4A is a diagram showing a part of the manufacturing process of the pressure sensor. FIG. 4B is a diagram showing a step subsequent to FIG. 4A. FIG. 4C is a diagram showing a step subsequent to FIG. 4B. FIG. 4D is a diagram showing a step subsequent to FIG. 4C. FIG. 4E is a diagram showing a step subsequent to that in FIG. 4D. FIG. 4F is a diagram showing a step subsequent to that in FIG. 4E. FIG. 4G is a diagram showing a step subsequent to FIG. 4F. 4H is a diagram showing a step subsequent to that in FIG. 4G. FIG. 4I is a diagram showing a step subsequent to that in FIG. 4H. FIG. 4J is a diagram showing a step subsequent to that in FIG. 4I. FIG. 4K is a diagram showing a step subsequent to that in FIG. 4J. 4L is a diagram showing a step subsequent to that in FIG. 4K. 4M is a diagram showing a step subsequent to that in FIG. 4L. 4N is a diagram showing a step subsequent to that in FIG. 4M. FIG. 5 is a plan view for explaining a process related to the simultaneous formation of the peripheral insulating layer and the central insulating layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view of a silicon wafer used in the manufacturing process of a pressure sensor according to an embodiment of the present invention. FIG. 2 is a plan view of a pressure sensor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along section line III-III in FIG.
The pressure sensor 1 is a capacitance-type pressure sensor that detects the amount of change in pressure based on the amount of change in capacitance, and as shown in FIG. Many are regularly arranged. In this embodiment, the SOI wafer 2 (hereinafter also referred to as “SOI substrate 2”) is an insulating film made of silicon oxide between a lower semiconductor layer 201 and an upper semiconductor layer 202 both made of silicon, as shown in FIG. The layer 203 is sandwiched. The lower semiconductor layer 201 and the upper semiconductor layer 202 of the SOI wafer 2 are preferably made of low-resistance silicon having a specific resistance of 5 mΩ · cm to 25 mΩ · cm, for example.

Each pressure sensor 1 includes an SOI substrate 2 as a semiconductor substrate. The surface 2A of the SOI substrate 2 (the upper surface of the upper semiconductor layer 202) is covered with an interlayer insulating film 3 made of an insulating material such as silicon oxide (SiO ₂ ). The thickness of the interlayer insulating film 3 is 5000 mm to 10,000 mm. The interlayer insulating film 3 has a single layer structure in this embodiment, but may have a multilayer structure. Further, the back surface 2B (the lower surface of the lower semiconductor layer 201) of the SOI substrate 2 is an exposed surface.

  Inside the SOI substrate 2, one reference pressure chamber 4 (cavity) is formed for each pressure sensor 1 by digging the upper surface of the lower semiconductor layer 201 toward the back surface 2B. In this embodiment, the reference pressure chamber 4 has a square shape in plan view (three-dimensionally rectangular parallelepiped shape) as shown in FIG. 2, and is parallel to the surface 2A of the SOI substrate 2 as shown in FIG. It is a flat space flat in the direction. Due to the reference pressure chamber 4, a portion of the upper semiconductor layer 202 facing the reference pressure chamber 4 is formed as a diaphragm 5 on the surface portion on the surface 2 </ b> A side of the SOI substrate 2. In FIG. 3, for convenience of explanation, the entire upper semiconductor layer 202 constituting the thin film diaphragm 5 is shown thicker than the lower semiconductor layer 201.

The diaphragm 5 is formed with two types of through holes penetrating between the surface 2 </ b> A of the SOI substrate 2 and the reference pressure chamber 4. One through-hole is an annular peripheral through-hole 6 formed along the peripheral edge of the diaphragm 5, and the other through-hole is a plurality of centers arranged in a portion surrounded by the peripheral through-hole 6 of the diaphragm 5. It is a through hole 7.
In this embodiment, a large number of dot-like central through holes 7 are arranged in a polka dot pattern. Specifically, the central through-holes 7 are regularly arranged in a matrix at equal intervals along two directions orthogonal to each other in plan view. The arrangement pattern of the plurality of central through holes 7 is not limited to a matrix shape, and may be a staggered pattern or the like. In this embodiment, the diameter of each central through hole 7 is, for example, 0.2 μm to 0.5 μm (preferably 0.4 μm).

The peripheral through-hole 6 has a plurality of dots having the same size (for example, a diameter of 0.2 μm to 0.5 μm) as the dot-shaped central through-holes 7 constituting the polka dot pattern so as to surround the central through-hole 7. Are formed in a slit shape that is connected to each other. The slit-shaped peripheral through hole 6 has a wavy outline formed by connecting peripheral surfaces of a plurality of dots in a plan view of the SOI substrate 2 viewed from the surface 2A side. As a result, the width W ₁ of the peripheral through-hole 6 is continuously changed, becoming narrower or wider along the periphery of the diaphragm 5.

A peripheral insulating layer 8 and a central insulating layer 9 are embedded in the peripheral through hole 6 and the central through hole 7, respectively. In this embodiment, the peripheral insulating layer 8 and the central insulating layer 9 are made of silicon oxide (SiO ₂ ).
Thus, the SOI substrate 2 is separated into a plurality of conductive regions that are electrically insulated from each other by the surrounding insulating layer 8. In this embodiment, it is separated into two regions, and one region is the upper electrode 10 that is disposed inside the surrounding insulating layer 8 and forms the top surface of the reference pressure chamber 4. The other region is a frame portion 11 that forms a side surface and a bottom surface of the reference pressure chamber 4 and integrally supports the upper electrode 10 by the surrounding insulating layer 8. The frame portion 11 includes a lower semiconductor layer 201 and an insulating layer 203, and a portion surrounding the upper electrode 10 in the upper semiconductor layer 202. In the pressure sensor 1, the upper electrode 10 is a movable electrode that can be displaced in a direction facing the reference pressure chamber 4 (thickness direction). On the other hand, a portion (a portion below the upper electrode 10) facing the upper electrode 10 across the reference pressure chamber 4 in the frame portion 11 is a lower electrode 12 as a fixed electrode. The upper electrode 10 and the lower electrode 12 constitute a capacitor structure (capacitor). In this structure, since the frame portion 11 is formed so as to cover the upper electrode 10 from the lower side to the side, both the contacts (electrical connections) to the upper electrode 10 and the lower electrode 12 are used for the SOI substrate 2. It can be taken from the surface 2A side.

In addition, since all the peripheral through holes 6 and the central through holes 7 are closed by the peripheral insulating layer 8 and the central insulating layer 9, the reference pressure chamber 4 below the diaphragm 5 has an internal pressure at the time of pressure detection. It is sealed as a standard cavity. In this embodiment, the reference pressure chamber 4 is held in a vacuum or a reduced pressure state (for example, 10 ⁻⁵ Torr). Further, the inner surface (bottom surface, side surface, and top surface) that defines the reference pressure chamber 4 is exposed to the semiconductor portion of the SOI substrate 2 in all regions except the region where the peripheral insulating layer 8 and the central insulating layer 9 are disposed. doing. That is, most of the reference pressure chamber 4 is defined by the inner surface made of a silicon semiconductor.

A first wiring 13 and a second wiring 14 are formed on the interlayer insulating film 3. The first wiring 13 and the second wiring 14 are made of aluminum (Al) in this embodiment. The first wiring 13 is connected to the upper electrode 10 through the interlayer insulating film 3. On the other hand, the second wiring 14 is connected to the lower semiconductor layer 201 (frame portion) by contact plugs 29 embedded in the contact holes 33 that penetrate the interlayer insulating film 3, the upper semiconductor layer 202, and the insulating layer 203 and reach the lower semiconductor layer 201. 11). The contact plug 29 is made of a conductive material such as tungsten (W). Further, between the contact plug 29 and the SOI substrate 2 (the inner surface of the contact hole 33), from the SOI substrate 2 side, a protective film 30 made of an insulating material such as silicon oxide (SiO ₂ ), Ti / TiN, and the like. A barrier film 31 made of a conductive material is interposed. Only the barrier film 31 is disposed on the bottom of the contact plug 29. As a result, the contact plug 29 is electrically connected to the lower semiconductor layer 201 at the bottom thereof. The first wiring 13 and the second wiring 14 are covered with a surface protective film 15 made of an insulating material such as silicon nitride (SiN). Openings 18 and 19 are formed in the surface protective film 15 to expose portions of the first wiring 13 and the second wiring 14 as the first pad 16 and the second pad 17, respectively. For example, the first pad 16 and the second pad 17 are arranged adjacent to each other along one peripheral edge of the diaphragm 5.

  A bias voltage is applied to each of the first pad 16 and the second pad 17, and the potential difference between the movable electrode (upper electrode 10) and the fixed electrode (lower electrode 12) is constant. Here, when the diaphragm 5 receives pressure (for example, gas pressure) from the surface 2 A side of the SOI substrate 2, a differential pressure is generated between the inside and the outside of the reference pressure chamber 4, so that the diaphragm 5 is attached to the SOI substrate 2. Displaces in the thickness direction. Accordingly, the distance between the upper electrode 10 and the lower electrode 12 (the depth of the reference pressure chamber 4) changes, and the capacitance between the upper electrode 10 and the lower electrode 12 changes. Based on the change in capacitance, the magnitude of the pressure generated in the pressure sensor 1 can be detected.

4A to 4N are diagrams showing a part of the manufacturing process of the pressure sensor of FIGS. 1 to 3 in the order of steps.
As shown in FIG. 4A, after the insulating layer 203 is formed on the upper surface of the lower semiconductor layer 201 by thermal oxidation, the upper semiconductor layer 202 is formed on the insulating layer 203 by epitaxial growth. At this time, the thickness of the upper semiconductor layer 202 to be the diaphragm 5 can be easily controlled by adjusting the epitaxial growth conditions. Thereby, the SOI substrate 2 is formed. If the SOI substrate 2 can be procured from the market, the labor for forming the SOI substrate 2 can be saved.

Next, an interlayer insulating film 3 is formed on the surface 2A of the SOI substrate 2 (wafer) by thermal oxidation. The formation of the interlayer insulating film 3 may be performed by plasma CVD. Next, a resist pattern 20 having a predetermined shape is formed on the interlayer insulating film 3 by photolithography.
Next, as shown in FIG. 4B, the upper semiconductor layer of the SOI substrate 2 is formed by anisotropic deep RIE (Reactive Ion Etching) using the resist pattern 20 as a mask, specifically by a Bosch process. Drill down 202. Etching is performed until the bottom surface of the recess formed by etching reaches the insulating layer 203, and when the insulating layer 203 is reached, the insulating layer 203 functions as an etching stop layer and ends. That is, the insulating layer 203 can be used as an etching stop layer by utilizing the difference in etching selectivity between the upper semiconductor layer 202 made of silicon and the insulating layer 203 made of silicon oxide. By this etching, a plurality of peripheral recesses 22 are formed in the upper semiconductor layer 202 so as to partition the closed region 21 on the surface 2A of the SOI substrate 2, and at the same time, a plurality of central recesses 23 are formed in the closed region 21 in the upper semiconductor layer 202. Formed. The closed region 21 is a portion that finally becomes the upper electrode 10. Specifically, as shown in FIG. 5A, the peripheral concave portion 22 and the central concave portion 23 are arranged such that the dot-shaped central concave portions 23 are arranged in a polka dot pattern (for example, a matrix shape, a staggered shape, etc.). At the same time, a plurality of peripheral recesses 22 made of dots having the same size as the respective center recesses 23 are closed at an interval (pitch) P ₂ narrower than an interval (pitch) P ₁ between adjacent center recesses 23. 21 is formed in a pattern arranged in a ring so as to surround 21 (P ₁ > P ₂ ).

In the Bosch process, a step of etching the SOI substrate 2 using SF ₆ (sulfur hexafluoride), a step of forming a protective film on the etching surface using C ₄ F ₈ (perfluorocyclobutane), Are repeated alternately. As a result, the SOI substrate 2 can be etched with a high aspect ratio, but wavy irregularities called scallops are formed on the etching surface (inner peripheral surfaces of the peripheral recess 22 and the central recess 23). After the formation of the peripheral recess 22 and the central recess 23, the resist pattern 20 is peeled off.

Next, as shown in FIG. 4C, an insulating material such as silicon oxide (SiO ₂ ) is applied to the entire inner surface of the peripheral recess 22 and the central recess 23 (that is, the inner peripheral surface and the bottom surface of the peripheral recess 22 and the central recess 23). A protective film 24 is formed. When the protective film 24 is made of silicon oxide, the protective film 24 can be formed by either thermal oxidation of the SOI substrate 2 or plasma CVD, but it is preferable to employ plasma CVD. Unlike the thermal oxidation of the SOI substrate 2, the plasma CVD uses a portion (a part of the upper semiconductor layer 202) inside the peripheral recess 22 and the central recess 23 to convert the portion into a silicon oxide film. It is not a method of forming by alteration. Plasma CVD is a method of depositing a silicon oxide film on the inner surfaces of the peripheral recess 22 and the central recess 23 from the outside. Therefore, even after the protective film 24 is formed, the area of the semiconductor portion (portion other than the peripheral concave portion 22 and the central concave portion 23) of the closed region 21 that finally becomes the upper electrode 10 can be maintained.

Next, as shown in FIG. 4D, portions of the protective film 24 on the bottom surfaces of the peripheral recess 22 and the central recess 23 are selectively removed together with the insulating layer 203 by etch back. As a result, the lower semiconductor layer 201 is exposed on the bottom surfaces of the peripheral recess 22 and the central recess 23.
Next, as shown in FIG. 4E, the bottom surfaces of the peripheral recess 22 and the central recess 23 are further dug down by anisotropic deep RIE using the interlayer insulating film 3 as a mask. As a result, exposed spaces 25 and 26 in which the crystal plane of the lower semiconductor layer 201 is exposed are formed at the bottoms of the peripheral recess 22 and the central recess 23.

  Next, as shown in FIG. 4F, reactive ions and etching gas are supplied to the exposed spaces 25 and 26 of the peripheral recess 22 and the central recess 23 by isotropic RIE. The lower semiconductor layer 201 is etched in the direction parallel to the surface 2A of the SOI substrate 2 while being etched in the thickness direction of the SOI substrate 2 starting from the exposed spaces 25 and 26 by the action of the reactive ions and the like. Is done. As a result, all the exposed spaces 25 and 26 adjacent to each other are integrated to form the reference pressure chamber 4 inside the SOI substrate 2, and at the same time, a diaphragm comprising the upper semiconductor layer 202 on the surface 2A side with respect to the reference pressure chamber 4. 5 is formed. Further, with the formation of the reference pressure chamber 4, the peripheral recess 22 and the central recess 23 are respectively formed with a peripheral through hole 6 and a central through hole 7 that penetrate between the surface 2 A of the SOI substrate 2 and the reference pressure chamber 4. Become. Further, the SOI substrate 2 is partitioned into an upper electrode 10 and a frame portion 11 that are formed of a closed region 21.

  Next, as shown in FIG. 4G, the protective film 24 remaining on the inner surfaces of the peripheral through hole 6 and the central through hole 7 is removed by supplying an etching gas to the peripheral through hole 6 and the central through hole 7. In this embodiment, for example, hydrofluoric acid (HF) is used as an etching gas, and the etching gas is supplied obliquely to the peripheral through hole 6 and the central through hole 7. Thereby, the protective film 24 can be removed to expose the crystal plane of the upper semiconductor layer 202 on the inner surfaces of the peripheral through hole 6 and the central through hole 7, and at the same time, the insulation remaining on the lower surface of the upper semiconductor layer 202. Layer 203 can be selectively removed.

  As described above, since the protective film 24 is formed by plasma CVD, the film quality is lower than that of the thermal oxide film. Therefore, as shown in FIG. 4G, once the inner surfaces of the peripheral through-hole 6 and the central through-hole 7 are cleaned by removing the protective film 24, the inner through-hole 6 and the central through-hole 6 are removed in the process described later. A peripheral insulating layer 8 and a central insulating layer 9 made of a thermal oxide film can be formed in each hole 7. Thereby, the film quality of the surrounding insulating layer 8 and the center insulating layer 9 can be made favorable.

  Next, as shown in FIG. 4H, the peripheral insulating layer 8 and the central insulating layer 9 are simultaneously formed by thermally oxidizing the SOI substrate 2 (for example, at 1100 ° C. to 1150 ° C. for 24 hours) in a vacuum, for example. . Specifically, as shown in FIG. 5B, when the SOI substrate 2 is thermally oxidized, a part of the diaphragm 5 is concentrically formed from the outer periphery of each peripheral through hole 6 and each central through hole 7. At the same time, the silicon oxide film thermally expands and fills each peripheral through hole 6 and each central through hole 7. In FIG. 5B, the circles indicated by broken lines are the outlines of the peripheral through hole 6 and the central through hole 7 that existed before the formation of the peripheral insulating layer 8 and the central insulating layer 9.

Then, the time of thermal oxidation, since the pitch P ₁ of the central through-hole 7 is wider than the pitch P ₂ around the through-hole 6, the silicon oxide film extending from one central through hole 7 to the outside, next to the central through The time until the silicon oxide film that spreads outward from the hole 7 is the time until the silicon oxide film that spreads outward from a certain peripheral through hole 6 meets the silicon oxide film that spreads outward from the adjacent peripheral through hole 6. It can be longer than that. As a result, the semiconductor portion 27 sandwiched between the adjacent central through-holes 7 is left in a silicon state, while the semiconductor portion 28 sandwiched between the adjacent peripheral through-holes 6 is transformed into a silicon oxide film so that the adjacent peripheral through The silicon oxide films in the holes 6 can be connected to each other. As a result, it is possible to form the slit-shaped peripheral insulating layer 8 having a wavy contour formed by connecting the peripheral surfaces of a plurality of dots.

  As described above, the manufacturing efficiency can be improved by forming the peripheral insulating layer 8 and the central insulating layer 9 at the same time. In addition, in the previous stage of forming the peripheral insulating layer 8 and the central insulating layer 9 (see FIG. 5A), the peripheral concave portion 22 and the central concave portion 23 are formed so as to be dots of the same size. The variation between the etching rate for forming 22 and the etching rate for forming the central recess 23 can be reduced.

  Next, as shown in FIG. 4I, the upper semiconductor of the SOI substrate 2 is formed by anisotropic deep RIE using a resist pattern 32 having an opening corresponding to the shape of the contact plug 29 as a mask, specifically by a Bosch process. Drill down layer 202. Etching is performed until the bottom surface of the recess formed by etching reaches the lower semiconductor layer 201 through the insulating layer 203. Thereby, the contact hole 33 is formed.

Next, as shown in FIG. 4J, a protective film 30 made of an insulating material such as silicon oxide (SiO ₂ ) is formed over the entire inner surface of the contact hole 33 (that is, the inner peripheral surface and the bottom surface of the contact hole 33). When the protective film 30 is made of silicon oxide, the protective film 30 can be formed by either thermal oxidation of the SOI substrate 2 or plasma CVD.
Next, as shown in FIG. 4K, the portion of the protective film 30 on the bottom surface of the contact hole 33 is selectively removed by etch back. As a result, the lower semiconductor layer 201 is exposed on the bottom surface of the contact hole 33.

  Next, as shown in FIG. 4L, a barrier film 31 made of a conductive material such as Ti / TiN is formed on the protective film 30 by sputtering. Next, after a conductive material such as tungsten (W) is deposited by plasma CVD until the contact hole 33 is filled, a portion outside the contact hole 33 of the deposited conductive film is removed by etch back. Thereby, the contact plug 29 embedded in the contact hole 33 is formed.

  Next, as shown in FIG. 4M, the interlayer insulating film 3 is selectively removed by, for example, plasma etching, and the upper electrode 10 and the contact plug 29 are selectively exposed. Prior to this step, the interlayer insulating film 3 may be thinned. Thinning can be performed, for example, by etch back or CMP (Chemical Mechanical Polishing).

Next, as shown in FIG. 4N, the first wiring 13 and the second wiring 14 are formed on the interlayer insulating film 3. Thereafter, by forming the surface protective film 15, the openings 18, 19 and the like, the pressure sensor 1 having the structure shown in FIG.
According to the above method, after forming the peripheral recess 22 and the central recess 23 in the upper semiconductor layer 202 by anisotropic deep RIE (FIG. 4B and FIG. 5A), anisotropic deep RIE and isotropic By continuously performing the RIE (FIGS. 4E to 4F), the lower semiconductor layer 201 can be dug to form the reference pressure chamber 4 in the SOI substrate 2 and the diaphragm 5 can be formed at the same time. And all the through-holes 6 and 7 can be obstruct | occluded by filling the surrounding through-hole 6 and the center through-hole 7 with the surrounding insulating layer 8 and the center insulating layer 9, respectively. As a result, the reference pressure chamber 4 can be sealed while being maintained at the reference pressure (vacuum) when the pressure is detected.

That is, according to the manufacturing method of this embodiment, in forming the reference pressure chamber 4, it is only necessary to perform various treatments such as deep RIE and thermal oxidation only on the SOI substrate 2. There is no need to separately prepare a substrate (for example, a glass substrate) or to attach the substrate to the SOI substrate 2.
Since the pressure sensor 1 manufactured by this method has the reference pressure chamber 4 inside one SOI substrate 2, an increase in cost due to the use of another substrate can be prevented. In addition, since the reference pressure chamber 4 is defined by one SOI substrate 2, the size is small. Therefore, in this embodiment, the low-cost and small pressure sensor 1 can be easily manufactured. Moreover, since the substrate used is an inexpensive material such as the SOI substrate 2, the cost required for the substrate can be further reduced.

The pressure sensor 1 is a capacitance type that detects the pressure received by the diaphragm 5 based on a change in capacitance between the upper electrode 10 and the lower electrode 12. That is, since a piezo element that is easily dependent on changes in the ambient temperature is not used as an element for pressure detection, variations in detection accuracy can be reduced even in situations where the ambient temperature changes in various ways.
Furthermore, when the lower portions of the peripheral recess 22 and the central recess 23 are made continuous with each other by isotropic etching (FIG. 4F), the lower surface of the upper semiconductor layer 202 is covered with the insulating layer 203. The semiconductor layer 202 can be protected. As a result, the upper semiconductor layer 202 is not eroded by the etchant, so that the diaphragm 5 can be formed with a desired thickness. Therefore, in the completed pressure sensor 1, variations in sensitivity can be eliminated, so that detection accuracy can be improved.

The top surface of the reference pressure chamber 4 (that is, the lower surface of the upper electrode 10 and the surface facing the lower electrode 12) is not covered with the insulating layer 203 and is exposed as a silicon semiconductor. Therefore, it is possible to avoid the upper electrode 10 from being charged when the upper electrode 10 contacts the lower electrode 12.
Moreover, since the inside of the reference pressure chamber 4 is kept in a vacuum, it is possible to prevent a change in the pressure in the reference pressure chamber 4 due to a temperature change in the external environment. As a result, the pressure detection accuracy of the pressure sensor 1 can be improved.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, the peripheral insulating layer 8 and the central insulating layer 9 are formed by the same thermal oxidation process, but these insulating layers can also be formed by separate thermal oxidation processes.
Further, since the peripheral insulating layer 8 and the central insulating layer 9 may have any shape that can seal the reference pressure chamber 4, the peripheral through hole 6 and the central through hole 7 are not necessarily embedded as in the above-described embodiment. There is no need to be.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Pressure sensor 2 SOI substrate 2A Front surface 2B Back surface 201 Lower semiconductor layer 202 Upper semiconductor layer 203 Insulating layer 4 Reference pressure chamber 5 Diaphragm 6 Peripheral through hole 7 Central through hole 8 Peripheral insulating layer 9 Central insulating layer 10 Upper electrode 11 Frame part 12 Lower electrode 13 First wiring 14 Second wiring 21 Closed area 22 Surrounding recess 23 Central recess 24 Protective film 28 Semiconductor portion

Claims (14)

A semiconductor substrate having a structure in which an insulating layer is sandwiched between a lower semiconductor layer and an upper semiconductor layer, and a reference pressure chamber in which the lower semiconductor layer is dug and partitioned; and
A diaphragm selectively formed in the upper semiconductor layer of the semiconductor substrate, wherein the upper electrode penetrates between the surface of the upper semiconductor layer and the reference pressure chamber, and is part of the diaphragm inside the diaphragm. A diaphragm in which a plurality of central through holes penetrating between the surface of the upper semiconductor layer and the reference pressure chamber in the upper electrode are formed;
A surrounding insulating layer provided in the surrounding through hole, closing the surrounding through hole, and electrically separating the upper electrode from other parts of the upper semiconductor layer;
A capacitance-type pressure sensor including a central insulating layer provided in each of the central through holes and closing the central through hole.   2. The capacitive pressure sensor according to claim 1, wherein a semiconductor portion other than a portion where the central insulating layer is disposed in the upper electrode is selectively exposed on a top surface of the reference pressure chamber. The central through holes are arranged in a polka dot pattern,
The peripheral through hole is formed in a slit shape in which a plurality of dots having the same size as each of the dot-shaped central through holes constituting the polka dot pattern are connected to each other so as to surround the upper electrode. The capacitive pressure sensor according to claim 1 or 2.   The slit-shaped peripheral through hole has a wavy contour formed by connecting peripheral surfaces of the plurality of dots when the upper semiconductor layer is viewed from the surface side. The capacitance-type pressure sensor described.   5. The capacitive pressure according to claim 1, wherein the semiconductor substrate is an SOI substrate in which the lower semiconductor layer and the upper semiconductor layer are made of silicon, and the insulating layer is made of silicon oxide. Sensor.   The capacitive pressure sensor according to claim 5, wherein the central insulating layer and the surrounding insulating layer are both made of silicon oxide. A first wiring connected to the upper electrode;
The capacitive pressure sensor according to claim 1, further comprising a second wiring connected to the lower semiconductor layer.   The capacitive pressure sensor according to any one of claims 1 to 7, wherein the reference chamber is a sealed space. A semiconductor substrate having a structure in which an insulating layer made of silicon oxide is sandwiched between a lower semiconductor layer made of silicon and an upper semiconductor layer, an annular peripheral recess that partitions a closed region on the surface of the upper semiconductor layer, and Selectively forming a plurality of central recesses disposed in a closed region so as to reach the insulating layer from the surface of the upper semiconductor layer;
Forming a protective film made of silicon oxide on each inner surface of the peripheral recess and the central recess;
Selectively removing portions of the protective film and the insulating layer on the bottom surface of the peripheral recess and the central recess;
The lower semiconductor layer is formed by digging the peripheral recess and the central recess into the lower semiconductor layer by anisotropic etching, and then making the lower portions of the peripheral recess and the plurality of central recesses continuous with each other by isotropic etching. Forming a reference pressure chamber dug in, and simultaneously forming a diaphragm including the upper electrode made of the closed region in the upper semiconductor layer disposed on the surface side with respect to the reference pressure chamber;
By thermally oxidizing the semiconductor substrate, the peripheral through hole is closed in the peripheral through hole formed of the peripheral recess passing through between the surface of the upper semiconductor layer and the reference pressure chamber, and Forming a peripheral insulating layer made of silicon oxide to electrically isolate the upper electrode from other parts of the upper semiconductor layer;
By thermally oxidizing the semiconductor substrate, the central through hole is closed in a central through hole formed by the central recess passing through between the surface of the upper semiconductor layer and the reference pressure chamber. And a step of forming a central insulating layer made of silicon oxide.   The method of manufacturing a capacitive pressure sensor according to claim 9, further comprising a step of forming the upper semiconductor layer on the insulating layer by epitaxial growth after forming an insulating film on the lower semiconductor layer.   Prior to the formation of the peripheral insulating layer and the central insulating layer, by supplying an etching gas to the peripheral through hole and the central through hole, the protection remaining on the inner surfaces of the peripheral through hole and the central through hole The method for manufacturing a capacitive pressure sensor according to claim 9 or 10, further comprising a step of removing the film.   The step of removing the protective film selectively supplies the etching gas to the peripheral through hole and the central through hole to selectively form the insulating layer forming the top surface of the reference pressure chamber. The method of manufacturing a capacitance type pressure sensor according to claim 11, comprising a step of removing the capacitor. The step of forming the peripheral recesses and the plurality of center recesses is formed by arranging the dot-like center recesses so as to be arranged in a polka dot pattern, and at the same time, a plurality of dots having the same size as each of the center recesses Forming the peripheral recesses by arranging the recesses in an annular shape so as to surround the closed region at an interval narrower than the interval between the adjacent central recesses;
The step of forming the surrounding insulating layer and the central insulating layer includes forming the central insulating layer by filling the central through-hole formed by the dot-shaped central concave portion with a silicon oxide film by the same thermal oxidation treatment, In addition, the peripheral through hole made of the dot-shaped peripheral concave portion is filled with a silicon oxide film, and a portion sandwiched between adjacent peripheral through holes is connected so that the silicon oxide films in the adjacent peripheral through holes are connected to each other. The method for manufacturing a capacitive pressure sensor according to any one of claims 9 to 12, comprising a step of forming the surrounding insulating layer by transforming into a silicon oxide film.   The method for manufacturing a capacitive pressure sensor according to claim 9, wherein in the step of forming the peripheral insulating layer and the central insulating layer, thermal oxidation is performed in a vacuum.

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