JP2013140948A - Semiconductor light-emitting element, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a semiconductor light-emitting element with electrodes of low contact resistance and high reflectance; and a method of manufacturing the same.SOLUTION: A semiconductor light-emitting element according to an embodiment comprises: a semiconductor laminated part; and a silver layer. The semiconductor laminated part comprises: a light-emitting layer including a nitride semiconductor; and gallium-containing semiconductor layers laminated with the light-emitting layer. The silver layer is in contact with the semiconductor layer. In X-ray diffraction analysis on the silver layer, the height of a peak originating from a silver (100) plane is equal to or less than 3% of the height of a peak originating a silver (111) plane. In secondary ion mass spectrometry, the detection intensity of a complex of Ga and N at a first position in the laminating direction from the semiconductor layer toward the silver layer in a region including the semiconductor layer and the silver layer is 1/100 of the maximum detection intensity of the complex in the semiconductor layer. The detection intensity of Ga atom at a second position at a distance of 40 nm from the first position in the silver layer is higher than 0.4% of the maximum detection intensity of Ga atom in the semiconductor layer and lower than 3.8% thereof.

Description

  Embodiments described herein relate generally to a semiconductor light emitting device and a method for manufacturing the same.

  In a semiconductor light emitting device such as an LED (Light Emitting Diode), there is a configuration in which silver (Ag) with high reflectivity is used as an electrode in order to increase light extraction efficiency. When heat treatment is performed to bring the Ag electrode into ohmic contact with the semiconductor layer, the reflectance may decrease, and it is difficult to obtain a low contact resistance and a high reflectance at the same time.

JP 2011-49322 A

  Embodiments of the present invention provide a semiconductor light emitting device having a low contact resistance and a high reflectivity electrode and a method of manufacturing the same.

  According to the embodiment of the present invention, a semiconductor light emitting device including a semiconductor stacked portion and a silver layer is provided. The semiconductor stacked portion includes a light emitting layer including a nitride semiconductor and a semiconductor layer including gallium stacked with the light emitting layer. The silver layer is in contact with the semiconductor layer. In the silver layer, the height of the peak attributed to the (100) plane of silver in the X-ray diffraction analysis is 3% or less of the height of the peak attributed to the (111) plane of silver. In secondary ion mass spectrometry, the detection intensity of the complex of gallium atoms and nitrogen atoms at the first position in the stacking direction from the semiconductor layer to the silver layer in the region including the semiconductor layer and the silver layer is , 1/100 of the maximum value of the detected intensity of the complex in the semiconductor layer. In the secondary ion mass spectrometry, the detected intensity of gallium atoms at a position where the distance from the first position in the silver layer is 40 nanometers is 0 of the maximum value of the detected intensity of gallium atoms in the semiconductor layer. It is higher than 4% and lower than 3.8%.

1 is a schematic cross-sectional view showing a semiconductor light emitting element according to a first embodiment. FIG. 2A to FIG. 2C are schematic cross-sectional views showing a part of the semiconductor light emitting device according to the first embodiment. It is a graph which shows the characteristic of a semiconductor light-emitting device. 4 (a) to 4 (d) are electron micrographs showing the characteristics of the semiconductor light emitting device. It is a graph which shows the characteristic of a semiconductor light-emitting device. It is a graph which shows the characteristic of a semiconductor light-emitting device. 7A and 7B are electron micrographs showing the characteristics of the semiconductor light emitting device. FIGS. 8A to 8C are X-ray diffraction profile diagrams showing characteristics of the semiconductor light emitting device. FIG. 9A to FIG. 9C are X-ray diffraction profile diagrams showing characteristics of the semiconductor light emitting device. FIG. 10 is a graph showing characteristics of the semiconductor light emitting device. FIG. 11A to FIG. 11F are graphs showing characteristics of the semiconductor light emitting device. It is a typical sectional view showing another semiconductor light emitting element concerning a 1st embodiment. FIG. 13A to FIG. 13C are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing another semiconductor light emitting element according to the first embodiment. FIG. 14A and FIG. 14B are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing a semiconductor light emitting element according to the first embodiment. It is a flowchart figure which shows the manufacturing method of the semiconductor light-emitting device which concerns on 2nd Embodiment.

Each embodiment will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(Embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the first embodiment. As shown in FIG. 1, the semiconductor light emitting device 110 according to this embodiment includes a semiconductor stacked unit 10 s and a metal layer 80. The semiconductor stacked unit 10s includes a light emitting layer 30 including a nitride semiconductor. The semiconductor stacked unit 10s includes a nitride semiconductor. The metal layer 80 is in contact with the semiconductor stacked portion 10s and contains Ag. The metal layer 80 is a silver layer (Ag layer). The metal layer 80 is, for example, a silver electrode. The metal layer 80 may be a layer containing only Ag. The metal layer 80 may be a layer mainly composed of Ag and containing other elements such as In, Cu, and Al. The content of elements other than Ag is preferably 0 at. % (Atomic percent) or more 10 at. % Or less, and more preferably 0 at. % Or more and 1 at. % Or less, more desirably 0 at. % Or more and 0.5 at. % Or less. The portion of the metal layer 80 that is in contact with the semiconductor stacked portion 10s (the portion including the interface 80a between the semiconductor stacked portion 10s and the metal layer 80) is an Ag film.

  The semiconductor stacked unit 10s includes, for example, a first semiconductor layer 10 of a first conductivity type, a second semiconductor layer 20 of a second conductivity type, and a light emitting layer 30. The light emitting layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. However, the embodiment is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type. In the following description, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type.

Here, a direction from the first semiconductor layer 10 toward the second semiconductor layer 20 is a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.
The metal layer 80 is in contact with the semiconductor layer. In this example, the metal layer 80 is in contact with the second semiconductor layer 20. The semiconductor stacked unit 10 s includes a light emitting layer 30 including a nitride semiconductor and a semiconductor layer (second semiconductor layer 20) including Ga stacked with the light emitting layer 30. The Z-axis direction corresponds to the stacking direction. The Z-axis direction is a direction from the light emitting layer 30 toward the second semiconductor layer 20. The Z-axis direction (stacking direction) is a direction from the second semiconductor layer 20 toward the metal layer 80.

  The first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 include a nitride semiconductor.

  As shown in FIG. 1, the semiconductor light emitting device 110 may further include a substrate 5 and a buffer layer 6. The substrate 5 has a main surface 5a (first surface). The first semiconductor layer 10 is disposed between the main surface 5 a of the substrate 5 and the light emitting layer 30. The buffer layer 6 is disposed between the main surface 5 a of the substrate 5 and the first semiconductor layer 10.

As the substrate 5, for example, a substrate made of sapphire is used. The main surface 5a of the substrate 5 is a (0001) plane, that is, a c-plane. The main surface 5a of the substrate 5 may be inclined at an angle of, for example, 5 degrees or less with respect to the (0001) plane. For the buffer layer 6, for example, an Al _x0 Ga _1-x0 N (0 ≦ x0 ≦ 1) layer is used.

  The first semiconductor layer 10 includes, for example, a first n-side layer 11 and a second n-side layer 12. The second n-side layer 12 is provided between the first n-side layer 11 and the light emitting layer 30. The first n-side layer 11 functions as an n-type contact layer. The second n-side layer 12 functions as an n-type guide layer. For the first n-side layer 11, for example, a GaN layer to which an n-type impurity (for example, silicon) is added at a high concentration is used. For the second n-side layer 12, for example, a GaN layer to which an n-type impurity is added at a lower concentration than the first n-side layer 11 is used.

  The second semiconductor layer 20 includes a first p-side layer 21 and a second p-side layer 22. The first p-side layer 21 is provided between the second p-side layer 22 and the light emitting layer 30. The first p-side layer 21 functions as, for example, an electron overflow prevention layer (suppression layer). The second p-side layer 22 functions as a p-type contact layer. For the first p-side layer 21, for example, an AlGaN layer to which a p-type impurity (for example, magnesium) is added is used. For the second p-side layer 22, a GaN layer or the like to which a p-type impurity is added at a high concentration is used. That is, the concentration of impurities in the second p-side layer 22 is higher than the concentration of impurities in the first p-side layer 21.

  The semiconductor light emitting device 110 further includes a counter electrode 70. The counter-side electrode 70 is electrically connected to the first semiconductor layer 10 (specifically, the first n-side layer 11 that is an n-type contact layer). For the counter electrode 70, for example, a laminated film of a Ti film, a Pt film, and an Au film is used.

  The metal layer 80 is electrically connected to the second semiconductor layer 20 (specifically, the second p-side layer 22 that is a p-type contact layer).

  Current is supplied to the light emitting layer 30 through the first semiconductor layer 10 and the second semiconductor layer 20 by the voltage applied between the counter electrode 70 and the metal layer 80, and light (light emission light) is emitted from the light emitting layer 30. Is released.

  The light emitting layer 30 emits at least one of ultraviolet, purple, blue and green light, for example. That is, the wavelength (main wavelength) of the emitted light emitted from the light emitting layer 30 is 360 nanometers (nm) or more and 580 nm or less.

  In this specific example, a part of the first semiconductor layer 10, a part of the light emitting layer 30, a part of the second semiconductor layer 20 and the first main surface 10 a on the second semiconductor layer 20 side of the semiconductor stacked unit 10 s , Has been removed.

  The semiconductor stacked unit 10 s includes a first main surface 10 a on the second semiconductor layer 20 side and a second main surface 10 b on the first semiconductor layer 10 side. The second main surface 10b is a surface on the opposite side to the first main surface 10a in the semiconductor stacked portion 10s. The first semiconductor layer 10 is exposed on the first major surface 10a of the semiconductor stacked portion 10s. An interface 80a between the semiconductor stacked portion 10s and the metal layer 80 corresponds to the first major surface 10a.

  That is, the light emitting layer 30 is provided between a part of the first semiconductor layer 10 and the second semiconductor layer 20. On the first main surface 10 a side, the opposing electrode 70 is provided in contact with the first semiconductor layer 10. A metal layer 80 is provided in contact with the second semiconductor layer 20 on the first major surface 10a side. The substrate 5 and the buffer layer 6 are provided on the second main surface 10b of the semiconductor stacked unit 10s.

  The light emitting layer 30 has a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.

FIG. 2A to FIG. 2C are schematic cross-sectional views illustrating the configuration of part of the semiconductor light emitting element according to the first embodiment.
These drawings are schematic views showing examples of the configuration of the light emitting layer 30. FIG.

  As shown in FIG. 2A, in the semiconductor light emitting device 110a according to this embodiment, the light emitting layer 30 has an SQW structure. That is, the light emitting layer 30 includes the barrier layer BL (first barrier layer BL1), the p-side barrier layer BLp, and the well layer WL (first layer) provided between the first barrier layer BL1 and the p-side barrier layer BLp. Well layer WL1).

  In the specification of the present application, “lamination” includes not only the case of direct stacking but also the case of stacking by inserting other layers. For example, as described later, another layer may be provided between the first barrier layer BL1 and the first well layer WL1 and between the first well layer WL1 and the p-side barrier layer BLp.

  As shown in FIG. 2B, in the semiconductor light emitting device 110b according to this embodiment, the light emitting layer 30 has an MQW structure. That is, the light emitting layer 30 includes a plurality of barrier layers stacked in the Z-axis direction (in this example, the first to fourth barrier layers BL1 to BL4 and the p-side barrier layer BLp), and a plurality of barrier layers. Well layers (first to fourth well layers WL1 to WL4) provided between the two. In this specific example, four well layers are provided, but the number of well layers is arbitrary.

  As described above, the light emitting layer 30 includes an Nth barrier layer provided on the opposite side of the (N-1) th well layer WL from the (N-1) th barrier layer in an integer N of 2 or more, And an Nth well layer provided on the opposite side of the N barrier layer from the (N-1) th well layer.

  As shown in FIG. 2C, in the semiconductor light emitting device 110c according to the present embodiment, the light emitting layer 30 further includes an intermediate layer provided between the barrier layer and the well layer. That is, the light emitting layer 30 includes the first intermediate layer IL1 provided between the (N-1) th barrier layer and the (N-1) th well layer, the (N-1) th well layer, and the Nth barrier. And a second intermediate layer IL2 provided between the layers. Further, the second intermediate layer IL2 is provided between the Nth well layer and the p-side barrier layer BLp. The first intermediate layer IL1 and the second intermediate layer IL2 are provided as necessary and can be omitted. Further, the first intermediate layer IL1 may be provided and the second intermediate layer IL2 may be omitted. Further, the second intermediate layer IL2 may be provided and the first intermediate layer IL1 may be omitted.

For the barrier layers (for example, the first to fourth barrier layers BL1 to BL4, the Nth barrier layer), for example, In _x1 Al _y1 Ga _1-x1-y1 N (0 ≦ x1 <1, 0 ≦ y1 <1, x1 + y1) <1) can be used. For example, In _0.02 Al _0.33 Ga _0.65 N can be used for the barrier layer. The thickness of the barrier layer can be set to 12.5 nm, for example.

For example, In _x2 Al _y2 Ga _1-x2-y2 N (0 ≦ x2 <1, 0 ≦ y2 <1, x2 + y2 ≦ 1) can be used for the p-side barrier layer BLp. For example, In _0.02 Al _0.33 Ga _0.65 N can be used for the p-side barrier layer BLp. The thickness of the barrier layer can be set to 12.5 nm, for example.

For example, In _x3 Al _y3 Ga _1-x3-y3 N (0 <x3 ≦ 1, 0 ≦ y3 <1, x3 + y3 ≦ 1) ) Can be used. For example, In _0.15 Ga _0.85 N can be used for the well layer. The thickness of the well layer can be set to 2.5 nm, for example.

  The composition ratio of In contained in the well layer (ratio of the number of In atoms in the group III element) is determined by the barrier layers (first to fourth barrier layers BL1 to BL4, Nth barrier layer, and p-side barrier layer BLp). ) In the composition ratio of In (the ratio of the number of In atoms in the group III element). Thereby, the band gap energy in the barrier layer can be made larger than the band gap energy in the well layer.

For example, In _x4 Ga _1-x4 N (0 ≦ x4 <1) can be used for the first intermediate layer IL1. For example, In _0.02 Ga _0.98 N can be used for the first intermediate layer IL1. The thickness of the first intermediate layer IL1 can be set to 0.5 nm, for example.

For example, In _x5 Ga _1-x5 N (0 ≦ x5 <1) can be used for the second intermediate layer IL2. For example, In _0.02 Ga _0.98 N can be used for the second intermediate layer IL2. The thickness of the second intermediate layer IL2 can be set to 0.5 nm, for example.

  The composition ratio of In contained in the well layer (ratio of the number of In atoms in the group III element) is the composition ratio of In contained in the first intermediate layer IL1 and the second intermediate layer IL2 (in the group III element). Higher than the ratio of the number of In atoms). Thereby, the band gap energy in the first intermediate layer IL1 and the second intermediate layer IL2 can be made larger than the band gap energy in the well layer.

  The first intermediate layer IL1 can also be regarded as a part of the barrier layer. The second intermediate layer IL2 can also be regarded as a part of the barrier layer. That is, the barrier layer stacked with the well layer may include a plurality of layers having different compositions.

  In the SQW structure illustrated in FIG. 2A, the first intermediate layer IL1 and the second intermediate layer IL2 may be provided. In this case, the first intermediate layer IL1 is provided between the first barrier layer BL1 and the first well layer WL1, and the second intermediate layer IL2 is formed between the first well layer WL1 and the p-side barrier layer BLp. Between.

  The above is an example of the configuration of the light emitting layer 30, and the embodiment is not limited thereto, and the materials and thicknesses used for the barrier layer, the p-side barrier layer BLp, the well layer, the first intermediate layer IL1, and the second intermediate layer IL2. Various modifications are possible. As described above, the barrier layer, the p-side barrier layer BLp, the well layer, the first intermediate layer IL1, and the second intermediate layer IL2 include a nitride semiconductor.

  Hereinafter, the semiconductor light emitting device 110 including the semiconductor light emitting devices 110a to 110c will be described with respect to the present embodiment. The semiconductor light emitting device 110 can be manufactured by the following method, for example.

  For example, on the substrate 5 for crystal growth of sapphire, a nitride semiconductor layer to be the semiconductor stacked portion 10s is sequentially grown using, for example, a metal organic vapor deposition (MOCVD) method. Thereafter, for example, the semiconductor stacked portion 10 s is processed, a part of the first semiconductor layer 10 is exposed, and the counter-side electrode 70 is formed on the first semiconductor layer 10.

  On the other hand, an Ag film to be the metal layer 80 is formed on the second p-side layer 22 (p-type contact layer) of the semiconductor stacked unit 10s. Next, after annealing (heat treatment) at 800 ° C. in a nitrogen atmosphere, for example, annealing at 300 ° C. is performed in an oxygen atmosphere. Thereby, the metal layer 80 is formed. Note that the order of the formation of the metal layer 80 and the formation of the counter electrode 70 may be interchanged.

  Thus, by subjecting the Ag film to high-temperature annealing in a nitrogen atmosphere and then low-temperature annealing in an oxygen atmosphere, a semiconductor light emitting device having a low contact resistance and a high reflectivity electrode can be obtained.

FIG. 3 is a graph illustrating characteristics of the semiconductor light emitting device.
FIG. 3 shows the contact resistance Rc (specific contact resistivity) between the Ag film and the second semiconductor layer 20 of a sample obtained by annealing the Ag film formed on the second semiconductor layer 20 under various conditions. ing. In this example, the annealing time is 1 min (minute). The horizontal axis represents the annealing temperature Ta (° C.), and the vertical axis represents the contact resistance Rc (Ωcm ² ). FIG. 3 shows an oxygen annealed sample group SPO in which the Ag film is annealed in an oxygen atmosphere, and a nitrogen annealed sample group SPN in which the Ag film is annealed in a nitrogen atmosphere.

As shown in FIG. 3, the contact resistance Rc of the oxygen annealed sample group SPO obtained by annealing the Ag film in an oxygen atmosphere is 1.5 × 10 ⁻⁴ Ωcm ² when the annealing temperature Ta is 200 ° C. to 400 ° C. The above is 6 × 10 ⁻⁴ Ωcm ² or less. On the other hand, the contact resistance Rc of the nitrogen annealed sample group SPN obtained by annealing the Ag film in a nitrogen atmosphere is 5 × 10 ⁻³ Ωcm ² or more and 4 × 10 ⁻² Ωcm ² or less. That is, the contact resistance Rc in the annealing in the oxygen atmosphere is lower than the contact resistance in the annealing in the nitrogen atmosphere.

  The reflectance of these samples is as follows. The reflectance of 450 nm light of the sample annealed under various conditions was measured, and the difference (R0−R1) between the reflectance R1 and the reflectance R0 of the unannealed Ag film was the reflectance reduction value ΔRf. And In the sample SPO300 annealed at 300 ° C. in an oxygen atmosphere, the reflectance drop value ΔRf is about 6%. On the other hand, in the sample SPN300 annealed at 300 ° C. in a nitrogen atmosphere, the reflectance drop value ΔRf is substantially 0, and no change is observed.

4A to 4D are electron micrographs illustrating the characteristics of the semiconductor light emitting device.
These figures are SEM photographic images of a sample SPO300 annealed at 300 ° C. in an oxygen atmosphere, a sample SPO500 annealed at 500 ° C. in an oxygen atmosphere, a sample SPN300 annealed at 300 ° C. in a nitrogen atmosphere, and a sample SPN500 annealed at 500 ° C. in a nitrogen atmosphere. Respectively. The SEM photographic image is an image taken along the Z-axis direction and corresponds to observing the XY plane.

  As shown in FIGS. 4A and 4B, in the annealing in an oxygen atmosphere, the grains 301 are three-dimensionally grown. Furthermore, at 500 ° C., holes are formed. In oxygen atmosphere annealing, it is considered that Ag migration occurs.

  On the other hand, as shown in FIGS. 4C and 4D, in the annealing in the nitrogen atmosphere, the grains 301 are two-dimensionally grown while maintaining a flat surface. It is considered that migration is suppressed under this annealing condition.

  It is considered that the difference in the reflectance change between the oxygen atmosphere and the nitrogen atmosphere is related to the morphology of the Ag film, that is, the degree of migration.

  As described above, in the annealing in an oxygen atmosphere, a low contact resistance Rc is obtained, but the reflectance is low. On the other hand, in the annealing in a nitrogen atmosphere, the contact resistance Rc is high, but a high reflectance can be maintained.

  The inventor of the present application prepared various samples after annealing the Ag film in a nitrogen atmosphere and further annealing in an oxygen atmosphere. As a result, it was found that a low contact resistance Rc and a high reflectance (small reflectance reduction value ΔRf) can be obtained under specific conditions.

FIG. 5 is a graph illustrating characteristics of the semiconductor light emitting device.
FIG. 5 shows the contact resistance Rc of a sample in which the Ag film is annealed in a nitrogen atmosphere and then annealed at 300 ° C. in an oxygen atmosphere. The horizontal axis represents the annealing temperature Tn (° C.) in a nitrogen atmosphere, and the vertical axis represents the contact resistance Rc (Ωcm ² ).

As shown in FIG. 5, when the annealing temperature Tn in the nitrogen atmosphere is 700 ° C. or higher and 800 ° C. or lower, or 300 ° C. or higher and 400 ° C. or lower, the contact resistance Rc is 1.5 × 10 ^−4. It becomes Ωcm ² or more and 1.5 × 10 ⁻³ Ωcm ² or less. When the temperature Tn of annealing in the nitrogen atmosphere is 500 ° C. or more and 600 ° C. or less, the contact resistance Rc is remarkably high at about 2.0 × 10 ⁻² Ωcm ² or more. When the annealing temperature Tn in a nitrogen atmosphere is 600 ° C., the contact resistance Rc is too high to be measured.

FIG. 6 is a graph illustrating characteristics of the semiconductor light emitting device.
FIG. 6 shows the change in reflectance of a sample that was annealed at 300 ° C. in an oxygen atmosphere after the Ag film was annealed in a nitrogen atmosphere. The horizontal axis represents the annealing temperature Tn (° C.) in a nitrogen atmosphere, and the vertical axis represents the reflectance reduction value ΔRf (%).

  As shown in FIG. 6, when the annealing temperature Tn in the nitrogen atmosphere is 300 ° C., the reflectivity reduction value ΔRf is as large as about 6%. On the other hand, when the annealing temperature Tn in the nitrogen atmosphere is 800 ° C., the reflectivity reduction value ΔRf is as small as about 3%.

  As described above, the Ag film is annealed at a high temperature (eg, 700 ° C. or more, eg, 800 ° C. or less) in a nitrogen atmosphere, and then annealed at a low temperature (eg, about 300 ° C.) in an oxygen atmosphere. Contact resistance Rc and high reflectivity (small reflectivity drop value ΔRf) are obtained.

FIG. 7A and FIG. 7B are electron micrographs illustrating the characteristics of the semiconductor light emitting device.
FIG. 7A is a SEM photographic image of the sample SPNO1, which was annealed at 300 ° C. in an oxygen atmosphere after annealing at 800 ° C. in a nitrogen atmosphere. FIG. 7B is a SEM photographic image of the sample SPNO2 that was annealed at 300 ° C. in an oxygen atmosphere after annealing at 300 ° C. in a nitrogen atmosphere. The SEM photographic image is an image taken along the Z-axis direction and corresponds to observing the XY plane.

  As shown in FIG. 7A, in the sample SPNO1, the grains 301 are greatly grown two-dimensionally. The state of the sample SPNO1 is substantially the same as the state of the samples SPN300 and SPN500 (see FIGS. 4C and 4D) annealed in a nitrogen atmosphere. The small reflectance drop value ΔRf of about 3% in the sample SPNO1 is considered to be related to the large grain 301 observed by the SEM and the flat surface.

  On the other hand, as shown in FIG. 7B, the diameter of the grain 301 is small in the sample SPNO2. It can be considered that the large reflectance decrease value ΔRf in the sample SPNO2 is related to the small grain 301.

In the sample SPNO1, the average area of the plurality of grains 301 observed by the SEM is 5 μm ² or more and 100 μm ² or less. The average area of the plurality of grains 301 is in a plane perpendicular to the stacking direction from the second semiconductor layer 20 toward the metal layer 80 (for example, in a plane parallel to the interface 80a, that is, an XY plane). (Inner) of the grain 301. High reflectivity is obtained when a relatively large grain 301 is present.

  In the sample SPNO1, the comparatively large grain 301 exists and a high reflectance can be obtained because the Ag film becomes stronger by annealing at a high temperature in a nitrogen atmosphere, and the subsequent migration in an oxygen atmosphere. This is thought to be due to the suppression. On the other hand, in the sample SPNO2, the grain 301 is small and the reflectance is low because annealing in a nitrogen atmosphere is low temperature and migration is likely to occur in a subsequent oxygen atmosphere. it is conceivable that.

Thus, in the semiconductor light emitting device 110 according to the present embodiment, the metal layer 80 that is an Ag film can have a plurality of grains 301. The average area of the plurality of grains 301 is 5 μm ² or more and 100 μm ² or less. Thereby, a high reflectance is obtained.

In the semiconductor light emitting device 110, the specific contact resistivity (contact resistance Rc) between the metal layer 80 and the semiconductor stacked portion 10s (specifically, the second semiconductor layer 20) is 1.5 × 10 ^{−. It is 4} Ωcm ² or more and 1.5 × 10 ⁻³ Ωcm ² or less. Thereby, in the semiconductor light emitting device 110, an electrode (metal layer 80) having a low contact resistance and a high reflectance can be obtained.

FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9C are X-ray diffraction profile diagrams illustrating characteristics of the semiconductor light emitting device.
FIG. 8A shows an X-ray diffraction (XRD) profile of a sample SPA in which an Ag film is formed and not annealed. FIGS. 8B, 8C, 9A, 9B, and 9C show a sample SPO300 (annealed at 300 ° C. in an oxygen atmosphere) and a sample SPO400 (in an oxygen atmosphere), respectively. 400 ° C. annealing), sample SPN300 (300 ° C. annealing in nitrogen atmosphere), sample SPNO2 (300 ° C. annealing in nitrogen atmosphere + 300 ° C. annealing in oxygen atmosphere), and sample SPNO1 (800 ° C. annealing in nitrogen atmosphere + 300 in oxygen atmosphere) The XRD profile of (annealing at 0 ° C.) is shown. These horizontal axes are twice the inclination angle θ in measurement (2θ (degrees)), and the vertical axis is the logarithm (relative value) of the intensity INT.

As shown in FIG. 9A, in the sample SPA that is not annealed, a peak attributed to the (111) plane of Ag is obtained when 2θ is about 38 degrees, and Ag ( A peak attributed to the (100) plane is obtained. In these samples, when 2θ is about 42 degrees, a peak attributed to the (0006) plane of Al ₂ O ₃ as a substrate is also obtained. In the following, attention is focused on the peak attributed to the (111) plane of Ag (2θ is about 38 degrees) and the peak attributed to the (100) plane of Ag (2θ is about 44 degrees).

  As shown in FIG. 8B, FIG. 8C, FIG. 9A, and FIG. 9B, in the sample SPO300, the sample SPO400, the sample SPN300, and the sample SPNO2, the (100) plane of Ag is used. The attributed peak is relatively high. The height of the peak attributed to the (100) plane of Ag is greater than 3% of the height of the peak attributed to the (111) plane of Ag. Here, for example, an average value of the intensity INT in a range where 2θ is 46 degrees or more and 48 degrees or less is used as a reference value (background value). That is, the height of the peak attributed to the (100) plane of Ag is the ratio of the intensity INT when 2θ is 44 degrees to the reference value (average value of the intensity INT when 2θ is 46 degrees or more and 48 degrees or less). . The height of the peak belonging to the (100) plane of Ag is the ratio of the intensity INT when 2θ is 38 degrees to the reference value.

  On the other hand, as shown in FIG. 9C, in the sample SPNO1, the peak attributed to the (100) plane of Ag is very low. That is, the height of the peak attributed to the (100) plane of Ag is 3% or less of the height of the peak attributed to the (111) plane of Ag. This corresponds to the fact that the metal layer 80 is preferentially oriented to <111> in the sample SPNO1. When preferentially oriented to <111>, it means that there are more parts oriented in the <111> direction than parts oriented in directions other than the <111> direction. When preferentially oriented to <111>, in X-ray diffraction analysis, a peak attributed to a plane other than the (111) plane (specifically, the (100) plane) is a peak attributed to the (111) plane. It is 3% or less of the height. The state in which the metal layer 80 is preferentially oriented to <111> can be evaluated, for example, by analysis using an electron beam.

  Thus, it was found that the crystal structure is unique in the metal layer 80 (Ag film) having low contact resistance and high reflectance. That is, when the height of the peak attributed to the (100) plane of the Ag film is 3% or less of the height of the peak attributed to the (111) plane of Ag, the low contact resistance Rc and the high reflectance (small reflection). The rate reduction value ΔRf) is obtained.

FIG. 10 is a graph illustrating characteristics of the semiconductor light emitting device.
FIG. 10 shows a SIMS (secondary ion mass spectrometry) profile of a sample in which the annealing temperature Tn in a nitrogen atmosphere is changed between 500 ° C. and 800 ° C. FIG. 10 shows the intensity distribution of Ga atoms in the second semiconductor layer 20 and the metal layer 80 (Ag layer). The horizontal axis in FIG. 10 is the depth Zd (position along the Z-axis direction). The vertical axis represents the detected intensity Int (Ga) (relative value) of Ga atoms and is expressed in logarithm.

Sample N5O3 is annealed at 300 ° C. in an oxygen atmosphere after annealing at 500 ° C. in a nitrogen atmosphere.
In the sample N6O3, after annealing at 600 ° C. in a nitrogen atmosphere, annealing at 300 ° C. is performed in an oxygen atmosphere.
Sample N7O3 is annealed at 300 ° C. in an oxygen atmosphere after annealing at 700 ° C. in a nitrogen atmosphere.
Sample N8O3 is annealed at 300 ° C. in an oxygen atmosphere after annealing at 800 ° C. in a nitrogen atmosphere. Sample N8O3 corresponds to sample SPNO1 described above.

  FIG. 10 also illustrates the characteristics of the sample SPA in which an Ag film is formed and annealing is not performed. FIG. 10 also illustrates the characteristics of the sample N8OX. In the sample N8OX, annealing is performed at 800 ° C. in a nitrogen atmosphere, and annealing is not performed in an oxygen atmosphere.

As shown in FIG. 10, in the sample SPA that is not annealed, the detected intensity Int (Ga) of Ga atoms in the metal layer 80 (Ag layer) is less than about 1 × 10 ¹ . The detected intensity of Ga atoms in the second semiconductor layer 20 is about 1 × 10 ⁶ . In the sample SPA that is not annealed, the Ga concentration is lower than 1 × 10 ⁻⁵ times the Ga concentration in the second semiconductor layer 20. In the sample SPA, Ga is not substantially detected from the metal layer 80.

Then, Ga is detected from the metal layer 80 by annealing.
In the sample N8OX (oxygen atmosphere annealing is not performed with nitrogen atmosphere 800 ° C. annealing), the detected intensity Int (Ga) of Ga atoms in the metal layer 80 is, for example, about 3 × 10 ^{2 to} 3 × 10 ³ .

In the sample N5O3 (after annealing at 500 ° C. in a nitrogen atmosphere + 300 ° C. annealing in an oxygen atmosphere), the detected intensity Int (Ga) of Ga atoms in the metal layer 80 is, for example, about 7 × 10 ¹ to 2 × 10 ^3. It is.

In the sample N6O3 (after annealing at 600 ° C. in a nitrogen atmosphere + 300 ° C. annealing in an oxygen atmosphere), the detection intensity Int (Ga) of Ga atoms in the metal layer 80 is, for example, about 1 × 10 ^{4 to} 5 × 10 ⁴ . .

In the sample N7O3 (after annealing at 700 ° C. in a nitrogen atmosphere + 300 ° C. annealing in an oxygen atmosphere), the detection intensity Int (Ga) of Ga atoms in the metal layer 80 is, for example, about 5 × 10 ^{3 to} 3 × 10 ⁴ . is there.

In the sample N8O3 (after annealing at 800 ° C. in a nitrogen atmosphere + 300 ° C. annealing in an oxygen atmosphere), the detection intensity Int (Ga) of the Ga atom in the metal layer 80 is, for example, about 3 × 10 ³ to 2 × 10 ⁴ . is there.

  Thus, in the sample N5O3 where the annealing temperature Tn in the nitrogen atmosphere is as low as 500 ° C., the Ga concentration in the metal layer 80 is low. When the annealing temperature Tn in the nitrogen atmosphere is increased from 500 ° C. to 600 ° C., the Ga concentration in the metal layer 80 increases rapidly. When the annealing temperature Tn in the nitrogen atmosphere is 700 ° C. to 800 ° C., the Ga concentration in the metal layer 80 is lower than the value of 600 ° C.

  When the annealing temperature Tn in the nitrogen atmosphere is as low as 500 ° C., it is natural that the Ga concentration in the metal layer 80 is low. On the other hand, when the annealing temperature Tn in the nitrogen atmosphere is 600 ° C., the Ga concentration in the metal layer 80 is very high, and when the annealing temperature Tn in the nitrogen atmosphere becomes 700 ° C. or more, the Ga in the metal layer 80 is increased. The low concentration is a phenomenon observed for the first time in this experiment.

As described with reference to FIG. 5, when the annealing temperature Tn in the nitrogen atmosphere is 700 ° C. or higher and 800 ° C. or lower, a low contact resistance Rc is obtained. When the annealing temperature Tn is 500 ° C. or higher and 600 ° C. or lower, the contact resistance Rc is high. Sometimes, when the annealing temperature Tn is 600 ° C., the contact resistance is so high that it cannot be measured. As described with reference to FIG. 3, in the sample N8OX that is not annealed in an oxygen atmosphere, the contact resistance Rc is about 6 × 10 ⁻³ (Ωcm ² ), which is high.

  There is a correlation between the relationship between the contact resistance Rc and the annealing temperature Tn shown in FIG. 5 and the relationship between the Ga concentration in the metal layer 80 and the annealing temperature Tn shown in FIG.

  That is, if the annealing temperature Tn is too low, such as about 500 ° C., the Ga concentration in the metal layer 80 is low and the contact resistance Rc is also high. When the annealing temperature Tn is about 600 ° C., the Ga concentration in the metal layer 80 is remarkably high, and the contact resistance Rc is remarkably high. When the annealing temperature Tn exceeds 600 ° C. and becomes as high as 700 ° C. or more and 800 ° C. or less, the Ga concentration in the metal layer 80 is medium and the contact resistance Rc is lowered.

  If the Ga concentration in the metal layer 80 is too low or too high, the contact resistance Rc increases. A low contact resistance Rc is obtained when the Ga concentration in the metal layer 80 is in the range of a certain level. Until now, it has not been known that there is an appropriate range for obtaining a low contact resistance Rc in the Ga concentration in the metal layer 80.

  In the SIMS analysis, the Ga concentration is detected as a relative value. As illustrated in FIG. 10, the Ga concentration changes in the region including the interface between the metal layer 80 and the second semiconductor layer 20. An example of an index that quantitatively indicates the Ga concentration in the metal layer 80 is introduced.

  In this index, in the SIMS analysis in the region including the second semiconductor layer 20 and the metal layer 80 (Ag layer), the intensity of “Ga + N” is measured in addition to the intensity of Ga atoms. The intensity of “Ga + N” is, for example, the detected intensity of a complex of gallium atoms and nitrogen atoms. Based on the detection intensity characteristic of “Ga + N” (composite), a reference position in the region including the metal layer 80 and the second semiconductor layer 20 is defined. Based on the reference position, the Ga concentration in the metal layer 80 is defined.

FIG. 11A to FIG. 11F are graphs illustrating characteristics of the semiconductor light emitting element.
11A to 11F correspond to the sample N5O3, the sample N6O3, the sample N7O3, the sample N8O3, the sample SPA, and the sample N8OX, respectively. These figures are examples of SIMS analysis results. The horizontal axis is the depth Zd. The vertical axis represents the detection intensity of Ga atoms or the detection intensity of “Ga + N” (complex). The vertical axis is a relative value and is expressed in logarithm.

For example, as illustrated in FIG. 11A, the maximum value V1 of the detected intensity of “Ga + N” (complex) in the second semiconductor layer 20 is about 1.4 × 10 ³ . A position in the depth Zd direction where the detection intensity of “Ga + N” (complex) becomes 1/100 of the maximum value V1 is defined as a first position IF. The first position IF may be regarded as an interface between the metal layer 80 and the second semiconductor layer 20. The first position IF is a position in the stacking direction from the second semiconductor layer 20 toward the metal layer 80 in a region including the second semiconductor layer 20 and the metal layer 80 (Ag layer). The detection intensity V2 of “Ga + N” (complex) at the first position IF is 1/100 of the maximum value V1.

  In the metal layer 80, a position (second position) 40 nm away from the first position IF along the Z-axis direction (stacking direction) is defined as a concentration defining position P0. In the embodiment, the thickness of the metal layer 80 (Ag layer) is practically, for example, not less than 40 nm and not more than 1000 nm. For this reason, the second position (concentration definition position P0) 40 nm away from the first position IF along the Z-axis direction (stacking direction) is included in the metal layer 80.

On the other hand, the detected intensity of Ga atoms in the second semiconductor layer 20 is the detected intensity of Ga atoms at a position sufficiently away from the first position IF. For example, in the examples of FIGS. 11A to 11F, the detected intensity of Ga atoms in the second semiconductor layer 20 is substantially constant when the distance from the first position IF is 100 nm or more. The detection intensity of Ga atoms at a position sufficiently away from the first position IF is the maximum value V1 of the detection intensity of Ga atoms in the second semiconductor layer 20. For example, the maximum value V1 of the detected intensity of Ga atoms in the second semiconductor layer 20 is the detected intensity of Ga atoms at a position where the distance from the first position IF is 100 nm. In any sample, the maximum value V3 of the detected intensity of Ga atoms in the second semiconductor layer 20 is about 1 × 10 ⁶ .

  In each sample, the detected intensity V4 of Ga atoms at the concentration defining position P0 in the metal layer 80 is different from each other.

In the sample N5O3, the detected intensity V4 of Ga atoms at the concentration defining position P0 is about 1.5 × 10 ³ . In the sample N5O3, the detection intensity V4 is about 0.1% of the maximum value V3 of the Ga atom detection intensity in the second semiconductor layer 20.
In the sample N6O3, the detected intensity V4 of Ga atoms at the concentration defining position P0 is about 4.5 × 10 ⁴ . In the sample N6O3, the detection intensity V4 is about 3.8% of the maximum detection intensity V3 of Ga atoms in the second semiconductor layer 20.
In the sample N7O3, the detected intensity V4 of Ga atoms at the concentration defining position P0 is about 2.0 × 10 ⁴ . In the sample N7O3, the detection intensity V4 is about 1.7% of the maximum detection intensity V3 of Ga atoms in the second semiconductor layer 20.
In the sample N8O3, the detected intensity V4 of Ga atoms at the concentration defining position P0 is about 1.4 × 10 ⁴ . In the sample N8O3, the detection intensity V4 is about 1.4% of the maximum value V3 of the Ga atom detection intensity in the second semiconductor layer 20.
In sample SPA, detected intensity V4 of Ga atoms at a concentration defined position P0 is about 2 × 10 ^0.
In the sample N8OX, the detected intensity V4 of Ga atoms at the concentration defining position P0 is about 4.2 × 10 ³ . In the sample N8OX, the detection intensity V4 is about 0.4% of the maximum value V3 of the Ga atom detection intensity in the second semiconductor layer 20.

  Therefore, using such a definition, when the detection intensity V4 is higher than 0.4% of the maximum value V3 of detection intensity of Ga atoms in the second semiconductor layer 20 and lower than 3.8%, a low contact is obtained. It can be seen that the resistance Rc is obtained.

  That is, in the embodiment, in SIMS analysis (secondary ion mass spectrometry), the stacking direction from the second semiconductor layer 20 to the metal layer 80 in the region including the second semiconductor layer 20 and the metal layer 80 (silver layer). The detection intensity V2 of the complex of gallium atoms and nitrogen atoms at the first position in FIG. 1 is 1/100 of the maximum value V1 of the detection intensity of the complex in the second semiconductor layer 20.

  In the secondary ion mass spectrometry, the detection intensity V4 of the gallium atom at the second position (concentration definition position P0) of the metal layer 50 with the distance from the first position IF of 40 nanometers is the second semiconductor layer 20. It is higher than 0.4% of the maximum value V3 of the detected intensity of gallium atoms in the inside and lower than 3.8%.

  Thereby, a low contact resistance can be obtained. The detection intensity V4 is desirably 1.4% or more of the maximum value V3 of the detection intensity of gallium atoms in the second semiconductor layer 20. The detection intensity V4 is desirably 1.7% or less of the maximum value V3 of the detection intensity of gallium atoms in the second semiconductor layer 20.

  The distance along the Z-axis direction (stacking direction from the second semiconductor layer 20 toward the metal layer 80) between the second position (concentration definition position P0) and the first position IF is, for example, 40 nm.

  At the first position IF, the detection intensity of the complex of gallium atoms and nitrogen atoms detected by SIMS analysis (secondary ion mass spectrometry) is the difference between the gallium atoms and nitrogen atoms in the second semiconductor layer 20. It is 1/100 of the maximum value of the detection intensity of the complex.

  The maximum value V3 of the Ga concentration in the second semiconductor layer 20 is, for example, a distance along the Z-axis direction between the metal layer 80 and the first position IF of the second semiconductor layer 20 in the second semiconductor layer 20. Is the detected intensity of Ga atoms at a position of 100 nm.

  If the SIMS analysis regarding the region including the metal layer 80 and the second semiconductor layer 20 can analyze a sample that is not annealed (for example, the sample SPA), the following definitions can also be used.

The first definition is as follows.
In the sample SPA illustrated in FIG. 10, a position where the detected intensity of Ga atoms is constant in the second semiconductor layer 20 is defined as a reference position ps. In this example, the detected intensity Int (Ga) of Ga atoms at the reference position ps is about 1 × 10 ⁶ .
In the region including the metal layer 80 and the second semiconductor layer 20, the first interface position p01 is set. The first interface position p01 is a position in the depth Zd direction. At the first interface position p01, the Ga atom detection intensity Int (Ga) is 1 / e of the Ga atom detection intensity Int (Ga) at the reference position ps. “E” is the base of the natural logarithm.

  As described above, the first interface position p01 is determined by the sample SPA as the reference position in the thickness Zd direction in the SIMS analysis. In this example, the position where the depth Zd is about 170 nm is the first interface position p01.

  In each sample, a region in which the Ga concentration in the metal layer 80 decreases and a region in which the Ga concentration increases in the Z-axis direction from the second semiconductor layer 20 toward the metal layer 80 are observed. In SIMS analysis, in general, the detection value is not necessarily correct in a region close to the surface (a region where the depth Zd is 10 nm or less). In order to exclude the value of this region, for convenience, the Ga concentration in the metal layer 80 decreases in the second semiconductor layer 20 along the Z-axis direction from the second semiconductor layer 20 to the metal layer 80. This region is used as a region for defining the Ga concentration.

In each sample, the position where the detected intensity of Ga atoms in the metal layer 80 is minimized is defined as the minimum position. Then, the detected intensity of Ga atoms in the metal layer 80 is maximized at the first interface position p01. In the depth Zd direction, an intermediate position between the minimum position and the first interface position p01 is set as an intermediate position. The detected intensity (first detected intensity) of Ga atoms at the intermediate position can be used as the detected intensity of Ga atoms in the metal layer 80 in each sample. The ratio of the Ga atom detection intensity at the intermediate position to the Ga atom detection intensity Int (Ga) (about 1 × 10 ⁶ ) at the reference position ps is defined as a first ratio R1.

For example, in the sample N5O3, the first detection intensity is about 2 × 10 ² and the first ratio R1 is about 0.01%.
For example, in the sample N6O3, the first detection intensity is about 3 × 10 ⁴ and the first ratio R1 is about 3%.
For example, in the sample N7O3, the first detection intensity is about 1.4 × 10 ⁴ and the first ratio R1 is about 1.2%.
For example, in the sample N8O3, the first detection intensity is about 7 × 10 ³ and the first ratio R1 is about 0.7%.
For example, in the sample N8OX, the first detection intensity is about 1 × 10 ³ and the first ratio R1 is about 0.1%.

  When this definition is used, the first ratio R1 is preferably larger than 0.1% and smaller than 3%. The first ratio R1 is preferably 0.7% or more. The first ratio R1 is preferably 1.2% or less.

The second definition is as follows.
In the sample SPA illustrated in FIG. 10, the second interface position p02 is set in a region including the metal layer 80 and the second semiconductor layer 20. The second interface position p02 is a position in the depth Zd direction. At the second interface position p02, the detected intensity Int (Ga) of Ga atoms is 1 / 100,000 of the detected intensity Int (Ga) of Ga atoms at the reference position ps.

Also in this case, the reference position ps is a position where the detection intensity of Ga atoms is constant in the second semiconductor layer 20, and the detection intensity Int (Ga) of Ga atoms at the reference position ps is about 1 × 10 ⁶ . . In the same manner as the first definition, the Ga concentration in the metal layer 80 is defined.

That is, the position where the detected intensity of Ga atoms in the metal layer 80 is minimized is defined as the minimum position. At the second interface position p02, the detected intensity of Ga atoms in the metal layer 80 is maximized. In the depth Zd direction, the average value (second detection intensity) of Ga atom detection intensity between the minimum position and the second interface position p02 is detected in each sample. Used as strength. The ratio of the average value of the Ga atom detection intensity to the Ga atom detection intensity Int (Ga) (about 1 × 10 ⁶ ) at the reference position ps is defined as a second ratio R2.

  In each sample, the second detection intensity is substantially the same value as the first detection intensity. In the case where the second definition is used, the second ratio R2 is preferably larger than 0.1% and smaller than 3%. The second ratio R2 is preferably 0.7% or more. The second ratio R2 is preferably 1.2% or less.

FIG. 12 is a schematic cross-sectional view illustrating the configuration of another semiconductor light emitting element according to the first embodiment.
As shown in FIG. 12, another semiconductor light emitting device 120 according to the present embodiment includes a counter electrode 70, a support substrate portion 90, an adhesive metal layer 82, in addition to the semiconductor stacked portion 10 s and the metal layer 80. Is further provided. In the semiconductor light emitting device 120, the metal layer 80 is electrically connected to the second semiconductor layer 20, and the counter electrode 70 is electrically connected to the first semiconductor layer 10.

  The support substrate unit 90 includes a conductive substrate 93 and a conductive layer 92 provided on the conductive substrate 93. For example, a silicon substrate is used as the conductive substrate 93. The adhesive metal layer 82 is provided between the conductive layer 92 and the counter electrode 70, and electrically connects the conductive layer 92 and the counter electrode 70. The adhesive metal layer 82 and the conductive layer 92 are joined to each other. By applying a voltage between the conductive substrate 93 and the counter electrode 70, a current flows through the light emitting layer 30 and light is emitted.

  In this example, the unevenness 10p is formed on the surface 10u (second main surface 10b) of the first semiconductor layer 10 opposite to the light emitting layer 30. The height of the unevenness 10p is, for example, larger than the dominant wavelength of the light emitted from the light emitting layer 30.

  Also in this case, the metal layer 80 is <111> oriented. For example, the height of the peak attributed to the (100) plane is 3% or less of the height of the peak attributed to the (111) plane of Ag.

Further, the average area of the plurality of grains 301 of the metal layer 80 is 5 μm ² or more and 100 μm ² or less. The contact resistance Rc between the metal layer 80 and the semiconductor stacked portion 10 s is 1.50 × 10 ⁻⁴ Ωcm ² or more and 1.5 × 10 ⁻³ Ωcm ² or less.

  As described above, the semiconductor light emitting device 120 can also provide a semiconductor light emitting device having a low contact resistance and a high reflectivity electrode.

Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 120 will be described.
FIGS. 13A to 13C and FIGS. 14A and 14B are schematic cross-sectional views in order of the processes, illustrating another method for manufacturing a semiconductor light emitting device according to the first embodiment. It is.
In the following manufacturing method, for example, metal organic chemical vapor deposition (MOCVD) is used for crystal growth of a semiconductor layer. In addition, crystal growth may be performed by molecular beam epitaxy (MBE).

As shown in FIG. 13A, the buffer layer 6 is formed on the main surface of the substrate 5 such as c-plane sapphire. Various materials such as GaN, SiC, Si, and GaAs can be used for the substrate 5 in addition to sapphire. For the buffer layer 6, for example, an Al _x0 Ga _1-x0 N (0 ≦ x0 ≦ 1) layer is used. A crystal of the first semiconductor layer 10 is grown on the buffer layer 6. For example, an n-type GaN layer is used for the first semiconductor layer 10. A crystal of the light emitting layer 30 is grown on the first semiconductor layer 10. Various configurations described with reference to FIGS. 2A to 2C are applied to the light emitting layer 30. A crystal of the second semiconductor layer 20 is grown on the light emitting layer 30. For example, a p-type GaN layer is used for the second semiconductor layer 20.

  An Ag film to be the metal layer 80 is formed on the second semiconductor layer 20. Thereafter, annealing is performed at 800 ° C. for 1 min in a nitrogen atmosphere, and then annealing is performed at 300 ° C. for 1 min in an oxygen atmosphere. Thereby, the metal layer 80 is obtained. A Ti film, a Pt film, and an Au film are laminated in this order so as to cover the metal layer 80, thereby forming an adhesive metal layer 82.

  As shown in FIG. 13B, a support substrate portion 90 having a conductive substrate 93 (for example, a silicon substrate) and a conductive layer 92 provided on the main surface of the conductive substrate 93 is prepared. The conductive layer 92 and the adhesive metal layer 82 are opposed to each other. As the conductive layer 92, a layer containing Au and Sn is used. In a state where the conductive layer 92 and the adhesive metal layer 82 are in contact with each other, a pressure is applied for a certain time at a high temperature of, for example, 250 ° C. or higher.

  Thereby, as shown in FIG. 13C, the adhesive metal layer 82 and the conductive layer 92 are bonded to each other.

Then, an ultraviolet laser (for example, a laser having a KrF wavelength of 248 nm) is pulsed from the side of the substrate 5 opposite to the first semiconductor layer 10.
Thereby, as illustrated in FIG. 14A, the semiconductor stacked unit 10 s is peeled from the substrate 5. Thus, by removing the substrate 5 used when forming the semiconductor stacked portion 10 s, the semiconductor light emitting device 120 can improve heat dissipation and obtain high light emission efficiency.

  Thereafter, the semiconductor stacked portion 10s is processed into a predetermined shape. That is, a plurality of semiconductor stacked portions 10 s are formed on the substrate 5 and are separated for each of the plurality of semiconductor stacked portions 10 s. At this time, the adhesive metal layer 82 is not patterned between the plurality of separated semiconductor stacked portions 10s, and the adhesive metal layer 82 is exposed between the semiconductor crystal films separated for each of the semiconductor stacked portions 10s. It will be in the state. Further, the patterned semiconductor crystal film has a tapered mesa shape, for example.

Next, as a protective layer, for example, a SiO ₂ film is formed. Note that the mesa shape improves the coverage of the protective layer. A part of the protective layer is removed to expose the surface of the first semiconductor layer 10.

  As shown in FIG. 14B, the counter electrode 70 is formed on the surface of the first semiconductor layer 10. Thereafter, the first semiconductor layer 10 is wet etched. In this etching, for example, the etching is performed for 15 minutes using potassium hydroxide having a concentration of 1 mol / l and a temperature of 70 ° C. Thereby, the surface of the first semiconductor layer 10 is roughened. That is, the unevenness 10 p is formed on the surface of the first semiconductor layer 10.

For the counter electrode 70, for example, an alkali-resistant material is used. For the counter electrode 70, for example, at least one of Pt, Au, Ni, and Ti is used. By using this material, the size (height difference) of the unevenness 10p formed by alkali etching can be increased.
The semiconductor light emitting device 120 illustrated in FIG. 12 can be manufactured through the steps as described above.

(Second Embodiment)
The present embodiment relates to a method for manufacturing a semiconductor light emitting device.
FIG. 15 is a flowchart illustrating the method for manufacturing the semiconductor light emitting element according to the second embodiment.
As illustrated in FIG. 15, a metal film (silver film) containing Ag is formed on the semiconductor stacked portion 10 s including the light emitting layer 30 and including the nitride semiconductor (Step S <b> 110). A first heat treatment step is performed in which the metal film is heat-treated in an atmosphere containing nitrogen (step S120). Further, after the first heat treatment step, a second treatment step is performed in which the metal film is heat treated in an atmosphere containing oxygen (step S130). The temperature of the heat treatment in the first heat treatment step is higher than the temperature of the heat treatment in the second heat treatment step. Thereby, a semiconductor light emitting device having an electrode having a low contact resistance and a high reflectance can be manufactured.

  The temperature of the heat treatment in the first heat treatment step is 700 ° C. or higher and 800 ° C. or lower. The temperature of the heat treatment in the second heat treatment step is 200 ° C. or higher and 400 ° C. or lower. As a result, as described with reference to FIGS. 5 and 6, an electrode (metal layer 80) having a low contact resistance and a high reflectance can be obtained. The heat treatment time in the first heat treatment step is, for example, 1 min or more and 10 min or less. If it is less than 1 min, crystal growth is insufficient, and migration suppression in the second heat treatment step becomes insufficient. If it exceeds 10 min, damage to the semiconductor laminate may occur. The heat treatment time in the second heat treatment step is, for example, 30 seconds (seconds) or more and 1 minute or less. If it is less than 30 sec, the contact resistance is not sufficiently lowered. If it exceeds 1 min, migration is promoted and the reflectance is lowered.

  In the manufacturing method according to this embodiment, after the second heat treatment step, in the silver film (metal layer 80), the peak height attributed to the (100) plane of Ag in the X-ray diffraction analysis is Ag. For example, it is 3% or less of the height of the peak attributed to the (111) plane.

  After the second heat treatment step, in SIMS analysis, gallium in the first position IF in the stacking direction from the semiconductor layer to the silver film in the region including the semiconductor layer (second semiconductor layer 20 in this example) and the silver film. The detected intensity V2 of the complex of atoms and nitrogen atoms is 1/100 of the maximum value V1 of the detected intensity of the complex of gallium atoms and nitrogen atoms in the semiconductor layer.

  After the second heat treatment step, in the SIMS analysis, the detected intensity V4 of gallium atoms at the second position (concentration definition position P0) at a distance of 40 nm from the first position IF in the silver film is the gallium in the semiconductor layer. It is higher than 0.4% of the maximum value V3 of atomic detection intensity and lower than 3.8%. Thereby, a low contact resistance can be obtained. The detection intensity V4 is desirably 1.4% or more of the maximum value V3. It is desirable that the detection intensity V4 is 1.7% or less of the maximum value V3.

  According to the embodiment, a semiconductor light emitting device having an electrode with low contact resistance and high reflectivity is provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, the specific configuration of each element included in the semiconductor light-emitting element, such as a semiconductor layer, an n-type semiconductor layer, a p-type semiconductor layer, a light-emitting layer, a transparent electrode layer, and an electrode, is appropriately determined by those skilled in the art from a well-known range. The present invention is included in the scope of the present invention as long as the present invention can be carried out in the same manner and the same effects can be obtained.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting devices and methods for manufacturing the same that can be implemented by those skilled in the art based on the semiconductor light-emitting devices and methods for manufacturing the same described above as embodiments of the present invention are also included in the gist of the present invention. As long as it is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 5 ... Board | substrate, 6 ... Buffer layer, 10 ... 1st semiconductor layer, 10a ... 1st main surface, 10b ... 2nd main surface, 10p ... Unevenness, 10s ... Semiconductor laminated part, 11 ... 1n side layer, 12 ... 1st 2n side layer, 20 ... second semiconductor layer (semiconductor layer), 21 ... first p side layer, 22 ... second p side layer, 30 ... light emitting layer, 70 ... counter electrode, 80 ... metal layer (Ag layer), 80a DESCRIPTION OF SYMBOLS ... Interface, 82 ... Adhesive metal layer, 90 ... Support substrate part, 92 ... Conductive layer, 93 ... Conductive substrate, [Delta] Rf ... Reflectance reduction value, [theta] ... Angle, 110, 110a to 110c, 120 ... Semiconductor light emitting device, 301 ... Grain, BL ... Barrier layer, BL1 to BLn ... First to nth barrier layers, BLp ... P-side barrier layer, IF ... First position, IL1, IL2 ... First and second intermediate layers, INT ... Strength, Int ... Detection intensity, P0 ... Concentration constant Position (second position), Rc ... Contact resistance, V1, V3 ... Maximum value, V2, V4 ... Detection intensity WL ... Well layer, WL1-WLn ... First to nth well layer, Zd ... Depth, p01 ... 1 interface position, p02 ... second interface position, ps ... reference position

Claims (5)

A semiconductor stack including a light-emitting layer including a nitride semiconductor, and a semiconductor layer including gallium stacked on the light-emitting layer;
A silver layer in contact with the semiconductor layer;
With
In the silver layer, the peak height attributed to the (100) plane of silver in the X-ray diffraction analysis is 3% or less of the peak height attributed to the (111) plane of silver,
In the secondary ion mass spectrometry, the detection intensity of the complex of gallium atoms and nitrogen atoms at the first position in the stacking direction from the semiconductor layer to the silver layer in the region including the semiconductor layer and the silver layer is , 1/100 of the maximum value of the detected intensity of the complex in the semiconductor layer,
In the secondary ion mass spectrometry, the detected intensity of gallium atoms at the second position of the silver layer at a distance of 40 nanometers from the first position is the maximum value of the detected intensity of gallium atoms in the semiconductor layer. A semiconductor light emitting device having a value higher than 0.4% and lower than 3.8%.   2. The semiconductor light emitting element according to claim 1, wherein the detected intensity of gallium atoms at the second position is not less than 1.4% and not more than 1.7% of the maximum value of the detected intensity of gallium atoms in the semiconductor layer. 3. The semiconductor light emitting device according to claim 1, wherein the silver layer has a plurality of grains, and an average area of the plurality of grains in a plane perpendicular to the stacking direction is 5 μm ² or more and 100 μm ² or less. element. 4. The specific contact resistivity between the silver layer and the semiconductor stacked portion is 1.5 × 10 ⁻⁴ Ωcm ² or more and 1.5 × 10 ⁻³ Ωcm ² or less. The semiconductor light-emitting device described in 1. Forming a silver film on a semiconductor layer containing gallium provided on a light emitting layer of a nitride semiconductor;
A first heat treatment step in which the silver film is heat-treated in an atmosphere containing nitrogen;
A second heat treatment step of performing heat treatment on the silver film in an atmosphere containing oxygen after the first heat treatment step;
With
The temperature of the heat treatment in the first heat treatment step is higher than the temperature of the heat treatment in the second heat treatment step,
After the second heat treatment step, in the silver film, in the X-ray diffraction analysis, the peak height attributed to the silver (100) plane is 3% of the peak height attributed to the silver (111) plane. And
After the second heat treatment step, in secondary ion mass spectrometry, gallium atoms and nitrogen atoms at a first position in the stacking direction from the semiconductor layer to the silver film in a region including the semiconductor layer and the silver film And the detected intensity of the complex is 1/100 of the maximum detected intensity of the complex in the semiconductor layer,
After the second heat treatment step, in the secondary ion mass spectrometry, the detected intensity of gallium atoms in the second position of the silver film at a distance of 40 nanometers from the first position is in the semiconductor layer. A method for manufacturing a semiconductor light emitting device, which is higher than 0.4% of the maximum value of the detected intensity of gallium atoms and lower than 3.8%.