JP2013038580A - Image processor and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus for synthesizing image data for synthesis such as character printing or stamp printing and input image data.
An image processing apparatus (10, 120) includes: input image data 200; means for acquiring image data 210 that is smaller than input image data; and input image data from the image data for synthesis. A generation unit 134 that generates a synthesis target image data having a region corresponding to the data image and in which the image of the synthesis image data is arranged in a predetermined region, the acquired input image data, and the generated synthesis target image And an image composition unit 136 that uses the data to generate a composite image 220 in which the image of the image data for composition is combined with an area corresponding to the predetermined area of the input image data.
[Selection] Figure 4

Description

  The present invention relates to an image composition technique, and more specifically, an image processing apparatus for synthesizing image data for composition such as character printing and stamp printing and input image data, and for realizing the image processing apparatus. Regarding the program.

  2. Description of the Related Art Conventionally, an image composition function for synthesizing a predetermined image with an input image such as a scan image or a print image is known in an image processing apparatus such as a multifunction peripheral. Examples of the image compositing function include a stamp compositing function that synthesizes character printing such as date, page number, security management number, “secret”, and stamp printing such as “secret” into an input image and prints it out. be able to.

  In the image composition function, it is necessary to secure a sufficient memory capacity for performing image composition processing of the input image and the composition image. On the other hand, an increase in the capacity of a storage device such as a system memory or a local memory leads to an increase in cost. Therefore, there is a demand for improving the efficiency of image composition processing and reducing the amount of memory consumed.

  However, in the conventional image composition technique, it is necessary to prepare memory areas of the same size for the input image and the composition image and to secure a memory amount proportional to the image resolution in the application. For this reason, in the conventional image composition technique, the amount of memory consumed has increased with an increase in the resolution of the image regardless of the size of the composition image.

  Several conventional techniques for reducing the memory consumption amount are known, and a technique disclosed in Japanese Patent Laid-Open No. 2001-253134 (Patent Document 1) is known. The technique of Patent Document 1 was made for the purpose of solving the problem that the number and size of stamp print image data is limited by the amount of free memory, or that it is necessary to increase the memory, which often increases the cost. Is. In order to achieve this object, Patent Document 1 stores a technique for storing specific image data in a storage unit in a compressed state, and decompressing the specific image data stored in the storage unit and combining it with input image data. Disclose.

  According to the prior art disclosed in Patent Document 1, the memory consumption capacity can be somewhat reduced. However, the prior art disclosed in Patent Document 1 is a technique for synthesizing input image data developed on a memory and synthesis image data developed on a memory on the memory. For this reason, there is a case where the input image data cannot be reused because the composite image is overwritten on the input image, etc., and it is necessary to decompress the input image data and expand it in the memory each time the image is combined. It was insufficient in that it led to a decrease in productivity. An example of the case where the input image data cannot be reused is a case where security management numbering for printing different numbering for each copy unit is performed.

  The present invention has been made in view of the insufficiency in the prior art described above, and the present invention is suitable for the image composition of the input image data and the image data for composition, and appropriate consumption according to the size of the image for composition. To provide an image processing apparatus that enables image composition only by securing the amount of memory and, in turn, reduces the amount of memory consumed and speeds up image composition processing, and a program for realizing the image processing apparatus. With the goal.

  In order to solve the above problems, the present invention provides an image processing apparatus having the following features. The image processing apparatus includes means for acquiring input image data and means for acquiring image data for synthesis that is smaller than the input image data. The image processing apparatus further generates synthesis target image data having an area corresponding to the image of the input image data from the synthesis image data and in which the image of the synthesis image data is arranged in a predetermined area. Generating means. The image processing apparatus further synthesizes the image of the image data for synthesis into an area corresponding to the predetermined area of the input image data using the acquired input image data and the generated synthesis target image data. Image synthesizing means for generating the synthesized image.

  According to the present invention, it is possible to further provide a device executable program for realizing a circuit configuration that functions as each of the above means.

  According to the above configuration, it is possible to achieve image composition between the composition image data and the input image data only by securing the necessary minimum memory for the composition image data, reducing the required memory capacity and increasing the image composition processing speed. Is achieved.

2 is a diagram illustrating a schematic configuration of hardware and software of a multifunction machine according to the present embodiment. 2 is a diagram illustrating a hardware configuration of the multifunction peripheral according to the present embodiment and an image data flow during a copying operation. FIG. FIG. 3 is a detailed functional block diagram of an ASIC in the hardware configuration of the multifunction peripheral according to the present embodiment. The detailed functional block diagram of the synthetic | combination circuit by 1st Embodiment. The figure which shows typically the image composition process in 1st Embodiment. The detailed functional block diagram of the synthetic | combination circuit by 2nd Embodiment. The figure which shows typically the image composition process in 2nd Embodiment. The detailed functional block diagram of the synthetic | combination circuit by 3rd Embodiment. The figure which shows typically the image composition process in 3rd Embodiment. The figure which shows typically the image composition process in 4th Embodiment. The detailed functional block diagram of the synthetic | combination circuit by 5th Embodiment. The figure which shows typically the image composition process in 5th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the embodiments of the present invention are not limited to the embodiments described below. In the embodiment described below, as an example of an image processing apparatus that performs image composition, a multifunction peripheral having a plurality of image-related functions such as a copy, a scanner, a printer, and a facsimile will be described.

  FIG. 1 is a diagram for explaining a schematic configuration of hardware and software of a multifunction machine according to the present embodiment. A multifunction device 10 shown in FIG. 1 includes a software group 12 composed of a plurality of software components, a multifunction device activation unit 14, and a hardware resource group 16 composed of a plurality of hardware components.

  The multifunction device starting unit 14 is executed first when the multifunction device 10 is powered on, and starts the application layer 18 and the platform layer 20. For example, the multifunction machine starting unit 14 reads programs corresponding to the software components of the application layer 18 and the platform layer 20 from an external storage device such as a hard disk device (hereinafter referred to as HDD), and stores the read programs in the memory. Then, the MFP 10 is activated.

  In the embodiment shown in FIG. 1, the hardware resource group 16 includes a monochrome laser printer (B & W LP) 26, a color laser printer (Color LP) 28, an image converter 30, and other hardware such as a scanner and a facsimile. Hardware resource 32.

  The software group 12 includes an application layer 18 and a platform layer 20. The application layer 18 and the platform layer 20 operate on an appropriate operating system (hereinafter referred to as an OS) such as UNIX (registered trademark) or Windows (registered trademark).

  The application layer 18 includes various software components that execute processing specific to user services relating to image processing, such as printers, copies, fuckssimuli, and scanners. In the embodiment shown in FIG. 1, the application layer 18 includes a printer application 34, a copy application 36, a fucksimilar application 38, and a scanner application 40.

  The platform layer 20 interprets a processing request from the application layer 18 and generates a hardware resource acquisition request, a system service manager (hereinafter referred to as SRM) 58, and a handler layer. 24. The SRM 58 manages one or more pieces of hardware in the hardware resource group 16 and arbitrates acquisition requests from the control service layer 22. The handler layer 24 manages the hardware resource group 16 in response to the acquisition request from the SRM 58.

  In the embodiment shown in FIG. 1, the control service layer 22 includes a network control service (hereinafter referred to as NCS) 42, a delivery control service (hereinafter referred to as DCS) 44, and an operation panel control service. (Hereinafter referred to as “OCS”) 46, Facsimile Control Service (hereinafter referred to as FCS) 48, Engine Control Service (hereinafter referred to as ECS) 50, and Memory Control Service (hereinafter referred to as MCS). 52), a user information control service (hereinafter referred to as UCS) 54, and a system control service (hereinafter referred to as SCS) 56, including one or more service modules. The

  The platform layer 20 includes an API (Application Programming Interface) 66 that can receive a processing request from the application layer 18 by a predefined function. The OS executes the software components of the application layer 18 and the platform layer 20 in parallel as processes.

  The process of the NCS 42 provides a service that can be commonly used for applications that require network input / output. More specifically, the process of the NCS 42 distributes data received from the network side to each application according to various protocols, and executes mediation processing when transmitting data from each application to the network side. For example, the NCS 42 can control data communication with a network device connected via a network according to HTTP (HyperText Transfer Protocol Daemon) according to HTTP (HyperText Transfer Protocol).

  The process of the DCS 44 controls the distribution of stored documents. The process of the OCS 46 controls an operation panel serving as information transmission means between the operator of the multifunction machine 10 and the main body control. The process of the FCS 48 is performed by the application layer 18 to send and receive facsimiles via a PSTN (Public Switched Telephone Networks) network or ISDN (Integrated Services Digital Network) network, registration and citation of various facsimile data managed in a backup memory, An API for performing facsimile reading, facsimile reception printing, and the like is provided.

  The ECS 50 process controls an engine unit (not shown in FIG. 1) including a monochrome laser printer 26, a color laser printer 28, a hardware resource 32, and the like. The process of the MCS 52 performs memory control such as acquisition and release of memory and use of the HDD. The UCS 54 manages user information. The process of the SCS 56 performs application management, operation unit control, system screen display, LED display, hardware resource management, interrupt application control, and the like.

  The process of the SRM 58 performs system control of the multifunction peripheral and management of the hardware resource group 16 together with the SCS 56. The process of the SRM 58 performs execution control by performing arbitration according to an acquisition request from an upper layer using the hardware resource group 16 such as the monochrome laser printer 26 and the color laser printer 28.

  More specifically, the process of the SRM 58 determines whether the resource of the requested hardware resource group 16 is available, that is, whether it is not used by another acquisition request. If the process of the SRM 58 is available, it notifies the upper layer that the requested resource is available. Further, the process of the SRM 58 performs scheduling for using each resource of the hardware resource group 16 in response to an acquisition request from an upper layer, and directly executes the request content. Examples of the request contents include paper conveyance and image forming operation by a printer engine, memory reservation, file generation, and the like.

  The handler layer 24 includes a fax control unit handler (hereinafter referred to as FCUH) 60, an image memory handler (hereinafter referred to as IMH) 62, and a media edit utility (hereinafter referred to as MEU) 64. Including. The FCUH 60 manages a facsimile control unit (hereinafter referred to as FCU, which will be described later) included in the hardware resource 32. The IMH 62 allocates memory for the process and manages the memory allocated to the process. The MEU 64 controls the image converter 30. The SRM 58 and the FCUH 60 make a processing request for each resource of the hardware resource group 16 by using an engine I / F 68 that can transmit a processing request for the hardware resource group 16 by a predefined function.

  The multi-function device 10 can centrally process processes that are commonly required by the applications 34 to 40 in the platform layer 20.

  FIG. 2 is a diagram illustrating a hardware configuration diagram of the multifunction peripheral according to the present embodiment and an image data flow during a copy operation. 2 includes a controller 100, an operation panel 150, an FCU 152, an image converter 30, and an engine unit 160 including a scanner engine and a plotter engine.

  The controller 100 includes a CPU 110, a memory 112 including a system memory (MEM-P) and a local memory (MEM-C), an ASIC (Application Specific Integrated Circuit) 120, a hard disk device (HDD) 114, and a ROM (Read Only). Memory) 116 and NIC (Network Interface Card) 118.

  The operation panel 150 is connected to the ASIC 120 of the controller 100. The image converter 30, the FCU 152, the engine unit 160, and other USB devices and IEEE 1394 devices (not shown) are connected to the ASIC 120 of the controller 100 via a PCI bus. The ASIC 120 is connected to the memory 112 and the HDD 114, and is also connected to the CPU 110 via the north bridge of the CPU chipset.

  The CPU 110 performs overall control of the multifunction machine 10. The ROM 116 stores various control programs. The NIC 118 connects the multifunction machine 10 to an external network. The memory 112 is used as a working memory, a drawing memory, a copy image buffer, and a code buffer of the multifunction machine 10.

  The CPU 110 reads various control programs from the ROM 116, the HDD 114, and the like, and loads them in the memory 112. Thereby, the CPU 110 starts and executes the NCS 42, DCS 44, OCS 46, FCS 48, ECS 50, MCS 52, UCS 54, SCS 56, SRM 58, FCUH 60, IMH 62, and MEU 64 shown in FIG. The CPU 110 further activates and executes the printer application 34, the copy application 36, the facsimile application 38, and the scanner application 40 in the application layer 18.

  Reading of an image is performed through the platform layer 20 when a request is generated in the copy application 36, the facsimile application 38, and the scanner application 40. The printer application 34 receives print data from an external terminal connected via the NIC 118 via the NCS 42, and writes it to the memory 112 and the HDD 114 using hardware resources via the platform layer 20.

  The engine unit 160 includes an ASIC 162, a CCD 164 for reading an image, and an image forming control unit 166 for forming an image. The ASIC 120 included in the controller 100 receives image data read and generated by the CCD 164 of the engine unit 160, image data read from the HDD 114 and the memory 112, and image data received from an external terminal connected via the NIC 118. The Hereinafter, the image data input to the ASIC 120 is collectively referred to as input image data. The ASIC 120 can perform various kinds of image processing on the input image data and can execute the image composition processing according to the present embodiment.

  The HDD 114 can store image data to be combined with input image data in the image combining process executed by the ASIC 120, and the image data is read by the ASIC 120. Hereinafter, image data to be combined with input image data is referred to as image data for synthesis. Examples of the image data for synthesis include image data such as date, page number, security management number, character printing such as “secret”, and stamp printing such as secret. Note that character printing such as date, page number, and security management number does not necessarily have to be stored in advance in the HDD 114 as image data, and may be generated from font data or the like as appropriate.

  Hereinafter, with reference to FIGS. 3 and 5, processing operations including the above-described image composition processing by the ASIC 120 will be described. In the following description, a copy operation will be described as an example of the processing operation. However, the present invention can be applied to various image processing operations such as a print operation, a facsimile transmission operation, a facsimile reception operation, and a scanner operation.

  In the copying operation, the processing flow shown below is executed in response to the operator of the multifunction machine 10 operating the operation panel 150 and instructing the start of the copying operation.

  First, as a first step, an original to be copied is read by the CCD 164 and converted into digital data. The converted digital data (hereinafter referred to as input image data) is temporarily stored in the memory 112 via the ASIC 162 of the engine unit 160 and the ASIC 120 of the controller 100.

  As a second step, for example, image data for synthesis for character printing or stamp printing stored in the HDD 114 is read from the HDD 114 or the like and stored in the memory 112.

  As a third step, under the control of the CPU 110, the input image data and the composition image data stored in the memory 112 are input to the ASIC 120, and an image composition process is performed. The combined image data generated by the image combining process (hereinafter referred to as combined image data) is transferred to the image forming control unit 116, and the combined image is transferred onto the transfer material.

  FIG. 3 is a diagram illustrating detailed functional blocks of the ASIC 120 in the hardware configuration of the multifunction machine according to the present embodiment. The ASIC 120 in this embodiment includes a compression / decompression unit 122 that performs compression and expansion of image data, an editing unit 124 that edits image data, a rotator 126, an input unit 128, and an output unit 130. The rotator 126 is a block that performs image rotation on the image data. The input device 128 is a block for inputting input image data read by the CCD 164 of the engine unit 160 to the memory 112. The output device 130 is a block that outputs image data to the engine unit 160.

  As shown in FIG. 3, the ASIC 120 according to the present embodiment further includes a combining circuit 132, and the combining circuit 132 executes image combining processing for combining the input image data and the combining image data. Note that the composition circuit 132 can be used by the editor 124 and the output device 130 to execute image composition as a preprocessing for image data editing processing or image data output to the engine unit 160.

  In the present embodiment, regardless of the size of the composition image data, a memory composition method that secures a memory area for the composition image data having the same size as the memory amount necessary for the input image data is not employed. Instead, a method of securing an appropriate amount of memory according to the image data for composition and performing image composition in the composition circuit 132 of the ASIC 120 is employed. Hereinafter, image synthesis processing executed by the ASIC according to the present embodiment will be described in more detail with reference to FIGS. 4 and 5.

  FIG. 4 is a detailed functional block diagram of the synthesis circuit 132 according to the present embodiment. As illustrated in FIG. 4, the synthesis circuit 132 includes a margin data generation unit 134, a synthesis unit 136, and a parameter setting unit 138.

  The combining circuit 132 receives input image data 200 and combining image data 210 to be combined with the input image data 200. In the present embodiment, the composition image data 210 is not limited to the same size as the input image data 200, and the image data 210 having a smaller size than the input image data 200 can be directly used. In the present embodiment, the composition circuit 132 constitutes means for obtaining input image data and means for obtaining image data for composition.

  The input image data 200 and the composition image data 210 are composed of RGB data of n bits (for example, 8 bits) for each color and separation data (XA_IN, XB_IN) for discrimination as appropriate. In FIG. 4, the RGB data is represented by RA_IN, GA_IN, and BA_IN for the input image data 200, and is represented by RB_IN, GB_IN, and BB_IN for the image data for synthesis 210. The separation data (XA_IN, XB_IN) is data used as data indicating the color, character, photo type, and the like of image data.

  The parameter setting unit 138 is an area (hereinafter referred to as a composite area) in which an image of composite image data (hereinafter referred to as a composite image) in an input image data image (hereinafter referred to as an input image). , The size of the synthesis area (composite image), and the parameters such as the synthesis method are set in the margin data generation unit 134 and the synthesis unit 136 described later. The above parameters include, for example, the main scanning and sub-scanning start pixel positions of the composition area for compositing the composition image in the input image, the number of main scanning and sub-scanning pixels of the composition image (composition area), and the composition image. The specified value that defines the synthesis method of.

  Examples of the synthesis method include overwrite synthesis and watermark synthesis. Overwriting composition is a composition method in which the composition area in an input image is overwritten with a composition image. Watermark composition is a composition method that selects the larger pixel value of the input image and composition image. More specifically, even if characters are composed on the photo, the characters can be seen through the photo. This is a compositing process.

  The margin data generation unit 134 uses the image data for synthesis (RB_IN, GB_IN, BB_IN, XB_IN) input to the synthesis circuit 132, and the image data to be synthesized (RC_IN, having area size corresponding to the image of the input image data 200). GC_IN, BC_IN, XC_IN). More specifically, the margin data generation unit 134 receives the parameter setting from the parameter setting unit 138 and fills the synthesis target image data with a region other than the region corresponding to the synthesis region in the input image data. Margin data is generated, and the composition image data 210 is complemented with the margin data. As a result, the synthesis target image data having the area size corresponding to the image of the input image data 200 is generated in which the image of the synthesis image data 210 is arranged in the area corresponding to the synthesis area.

  Complementation of the composition image data 210 with the margin data can be realized by a margin addition function provided in the ASIC 120. In addition, the blank portion to be complemented is a portion in which the pixel value of the input image data is preferentially selected in the subsequent image composition. The margin is composed of data as white, black, or a color value meaning transparency.

  The synthesis unit 136 includes the input image data (RA_IN, GA_IN, BA_IN, XA_IN) input to the synthesis circuit 132 and the synthesis target image data (RC_IN, GC_IN, BC_IN, XC_IN) output from the margin data generation unit 134. Entered. The synthesizing unit 136 uses these image data to generate a synthesized image in which the synthesizing image is synthesized with the synthesis area in the input image. More specifically, the synthesizing unit 136 performs a synthesizing process of RGB data and separation data of the synthesis target image data and the input image data, and outputs synthesized image data (R_OUT, G_OUT, B_OUT, X_OUT).

  Hereinafter, the image composition processing according to the present embodiment will be described in more detail with reference to FIG. FIG. 5 is a diagram schematically showing image composition processing in the present embodiment. As shown in FIG. 5, for example, the input image data 200 and the composition image data 210 are input to the composition circuit 132 under the control of the CPU 110. At this time, setting information for defining the size of the input image and setting information for defining the composite area in the input image (Left (L), Top (T), Width (W), Height (H)) are provided by the CPU 110, for example. Given. In the synthesizing circuit 132, the parameter setting unit 138 instructs the margin data generation unit 134 according to the given setting information to start pixel position (Left) in the main scanning direction, start pixel position (Top) in the sub-scanning direction, Parameters such as the number of pixels in the main scanning direction (Width) and the number of pixels in the sub-scanning direction (Height) of the composite image are set. Further, the parameter setting unit 138 sets the synthesis method in the synthesis unit 136 according to the given setting information.

  The margin data generation unit 134 generates margin data in which each line is filled with a blank value from the first line in the sub-scanning direction to the start pixel position (Top). The margin data generation unit 134 generates data in which each line of image data for synthesis is included as a pixel column for a section after the start pixel position (Top) in the sub-scanning direction and before the end pixel position (Top + Height). . More specifically, the margin data generation unit 134 includes the pixel sequence of the image data for synthesis in the region of the start pixel position (Left) −the end pixel position (Left + Width) in the main scanning direction, and the other regions Generate data padded with blank values. An area from the first pixel in the main scanning direction to the start pixel position (Left) and an area from the end pixel position (Left + Width) to the end position are filled with blank values. The margin data generation unit 134 generates margin data in which each line is filled with blank values from the end pixel position (the pixel position obtained by adding the end pixel position (Top + Height) in the sub-scanning direction) to the last line.

  The synthesizing unit 136 synthesizes the input image data (RA_IN, GA_IN, BA_IN, XA_IN) and the synthesis target image data (RC_IN, GC_IN, BC_IN, XC_IN) by a synthesis method set as a parameter. At this time, for the blank value, a pixel value in the input image data 200 is selected, and for the synthesis region, a synthesis image is synthesized by the set synthesis method.

  According to the first embodiment described above, the image synthesis of the input image data and the image data for synthesis is realized using the margin creation function in the synthesis circuit in the ASIC 120. At this time, the composition image data does not need to have the same size as the input image data, and the composition image data having a smaller size than the input image can be used as it is. For this reason, only the memory capacity corresponding to the size of the image data for synthesis is secured on the memory 112. Therefore, according to the above-described embodiment, image synthesis between images of different sizes can be realized with a minimum amount of memory consumption, the reading load at that time can be reduced, and the image synthesis process can be speeded up.

  In the above-described embodiments, the synthesis image is directly synthesized with the input image. However, in another embodiment, by using a similar mechanism, it is also possible to arrange the synthesis images in a tile shape and synthesize them with the input image. Hereinafter, the image composition processing according to the second embodiment will be described with reference to FIGS. 6 and 7. In addition, since 2nd Embodiment demonstrated below is equipped with the structure similar to 1st Embodiment, it demonstrates below centering on difference. More specifically, the MFP 10 of the second embodiment has the same software configuration and hardware configuration as those shown in FIGS. 1 and 2, and the ASIC 120 of the second embodiment is shown in FIG. A configuration similar to that shown is provided.

  FIG. 6 is a detailed functional block diagram of the synthesis circuit 132 according to the second embodiment. The synthesizing circuit 132 according to the second embodiment shown in FIG. 6 includes a margin data generating unit 134, a synthesizing unit 136, and a parameter setting unit 138, similar to that shown in FIG. In the embodiment shown in FIG. 6, the multifunction machine 10 further includes a repetition control unit 140. The first input image data input to the combining circuit 132 is input to the combining unit 136. In the second embodiment, the combining unit 136 temporarily outputs the data under the control of the repetitive control unit 140. The combined image data 220 is input instead of the input image data 200.

  The repetition control unit 140 performs control to repeatedly perform image composition while changing the position of the composition area using the composite image data as second input image data. In the above control, the repetition control unit 140 causes the margin data generation unit 134 to generate second synthesis target image data, and the synthesis unit 136 causes the second input image data (first synthesis image data) and the second synthesis target data to be generated. Combine with image data. The repetitive control unit 140 can be configured as a process by the CPU 110 or a circuit function in the ASIC 120.

  The margin data generation unit 134 generates synthesis target image data having a region size corresponding to the image of the input image data 200 from the synthesis image data input to the synthesis circuit 132 under the control of the repetition control unit 140. Repeat the process. The parameter setting unit 138 repeatedly sets parameters such as the position of the composite region and the size of the composite region (composite image) from the given setting information to the margin data generation unit 134 under the control of the repeat control unit 140. To do.

  The synthesizing unit 136 according to the second embodiment can synthesize the synthesizing images into tiles and synthesize the input images by repeating the image synthesizing of the synthesizing images under the control of the repetitive control unit 140. More specifically, the composition unit 136 generates a composite image in which the composite image is combined with a predetermined composite region in the input image, and further, the composite image is combined with another composite region. Is further generated, and this is repeated a predetermined number of times.

  Hereinafter, the image composition processing according to the second embodiment will be described in more detail with reference to FIG. FIG. 7 is a diagram schematically illustrating image composition processing according to the second embodiment. As shown in FIG. 7, in the second embodiment, the original first input image data 200 and the composition image data 210 are input to the composition circuit 132.

  At this time, setting information (Width, Height) for specifying the size of the image for synthesis and setting information (Left, Top, Main_Interval, Sub_Interval, Main_Rep, Sub_Rep) for specifying the repetition condition are given from the CPU 110 to the repetition control unit 140, for example. It is done. Main_Interval and Sub_Interval are values that specify repetitive pixel intervals in main scanning and sub-scanning, respectively. Main_Rep and Sub_Rep are values that specify the number of repetitions in main scanning and sub scanning, respectively. In the example shown in the figure, the setting value `` Sub_Rep = full '' which means repeating as much as possible in the sub-scanning direction is set, and the setting value `` Main_Rep = full '' which means that repeated control is not performed in the main scanning direction. "false" is set.

  The repetitive control unit 140 sets setting information (Left (L), Top (T), Width (W), Height (H)) that defines a compositing region in which a compositing image in the input image is composited in each repetitive cycle. Is generated and given to the parameter setting unit 138. In the synthesizing circuit 132, the parameter setting unit 138 causes the margin data generation unit 134 to send the start pixel position (Left) and sub-scan start pixel position (sub-scan) (in the synthesis area) according to the given setting information for each cycle. Top), the parameters of the main scanning pixel number (Width) and the sub-scanning pixel number (Height) of the composite image are set.

  In the first cycle, the margin data generation unit 134 generates first synthesis target image data in which a synthesis image having a predetermined size (Height, Width) is arranged at the start pixel position (Top1, Left1), and the synthesis unit 136 synthesizes the first composition target image data and the first input image data. The generated first combined image data is input to the combining circuit 132 as second input image data via the memory. In the first cycle, a memory area for storing the first composite image data is secured separately.

  In the second cycle, the margin data generation unit 134 obtains the second synthesis target image data in which the synthesis image having a predetermined size (Height, Width) is arranged at the start pixel position (Top2, Left2) in the same manner as described above. The composition unit 136 synthesizes the second composition target image data and the second input image data. The second combined image data generated in the second cycle is input to the combining circuit 132 as third input image data via the memory. Note that a memory area for storing the first composite image data is separately secured in the first cycle, but in the subsequent cycles including the second cycle, the memory area secured in the first cycle is used. . The same applies to the third and fourth cycles. Finally, final synthesized image data in which the synthesis images are arranged in four rows and synthesized with the input image is obtained.

  In a function such as security management numbering, numbers for managing the number of copies may be arranged on one surface. According to the second embodiment described above, it is possible to realize image composition in a state in which images for composition are arranged on one surface in a tile shape with the minimum necessary memory consumption.

  In the above-described embodiments, the description has been made assuming that one synthesis image is synthesized with the input image. However, in other embodiments, the case where there are a plurality of images for composition can be expanded. Hereinafter, the image composition processing according to the third embodiment will be described with reference to FIGS. 8 and 9. In addition, since 3rd Embodiment demonstrated below is equipped with the structure similar to 1st Embodiment, it demonstrates below centering on difference.

  FIG. 8 is a detailed functional block diagram of the synthesis circuit 132 according to the third embodiment. The synthesis circuit 132 shown in FIG. 8 includes a margin data generation unit 134, a synthesis unit 136, and a parameter setting unit 138, as in the first embodiment. In the third embodiment, input image data 200 and a plurality of composition image data 210 are input to the composition circuit 132. In the example shown in FIG. 8, two synthesis images 210a and 210b are input. As the composition image data 210a and 210b, those having a smaller size than the input image data 200 can be directly used.

  The parameter setting unit 138 sets parameters such as the position of the synthesis area in the input image, the size of the synthesis area (synthesized image), and the synthesis method in the margin data generation unit 134 and the synthesis unit 136 for each synthesis image. To do.

  The margin data generating unit 134 is a combination of image data (RBn_IN, GB_IN, BBn_IN, XBn_IN: where n is the number of images for synthesis, 1 to N) input to the synthesis circuit 132. ) To generate compositing target image data (RC_IN, GC_IN, BC_IN, XC_IN) having a region size corresponding to the input image. More specifically, the margin data generation unit 134 receives the parameter setting from the parameter setting unit 138, generates margin data that fills an area other than the area corresponding to the plurality of synthesis areas in the input image, and The plurality of compositing image data 210a and 210b are complemented with the margin data. Thus, one compositing target image data is generated in which each compositing image is arranged in a region corresponding to each corresponding compositing region and has a region size corresponding to the image of the input image data 200.

  The synthesis unit 136 includes input image data (RA_IN, GA_IN, BA_IN, XA_IN) input to the synthesis circuit 132 and synthesis target image data (RC_IN, GC_IN, BC_IN, XC_IN) output from the margin data generation unit 134. Is entered. The synthesizing unit 136 generates a synthesized image in which each of the synthesis images is synthesized with each of the synthesis regions in the input image data, and outputs the synthesized image data (R_OUT, G_OUT, B_OUT, X_OUT).

  Hereinafter, the image composition processing according to the present embodiment will be described in more detail with reference to FIG. FIG. 9 is a diagram schematically illustrating image composition processing according to the third embodiment. As shown in FIG. 9, input image data 200 and a plurality of composition image data 210 are input to the composition circuit 132. At this time, setting information (Left (L), Top (T), Width (W), Height (H)) for defining each composite area in the input image is given by, for example, the CPU 110.

  In the synthesizing circuit 132, the parameter setting unit 138 causes the margin data generation unit 134 to perform the main scanning start pixel position (Left1, Left2) and the sub-scanning start pixel position (Top1, Top2), the parameters of the number of main scanning pixels (Width1, Width2) and the number of subscanning pixels (Height1, Height2) of the composition image are set.

  The margin data generation unit 134 has a blank value for each line in a section that does not correspond to any section after the start pixel position (Top) in the sub-scanning direction and before the end pixel position (Top + Height) in each composite image. Generates padded margin data. For the section corresponding to the section from the start pixel position (Top) in the sub-scanning direction to the end pixel position (Top + Height) in the sub-scanning direction of each compositing image, the margin data generation unit 134 displays each line of the compositing image data. Data included as a pixel column is generated. Here, when there is an area where a plurality of compositing images overlap, a pixel value of the compositing image data to be preferentially given as a default or preferentially is overwritten or watermarked. Then, the synthesizing unit 136 performs a synthesizing process on the generated synthesis target image data and the input image data by a synthesis method set as a parameter.

  According to the embodiments described above, a plurality of compositing image data is combined with the input image data using the margin generation function in the combining circuit in the ASIC 120. At this time, the plurality of compositing image data does not need to have the same size as the input image data, and the compositing image data having a small size can be used as they are. Therefore, according to the third embodiment, image composition between three or more images having different sizes can be realized with a minimum of memory consumption.

  In another embodiment, the image synthesis processing according to the fourth embodiment shown in FIG. 10 can be realized by further combining the second embodiment and the third embodiment. Since the fourth embodiment described below has the same configuration as that of the first embodiment, the following description will focus on differences.

  FIG. 10 is a diagram schematically illustrating an image composition process according to the fourth embodiment. As shown in FIG. 10, the first input image data and a plurality of composition image data are input to the composition circuit 132. In the example shown in FIG. 10, two images for composition are input. As the image data for synthesis, those having a smaller size than the first input image data can be directly used.

  At this time, setting information (Width1, Height1, Width2, Height2) specifying the size of each composition image, setting information (Left1, Top1, Left2, Top2, Main_Interval, Sub_Interval, Main_Rep, Sub_Rep) specifying the repetition condition are For example, it is given from the CPU 110 to the repetitive control unit 140. Main_Interval and Sub_Interval, and Main_Rep and Sub_Rep are commonly given to the composite image in the embodiment to be described.

  Similar to the third embodiment, the iterative control unit 140 according to the fourth embodiment sets setting information (Left (L), Top (T)) that defines a composition area for each of a plurality of composition images in each repetition cycle. , Width (W), Height (H)) to the parameter setting unit 138. For each repeated cycle, the parameter setting unit 138 instructs the margin data generation unit 134 according to the setting information given above for each composite region to start pixel position (Left1m, Left2m) and subscanning start pixel position ( Top1m, Top2m), the number of main scanning pixels (Width1, Width2) and the number of sub-scanning pixels (Height1, Height2) of the composition image are set. Here, m is a natural number of 1.

  In the first cycle, the margin data generation unit 134 arranges the first composition image having a predetermined size (Height1, Width1) at the start pixel position (Top11, Left11), and the first data having the predetermined size (Height2, Width2). The first compositing target image data in which the two compositing images are arranged at the start pixel position (Top21, Left21) is generated. The combining unit 136 combines the first combining target image data and the first input image data, and outputs the first combined image data.

  In the second cycle, the first composite image data is input as second input data. The margin data generation unit 134 arranges a first composition image having a predetermined size (Height1, Width1) at a start pixel position (Top12, Left12), and starts a second composition image having a predetermined size (Height2, Width2). Second synthesis target image data arranged at the pixel position (Top22, Left22) is generated. The synthesizing unit 136 synthesizes the second synthesis target image data and the first input image data, and inputs them to the synthesis circuit 132 as third input image data. The same applies to the third and fourth cycles. Finally, final composite image data in which a plurality of composite images are arranged in four rows and combined with the input image is obtained.

  According to the fourth embodiment described above, in a function such as security management numbering, a plurality of compositing images are arranged in a tiled manner on a single surface as described above with a minimum memory consumption. Synthesis can be realized.

  Furthermore, in another embodiment, the fifth embodiment as shown in FIGS. 11 and 12 can be realized. The fifth embodiment to be described below has the same configuration as that of the first embodiment, and therefore the following description will focus on the differences. FIG. 11 is a detailed functional block diagram of the synthesis circuit 132 according to the fifth embodiment. The synthesis circuit 132 according to the fifth embodiment shown in FIG. 11 includes a margin data generation unit 134, a synthesis unit 136, and a parameter setting unit 138, similar to that shown in FIG. In the fifth embodiment, input image data 200 and a plurality of image data for synthesis 210-1 to 210-n are input to the synthesis circuit 132.

  In the embodiment shown in FIG. 11, the multifunction machine 10 further includes an array control unit 142. The first input image data input to the combining circuit 132 is input to the combining unit 136. In the fifth embodiment, the combining unit 136 once outputs the combination under the control of the array control unit 142. Image data is further input instead of the input image data.

  The arrangement control unit 142 determines a synthesis area in which each of the synthesis images of the plurality of synthesis image data is arranged according to the given arrangement setting of the plurality of synthesis images, controls the synthesis image data to be input, The composition position of the composition image data is controlled. The array setting defines how to arrange the composition images, and can be configured as, for example, a one-dimensional or two-dimensional array of identification values for identifying the composition image data. For example, when four images for composition are arranged in four rows and one column, they can be configured as (1, 2, 3, 4).

  As in the first embodiment, the margin data generation unit 134 generates synthesis target image data having a region size corresponding to the image of the input image data 200 from the synthesis image data input to the synthesis circuit 132. Repeat that. The parameter setting unit 138 repeatedly sets parameters such as the position of the synthesis area and the size of the synthesis area (synthesis image) from the given setting information to the margin data generation unit 134.

  The composition unit 136 according to the fifth embodiment repeats image composition of a plurality of composition images under the control of the array control unit 142, thereby arranging a plurality of composition images to be tiled according to the array setting. It can be combined with the input image data. More specifically, the combining unit 136 generates a composite image in which one composite image is combined with one composite region in the input image, and another composite image is combined with another composite region. A composite image is further generated, and this is repeated a predetermined number of times.

  Hereinafter, the image composition processing according to the fifth embodiment will be described in more detail with reference to FIG. FIG. 12 is a diagram schematically illustrating image composition processing according to the fifth embodiment. As shown in FIG. 12, either the first input image data or a plurality of composition image data is input to the composition circuit 132. In the example shown in FIG. 12, four synthesis images are sequentially input.

  At this time, setting information (Width, Height) specifying the size of each image for synthesis, setting information (Left, Top, Main_Interval, Sub_Interval, Main_Rep, Sub_Rep) specifying the repetition condition, and array setting (Arrangement) are, for example, the CPU 110. To the array control unit 142. In the example shown in the figure, the Arrangement has an ID = 2 composition image, an ID = 1 composition image, an ID = 4 composition image, and an ID = 3 composition image arranged in order of 4 rows and 1 column. Is stipulated. Since Main_Interval, Sub_Interval, Main_Rep, and Sub_Rep are the same as those in the second embodiment, detailed description thereof is omitted.

  In each repetition cycle, the array control unit 142 inputs the composition image data to the composition circuit, defines an identification value (ID) for identifying the composition image, and a composition area in which the composition image in the input image is composed. Setting information (Left (L), Top (T), Width (W), Height (H)) is given to the parameter setting unit 138. In the synthesizing circuit 132, the parameter setting unit 138 causes the margin data generation unit 134 to send the start pixel position (Left) and sub-scan start pixel position (sub-scan) (in the synthesis area) according to the given setting information for each cycle. Top), the parameters of the main scanning pixel number (Width) and the sub-scanning pixel number (Height) of the composite image are set. In the embodiment to be described, the image composition is performed from the image data for composition of the youngest ID, but is not particularly limited, and in other embodiments, the image composition can be performed according to the arrangement order. .

  In the first cycle, the margin data generation unit 134 determines that the first composite image having a predetermined size (Height1, Width1) identified by ID = 1 is the start pixel position (Top11, Left11, second line). The first compositing target image data arranged in (1) is generated. The combining unit 136 combines the first combining target image data and the first input image data, and outputs the first combined image data.

  In the second cycle, the first composite image data is input as second input data. In the margin data generation unit 134, the second composition image having a predetermined size (Height2, Width2) identified by ID = 2 is arranged at the start pixel position (Top12, Left12, corresponding to the first row). The second image data to be synthesized is generated. In the cycle, the combining unit 136 combines the second combining target image data and the second input image data, and outputs the second combined image data. The same applies to the third and fourth cycles. Finally, the synthesis images are arranged in the order of the second, first, fourth, and third from the top and synthesized into the input image of the first input image data. The final composite image data is obtained.

  According to the fifth embodiment described above, image composition can be realized in a state where a plurality of compositing images are arbitrarily combined and arranged on one surface as described above, with a minimum required memory consumption.

  According to the embodiment described above, in the image composition of the input image data and the image data for composition, it is possible to perform image composition only by securing an appropriate memory consumption amount corresponding to the size of the image for composition. It is possible to provide an image processing apparatus in which the amount of memory is reduced and the speed of image composition processing is increased, and a program for realizing the image processing apparatus.

  Note that a synthesis circuit that performs image synthesis can be implemented as an ASIC as described above, and in other embodiments on a programmable logic device (PLD) such as a field programmable gate array (FPGA). Can be implemented. When implemented as a PLD, circuit configuration data (bit stream data) downloaded to the PDL for realizing the above circuit configuration on the PDL, HDL (Hardware Description Language) for generating the circuit configuration data, VHDL (Very High Speed Integrated Circuits) HDL) and (Verilog-HDL) can be distributed by a recording medium that records programs such as data described in (Verilog-HDL). In the above-described embodiment, the multifunction peripheral is an image processing apparatus. However, an image processing apparatus according to another embodiment may be configured as the ASIC 120 alone.

  The present invention has been described above with specific embodiments and examples. However, the present invention is not limited to the above-described embodiments or examples, and other embodiments, additions, modifications, deletions, etc. It can be changed within the range that can be conceived by those skilled in the art, and any embodiment is included in the scope of the present invention as long as the effects and effects of the present invention are exhibited.

DESCRIPTION OF SYMBOLS 10 ... MFP, 12 ... Software group, 14 ... MFP starter, 16 ... Hardware resource group, 18 ... Application layer, 20 ... Platform layer, 22 ... Control service layer, 24 ... Handler layer, 26 ... Monochrome Laser printer, 28 ... color laser printer, 30 ... image converter, 32 ... hardware resources, 34 ... printer application, 36 ... copy application, 38 ... facsimile application, 40 ... scanner application, 42 ... NCS, 44 ... DCS, 46 ... OCS, 48 ... FCS, 50 ... ECS, 52 ... MCS, 54 ... UCS, 56 ... SCS, 58 ... SRM, 60 ... FCUH, 62 ... IMH, 64 ... MEU, 66 ... API, 68 ... Engine I / F, 100 ... Controller, 11 ... CPU, 112 ... memory, 114 ... HDD, 116 ... ROM, 118 ... NIC, 120 ... ASIC, 122 ... compressor, 124 ... editor, 126 ... rotor, 128 ... input device, 130 ... output device, 132 ... Composition circuit, 134 ... Margin data generation unit, 136 ... Composition unit, 138 ... Parameter setting unit, 140 ... Repetition control unit, 142 ... Array control unit, 150 ... Operation panel, 152 ... FCU, 160 ... Engine unit, 162 ... ASIC, 164... CCD, 166... Image formation control unit, 200... Input image data, 210.

JP 2001-253134 A

Claims (7)

Means for obtaining input image data;
Means for obtaining image data for synthesis smaller than the input image data;
Generating means for generating, from the composition image data, composition target image data having an area corresponding to the image of the input image data and having the image of the composition image data arranged in a predetermined area;
Using the acquired input image data and the generated synthesis target image data, generate a synthesized image in which the image of the synthesis image data is synthesized with an area corresponding to the predetermined area of the input image data An image processing apparatus, comprising:   The generating means generates margin data for filling an area other than the predetermined area in the composition target image data, and generates the composition target image data by complementing the composition image data with the margin data. The image processing apparatus according to claim 1, wherein the image processing apparatus is a means for performing the processing.   Using the image data of the synthesized image as second input image data, the second image data to be synthesized is generated by the generating means while changing the position of the predetermined area, and the second input by the image synthesizing means. The image processing apparatus according to claim 1, further comprising a repetitive control unit that performs control for generating a second composite image from the image data and the second composition target image data.   The image processing apparatus according to claim 1, wherein there are a plurality of the composition image data, and a corresponding number of predetermined areas are set. There are a plurality of the composition image data, and the image processing apparatus further includes:
An array for determining a predetermined area in which each of the plurality of compositing image data images is arranged in accordance with an arrangement setting that defines an image arrangement of the plurality of compositing image data, and for controlling a composite arrangement of the plurality of compositing image data The image processing apparatus according to claim 1, comprising a control unit.   The means for acquiring the input image data, the means for acquiring the image data for synthesis, the generation means, and the image synthesis means are integrated circuits for specific applications or programmable logic devices as circuits having the functions of the respective means. The image processing apparatus according to claim 1, wherein the image processing apparatus is configured as described above. Means for acquiring input image data;
Means for obtaining image data for synthesis smaller than the input image data;
Generating means for generating image data to be combined having an area corresponding to the image of the input image data from the image data for combining, and the image of the image data for combining arranged in a predetermined area; and Image combining means for generating a combined image in which an image of the image data for combining is combined with a region corresponding to the predetermined region of the input image data, using the input image data and the generated image data to be combined A device-executable program for realizing a circuit configuration that functions as a device.