JP2013033873A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a configuration that can protect a switch element more securely when static electricity is applied to terminals while keeping its device configuration from becoming larger in a semiconductor device controlling output from an output terminal by means of the switch element for drive.SOLUTION: In a semiconductor device 1, a reference part made of one of a higher potential side power supply or a lower potential side power supply is connected to a first terminal of a switch element, and an output terminal P1 is connected to a second terminal of the switch element. Further, a first protection element is arranged in parallel with the first protection element. In addition, a second protection element is connected between the opposite side power supply (the other part) from the reference part and the output terminal. Then, nullification means is connected to the opposite side power supply (the other part) from the reference part. If driving voltage has been generated by application of surge voltage to the output terminal, the nullification means functions to nullify input of a current conduction signal to a control input terminal for a certain time period after the driving voltage generation, and cancel nullification after a prescribed time has passed.

Description

  The present invention relates to a semiconductor device.

  In a semiconductor device that controls output from an output terminal by controlling a semiconductor switch element such as a MOS transistor, there is a concern that internal electronic components may be destroyed when static electricity is applied to the input terminal or the output terminal. Therefore, it is required to protect the inside of the circuit from such static electricity.

JP 2007-173444 A Special table 2003-510825 gazette

  For example, as a method for protecting internal components from such static electricity, a configuration as shown in FIG. 16 is assumed, for example. In the configuration of FIG. 16, a protective resistor is provided between the output circuit and the output terminal in order to prevent the on-breakage of the driving MOS transistors Ta and Tb. However, if it is attempted to prevent the on-breakage by using only the protective resistance, the driving capability of the MOS transistors Ta and Tb is limited as the protective resistance increases. On the contrary, if the protection resistance is reduced to improve the characteristics of the output circuit, the withstand voltage against static electricity is lowered, and these have a trade-off relationship.

  As a technique related to the above-described problem, Patent Document 1 is also provided. In the technique of Patent Document 1, in the output unit (1), an output protection circuit (2), an output PchMOS transistor (POT1), an NchMOS transistor (NT1), an inverter (INV1), a protection diode (PD1, PD2), a resistor 2 Etc. are provided. The output protection circuit (2) is provided with an output protection PchMOS transistor (PPT1), a resistor (R1), a resistor (R3), and diodes (D2, D3, Dn). In this configuration, in order to prevent the on breakdown of the output PchMOS transistor (POT1), the output protection PchMOS transistor (PPT1) is operated to turn off the output PchMOS transistor (POT1). In addition to the output PchMOS transistor (POT1), it is necessary to provide a relatively large output protection PchMOS transistor (PPT1) that can overcome the prebuffer (NT1), which may increase the size of the device configuration.

  Further, as another related technique, Patent Document 2 is also provided. The technique of Patent Document 2 includes an output driver PMOS transistor (Pout) and an output driver NMOS transistor (Nout) connected in series between a Vss line and a Vdd line, which have gates connected together. Furthermore, an I / O pad (36) connected to the junction between the two output driver transistors (Pout, Nout), a PMOS transistor (Pdrv) and NMOS connected in series between the Vdd line and the Vss line A pre-driver stage including a transistor (Ndrv), and a gate of the output driver transistor (Pout, Nout) is connected to a junction between the pre-driver transistors (Pdrv, Ndrv). A gate clamp is connected between the Vss line and the I / O pad, and is connected to a junction between the pre-driver transistor (Pdrv, Ndrv) and the gate of the output driver NMOS transistor (Nout). The ESD clamp is connected between the I / O pad, the Vss line and the gate clamp. Even in this technique, the output MOS is turned off in order to prevent the output MOS from being destroyed. However, the drive circuit of the output driver NMOS transistor (Nout) mainly composed of the gate clamp 44 has a predriver transistor ( Pdrv, Ndrv) and the resistance (Rdrv) are connected to each other, and these outputs collide and interfere with each other. Therefore, the resistance Rdrv is increased at the expense of speed or the size of the gate clamp 44 is increased. It is necessary to turn off the output driver NMOS transistor (Nout). Further, since the gates of the output driver PMOS transistor (Pout) and the output driver NMOS transistor (Nout) are connected to each other, the output driver PMOS transistor (Pout) is required when a tolerance is required with respect to a plurality of surge standards as in the HBM. ) Cannot be protected.

  The present invention has been made to solve the above-described problems, and in a semiconductor device that controls output from an output terminal by a driving switch element, the switch element is more effective when static electricity is applied to the terminal. An object of the present invention is to realize a configuration that can be reliably protected while suppressing an increase in the size of the device configuration.

In order to achieve the above object, the present invention provides:
A control input terminal; a first terminal connected to a reference portion including one of a high-potential-side power supply and a low-potential-side power supply; and a second terminal connected to a predetermined output terminal. A switch element that is energized when a signal is input;
One end side is connected in parallel to the switch element so that the other end side is connected to the output terminal and the other end side is connected to the output terminal, and when the surge voltage is applied to the output terminal, the one end side and the other end side A first protective element that is energized,
Connected to the other part opposite to the reference part in the high-potential side power supply or the low-potential side power supply and energized when a surge voltage is applied to the output terminal to generate a drive voltage on the other part side A second protection element;
When the drive voltage is generated by applying a surge voltage to the output terminal while being connected to the other side, the energization signal is input to the control input terminal for a predetermined time after the drive voltage is generated. Invalidating means for canceling the invalidation after elapse of the predetermined time;
It is provided with.

  According to the first aspect of the present invention, a switch element that is energized when an energization signal is input to the control input terminal is provided, and the first of the switch elements is provided in the reference portion that is one of the high potential side power source and the low potential side power source. The terminal is connected, and the second terminal of the switch element is connected to the predetermined output terminal. In addition, a first protection element is provided in parallel with the switch element. The first protection element has one end connected to the reference portion and the other end connected to the output terminal, and a surge voltage is applied to the output terminal. The one end side and the other end side are energized. In addition, a second protection element is connected between the opposite side (the other part) of the high potential side power supply or the low potential side power supply (the other part) and the output terminal, and this second protection element is connected to the output terminal by a surge. When a voltage is applied, it is energized and functions to generate a drive voltage on the other side. And the invalidation means is connected to the other side, and when a drive voltage is generated by applying a surge voltage to the output terminal, the energization signal to the control input terminal is generated for a predetermined time after the drive voltage is generated. It functions to invalidate the input and cancel the invalidation after a lapse of a predetermined time.

  In this configuration, when the low potential side power supply is used as the reference unit, the first terminal of the switch element is connected to the low potential side power supply, and the second terminal of the switch element is connected to the output terminal. The first protection element is provided in parallel with the switch element, and one end side is connected to the low-potential side power source, the other end side is connected to the output terminal, and one end side and the other end are applied when a surge voltage is applied to the output terminal. It functions to energize the side. In addition, the high-potential-side power supply is the other part, and the second protection element is provided between the high-potential-side power supply and the output terminal. The second protection element functions to be energized when a surge voltage is applied to the output terminal and generate a drive voltage on the high potential side power supply side. When a disabling means is connected to the high-potential side power supply and a drive voltage is generated by applying a surge voltage to the output terminal, an energization signal is input to the control input terminal for a predetermined time after the drive voltage is generated. It functions to invalidate and cancel the invalidation after a lapse of a predetermined time.

  Further, when the high potential side power source is used as the reference portion, the first terminal of the switch element is connected to the high potential side power source, and the second terminal of the switch element is connected to the output terminal. The first protection element is provided in parallel with the switch element, and one end side is connected to the high-potential side power source, the other end side is connected to the output terminal, and one end side and the other end are applied when a surge voltage is applied to the output terminal. It functions to energize the side. In addition, the low-potential side power source is the other part, and the second protection element is provided between the low-potential side power source and the output terminal. The second protection element functions to be energized when a surge voltage is applied to the output terminal to generate a drive voltage on the low potential side power supply side. When a disabling means is connected to the low-potential side power supply and a drive voltage is generated by applying a surge voltage to the output terminal, an energization signal is input to the control input terminal for a predetermined time after the drive voltage is generated. It functions to invalidate and cancel the invalidation after a lapse of a predetermined time.

In the above configuration, when a surge voltage is applied to the terminal, paying attention to the point that the current flows from the application terminal to the power supply side and the power supply voltage rises temporarily, even when the low potential power supply is used as the reference part, Even when the high potential side power source is used as the reference portion, the input of the energization signal to the control input terminal is forcibly disabled in the period immediately after the application of the surge voltage, and the switch element is forcibly turned off. In this way, the switch can be forcibly maintained in the OFF state for a certain period of time during which the surge voltage is applied by using the current that flows from the application terminal when the surge voltage is applied to the terminal. Thus, it is possible to prevent a large current due to the surge voltage from flowing to the switch element, and to more reliably prevent thermal destruction of the switch element.
Further, after the predetermined time elapses, it is possible to cancel the invalidation of the input of the energization signal and cancel the forced off state, so that it is possible to perform a specified operation without any problem during normal use.

In the invention of claim 2, the invalidating means changes the output voltage with a predetermined time constant when a surge voltage is applied to a line connected to the other part (the power supply opposite to the reference part). The output unit, the comparison unit for determining whether or not the output voltage from the output unit has reached a threshold value, and until the output voltage has reached the threshold value in the comparison unit, the switch element is forcibly turned off and output And a switching unit that turns on the switch element when it is determined that the voltage has reached the threshold value.
That is, in the configuration in which the high-potential side power supply is the “other part”, the output section changes the output voltage with a predetermined time constant when the surge voltage wraps around the line connected to the high-potential side power supply, and compares The unit determines whether or not the output voltage from the output unit has reached a threshold value. Then, the switching unit forcibly turns off the switch element until the comparison unit determines that the output voltage has reached the threshold, and sets the switch element to the on-allowed state when it is determined that the output voltage has reached the threshold. To function.
In the configuration where the low-potential side power supply is the “other part”, the output section changes the output voltage with a predetermined time constant when the surge voltage wraps around the line connected to the low-potential side power supply, The unit determines whether or not the output voltage from the output unit has reached a threshold value. Then, the switching unit forcibly turns off the switch element until the comparison unit determines that the output voltage has reached the threshold, and sets the switch element to the on-allowed state when it is determined that the output voltage has reached the threshold. To function.
In any configuration, when a surge voltage is applied to the terminal and wraps around the output part, the output voltage of the output part changes with a predetermined time constant, and this output voltage approaches the threshold with a certain delay. The switching unit operates to forcibly turn off the switch for a certain period until the output voltage from the output unit reaches the threshold value. In this manner, the switch element can be stably turned off (operation restricted state) for a certain period of time immediately after the surge voltage has circulated, and the switch element can be stably turned on (returned) after a certain period of time. It can be realized more easily.

The invention of claim 3 is connected to the other part (the power source opposite to the reference part) and outputs a predetermined ON signal when the voltage of the line connected to the other part reaches a predetermined voltage. A signal output circuit is provided. The output unit is configured to change the output voltage with a predetermined time constant when the ON signal is output from the signal output circuit.
In this configuration, a certain amount of time from the application of the surge voltage (the time until the voltage of the line connected to the “other part” reaches a predetermined voltage) can suppress the voltage from being applied to the output unit, A delay with respect to the output unit can be caused. The output unit changes the output voltage with a predetermined time constant after the delay time in the signal output circuit has elapsed (that is, after the output from the signal output circuit is started). It becomes easier to cause a delay in the output section. Accordingly, the time constant can be relatively lowered and the circuit scale of the output unit can be easily suppressed as compared with a configuration in which such a signal output circuit is not provided.

In the invention of claim 4, the switch element is configured to switch the conduction path between the output terminal and the high potential side power source to a conductive state or a non-conductive state in accordance with a signal input to the control input terminal. A zener diode having an output terminal side as an anode and a high potential side power supply side as a cathode is connected in parallel with the switch element between the power supply side and the high potential side power supply. A Zener diode is connected between the output terminal and the low-potential side power source, with the output terminal side serving as a cathode and the low-potential side power source side serving as an anode.
According to this configuration, a configuration in which a high-side drive is performed by the switch element is suitably realized, and when the surge voltage is applied to the terminal, a malfunction (such as a thermal breakdown due to the surge voltage) occurs in the switch element. Can be prevented more reliably.

In the invention of claim 5, the switch element is configured to switch the conduction path between the output terminal and the low-potential-side power source to a conductive state or a non-conductive state in accordance with a signal input to the control input terminal. A zener diode having an output terminal side as a cathode and a low potential side power supply side as an anode is connected in parallel with the switch element between the power supply and the low potential power supply. A Zener diode is connected between the output terminal and the high-potential power supply, with the output terminal side serving as an anode and the high-potential power supply side serving as a cathode.
According to this configuration, it is possible to suitably realize a configuration in which low-side driving is performed by the switch element, and that when the surge voltage is applied to the terminal, a malfunction (thermal destruction caused by the surge voltage) occurs in the switch element. This can be prevented more reliably.

1 is a circuit diagram schematically illustrating a semiconductor device according to a first embodiment of the invention. FIG. 2 is an explanatory diagram for explaining the relationship among the output voltage of the output unit, the input signal from the outside, and the operating state of each switch element in the semiconductor device of FIG. FIG. 3 shows changes in output terminal voltage, VDD side voltage change, output unit output voltage change, and comparison unit threshold voltage change when positive electrostatic noise is applied to the output terminal in an HBM test or the like. It is a graph to explain. FIG. 4 shows changes in the output terminal voltage, GND side voltage change, output unit output voltage change, and comparison unit threshold voltage change when negative electrostatic noise is applied to the output terminal in an HBM test or the like. It is a graph to explain. FIG. 5 is a circuit diagram schematically illustrating a semiconductor device according to the second embodiment. FIG. 6 is a circuit diagram schematically illustrating a semiconductor device according to the first modification obtained by modifying FIG. FIG. 7 is a circuit diagram schematically illustrating a semiconductor device according to Modification 2 in which FIG. 5 is modified. FIG. 8 is a circuit diagram schematically illustrating a semiconductor device according to Modification 3 in which FIG. 5 is modified. FIG. 9 is a circuit diagram schematically illustrating a semiconductor device according to a fourth example of another embodiment. FIG. 10 is a circuit diagram schematically illustrating a semiconductor device according to a fifth example of another embodiment. FIG. 11 is a circuit diagram schematically illustrating a part of a semiconductor device according to a sixth example of another embodiment. FIG. 12 is a circuit diagram schematically illustrating a part of the semiconductor device according to the seventh example of the other embodiments. FIG. 13 is a circuit diagram schematically illustrating a semiconductor device according to an eighth example of another embodiment. FIG. 14 is a circuit diagram schematically illustrating a semiconductor device according to a ninth example of another embodiment. FIG. 15 is a circuit diagram schematically illustrating a semiconductor device according to a tenth example of another embodiment. FIG. 16 is an explanatory diagram for explaining a problem in another configuration other than the present invention.

[First embodiment]
Hereinafter, a first embodiment embodying the present invention will be described with reference to the drawings.
1 is a circuit diagram schematically illustrating a semiconductor device according to a first embodiment of the invention. FIG. 2 is an explanatory diagram for explaining the relationship among the output voltage of the output unit, the input signal from the outside, and the operating state of each switch element in the semiconductor device of FIG. FIG. 3 shows changes in output terminal voltage, VDD side voltage change, output unit output voltage change, and comparison unit threshold voltage change when positive electrostatic noise is applied to the output terminal in an HBM test or the like. It is a graph to explain. FIG. 4 shows changes in the output terminal voltage, GND side voltage change, output unit output voltage change, and comparison unit threshold voltage change when negative electrostatic noise is applied to the output terminal in an HBM test or the like. It is a graph to explain.

  The semiconductor device 1 shown in FIG. 1 is configured as a drive circuit that operates the switch elements T1 and T2 in response to an input signal (for example, a PWM signal) from the input line IN, and a surge voltage is applied to the output terminal P1. Sometimes it operates to protect the switch elements T1, T2. The semiconductor device 1 includes switch elements T1 and T2, Zener diodes ZD1 and ZD2, an output unit 10, a comparison unit 20, and a switching unit 30, and is connected to a power source VDD as a high potential side power source and has a low potential. It is connected to a ground GND as a side power supply.

  The switch element T1 is configured as a P-type MOSEFT (P-channel MOSFET), the source terminal is connected to the power supply VDD side, and the drain terminal is connected to the output terminal P1 side. The switch element T1 is configured to switch the conduction path between the output terminal P1 and the power supply VDD to a conductive state or a non-conductive state according to a signal input to the gate terminal (control input terminal) of the switch element T1. When the ON signal (energization signal) is input to the gate terminal, the energization path between the power supply VDD and the output terminal P1 is energized, and when the OFF signal (non-energization signal) is input, the power supply VDD And the output terminal P1 are operated so as to be in a non-energized state. Here, the L level signal is the ON signal for the switch element T1, and the H level signal is the OFF signal for the switch element T1.

  The switch element T2 is configured as an N-type MOSEFT (N-channel MOSFET), the source terminal is connected to the ground GND side, and the drain terminal is connected to the output terminal P1 side. The switch element T2 is configured to switch the conduction path between the output terminal P1 and the ground GND to a conductive state or a non-conductive state according to a signal input to the gate terminal (control input terminal). When an ON signal (energization signal) is input to the gate terminal, the energization path between the ground GND and the output terminal P1 is energized, and when an OFF signal is input to the gate terminal, the ground GND and the output terminal P1 It is comprised so that the electricity supply path between may be made into a non-energized state. Here, the H level signal is the ON signal for the switch element T2, and the L level signal is the OFF signal for the switch element T2.

  The Zener diode ZD1 is configured as a protection diode, and is connected in parallel with the switch element T1 between the output terminal P1 and the power supply VDD. The Zener diode ZD1 has an anode connected to the output terminal P1 and the cathode of the Zener diode ZD2, and a cathode connected to the power supply VDD. The zener diode ZD2 is connected in parallel with the switch element T2 between the output terminal P1 and the ground GND. The Zener diode ZD1 has a cathode connected to the output terminal P1 and the anode of the Zener diode ZD1, and an anode connected to the ground GND. These Zener diodes ZD1 and ZD2 function to suppress electrostatic breakdown of elements provided in the semiconductor device 1 when static electricity is applied to the output terminal P1.

  The output unit 10 functions as an integrating circuit including a resistor R1 and a capacitor C1, and the resistor R1 and the capacitor C1 are connected in series, and the potential between the resistor R1 and the capacitor C1 is output. . Hereinafter, this output is referred to as an output voltage Vcr. The resistor R1 has one end connected to the power supply VDD, the source terminal of the switch element T1, and the cathode of the Zener diode ZD1, and the other end connected to the input side of the comparison unit 20 and one end side of the capacitor C1 (opposite of the ground GND). Side). One end of the capacitor C1 is connected to the other end of the resistor R1 (the side opposite to the power supply VDD) and the input side of the comparator 20, and the other end is connected to the ground GND, the source terminal of the switch element T2, and the Zener diode ZD2. Are respectively connected to the anodes.

  The comparison unit 20 functions to determine whether or not the output voltage Vcr from the output unit 10 has reached the threshold voltage Vth. The comparison unit 20 compares the output voltage Vcr from the output unit 10 (voltage of the input line connected between the other end side of the resistor R1 and one end side of the capacitor C1) and the threshold voltage Vth (reference voltage). A comparator is provided, and when the output voltage Vcr of the output unit 10 is lower than the threshold voltage Vth (reference voltage), an L level signal is output, and the output voltage Vcr of the output unit 10 exceeds the threshold voltage Vth. If so, an H level signal is output. The reference voltage (threshold voltage Vth) used as one input of the comparator is, for example, a reference higher than the ground potential by a predetermined ratio (for example, ½) of the potential difference between the power supply VDD and the ground GND by a known level conversion circuit. A voltage is generated and set as a threshold voltage Vth. Hereinafter, a case where the threshold voltage Vth is set to be higher than the ground potential by a value that is ½ of the potential difference between the power supply VDD and the ground GND will be described as a representative example.

  The switching unit 30 forcibly turns off the switch elements T1 and T2 to be protected until the comparison unit 20 determines that the output voltage Vcr has reached the threshold value (reference voltage Vth), and the output voltage Vcr is set to the threshold value (reference voltage). When it is determined that it has reached Vth), the switch elements T1 and T2 to be protected function so as to be in an ON-permitted state.

  The switching unit 30 includes a NAND circuit 31, a NOR circuit 32, an OR circuit 33, an AND circuit 34, and an inverting circuit 35. A first input terminal of the NAND circuit 31 is connected to the input line IN. The second input terminal of the NAND circuit 31 is connected to the output terminal of the comparison unit 20. The input line is a line to which an input signal is applied from the outside. In the example of FIG. 1, a signal for turning on the switch element T1 and turning off the switch element T2 is a first signal (H level signal). A signal for turning off the switch element T1 and turning on the switch element T2 is a second signal (L level signal).

  The inverting circuit 35 is connected to the output terminal of the comparison unit 20 and the second input terminal of the NAND circuit 31, and is configured to invert the signal from the output terminal of the comparison unit 20 and output it.

  The NOR circuit 32 has a first input terminal connected to the output terminal of the inverting circuit 35, and a second input terminal connected to the input line IN and the first input terminal of the NAND circuit 31.

  The OR circuit 33 has a first input terminal connected to the output terminal of the NAND circuit 31, and a second input terminal connected to the output terminal of the AND circuit 34 and the gate terminal of the switch element T2. The output terminal is connected to the gate terminal of the switch element T1.

  The AND circuit 34 has a first input terminal connected to the output terminal of the OR circuit 33 and the gate terminal of the switch element T 1, and a second input terminal connected to the output terminal of the NOR circuit 32. The output terminal is connected to the gate terminal of the switch element T2.

  In the switching unit 30, as conceptually shown in FIG. 2, when the output voltage Vcr from the output unit 10 is at L level (that is, the output voltage Vcr is lower than the threshold voltage Vth), Regardless of the signal state, the switch element T1 (hereinafter also referred to as Pch) and the switch element T2 (hereinafter also referred to as Nch) are operated to be in an OFF state.

  Specifically, when the output voltage Vcr is lower than the threshold voltage Vth, an L level signal is output from the comparison unit 20, and this L level signal is input to the second input terminal of the NAND circuit 31. In this case, an H level signal is always output from the NAND circuit 31 regardless of the state of the input line IN. When the L level signal is output from the comparison unit 20, the L level signal is input to the inverting circuit 35, and the H level signal is input to the first input terminal of the NOR circuit 32. In this case, an L level signal is always output from the NOR circuit 32 regardless of the state of the input line IN. Since the H level signal is always output from the NAND circuit 31, the H level signal is always output from the OR circuit 33. The switch element T1 to which the output of the OR circuit 33 is applied to the gate terminal is Maintained in the off state. In this case, since the NOR circuit 32 always outputs the L level signal, the AND circuit 34 always outputs the L level signal, and the switch element T2 to which the output of the AND circuit 34 is applied to the gate terminal is in the OFF state. Maintained. Thus, while the output voltage Vcr is lower than the threshold voltage Vth, both the switch elements T1 and T2 are maintained in the off state. That is, the switching unit 30 maintains the switch elements T1 and T2 in the forced-off state while the output voltage Vcr is lower than the threshold voltage Vth.

  On the other hand, when the output voltage Vcr exceeds the threshold voltage Vth, an H level signal is output from the comparison unit 20, and this H level signal is input to the second input terminal of the NAND circuit 31. In this case, the NAND circuit 31 outputs an H level when the input line IN is at an L level, and outputs an L level when the input line IN is at an H level. That is, it functions to invert and output the signal of the input line IN. Further, since the H level signal from the comparison unit 20 is input to the inverting circuit 35, the L level signal is output, and the L level signal is continuously input to the first input terminal of the NOR circuit 32. In this case, the NOR circuit 32 outputs the H level when the input line IN is at the L level, and outputs the L level when the input line IN is at the H level. That is, the signal of the input line IN is inverted and output.

  As described above, when the output voltage Vcr exceeds the threshold voltage Vth, both the NAND circuit 31 and the NOR circuit 32 invert the signal of the input line IN and output it. In this case, when the input line IN is at the L level, the H level signal is output from the NAND circuit 31, the H level is output from the OR circuit 33, and the H level signal is applied to the gate terminal of the switch element T1. Therefore, the switch element T1 is turned off. When the input line IN is at the L level as described above, the NOR level 32 is output at the H level and input to the second input terminal of the AND circuit 34. The AND circuit 34 has an OR circuit connected to the first input terminal. Since the H level signal output from 33 is output, the AND circuit 34 outputs the H level signal. Accordingly, since the H level signal is applied to the gate terminal of the switch element T2, the switch element T2 is turned on.

  When the output voltage Vcr exceeds the threshold voltage Vth and the input line IN is at the H level, an L level signal is output from the NOR circuit 32 and an L level signal is also output from the AND circuit 34. The Therefore, the switch element T2 to which the output (L level output) from the AND circuit 34 is applied to the gate terminal is maintained in the OFF state. The L level output from the AND circuit 34 is input to the second input terminal of the OR circuit 33, and the second input terminal of the OR circuit 33 is maintained at the L level. Further, when the input line IN is at the H level, an L level signal is output from the NAND circuit 31 and is input to the first input terminal of the OR circuit 33, so that an L level signal is output from the OR circuit 33. Will be output. Therefore, the switch element T1 to which the output from the OR circuit 33 (L level output) is applied to the gate terminal is turned on.

  As described above, when the output voltage Vcr exceeds the threshold voltage Vth, the input of the input line IN is inverted and input to the switch elements T1 and T2, and the switch elements T1 and T2 are input to the input line. It operates according to the state of IN. That is, when the input line IN is at the L level, an H level signal is input to the gate terminals of the switch elements T1 and T2, the switch element T1 (Pch) is turned off, and the switch element T2 (Nch) is turned on. (See FIG. 2). When the input line IN is at the H level, an L level signal is input to the gate terminals of the switch elements T1 and T2, and the switch element T1 is turned on and the switch element T2 is turned off. That is, when the output voltage Vcr is higher than the threshold voltage Vth, the switching unit 30 cancels the forced OFF state when the output voltage Vcr is lower than the threshold voltage Vth, and allows the switch elements T1 and T2 to be turned on. It is functioning as a state.

  Next, a case where a voltage higher than the voltage during normal use is applied between the output terminal P1 and the ground GND due to static electricity (ground reference, positive application) will be described. For example, when a positive voltage Vz is applied to the output terminal P1, a current flows from the output terminal P1 through the protective Zener diode ZD1, and the voltage on the power supply VDD side rises. In the following, the voltage on the VDD side after the rise is Ve1, and in the case of HBM (Human Body Model) evaluation described later, Ve1 is Vz−Vf. As the voltage on the power supply VDD side increases to Ve1, the output voltage Vcr of the output unit 10 gradually increases, and after a predetermined time has elapsed, Vth (a predetermined ratio of the potential difference between the power supply VDD and the ground GND (for example, 1/2) ) Only reaches a threshold voltage higher than the ground potential). In this configuration, even when a high voltage is applied to the output terminal P1, the output from the output unit 10 does not rapidly increase but changes with a predetermined time constant, and the output voltage Vcr reaches the threshold voltage Vth. The output from the comparison unit 20 is maintained at the L level for a certain period of time.

  In this case, the switch element T2 is the protection target element, and the ground GND (low potential side power supply) is the reference portion. Also, the Zener diode ZD2 serves as a first protection element, and functions so that one end side and the other end side are energized when a surge voltage exceeding a predetermined break voltage is applied to the output terminal P1. Further, the power supply VDD (high potential side power supply) becomes the “other part”, and the Zener diode ZD1 disposed between the power supply VDD and the output terminal P1 corresponds to the second protection element. The Zener diode ZD1 is energized when the surge voltage Vz is applied to the output terminal P1, and functions to generate a drive voltage (Vz-Vf in the case of Ve1: HBM) on the power supply VDD side. . The protection circuit (invalidating means) described above is connected to the power supply VDD side where the drive voltage (Ve) is generated, and when the drive voltage (Ve1) is generated by applying the surge voltage Vz to the output terminal P1, It functions to invalidate the input of energization signals to the gate terminals (control input terminals) of the switch elements T1 and T2 for a predetermined time after the generation of the drive voltage (Ve1), and to cancel the invalidation after the lapse of the predetermined time. It will be.

  Next, the case where a voltage lower than the voltage during normal use is applied between the output terminal P1 and the power supply VDD due to static electricity (when the power supply VDD is a reference, negative application) will be described. For example, when a negative voltage −Vz is applied to the output terminal P1, a current flows through the protective Zener diode ZD2, and the voltage on the ground GND side changes rapidly. In the following, the voltage after this change is assumed to be −Ve2, and in the case of HBM evaluation described later, −Ve2 becomes −Vz + Vf. After the voltage on the ground GND side suddenly becomes −Ve2 in this way, the output voltage Vcr of the output unit 10 gradually increases, and after a predetermined time has passed, Vth (a predetermined ratio of the potential difference between the power supply VDD and the ground GND). (For example, a threshold voltage higher than the ground potential by 1/2). In this configuration, even when a large negative voltage is applied to the output terminal P1, the output from the output unit 10 does not rapidly increase but changes with a predetermined time constant, and the output voltage Vcr becomes the threshold voltage Vth. The output from the comparison unit 20 is maintained at the L level for a certain time until it reaches.

  In this case, the switch element T1 is the protection target element, and the power supply VDD (high potential side power supply) is the reference portion. The Zener diode ZD1 corresponds to the first protection element, and functions so that one end side and the other end side are energized when a surge voltage exceeding a predetermined break voltage is applied to the output terminal P1. Further, the ground GND (low potential side power supply) is the “other part”, and the Zener diode ZD2 provided between the ground GND and the output terminal P1 corresponds to the second protection element. The Zener diode ZD2 is energized when the surge voltage −Vz is applied to the output terminal P1, and functions to generate a drive voltage (−Ve2: −Vz + Vf in the HBM evaluation described later) on the ground GND side. It will be. The protection circuit (invalidating means) is connected to the ground GND (low potential side power supply), and when the drive voltage (-Ve2) is generated by applying the surge voltage -Vz to the output terminal P1, the drive circuit It functions to invalidate the input of the energization signal to the gate (control input terminal) of the switch element T1 for a predetermined time after the voltage (--Ve2) is generated, and to cancel the invalidation after the elapse of the predetermined time.

In the present embodiment, the protection circuit configured by the output unit 10, the comparison unit 20, and the switching unit 30 corresponds to an example of “invalidating means”, and the output unit 10 includes the other unit (the side opposite to the reference unit). It functions to change the output voltage Vcr with a predetermined time constant when a surge voltage is applied to the line connected to the power source. For example, when the power supply VDD (high potential side power supply) is set as the “other part” (ground reference, positive application), the output unit 10 is connected to the power supply VDD (from the power supply VDD to the output unit 10). The output voltage Vcr is changed with a predetermined time constant when the surge voltage wraps around the line), and the comparison unit 20 determines whether or not the output voltage Vcr from the output unit 10 has reached the threshold value Vth. become. Then, the switching unit 30 forcibly turns off the switch elements T1 and T2 until the comparison unit 20 determines that the output voltage Vcr has reached the threshold value Vth, and has determined that the output voltage Vcr has reached the threshold value Vth. In this case, the switch elements T1 and T2 function to be in an on-allowed state. Further, when the ground GND (low potential side power supply) is set to the “other part” (power supply VDD reference, negative application), the output unit 10 is connected to the ground GND (from the ground GND to the output unit 10). The output voltage Vcr is changed with a predetermined time constant when the surge voltage wraps around the line), and the comparison unit 20 determines whether or not the output voltage Vcr from the output unit 10 has reached the threshold value Vth. Become. Then, the switching unit 30 forcibly turns off the switch elements T1 and T2 until the comparison unit 20 determines that the output voltage Vcr has reached the threshold value Vth, and has determined that the output voltage Vcr has reached the threshold value Vth. In this case, the switch elements T1 and T2 function to be in an on-allowed state.
In any case, when a surge voltage is applied to the output terminal P1 and wraps around the output unit 10, the output unit 10 changes the output voltage Vcr with a predetermined time constant, and the output voltage Vcr is The switching unit 30 forcibly turns off the switch elements T1 and T2 for a certain period until the output voltage Vcr from the output unit 10 reaches the threshold value Vth after a certain delay from the application of the surge voltage. Operates to state.

  Next, the ESD withstand voltage of the switch elements T1, T2 will be described with reference to the drawings. 3 and 4 show the voltage (OUT) of the output terminal P1, the voltage on the power supply VDD side, the threshold voltage Vth of the comparison unit 20, and the output voltage of the output unit 10 when evaluated in a specified HBM (Human Body Model) test. It is a graph which shows each change of Vcr. 3 shows the case where the ground GND is used as a reference part and a positive voltage is applied to the output terminal P1, and FIG. 4 shows the case where the power supply VDD is used as a reference part and a negative voltage is applied to the output terminal P1. Is shown. In this HBM evaluation, evaluation is performed without applying a power supply voltage (power supply voltage during actual use) to the power supply VDD side.

  In the example of FIG. 3, a charge / discharge capacitor having a capacity of 100 pF is connected between the ground GND of the semiconductor device 1 being the device under test and the output terminal P1, and a resistance value of 1 is provided between the charge / discharge capacitor and the output terminal P1. .5 kΩ resistor is connected. Then, power is supplied to the charge / discharge capacitor by using a power supply to charge, and then the charge / discharge capacitor is discharged to operate so as to apply a positive voltage to the output terminal P1. In this case, the positive voltage Vz is applied to the output terminal P1 (OUT) at the time t1 when the positive voltage is applied as shown in FIG. 3, and the voltage on the VDD side is Vz−Vf at the time t1. Soaring. On the other hand, the output voltage Vcr of the output unit 10 gradually rises with a predetermined time constant. Further, the threshold voltage Vth changes so as to be ½ of the voltage on the power supply VDD side. Since the output voltage Vcr does not reach the threshold voltage Vth during a predetermined time from the time t1 to the time t2, an L level signal is output from the comparison unit 20, and the switch elements T1 and T2 are in the state of the input line IN. Regardless of whether it is forcibly turned off and protected. On the other hand, since the output voltage Vcr reaches the threshold voltage Vth at time t2 when the predetermined time has elapsed and the H level signal is output from the comparison unit 20, the switch elements T1 and T2 are connected to the input line IN. Operates according to the state.

  In the example of FIG. 4, a charge / discharge capacitor having a capacity of 100 pF is connected between the power supply VDD of the semiconductor device 1 being the device under test and the output terminal P1, and a resistance value of 1 is provided between the charge / discharge capacitor and the output terminal P1. .5 kΩ resistor is connected. And it is made to operate | move so that electric power may be supplied and charged using a power supply to a charging / discharging capacitor, and a charging / discharging capacitor may be discharged after that, and a negative voltage may be applied to output terminal P1. In this case, the negative voltage −Vz is applied to the output terminal P1 (OUT) at the time t1 when the negative voltage is applied as shown in FIG. 4, and the voltage on the ground GND side at the time t1 is − It changes to Vz + Vf. On the other hand, the output voltage Vcr of the output unit 10 gradually rises with a predetermined time constant. The threshold voltage Vth changes so as to be higher than the potential of the ground GND by ½ of the potential difference between the power supply VDD and the ground GND. Since the output voltage Vcr does not reach the threshold voltage Vth during a predetermined time from the time t1 to the time t2, an L level signal is output from the comparison unit 20, and the switch elements T1 and T2 are in the state of the input line IN. Regardless of whether it is forcibly turned off and protected. On the other hand, since the output voltage Vcr reaches the threshold voltage Vth at time t2 when the predetermined time has elapsed and the H level signal is output from the comparison unit 20, the switch elements T1 and T2 are connected to the input line IN. Operates according to the state.

(Main effects of the first embodiment)
In the semiconductor device 1, focusing on the point that when a surge voltage is applied to the output terminal P 1, current flows from the application terminal to the power supply side and the power supply voltage temporarily rises, the low-potential-side power supply is used as the reference portion. Even when the high-potential side power supply is used as a reference part, the input of the energization signal to the control input terminal is forcibly disabled and the switch element is forcibly turned off in the period immediately after the surge voltage is applied. . In this way, the switch can be forcibly maintained in the OFF state for a certain period of time during which the surge voltage is applied by using the current that flows from the application terminal when the surge voltage is applied to the terminal. Thus, it is possible to prevent a large current due to the surge voltage from flowing to the switch element, and to more reliably prevent thermal destruction of the switch element.
Further, after the predetermined time elapses, it is possible to cancel the invalidation of the input of the energization signal and cancel the forced off state, so that it is possible to perform a specified operation without any problem during normal use.

The invalidating means includes an output unit 10 that changes an output voltage with a predetermined time constant when a surge voltage is applied to a line connected to the other part (a power source opposite to the reference unit), The comparison unit 20 that determines whether or not the output voltage Vcr from the output unit 10 has reached the threshold voltage Vth, and the switch element is forced until the comparison unit 20 determines that the output voltage Vcr has reached the threshold voltage Vth The switching unit 30 is set to an off state, and when the output voltage Vcr is determined to have reached the threshold voltage Vth, the switching element is set to an on-allowed state.
In this configuration, when a surge voltage is applied to the output terminal P1 and wraps around the output unit 10, the output unit 10 changes the output voltage Vcr with a predetermined time constant, and this output voltage Vcr is delayed to some extent by a threshold voltage. It approaches Vth. The switching unit 30 operates to forcibly turn off the switch element for a certain period until the output voltage Vcr from the output unit 10 reaches the threshold voltage Vth. In this manner, the switch element can be stably turned off (operation restricted state) for a certain period of time immediately after the surge voltage has circulated, and the switch element can be stably turned on (returned) after a certain period of time. It can be realized more easily.

Further, the switch element T1 is in a conductive state or a non-conductive state in an energization path between the output terminal P1 and the power supply VDD (high potential side power supply) according to a signal input to the gate (control input terminal) of the switch element T1. It is configured to switch to the state. A Zener diode ZD1 having an output terminal P1 side as an anode and a power supply VDD side as a cathode is connected between the output terminal P1 and the power supply VDD in parallel with the switch element T1. Further, a Zener diode ZD2 having a cathode on the output terminal P1 side and an anode on the ground GND side is connected between the output terminal P1 and the ground GND.
According to this configuration, a configuration in which high-side driving is performed by the switch element T1 is preferably realized, and when a surge voltage is applied to the output terminal P1, the switch element T1 has a problem (such as thermal destruction caused by the surge voltage). ) Can be prevented more reliably.

Similarly, the switch element T2 is configured to switch the conduction path between the output terminal P1 and the ground GND to a conductive state or a nonconductive state according to a signal input to the gate (control input terminal) of the switch element T2. There is no. A Zener diode ZD2 having a cathode on the output terminal P1 side and an anode on the ground GND side is connected in parallel with the switch element T2 between the output terminal P1 and the ground GND. A Zener diode ZD1 having an anode on the output terminal P1 side and a cathode on the power source VDD side is connected between the output terminal P1 and the power source VDD.
According to this configuration, a configuration in which low-side driving is performed by the switch element T2 is suitably realized, and when the surge voltage is applied to the output terminal P1, this switch element T2 has a defect (thermal destruction caused by the surge voltage). Can be prevented more reliably.

[Second Embodiment]
Next, a second embodiment will be described.
FIG. 5 is a circuit diagram schematically illustrating a semiconductor device according to the second embodiment. FIG. 6 is a circuit diagram schematically illustrating a semiconductor device according to Modification 1 of the second embodiment. FIG. 7 is a circuit diagram schematically illustrating a semiconductor device according to Modification 2 of the second embodiment. FIG. 8 is a circuit diagram schematically illustrating a semiconductor device according to Modification 3 of the second embodiment.

  The configuration of FIG. 5 is different from that of the first embodiment in that a power-on reset circuit 201 is added to the configuration of FIG. 1, and the other configurations are the same as those of the first embodiment. Accordingly, the same configurations as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description thereof is omitted.

  The power-on reset circuit 201 corresponds to an example of a “signal output circuit”. The power-on reset circuit 201 inputs a potential on the power supply VDD side with respect to the ground GND, and outputs an H level signal when the input voltage exceeds a predetermined value. Subsequently, while the input voltage does not reach a predetermined value, the L level signal is continuously output.

  In this configuration, for example, when a positive voltage Vz is applied to the output terminal P1, for example, a current flows from the output terminal P1 through the protective Zener diode ZD1, and the voltage on the power supply VDD side increases by Ve1. Thus, in the process in which the voltage on the power supply VDD side rises to Ve1, no voltage is applied to the output unit 10 until the voltage on the power supply VDD side reaches a predetermined value (threshold value of the power-on reset circuit 201). Then, after the voltage on the power supply VDD side becomes a predetermined value, an H level signal is output from the power-on reset circuit 201, and the output voltage Vcr starts to increase from the output time point. The output unit 10 operates so that the output voltage increases with a predetermined time constant after the H level signal is output from the power-on reset circuit 201. The operations of the comparison unit 20 and the switching unit 30 are the same as those in the first embodiment.

  In this configuration, the voltage applied to the output unit 10 can be suppressed for a certain period of time after the surge voltage is applied (the time until the voltage of the line connected to the “other part” reaches a predetermined voltage). A delay with respect to the output unit 10 can be caused. The output unit 10 outputs the output voltage with a predetermined time constant after the delay time in the power-on reset circuit 201 (signal output circuit) has elapsed (that is, after the output from the signal output circuit is started). Therefore, the output unit 10 is more likely to cause a delay. Therefore, the time constant can be relatively lowered and the circuit scale of the output unit 10 can be easily suppressed as compared with a configuration in which such a signal output circuit is not provided.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  Instead of the configuration in FIG. 5, configurations as in FIGS. 6 to 8 may be adopted. In the semiconductor device 210 of FIG. 6, another reference voltage generation circuit 211 is provided instead of the power-on reset circuit 201. The reference voltage generation circuit 211 is a circuit that generates a predetermined reference voltage, and is configured as a known reference voltage circuit that generates a reference voltage using a band gap regulator, a resistance voltage divider, or the like. Further, a power supply circuit 221 as shown in FIG. 7 may be provided instead of the reference voltage generation circuit 211 as shown in FIG. In the semiconductor device 220 of FIG. 7, the power supply circuit 221 is configured as a known power supply circuit, and is configured to output a predetermined power supply voltage. Further, as in the semiconductor device 230 of FIG. 8, the power supply voltage of the in-vehicle battery or the power supply voltage of the IG power supply may be input to the output unit 10.

  Further, as shown in FIG. 9, only the switch element T1 on the high side may be provided. Even in the configuration of FIG. 9, when a surge voltage is applied to the output terminal P1, the output voltage Vcr of the output unit 10 gradually increases, and when the threshold voltage Vth is reached, an H level signal is output from the comparison unit 20. Will be. In this configuration, until the output voltage Vcr reaches the threshold voltage Vth, the L level signal is continuously input to the NAND circuit 331, and the H level is continuously output from the NAND circuit 331. Therefore, the switch element T1 is maintained in the forced off state. After the output voltage Vcr reaches the threshold voltage Vth, since the H level signal is continuously input to one terminal of the NAND circuit 331, the switch element T1 operates according to the state of the input line IN. In this case, when an H level signal is input from the input line IN, an L level signal is output from the NAND circuit 331, the switch element T1 is turned on, and when an L level signal is input from the input line IN, An H level signal is output from the circuit 331, and the switch element T1 is turned off.

  Further, as shown in FIG. 10, only the low-side switch element may be provided. In the configuration of FIG. 10, when a surge voltage is applied to the output terminal P1, the output voltage Vcr of the output unit 10 gradually increases, and when the threshold voltage Vth is reached, an L level signal is output from the comparison unit 20. It has become so. When the output voltage Vcr is equal to or lower than the threshold voltage Vth, the comparison unit 20 outputs an H level signal. In this configuration, until the output voltage Vcr reaches the threshold voltage Vth, the H level signal is continuously input to the NOR circuit 432 and the L level is continuously output from the NOR circuit 432. Therefore, the switch element T2 is maintained in the forced off state. After the output voltage Vcr reaches the threshold voltage Vth, since the L level signal continues to be input to one terminal of the NOR circuit 432, the switch element T2 operates according to the state of the input line IN. In this case, when an H level signal is input from the input line IN, an L level signal is output from the NOR circuit 432, the switch element T2 is turned off, and when an H level signal is input from the input line IN, NOR is output. An H level signal is output from the circuit 432, and the switch element T2 is turned on.

  In the above embodiment, an example in which Zener diodes are used as the first protection element and the second protection element has been described. However, as shown in FIGS. 11 and 12, protection MOS transistors T3 and T4 are used instead of the Zener diodes. May be provided. In the examples of FIGS. 11 and 12, the MOS snapback operation is used as the operation of the ESD protection operation. 11 and 12 differs from the first embodiment in that a protection MOS transistor is provided in place of the Zener diode and a minute resistance is added, and other configurations (especially the output section) are different. 10, the comparison unit 20, the switching unit 30 and the like are the same as those in the first embodiment. FIG. 11 shows that Vds of the protective MOS transistor T3 is smaller than Vds of the output MOS transistor (switch element T1), and Vds of the protective MOS transistor T4 is Vds of the output MOS transistor (switch element T2). The smaller case is shown. As described above, even in a device manufactured by a general PureCMOS process, the output MOS transistor can be reliably protected. In the example of FIG. 12, the Vds of the protection MOS transistor T3 is substantially the same as the Vds of the output MOS transistor (switch element T1), and the Vds of the protection MOS transistor T4 is the output MOS transistor (switch This shows a case where it is approximately equal to Vds of the element T2). In this configuration, since the output MOS transistor and the protection MOS transistor snap back simultaneously in parallel, it is easy to reduce the size of the protection MOS transistor.

Moreover, it is good also as a structure like FIG.
In the semiconductor device 500 of FIG. 13, the output switch element T2 is configured as an NPN bipolar transistor, the collector terminal is connected to the output terminal P1, and the emitter terminal is connected to the ground GND. The base terminal is connected to one end side of the resistor R3, and the other end side of the resistor R3 is connected to the drain terminal of the MOS transistor Ta. The base terminal is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the ground GND. In the configuration of FIG. 13, when a surge voltage is applied to the output terminal P1, the output voltage Vcr of the output unit 10 gradually increases, and when the threshold voltage Vth is reached, an H level signal is output from the comparison unit 20. It has become so. Note that when the output voltage Vcr is equal to or lower than the threshold voltage Vth, the comparison unit 20 outputs an L level signal. In this configuration, the L level signal is continuously input to the NAND circuit 501 and the H level is continuously output from the NAND circuit 501 until the output voltage Vcr reaches the threshold voltage Vth. Accordingly, the MOS transistor Ta is maintained in the forced-off state, and at this time, the base of the switch element T2 is maintained in the L-level state, so that the switch element T2 is also maintained in the forced-off state.
On the other hand, after the output voltage Vcr reaches the threshold voltage Vth, the H level signal continues to be input to one terminal of the NAND circuit 501, so that the MOS transistor Ta operates according to the state of the input line IN, and the MOS transistor Ta The switch element T2 operates according to the operating state. In this case, when an H level signal is input from the input line IN, an L level signal is output from the NAND circuit 501, the MOS transistor Ta is turned on, and the switch element T2 is turned on. On the other hand, when an L level signal is input from the input line IN, an H level signal is output from the NAND circuit 501, the MOS transistor Ta is turned off, and the switch element T2 is turned off.

Moreover, it is good also as a structure like FIG.
In the semiconductor device 600 of FIG. 14, the output switch element T1 is configured as a PNP-type bipolar transistor, the collector terminal is connected to the output terminal P1, and the emitter terminal is connected to the power supply VDD. The base terminal is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the drain terminal of the MOS transistor Tb. The base terminal is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the power supply VDD. In the configuration of FIG. 14, when a surge voltage is applied to the output terminal P1, the output voltage Vcr of the output unit 10 gradually increases, and when the threshold voltage Vth is reached, an L level signal is output from the comparison unit 20. It has become so. When the output voltage Vcr is equal to or lower than the threshold voltage Vth, the comparison unit 20 outputs an H level signal. In this configuration, until the output voltage Vcr reaches the threshold voltage Vth, the H level signal is continuously input to the NOR circuit 601 and the L level is continuously output from the NOR circuit 601. Accordingly, the MOS transistor Tb is maintained in the forced-off state, and at this time, the base of the switch element T1 is maintained in the same H level state as that of the power supply VDD side, so that the switch element T1 is also maintained in the forced-off state.
On the other hand, after the output voltage Vcr reaches the threshold voltage Vth, since the L level signal is continuously input to one terminal of the NOR circuit 601, the MOS transistor Tb operates according to the state of the input line IN, and the MOS transistor Tb The switch element T1 operates according to the operating state. In this case, when an H level signal is input from the input line IN, an L level signal is output from the NOR circuit 601, the MOS transistor Ta is turned off, and the switch element T 1 is turned off. On the other hand, when an L level signal is input from the input line IN, an H level signal is output from the NOR circuit 601, the MOS transistor Tb is turned on, and the switch element T2 is turned on.

Moreover, you may make it like FIG. In the semiconductor device 700 of FIG. 15, an IGBT is used as the switch element T2, the collector terminal of the switch element T2 is connected to the output terminal P1, and the emitter terminal of the switch element T2 is connected to the ground GND. The gate terminal of the switch element T2 is connected to the drain terminal of the P-type MOS transistor Tc and the drain terminal of the N-type MOS transistor Td, respectively. The source terminal of the P-type MOS transistor Tc is connected to the power supply Vdd, and the source terminal of the N-type MOS transistor Td is connected to the ground GND.
In the configuration of FIG. 15, when a surge voltage is applied to the output terminal P1, the output voltage Vcr of the output unit 10 gradually increases, and when the threshold voltage Vth is reached, an H level signal is output from the comparison unit 20. It has come to be. Note that when the output voltage Vcr is equal to or lower than the threshold voltage Vth, the comparison unit 20 outputs an L level signal. In this configuration, until the output voltage Vcr reaches the threshold voltage Vth, the L level signal is continuously input to the NAND circuit 701, and the H level is continuously output from the NAND circuit 701. Therefore, the P-type MOS transistor Tc is maintained in the off state, and the N-type MOS transistor Td is maintained in the on state. At this time, the switch element T2 is maintained in a forced off state.
On the other hand, after the output voltage Vcr reaches the threshold voltage Vth, the H level signal continues to be input to one terminal of the NAND circuit 701. In this case, when an H level signal is input from the input line IN, an L level signal is output from the NAND circuit 701. Therefore, the P-type MOS transistor Tc is maintained in an on state, and the N-type MOS transistor Td is turned off. Maintained in a state. Accordingly, the switch element T2 is turned on. On the other hand, when an L level signal is input from the input line IN, an H level signal is output from the NAND circuit 701. Therefore, the P-type MOS transistor Tc is maintained in an off state, and the N-type MOS transistor Td is in an on state. Maintained at. At this time, the switch element T2 is maintained in the off state.

1,200,210,220,230,300,400,500,600,700 ... semiconductor device 10 ... output unit (invalidation means)
20: Comparison unit (invalidation means)
30 ... Switching unit (invalidation means)
50 ... Power-on reset circuit (signal output circuit)
T1 ... Switch element T2 ... Switch element ZD1 ... Zener diode ZD2 ... Zener diode VDD ... Power supply (high potential side power supply)
GND: Ground (Low-potential side power supply)

Claims (5)

A control input terminal; a first terminal connected to a reference portion including one of a high-potential-side power supply and a low-potential-side power supply; and a second terminal connected to a predetermined output terminal. A switch element that is energized when a signal is input;
One end side is connected in parallel to the switch element so that the other end side is connected to the output terminal and the other end side is connected to the output terminal, and when the surge voltage is applied to the output terminal, the one end side and the other end side A first protective element that is energized,
Connected to the other part opposite to the reference part in the high-potential side power supply or the low-potential side power supply and energized when a surge voltage is applied to the output terminal to generate a drive voltage on the other part side A second protection element;
When the drive voltage is generated by applying a surge voltage to the output terminal while being connected to the other side, the energization signal is input to the control input terminal for a predetermined time after the drive voltage is generated. Invalidating means for canceling the invalidation after elapse of the predetermined time;
A semiconductor device comprising: The invalidating means, an output section for changing an output voltage with a predetermined time constant when a surge voltage is applied to a line connected to the other section;
A comparison unit for determining whether the output voltage from the output unit has reached a threshold;
The switch element is forcibly turned off until it is determined by the comparator that the output voltage has reached the threshold value, and the switch element is turned on when the output voltage has been determined to have reached the threshold value. A switching unit and
The semiconductor device according to claim 1, comprising: A signal output circuit that outputs a predetermined ON signal when a voltage of a line connected to the other part and connected to the other part reaches a predetermined voltage;
3. The semiconductor device according to claim 2, wherein the output unit changes the output voltage with a predetermined time constant when an ON signal is output from the signal output circuit. The switch element is configured to switch a conduction path between the output terminal and the high-potential-side power source to a conductive state or a non-conductive state according to a signal input to the control input terminal,
A Zener diode is connected between the output terminal and the high potential side power source in parallel with the switch element, the output terminal side being an anode and the high potential side power source side being a cathode,
2. A Zener diode having a cathode on the output terminal side and an anode on the low potential power source side is connected between the output terminal and the low potential power source. The semiconductor device according to claim 3. The switch element is configured to switch a conduction path between the output terminal and the low-potential-side power source to a conductive state or a non-conductive state according to a signal input to the control input terminal,
A Zener diode is connected between the output terminal and the low-potential side power supply in parallel with the switch element, the output terminal side being a cathode and the low-potential side power supply side being an anode,
2. A zener diode having an anode on the output terminal side and a cathode on the high potential power source side is connected between the output terminal and the high potential power source. The semiconductor device according to claim 3.

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