JP2013033335A - Contactless electronic device - Google Patents

Abstract

An object of the present invention is to stably operate a non-contact electronic device including a transistor using carrier accumulation regardless of a communication distance and a communication state, and to increase a communicable distance of the non-contact electronic device. To do.
A non-contact electronic device including a transistor using carrier accumulation, a first rectifier circuit that converts a signal received by an antenna into a first DC power supply voltage, and a signal received by the antenna. A second rectifier circuit for converting to a second DC power supply voltage; a logic circuit that operates using a voltage obtained by smoothing the first DC power supply voltage by the first smoothing capacitor; and a first output from the logic circuit. A modulation signal amplification circuit that outputs a second modulation signal obtained by amplifying one modulation signal, and a voltage obtained by smoothing the first DC power supply voltage by the first smoothing capacitor varies based on the second modulation signal. And a load modulation circuit.
[Selection] Figure 2

Description

  The present invention relates to a contactless electronic device constituted by a transistor, and more particularly to a contactless electronic device constituted by a transistor using carrier accumulation.

  A contactless electronic device (so-called IC tag) equipped with an antenna and a semiconductor integrated circuit device enables individual identification by wireless communication, and is used for production and management of identification objects.

  The function of the IC tag will be described.

  The IC tag exchanges information with the reader / writer device, and transmits the data held by itself to the reader / writer device, and the data transmitted from the reader / writer device. It has a function to hold.

  Specifically, an IC tag receives a carrier signal supplied from a reader / writer device via an antenna, generates a DC power supply voltage from the received carrier signal, and the generated DC power supply voltage is mounted on the IC tag. To the semiconductor integrated circuit device. The IC tag transmits data superimposed on the carrier signal in the semiconductor integrated circuit device to the reader / writer device.

  When the IC tag transmits data to the reader / writer device, a load modulation circuit mounted in the semiconductor integrated circuit device is used.

  The load modulation circuit is a circuit that varies the power consumption of the semiconductor integrated circuit device. The voltage between the antenna terminals constituting the antenna varies by the load modulation circuit, and the variation is transmitted to the reader / writer device via the electromagnetic field, whereby the reader / writer device detects data.

  A semiconductor integrated circuit device mounted on an IC tag is manufactured mainly using a transistor (MOSFET (Metal Oxide Field Effect Effect Transistor)) using silicon. As a result, cost reduction by mass production of IC tags can be realized, which helps spread of IC tags.

  In recent years, semiconductor materials and transistor structures used for transistors have been proposed in order to realize new functions of IC tags that are difficult to achieve with conventional transistors using silicon.

  Even in the case of an IC tag equipped with a transistor composed of a novel semiconductor material or a transistor having a novel structure, the same communication form and communication range as those of an existing IC tag are required.

  A transistor using carrier accumulation that has recently been used for an IC tag will be described with reference to FIGS.

  FIG. 16 is a cross-sectional view for explaining a transistor using carrier accumulation.

  The transistor using carrier accumulation is a thin film transistor (TFT) in which a semiconductor layer (channel layer CL1) is an oxide semiconductor, and specifically includes a first metal layer ML1, a channel layer CL1, an insulator layer IL1, and a second layer. It consists of a metal layer ML2 and a substrate layer SL1.

  The first metal layer ML1 is made of molybdenum and forms a drain electrode and a source electrode. The channel layer CL1 is made of a semiconductor (oxide) mainly containing a metal oxide. The oxide semiconductor is amorphous indium zinc oxide (a-IGZO), zinc tin oxide (ZTO), or the like. The insulator layer IL1 is made of silica (SiO2). Similar to the first metal layer ML1, the second metal layer ML2 is made of molybdenum. The second metal layer ML2 forms a gate electrode. The substrate layer SL1 is made of quartz.

  The operation of the transistor using carrier accumulation will be briefly described.

  When a voltage is applied between the gate electrode and the source electrode, carriers accumulate in the channel layer CL1 due to the capacitance between the gate electrode and the source electrode. In this state, when a voltage is applied between the drain electrode and the source electrode, the number of carriers accumulated in the carrier layer CL1 increases, whereby the conductivity between the drain electrode and the source electrode increases. As a result, a current flows from the drain electrode to the source electrode.

  Note that a normal transistor (eg, MOSFET) uses an inversion layer in order to increase the conductivity between the drain electrode and the source electrode. As described above, the transistor using carrier storage uses the channel layer CL1 (storage layer) in order to increase the conductivity between the drain electrode and the source electrode. For this reason, the capacitance between the gate electrode and the source electrode of a normal transistor is several femtofarads or less, whereas the capacitance between the gate electrode and the source electrode of a transistor using carrier accumulation is Tens to hundreds of femtofarads, and the capacitance between the gate electrode and the source electrode of a transistor using carrier accumulation is larger than the capacitance between the gate electrode and the source electrode of a normal transistor. growing.

  FIG. 17 is an explanatory diagram of a first circuit configuration of a conventional semiconductor integrated circuit device mounted on an IC tag.

  The semiconductor integrated circuit device includes antenna terminals LA and LB, a rectifier circuit T1, a load modulation circuit T2, and a logic circuit L1.

  The antenna terminals LA and LB are connected to an antenna mounted on the IC tag.

  The rectifier circuit T1 converts the power received via the antenna into DC power. The rectifier circuit T1 is connected to the smoothing capacitor C1. The smoothing capacitor C1 smoothes the DC power converted by the rectifier circuit T1.

  The logic circuit L1 operates with the DC power output from the rectifier circuit T1 and executes various processes.

  The load modulation circuit T2 varies the voltage between the antenna terminals LA and LB by varying the power consumption of the semiconductor integrated circuit device in order to output the modulation signal from the logic circuit L1 from the antenna. Specifically, the load modulation circuit T2 reduces the voltage between the antenna terminals LA and LB by increasing the power consumption of the semiconductor integrated circuit device, and reduces the power consumption of the semiconductor integrated circuit device. Increase the voltage between terminals LA and LB.

  FIG. 18 is an explanatory diagram of numerical analysis results of the DC power supply voltage (VDD1), the modulation signal voltage (MOD1), and the antenna terminal voltage (LA-LB) in the semiconductor integrated circuit device shown in FIG.

  As described in FIG. 17, the load modulation circuit T2 can reduce the voltage (LA-LB) between the antenna terminals LA and LB by increasing the power consumption in the semiconductor integrated circuit device. However, this also decreases the voltage (VDD1) of the DC power output from the rectifier circuit T1.

  When the voltage of the DC power output from the rectifier circuit T1 decreases, the logic circuit L1 that operates with the DC power has a problem. This defect includes, for example, a problem that an initialization signal is issued even though the initialization is not performed, a problem that the operation speed becomes unstable, and a problem that the clock signal becomes unstable.

  For this reason, it is desirable to prevent a decrease in the DC power voltage (VDD1) by the load modulation circuit T2 as much as possible.

  However, the longer the distance between the IC tag and the reader / writer device, the larger the amplitude of the voltage between the antenna terminals, and the load modulation circuit T2 causes fluctuations in power consumption in the semiconductor integrated circuit device. Must be increased. For this reason, it cannot prevent that the load modulation circuit T2 reduces the voltage (VDD1) of DC power.

  From the above, the semiconductor integrated circuit device shown in FIG. 17 has a drawback in that when the load modulation circuit T2 increases the fluctuation of the DC power voltage (VDD1), the operating voltage of the logic circuit L1 also fluctuates.

  Therefore, a semiconductor integrated circuit device as shown in FIG. 19 in which the load modulation circuit T2 is directly connected to the antenna terminals LA and LB is used.

  FIG. 19 is an explanatory diagram of a second circuit configuration of a conventional semiconductor integrated circuit device mounted on an IC tag.

  As described above, the load modulation circuit T2 of the semiconductor integrated circuit device shown in FIG. 19 is directly connected to the antenna terminals LA and LB.

  Here, when the load modulation circuit T2 is a transistor using carrier accumulation shown in FIG. 16, the capacitance between the drain electrode and the gate electrode of the transistor using carrier accumulation, and the relationship between the source electrode and the gate electrode, In some cases, a high-frequency signal received by the antenna terminal is transmitted to the logic circuit L <b> 1 via the capacitance between them. As described with reference to FIG. 16, the capacitance between the drain electrode and the gate electrode of the transistor using carrier accumulation and the capacitance between the source electrode and the gate electrode are the same as those of a normal transistor. This is because the capacitance between the drain electrode and the gate electrode and the capacitance between the source electrode and the gate electrode are, for example, 10 times to 100 times larger.

  20 is an explanatory diagram of the numerical analysis results of the DC power supply voltage (VDD1), the modulation signal voltage (MOD1), and the antenna terminal voltage (LA-LB) in the semiconductor integrated circuit device shown in FIG.

  In the semiconductor integrated circuit device shown in FIG. 19, a high frequency signal propagates to the modulation signal voltage (MOD1) output from the logic circuit L1, as shown in FIG.

  When a high frequency signal is transmitted to the logic circuit L1, there is a problem that the operation of the logic circuit L1 becomes unstable.

  Patent Documents 1 and 2 include a rectifier circuit that generates a power supply voltage for the logic circuit L1 from power received by an antenna and a rectifier circuit that generates a power supply voltage for a load modulation circuit from power received by the antenna. An integrated circuit device, that is, a semiconductor integrated circuit device similar to the semiconductor integrated circuit device shown in FIG. 19 is disclosed.

  Patent Document 3 discloses that the capacitance of a capacitor connected between antenna terminals suppresses transmission of a high-frequency signal.

International Publication No. 2004/064346 Japanese Patent Laid-Open No. 10-322250 Japanese Patent Laid-Open No. 2005-267643

  In the techniques disclosed in Patent Documents 1 and 2, a technique for improving transmission / reception characteristics by separating a transmission / reception circuit and a power supply circuit has been disclosed. However, as described with reference to FIGS. This is not a technique for preventing high-frequency signals from being transmitted, and there is a case where a sufficient degree of modulation cannot be obtained as disclosed in Patent Document 3.

  Further, the disclosed technique disclosed in Patent Document 3 cannot prevent transmission of a high-frequency signal to the logic circuit.

  An object of the present invention is to stably operate a non-contact electronic device including a transistor using carrier accumulation regardless of a communication distance and a communication state, and to increase a communicable distance of the non-contact electronic device. And

  A typical example of the present invention is a non-contact electronic device constituted by a transistor using carrier accumulation, which is connected to a first smoothing capacitor and is constituted by the first transistor using carrier accumulation. A first rectifier circuit configured to convert a signal received by an antenna connected to the non-contact electronic device into a first DC power supply voltage and a second smoothing capacitor, and using the carrier accumulation A second rectifier circuit configured by a second transistor for converting a signal received by an antenna connected to the contactless electronic device into a second DC power supply voltage; and the first smoothing capacitor And outputs a second modulation signal obtained by amplifying the first modulation signal output from the logic circuit. A modulation signal amplifying circuit and a load modulation for varying a voltage obtained by smoothing the second DC power supply voltage by the second smoothing capacitor based on a second modulation signal output from the modulation signal amplifying circuit And a circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a non-contact electronic device including a transistor using carrier accumulation can be stably operated regardless of a communication distance and a communication state, and a communicable distance of the non-contact electronic device can be increased.

It is explanatory drawing of the IC tag system of 1st Embodiment of this invention. It is explanatory drawing of the circuit structure of the IC chip of 1st Embodiment of this invention. It is explanatory drawing of the rectifier circuit applicable to the rectifier circuit of 1st Embodiment of this invention. It is explanatory drawing of the rectifier circuit applicable to the rectifier circuit of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the regulator circuit of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the regulator circuit of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the load modulation circuit of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the amplifier circuit for transmission of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the amplifier circuit for transmission of 1st Embodiment of this invention. It is explanatory drawing of the circuit applicable to the amplifier circuit for transmission of 1st Embodiment of this invention. It is explanatory drawing of the numerical analysis result of the DC power supply voltage in the IC chip of 1st Embodiment of this invention, a modulation signal voltage, and the voltage between antenna terminals. It is explanatory drawing of the circuit structure of the IC chip of 2nd Embodiment of this invention. It is explanatory drawing of the circuit structure of the IC chip of 3rd Embodiment of this invention. It is explanatory drawing of the circuit applicable to the comparison circuit of 3rd Embodiment of this invention. It is explanatory drawing of the circuit structure of the IC chip of 4th Embodiment of this invention. It is a sectional view for explaining a transistor using carrier accumulation. It is explanatory drawing of the 1st circuit structure of the conventional semiconductor integrated circuit device mounted in an IC tag. It is explanatory drawing of the numerical analysis result of the DC power supply voltage in the semiconductor integrated circuit device of a 1st circuit structure, a modulation signal voltage, and the voltage between antenna terminals. It is explanatory drawing of the 2nd circuit structure of the conventional semiconductor integrated circuit device mounted in an IC tag. It is explanatory drawing of the numerical analysis result of the DC power supply voltage in the 2nd circuit structure semiconductor integrated circuit device, a modulation signal voltage, and the voltage between antenna terminals.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an explanatory diagram of an IC tag system according to a first embodiment of the present invention.

  The IC tag system includes a reader / writer device RW1 and an IC tag TG1.

  The IC tag TG1 receives data from the reader / writer device RW1, and transmits the data stored therein to the reader / writer device RW1.

  The reader / writer device RW1 receives data from the IC tag TG1 (reads data) and transmits data to the IC tag TG1 (writes data). In this embodiment, the reader / writer device RW1 is described as having a data reading function and a data writing function, but the data writing function is not an essential configuration.

  The IC tag TG1 includes an antenna coil A1, a resonance capacitor C4, and an IC chip IC1.

  The reader / writer device RW1 includes an antenna coil A2, and radiates a high-frequency signal through the antenna coil A2. Since the reader / writer device RW1 and the IC tag TG1 are magnetically coupled, the high-frequency signal radiated from the antenna coil A1 is input to the IC chip IC1 via the antenna coil A1 and the resonant capacitor C4. The magnetic field coupling is a state in which the antenna coils A1 and A2 are coupled by a magnetic field generated by the antenna coils A1 and A2.

  The input of a high frequency signal to the IC tag TG1 will be described.

  The reader / writer device RW1 changes the magnetic field generated by the antenna coil A2 by changing the voltage applied to the antenna coil A2. Further, since the high frequency signal observed as the voltage of the antenna coil A1 of the IC tag TG1 is generated by the fluctuation of the magnetic field, the IC tag TG1 can detect the transmission signal. In this way, a high frequency signal is input from the antenna coil A1 to the antenna coil A2.

  The IC chip IC1 generates a power supply voltage for starting itself from the input high-frequency signal, and extracts a command from the input high-frequency signal when necessary. In addition, the IC chip IC1 generates a response signal for the command from the reader / writer device RW1, and transmits the generated response signal to the reader / writer device RW1 via the antenna coil A2.

  The function of transmitting the response signal of the IC chip IC1 to the reader / writer device RW1 will be described.

  When the response signal is transmitted to the reader / writer device RW1, the IC chip IC1 varies the voltage between the terminals (LA-LB) of the antenna coil A1 by varying its power consumption. As described above, since the antenna coils A1 and A2 are magnetically coupled, the voltage variation between the terminals of the antenna coil A1 is detected by the reader / writer device RW1 as the voltage variation between the terminals of the antenna coil A2. . In this way, the IC chip IC1 can transmit a response signal to the reader / writer device RW1.

  In FIG. 1, the power supply voltage of the IC chip IC1 is generated by using magnetic field coupling between the reader / writer device RW1 and the IC tag TG1, and data is transferred between the reader / writer device RW1 and the IC tag TG1. However, a microwave method may be used.

  In the microwave method, the reader / writer device RW1 emits radio waves, and the IC chip IC1 generates a power supply voltage by receiving the high-frequency signal through an antenna. The reader / writer device RW1 and the IC tag TG1 use radio waves. This is a method for communicating data between and.

  Whether the magnetic field coupling method or the microwave method is used depends on the wireless communication frequency between the reader / writer device RW1 and the IC tag TC1. When the wireless communication frequency is 2.45 GHz, the microwave method is used.

  FIG. 2 is an explanatory diagram of a circuit configuration of the IC chip IC1 according to the first embodiment of the present invention.

  The IC chip IC1 includes antenna terminals LA and LB, a rectifier circuit R1, a smoothing capacitor C1, a regulator circuit G1, a logic circuit L1, a transmission amplifier circuit (modulation signal (MOD1) amplifier circuit) AMP1, a load modulation circuit MOD2, and a smoothing circuit. A capacitor C2 and a rectifier circuit R2 are provided.

  An antenna coil A1 and a resonant capacitor C4 shown in FIG. 1 are connected to the antenna terminals LA and LB. Further, rectifier circuits R1 and R2 are connected to the antenna terminals LA and LB.

  The rectifier circuits R1 and R2 are circuits that convert a voltage (AC voltage) between the antenna terminals LA and LA into a DC power supply voltage by a high-frequency signal received by the antenna coil A1 from the reader / writer device R1, and the rectifier circuits R1 and R2 Details will be described with reference to FIGS.

  The present invention is based on the premise that the rectifier circuits R1 and R2 connected to the antenna terminals LA and LB are constituted by transistors using carrier accumulation shown in FIG. Note that all the transistors mounted on the IC chip IC1 of the present invention may be constituted by the transistors using carrier accumulation shown in FIG.

  The DC power supply voltage VDD1 converted into the DC power supply voltage is output from the rectifier circuit R1, and the DC power supply voltage VDD2 converted into the DC power supply voltage is output from the rectifier circuit R2. The reference voltage is the voltage VSS. The DC power supply voltage VDD1 is used for the operation of the logic circuit L1, and the DC power supply voltage VDD2 is used for the operation of the transmission amplifier circuit AMP1 and the load modulation circuit M1.

  A smoothing capacitor C1, a regulator circuit G1, and a logic circuit L1 are connected to the output destination of the DC power supply voltage VDD1 of the rectifier circuit R1.

  The smoothing capacitor C1 smoothes the DC power supply voltage VDD1 and removes high frequency noise of the DC power supply voltage VDD1.

  The regulator circuit G1 prevents an excessive voltage and current from being applied to the logic circuit L1. Further, the regulator circuit G1 stabilizes the operation of the logic circuit L1 by generating a stable voltage even when the amplitude of the high-frequency signal is large (for example, 1 μW to 10 μW). Details of the regulator circuit G1 will be described in detail with reference to FIGS.

  The logic circuit L1 operates with the DC power supply voltage VDD1 and executes processing corresponding to the command superimposed on the high-frequency signal. The logic circuit L1 holds ID data and the like, and executes arithmetic processing based on the ID data and the like. Further, the logic circuit L1 generates a transmission signal or the like to be transmitted to the reader / writer device RW1.

  A smoothing capacitor C2, a load modulation circuit M1, and a transmission amplifier circuit AMP1 are connected to the output destination of the DC power supply voltage circuit VDD2 of the rectifier circuit R2.

  As with the smoothing capacitor C1, the smoothing capacitor C2 smoothes the DC power supply voltage VDD2 and removes high frequency noise from the DC power supply voltage VDD2.

  The load modulation circuit M1 varies the power consumption of the IC chip IC1 by varying its power consumption according to the modulation signal MOD2, varies the voltage between the antenna terminals LA and LB, and reads the modulation signal MOD2 as a reader. Transmit to writer device RW1. In other words, the load modulation circuit M1 varies its power consumption according to the modulation signal MOD2, and varies the DC power supply voltage VDD2 output from the rectifier circuit R2, thereby changing the voltage between the antenna terminals LA and LB. Fluctuate. Details of the load modulation circuit M1 will be described with reference to FIG.

  The transmission amplifier circuit AMP1 inputs a modulation signal MOD2 obtained by amplifying the modulation signal MOD1, which is a transmission signal output from the logic circuit L1, to the load modulation circuit M1. Details of the transmission amplifier circuit AMP1 will be described with reference to FIGS.

  As described above, the IC chip IC1 of the present embodiment generates the DC power supply voltage VDD1 for operating the logic circuit L1 by the rectifier circuit R1, and further the DC power supply that the load modulation circuit M1 varies by the rectifier circuit R2. A voltage VDD2 is generated. For this reason, even if the load modulation circuit M1 reduces the DC power supply voltage VDD2, the DC power supply voltage VDD1 is not affected. Therefore, the amplitude of the modulation signal MOD2 can be increased while stabilizing the power supply voltage to the logic circuit L1. it can. Further, even if a thin film transistor which is a transistor using carrier accumulation shown in FIG. 16 is adopted as the transistor of the rectifier circuits R1 and R2, the high frequency is generated by the smoothing capacitors C1 and C2 connected to the rectifier circuits R1 and R2. Can be prevented from being input.

  Further, the maximum voltage of the modulation signal MOD1 output from the logic circuit L1 is lower than the DC power supply voltage VDD1 by the logic circuit L1 and the regulation circuit G1. For this reason, the total credit amplification circuit AMP1 amplifies the voltage of the modulation signal MOD1 to the DC power supply voltage VDD2. As a result, the amplitude of the modulation signal MOD2 can be amplified, and the communicable distance of the IC tag TG1 can be increased.

  FIG. 3 is an explanatory diagram of a rectifier circuit applicable to the rectifier circuits R1 and R2 according to the first embodiment of the present invention.

  The rectifier circuit shown in FIG. 3 is a half-wave rectifier circuit that outputs only a voltage when the voltage applied to the antenna terminal LA is larger than the voltage applied to the antenna terminal LB.

  The rectifier circuit shown in FIG. 3 includes a transistor T1. The gate electrode and drain terminal of the transistor T1 are connected to the antenna terminal LA, and the source electrode is an output destination of the DC power supply voltage VDD4. The antenna terminal LB is not connected to the transistor T1, and the voltage applied to the antenna terminal LB is the reference voltage VSS.

  The transistor T1 outputs only a voltage at which a current flows from the drain terminal to the source electrode (a voltage when the voltage applied to the antenna terminal LA is larger than the voltage applied to the antenna terminal LB).

  When the half-wave rectifier circuit shown in FIG. 3 is used, the number of transistors used in the rectifier circuit can be reduced as compared with the case where the full-wave rectifier circuit shown in FIG. 4 is used, so that the manufacturing cost of the IC chip IC1 can be reduced.

  When the half-wave rectifier circuit shown in FIG. 3 is applied to the rectifier circuits R1 and R2, the current characteristics between the drain terminal and the source terminal of the transistor T1 mounted on the rectifier circuit R1 are mounted on the rectifier circuit R2. It is preferable to design such that a larger current flows than the current characteristic between the drain terminal and the source terminal of the transistor T1. However, the current characteristic between the drain terminal and the source terminal of the transistor T1 mounted on the rectifier circuit R1 is made the same as the current characteristic between the drain terminal and the source terminal of the transistor T1 mounted on the rectifier circuit R2. Alternatively, the current characteristic between the drain terminal and the source terminal of the transistor T1 mounted on the rectifier circuit R1 is more than the current characteristic between the drain terminal and the source terminal of the transistor T1 mounted on the rectifier circuit R2. Alternatively, it may be designed so that a small current flows.

  FIG. 4 is an explanatory diagram of a rectifier circuit applicable to the rectifier circuits R1 and R2 according to the first embodiment of the present invention.

  In the rectifier circuit shown in FIG. 4, when the voltage applied to the antenna terminal LA is larger than the voltage applied to the antenna terminal LB, the antenna terminal LA is connected to the VDD4 terminal via the transistor T5, and the antenna terminal LB Is connected to the reference voltage VSS terminal via the transistor T4, and when the voltage applied to the antenna terminal LA is smaller than the voltage applied to the antenna terminal LB, the antenna terminal LA is connected to the reference voltage VSS via the transistor T3. The antenna terminal LB is connected to the voltage VDD4 terminal via the transistor T6. Thus, the rectifier circuit shown in FIG. 4 is a full-wave rectifier circuit that outputs voltages of all cycles as a DC power supply voltage.

  The rectifier circuit shown in FIG. 4 includes transistors T3, T4, T5, and T6.

  The drain terminal of the transistor T3 is connected to the antenna terminal LA, the gate terminal is connected to the antenna terminal LB, and the reference voltage VSS is output from the source terminal.

  The drain terminal of the transistor T4 is connected to the antenna terminal LB, the gate terminal is connected to the antenna terminal LA, and the reference voltage VSS is output from the source terminal.

  The drain terminal and gate terminal of the transistor T5 are connected to the antenna terminal LA, and the DC power supply voltage VDD4 is output from the source terminal.

  The drain terminal and the gate terminal of the transistor T6 are connected to the antenna terminal LB, and the DC power supply voltage VDD4 is output from the source terminal.

  When the voltage applied to the antenna terminal LA is higher than the voltage applied to the antenna terminal LB, the transistors T3 and T6 are turned off so that almost no current flows from the drain terminal to the source terminal. In this case, the transistors T4 and T5 are turned on so that current flows from the drain terminal to the source terminal.

  Therefore, the DC power supply voltage VDD4 is a voltage close to the voltage applied to the antenna terminal LA, and the reference voltage VSS is a voltage close to the voltage applied to the antenna terminal LB.

  On the other hand, when the voltage applied to the antenna terminal LA is lower than the voltage applied to the antenna terminal LB, the transistors T4 and T5 are turned off so that almost no current flows from the drain terminal to the source terminal. In this case, the transistors T3 and T6 are turned on so that current flows from the drain terminal to the source terminal.

  Therefore, the DC power supply voltage VDD4 is a voltage close to the voltage applied to the antenna terminal LB, and the reference voltage VSS is a voltage close to the voltage applied to the antenna terminal LA.

  In this way, the rectifier circuit shown in FIG. 4 can output the voltage of all cycles as the DC power supply voltage VDD4 regardless of the magnitude of the voltage applied to the antenna terminals LA and LB. Thus, when the full-wave rectifier circuit shown in FIG. 4 is applied to the rectifier circuit, the number of transistors used is increased compared to the case where the half-wave rectifier circuit shown in FIG. Get higher.

  When the full-wave rectifier circuit shown in FIG. 4 is applied to the rectifier circuits R1 and R2, the current characteristics between the drain terminal and the source terminal of the transistor mounted on the rectifier circuit R1 are mounted on the rectifier circuit R2. It is preferable to design so that a larger current flows than current characteristics between the drain terminal and the source terminal of the transistor. However, even if the current characteristic between the drain terminal and the source terminal of the transistor mounted on the rectifier circuit R1 is the same as the current characteristic between the drain terminal and the source terminal of the transistor mounted on the rectifier circuit R2. In addition, the current characteristic between the drain terminal and the source terminal of the transistor mounted on the rectifier circuit R1 is smaller than the current characteristic between the drain terminal and the source terminal of the transistor mounted on the rectifier circuit R2. May be designed to flow.

  Further, the full-wave rectifier circuit shown in FIG. 4 may be applied to one of the rectifier circuits R1 and R2, and the half-wave rectifier circuit may be applied to the other in FIG. 3, or the rectifier circuits R1 and R2 may be applied to FIG. The half-wave rectifier circuit shown or the full-wave rectifier circuit shown in FIG. 4 may be applied.

  FIG. 5 is an explanatory diagram of a circuit applicable to the regulator circuit G1 according to the first embodiment of the present invention.

  The regulator circuit G1 shown in FIG. 5 has a configuration called a so-called shunt regulator.

  In the regulator circuit shown in FIG. 5, the transistor T7 and the power supply monitor circuit MON1 are connected between the DC power supply voltage VDD1 and the reference voltage VSS.

  A DC power supply voltage VDD1 is input to the power supply monitor circuit MON1, and the power supply monitor circuit MON1 inputs a REG signal that increases in accordance with an increase in the DC power supply voltage VDD1 to the gate terminal of the transistor T7.

  Since the transistor increases the current flowing from the drain terminal to the source terminal when the current flowing to the gate terminal increases, the transistor T7 has a current flowing between the DC power supply voltage VDD1 and the reference voltage VSS as the REG signal increases. And the current consumption of the IC chip IC1 is increased. Thus, the transistor T7 can decrease the voltage between the DC power supply voltage VDD1 and the reference voltage VSS as the REG signal increases.

  In this way, the regulator circuit G1 shown in FIG. 5 can prevent the excessive DC power supply voltage VDD1 from being input to the logic circuit L1 when the DC power supply voltage VDD1 becomes excessive.

  Although a detailed description of the power supply monitor circuit MON1 is omitted, the power supply monitor circuit MON1 can be configured using, for example, a transistor.

  FIG. 6 is an explanatory diagram of a circuit applicable to the regulator circuit G1 according to the first embodiment of the present invention.

  The regulator circuit G1 shown in FIG. 6 is a so-called clamp circuit.

  The regulator circuit G1 shown in FIG. 6 includes a Schottky barrier diode D1 between the DC power supply voltage VDD1 and the reference voltage VSS. The DC power supply voltage VDD1 is input to the cathode of the Schottky barrier diode D1, and the reference voltage VSS is input to the anode.

  Here, when the breakdown voltage is lower than that of the PN junction diode and the DC power supply voltage VDD1 applied to the cathode is equal to or higher than the breakdown voltage, the Schottky barrier diode D1 increases the current flowing through the Schottky barrier diode D1.

  Accordingly, the regulator circuit G1 shown in FIG. 6 can drop the DC power supply voltage VDD1 when the DC power supply voltage VDD1 is equal to or higher than the breakdown voltage. Therefore, the excessive DC power supply voltage VDD1 is input to the logic circuit L1. Can be prevented.

  The regulator circuit shown in FIG. 6 uses the Schottky barrier diode D1, but a constant voltage diode may be used instead of the Schottky barrier diode D1.

  FIG. 7 is an explanatory diagram of a circuit applicable to the load modulation circuit M1 according to the first embodiment of this invention.

  The load modulation circuit M1 shown in FIG. 7 includes an impedance element Z1 and a transistor T2.

  Specifically, the transistor T2 is connected between the DC power supply voltage VDD and the reference voltage VSS via the impedance element Z1.

  The modulation signal MOD2 is inputted to the gate terminal of the transistor T2, the voltage obtained by subtracting the voltage applied to the impedance element Z1 from the DC power supply voltage VDD is inputted to the drain terminal of the transistor T2, and the reference terminal is inputted to the source terminal of the transistor T2. The voltage VSS is input.

  The transistor T2 increases or decreases the current flowing from the drain terminal to the source terminal as the voltage of the modulation signal MOD2 input to the gate terminal increases or decreases. As a result, the transistor T2 can increase or decrease the power consumption of the IC chip IC1, and change the voltage between the antenna terminals LA and LB as the voltage of the modulation signal MOD2 increases or decreases.

  The impedance element Z1 may be an element having impedance, for example, a resistor and a capacitor. The impedance of the impedance element Z1 may be “0”. That is, the DC power supply voltage VDD may be directly input to the drain terminal of the transistor T2.

  In addition, the power consumption of the load modulation circuit M1 can be adjusted by adjusting the current characteristics between the drain terminal and the source terminal of the transistor T2 and the impedance of the impedance element Z1 in view of the power consumption of the IC chip IC1.

  FIG. 8 is an explanatory diagram of a circuit applicable to the transmission amplifier circuit AMP1 according to the first embodiment of the present invention.

  The transmission amplifier circuit AMP1 shown in FIG. 8 includes transistors T8 and T9.

  The DC power supply voltage VDD2 is input to the drain terminal and the gate terminal of the transistor T8, and the drain terminal of the transistor T9 is connected to the source terminal. Note that the modulation signal MOD2 is output from a connection line between the source terminal of the transistor T8 and the drain terminal of the transistor T9.

  Further, the modulation signal MOD1 is input to the gate terminal of the transistor T9, and the reference voltage is input to the source terminal.

  When the voltage of the modulation signal MOD1 is lower than the threshold voltage of the transistor T9 (voltage for turning on the transistor T9) and is near the reference voltage VSS (the voltage of the modulation signal MOD1 is in a low potential state) ), The transistor T9 is in an off state, and the DC power supply voltage VDD2 is input to the gate terminal of the transistor T8, so that the transistor T8 is in an on state.

  In this case, a current flows more easily between the drain terminal and the source terminal of the transistor T8 than between the drain terminal and the source terminal of the transistor T9. For this reason, the modulation signal MOD2 outputs a voltage substantially the same as the DC power supply voltage VDD2.

  On the other hand, when the voltage of the modulation signal MOD1 is equal to or higher than the threshold voltage of the transistor T9, the transistor T9 is turned on. The threshold voltage is a voltage lower than the DC power supply voltage VDD2. Here, if the voltage of the modulation signal MOD1 is in a high potential state where the voltage is substantially the same as the DC power supply voltage VDD2, the gap between the drain terminal and the source terminal of the transistor T9 is between the drain terminal and the source terminal of the transistor T8. Current flows more easily. For this reason, when the voltage of the modulation signal MOD1 is in a high potential state, the modulation signal MOD2 outputs a voltage substantially the same as the reference voltage VSS.

  When the voltage of the modulation signal MOD1 is in a low potential state, the modulation signal MOD2 is a voltage close to the DC power supply voltage VDD2, and when the voltage of the modulation signal MOD1 is in a high potential state, the modulation signal MOD2 is a voltage close to the reference voltage VSS. Become. Accordingly, the transmission amplifier circuit AMP1 shown in FIG. 8 can amplify the voltage of the modulation signal MOD1 and output the modulation signal MOD2 in a wide voltage range (a range from the reference voltage VSS to the DC power supply voltage VDD).

  When the transmission amplifier circuit AMP1 shown in FIG. 8 is mounted on the IC chip IC1, if the voltage of the modulation signal MOD1 becomes a high potential state, the modulation signal MOD2 having a voltage near the reference voltage VSS is output, and the modulation signal MOD1 is low. In the potential state, a modulation signal MOD2 having a voltage near the DC power supply voltage VDD2 is output. As described above, the modulation signal MOD2 output from the transmission amplifier circuit AMP1 illustrated in FIG. 8 is an inverted signal of the modulation signal MOD1 that is an input signal.

  FIG. 9 is an explanatory diagram of a circuit applicable to the transmission amplifier circuit AMP1 according to the first embodiment of the present invention.

  The transmission amplifier circuit AMP1 shown in FIG. 9 includes transistors T8, T9, T10, and T11. The operations of the transistors T8 and T9 are the same as the operations of the transistors T8 and T9 of the transmission amplifier circuit AMP1 shown in FIG.

  The DC power supply voltage VDD2 is input to the drain terminal and gate terminal of the transistor T8, and the source terminal is connected to the drain terminal of the transistor T9. The connection line between the source terminal of the transistor T8 and the drain terminal of the transistor T9 is connected to the gate terminal of the transistor T10.

  The modulation signal MOD1 is input to the gate terminal of the transistor T9, and the reference voltage VSS is input to the source terminal. The DC power supply voltage VDD2 is input to the drain terminal of the transistor T10, and the source terminal is connected to the drain terminal of the transistor T11. A modulation signal MOD2 is output from a connection line between the source terminal of the transistor T10 and the drain terminal of the transistor T11. The modulation signal MOD1 is input to the gate terminal of the transistor T11, and the reference voltage VSS is input to the source terminal.

  Detailed operations of the transistors T8 and T9 are the same as those in FIG. When the modulation signal MOD1 is in a low potential state, the gate terminal of the transistor T10 is input with a voltage substantially the same as the DC power supply voltage VDD2, and when the modulation signal MOD1 is in a high potential state, the reference voltage is applied to the gate terminal of the transistor T10. The same voltage as VSS is input.

  The operation of the transistors T10 and T11 when the modulation signal MOD1 is in the low potential state will be described.

  In this case, since the low-potential modulation signal MOD1 is input to the gate terminal of the transistor T11, the transistor T11 is turned off. A current flows more easily between the drain terminal and the source terminal of the transistor T10 than between the drain terminal and the source terminal of the transistor T11. For this reason, the modulation signal MOD2 outputs a voltage substantially the same as the DC power supply voltage VDD2.

  Next, the operation of the transistors T10 and T11 when the modulation signal MOD1 is in a high potential state will be described.

  In this case, since the modulation signal MOD1 in a high potential state is input to the gate terminal of the transistor T11, the transistor T11 is turned on. On the other hand, since the same voltage as the reference voltage VSS is input to the gate terminal of the transistor T10, the transistor T10 is turned off, or the drain terminal of the transistor T10 is connected to the drain terminal of the transistor T11. The current is less likely to flow than between the terminal and the source terminal. For this reason, the modulation signal MOD2 outputs substantially the same voltage as the reference voltage VSS.

  Note that the transmission amplifier circuit AMP1 shown in FIG. 9 outputs a modulation signal MOD2 that is an inverted signal with respect to the modulation signal MOD1, as with the transmission amplifier circuit AMP1 shown in FIG. Specifically, the transmission amplifier circuit AMP1 shown in FIG. 9 outputs the modulation signal MOD2 having a voltage near the reference voltage VSS when the voltage of the modulation signal MOD1 is in a high potential state, and the modulation signal MOD1 is in a low potential state. If so, the modulation signal MOD2 having a voltage in the vicinity of the DC power supply voltage VDD2 is output.

  However, since the transmission amplifier circuit AMP1 shown in FIG. 9 inputs the voltage amplified by the transistors T8 and T9 to the gate terminal of the transistor T10 and amplifies the voltage by the transistors T10 and T11, the transmission circuit shown in FIG. The maximum voltage of the modulation signal MOD2 can be made closer to the DC power supply voltage VDD2 and the minimum voltage of the modulation signal MOD2 can be made closer to the reference voltage VSS than the credit amplification circuit AMP1.

  FIG. 10 is an explanatory diagram of a circuit applicable to the transmission amplifier circuit AMP1 according to the first embodiment of this invention.

  The transmission amplifier circuit AMP1 shown in FIG. 10 includes transistors T8, T9, T12, and T13. The transistors T8 and T9 are the same as the transistors T8 and T9 of the transmission amplifier circuit AMP1 shown in FIGS.

  In the transmission amplifier circuit AMP1 shown in FIG. 10, the DC power supply voltage VDD2 is input to the gate terminal of the transistor T12, and the connection line between the source terminal of the transistor T8 and the drain terminal of the transistor T9 is the gate terminal of the transistor T13. Is different from the transmission amplifier circuit AMP1 shown in FIG.

  Thus, the transmission amplifier circuit AMP1 shown in FIG. 10 can output the modulation signal MOD2 having the same phase as the modulation signal MOD1.

  Specifically, when the modulation signal MOD1 is in a low potential state, the transistor T13 is turned on because substantially the same voltage as the DC power supply voltage VDD2 is input to the gate terminal of the transistor T13. On the other hand, the DC power supply voltage VDD2 is input to the gate terminal of the transistor T12. For this reason, a current is less likely to flow between the drain terminal and the source terminal of the transistor T12 than between the drain terminal and the source terminal of the transistor T13. Therefore, the modulation signal MOD2 outputs a voltage that is substantially the same as the reference voltage VSS.

  When the modulation signal MOD1 is in a high potential state, the transistor T13 is turned off because the gate terminal of the transistor T13 is input with a voltage that is substantially the same as the reference voltage VSS. A current flows more easily between the drain terminal and the source terminal of the transistor T12 than between the drain terminal and the source terminal of the transistor T13. For this reason, the modulation signal MOD2 outputs a voltage substantially the same as the DC power supply voltage VDD2.

  In this way, the modulation signal MOD1 is once inverted and amplified by the transistors T8 and T9, and then inverted and amplified again by the transistors T12 and T13, so that the modulation signal MOD2 is in phase with the modulation signal MOD1.

  Further, the amplitude of the modulation signal MOD2 output from the transmission amplifier circuit AMP1 shown in FIG. 10 is equal to or larger than the amplitude of the modulation signal MOD2 output from the transmission amplifier circuit AMP1 shown in FIG.

  FIG. 11 is an explanatory diagram of numerical analysis results of the DC power supply voltage (VDD1), the modulation signal voltage (MOD1), and the antenna terminal voltage (LA-LB) in the IC chip IC1 according to the first embodiment of the present invention.

  The fluctuation of the amplitude of the DC power supply voltage (VDD1) shown in FIG. 11 can be reduced more than the fluctuation of the amplitude of the DC power supply voltage (VDD1) shown in FIGS. 18 and 20, and the voltage between the antenna terminals (LA-LB) can be reduced. The variation in the amplitude can be made larger than the variation in the amplitude of the voltage between the antenna terminals (LA-LB) shown in FIGS.

  This is because the IC chip IC1 of the embodiment generates the DC power supply voltage VDD1 for operating the logic circuit L1 by the rectifier circuit R1, and further generates the DC power supply voltage VDD2 that the load modulation circuit M1 varies by the rectifier circuit R2. By generating.

  Further, since the high frequency is removed by the smoothing capacitors C1 and C2 connected to the rectifier circuits R1 and R2, as shown in FIG. 11, the high frequency signal does not propagate to the modulation signal voltage (MOD1).

  As a result, it is possible to increase the amplitude of the voltage between the antenna terminals (LA-LB) while preventing the amplitude of the DC power supply voltage (VDD1), which is a voltage for operating the logic circuit L1, from being reduced. The operation of the IC chip IC1 can be stabilized without reducing the distance. In addition, since the high frequency signal does not propagate to the DC power supply voltage (VDD1) that is a voltage for operating the logic circuit L1, the operation of the IC chip IC1 can be stabilized.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.

  FIG. 12 is an explanatory diagram of a circuit configuration of the IC chip IC1 according to the second embodiment of the present invention.

  Of the components of the IC chip IC1 shown in FIG. 12, the same components as those of the IC chip IC1 of the first embodiment shown in FIG.

  The IC chip IC1 shown in FIG. 12 is the first in that the DC power supply voltage VDD2 is input to the logic circuit L1 in order to input the demodulated signal obtained by demodulating the signal transmitted from the reader / writer device RW1 to the logic circuit L1. Different from the IC chip IC1 of the embodiment.

  The signal transmitted from the reader / writer device RW1 is demodulated by the rectifier circuit R2 and the smoothing capacitor C2. This demodulated voltage (VDD2) is input to the logic circuit L1 as a demodulated signal.

  When a demodulated signal is input to the logic circuit L1, the logic circuit L1 detects a command indicated by the input demodulated signal and executes processing corresponding to the detected command.

  Here, in the circuit configuration of the IC chip IC1 shown in FIG. 2 of the first embodiment, when the demodulated signal is input to the logic circuit L1, the logic circuit L1 detects the demodulated signal from the DC power supply voltage VDD1. I must.

  The DC power supply voltage VDD1 input to the logic circuit L1 is a voltage obtained by removing a voltage equal to or higher than a predetermined value by the regulator circuit G1. For this reason, the logic circuit L1 cannot accurately detect the command indicated by the demodulated signal.

  For this reason, in the second embodiment of the present invention, a DC power supply voltage VDD2 for inputting a demodulated signal to the logic circuit L1 is input to the logic circuit L1 separately from the DC power supply voltage VDD1 for starting the logic circuit L1. I did it.

  Since the DC power supply voltage VDD2 is not affected by the regulator circuit G1, the logic circuit L1 can accurately detect the command indicated by the demodulated signal.

  The operation in which the rectifier circuit R2 and the smoothing capacitor C2 demodulate the signal transmitted from the reader / writer device RW1 does not affect the operation of the load modulation circuit M1, and the operation of the load modulation circuit M1 The demodulation operation of R2 and the smoothing capacitor C2 is not affected.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS.

  FIG. 13 is an explanatory diagram of a circuit configuration of the IC chip IC1 according to the third embodiment of the present invention.

  Of the components of the IC chip IC1 shown in FIG. 13, the same components as those of the IC chip IC1 of the first embodiment shown in FIG.

  The IC chip IC1 shown in FIG. 13 has a modulation signal MOD1 output from the logic circuit L1 and a modulation signal MOD2 output from the transmission amplifier circuit AMP1 in addition to the configuration of the IC chip IC1 of the first embodiment shown in FIG. And a comparison circuit CMP1 for inputting the modulation signal having the larger voltage as the modulation signal MOD3 to the load modulation circuit M1. Details of the comparison circuit CMP1 will be described with reference to FIG. The modulation signal MOD2 is a signal obtained by amplifying the modulation signal MOD1 by the transmission amplifier circuit AMP1, and the modulation signal MOD1 and the modulation signal MOD2 are in-phase signals. Therefore, in this embodiment, the transmission amplifier circuit AMP1 shown in FIG. 10 is employed as the transmission amplifier circuit AMP1.

  The load modulation circuit M1 varies the power consumption of the IC chip IC1 by varying its power consumption according to the modulation signal MOD3 output from the comparison circuit CMP1, and varies the voltage between the antenna terminals LA and LB. Let

  Since the modulation signal having the larger voltage of the modulation signal M1 and the modulation signal M2 is input to the load modulation circuit M1, the voltage of the modulation signal MOD3 input to the load modulation circuit M1 is less than the DC power supply voltage VDD1. To prevent. As a result, it is possible to prevent fluctuations in the amplitude of the voltage between the antenna terminals (LA-LB) from decreasing.

  The effect of this embodiment will be specifically described.

  In the IC chip IC1 of the first embodiment shown in FIG. 2, the modulation signal MOD2 is input to the load modulation circuit M1. When the modulation signal MOD2 input to the load modulation circuit M1 shown in FIG. 7 is in a high potential state, a current easily flows between the drain terminal and the source terminal of the transistor T2. Therefore, the load modulation circuit M1 The DC power supply voltage VDD2 is lowered. For this reason, the amplification factor of the amplification enhancement circuit AMP1 decreases, and the voltage of the modulation signal MOD2 amplified by the transmission amplification circuit AMP1 also decreases as the DC power supply voltage VDD2 decreases. As a result, a sufficient amplitude of the modulation signal MOD2 may not be obtained.

  On the other hand, in the IC chip IC1 of this embodiment, the modulation signal having the larger voltage of the modulation signal MOD1 and the modulation signal MOD2 is input to the load modulation circuit M1 by the comparison circuit CMP1, so that the DC power supply voltage VDD2 Even if the modulation signal MOD2 output from the transmission amplifier circuit AMP1 decreases due to the decrease, it is possible to prevent the voltage of the modulation signal MOD1 input to the load modulation circuit M1 from being equal to or lower than the voltage of the modulation signal MOD1. Thus, the amplitude of the modulation signal MOD3 input to the transmission amplifier circuit M1 can be secured to the amplitude of the modulation signal MOD1, and a modulation signal equal to or lower than the amplitude of the modulation signal MOD1 is input to the transmission amplifier circuit M1. Can be prevented, and the reduction of the communicable distance of the IC tag TG1 can be prevented.

  FIG. 14 is an explanatory diagram of a circuit applicable to the comparison circuit CMP1 according to the third embodiment of the present invention.

  The comparison circuit CMP1 includes transistors T14 and T15.

  The modulation signal MOD1 is input to the gate terminal and the drain terminal of the transistor T14, and the modulation signal MOD2 is input to the gate terminal and the drain terminal of the transistor T15. Further, the source terminal of the transistor T14 and the source terminal of the transistor T15 are connected. A modulation signal MOD3 is output from a connection line between the source terminal of the transistor T14 and the source terminal of the transistor T15.

  When the voltage of the modulation signal MOD1 is higher than the voltage of the modulation signal MOD2, the transistor T14 is turned on and the transistor T15 is turned off. For this reason, since a current flows more easily between the drain terminal and the source terminal of the transistor T14 than between the drain terminal and the source terminal of the transistor T15, a voltage close to the change signal MOD1 is output to the modulation signal MOD3. Is done.

  When the voltage of the modulation signal MOD2 is higher than the voltage of the modulation signal MOD1, the transistor T15 is turned on and the transistor T14 is turned off. For this reason, since a current flows more easily between the drain terminal and the source terminal of the transistor T15 than between the drain terminal and the source terminal of the transistor T14, a voltage close to the change signal MOD2 is output to the modulation signal MOD3. Is done.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG.

  FIG. 15 is an explanatory diagram of a circuit configuration of the IC chip IC1 according to the fourth embodiment of the present invention.

  Of the configurations of the IC chip IC1 shown in FIG. 15, the same configurations as those of the IC chip IC1 of the first embodiment shown in FIG.

  The IC chip IC1 shown in FIG. 15 includes the rectifier circuit R3 and the smoothing capacitor C3, and the point that the DC power supply voltage VDD3 is input to the transmission amplifier circuit AMP1 is the IC of the first embodiment shown in FIG. Different from the chip IC1.

  Rectifier circuits R1, R2, and R3 are connected to the antenna terminals LA and LB.

  The rectifier circuit R3 is a circuit that converts a voltage (AC voltage) between the antenna terminals LA and LA into a DC power supply voltage VDD3 by a high-frequency signal received by the antenna coil A1 from the reader / writer device R1. As with the rectifier circuits R1 and R2, the rectifier circuit shown in FIG. 3 or 4 may be applied to the rectifier circuit R3.

  Note that the transistor constituting the rectifier circuit R3 is a transistor using carrier accumulation shown in FIG.

  The transmission amplifier circuit VDD3 operates using the DC power supply voltage VDD3 output from the rectifier circuit R3, and does not share the DC power supply voltage VDD2 input to the load DC circuit M1.

  Accordingly, even when the modulation signal MOD2 input to the load modulation circuit M1 shown in FIG. 7 is in a high potential state, even if the load modulation circuit M1 decreases the DC power supply voltage VDD2, the transmission amplifier circuit AMP1 MOD1 can be amplified in the range from the DC power supply voltage VDD3 to the reference voltage VSS. As a result, the transmission amplifier circuit AMP1 can input the modulation signal MOD2 having a large amplitude to the load modulation circuit M1.

  Therefore, according to the present embodiment, it is possible to prevent a variation in the amplitude of the voltage between the antenna terminals (LA-LB) from decreasing, and to increase the communicable distance of the IC tag TG1.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is applicable to non-contact electronic devices, so-called IC tags and the like.

A1 and A2 ... coil antenna AMP1 ... transmission amplifier circuit C1 to 4 ... smoothing capacitor CL1 ... channel layer IL1 ... insulator layers ML1 and ML2 ... metal layers MOD1 to MOD3 ... modulation signals LA and LB ... antenna terminals R1 to R3 ... Rectifier circuit RW1 ... Reader / writer device SL1 ... Substrate layers T1-15 ... Transistor TG1 ... IC tag

Claims (6)

A non-contact electronic device composed of a transistor using a carrier storage layer,
A first transistor connected to a first smoothing capacitor and configured by a first transistor using the carrier accumulation, which is received by an antenna connected to the non-contact electronic device, is converted into a first DC power supply voltage. Rectifier circuit of
A second transistor connected to a second smoothing capacitor and configured by a second transistor using the carrier accumulation, which converts a signal received by an antenna connected to the non-contact electronic device into a second DC power supply voltage. Rectifier circuit of
A logic circuit that operates using a voltage obtained by smoothing the first DC power supply voltage by the first smoothing capacitor;
A modulation signal amplification circuit that outputs a second modulation signal obtained by amplifying the first modulation signal output by the logic circuit;
A load modulation circuit that varies a voltage obtained by smoothing the second DC power supply voltage by the second smoothing capacitor based on a second modulation signal output from the modulation signal amplification circuit. Non-contact electronic device characterized.   The modulation signal amplifying circuit operates using a voltage obtained by smoothing the second DC power supply voltage by the second smoothing capacitor, and converts the voltage of the first modulation signal to the second smoothing capacitor. The contactless electronic device according to claim 1, wherein the second DC power supply voltage can be amplified without exceeding a smoothed voltage. Comparing the voltage of the first modulation signal and the voltage of the second modulation signal, comprising a comparison circuit that outputs the modulation signal having the larger voltage as the modulation signal,
2. The load modulation circuit varies a voltage obtained by smoothing the second DC power supply voltage by the second smoothing capacitor based on a modulation signal output from the comparison circuit. A non-contact electronic device according to 1. A third transistor connected to a third smoothing capacitor and configured by a third transistor using the carrier accumulation, which converts a signal received by an antenna connected to the non-contact electronic device into a third DC power supply voltage. Rectifier circuit,
The modulation signal amplifier circuit operates using a voltage obtained by smoothing the third DC power supply voltage by the third smoothing capacitor, and the voltage of the first modulation signal is obtained by the third smoothing capacitor. The contactless electronic device according to claim 1, wherein the third DC power supply voltage can be amplified to a smoothed voltage.   The contactless electronic device according to any one of claims 1 to 4, wherein the transistor is a thin film transistor.   6. The contactless electronic device according to claim 1, wherein the semiconductor layer of the transistor is a semiconductor mainly composed of a metal oxide.

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